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1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  Versatile library, clock and reset                          ////
4
////                                                              ////
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////  Description                                                 ////
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////  Logic related to clock and reset                            ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
10
////   - add more different registers                             ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
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////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
// Global buffer
43
// usage:
44
// use to enable global buffers for high fan out signals such as clock and reset
45
`timescale 1 ns/100 ps
46
// Version: 8.4 8.4.0.33
47
module gbuf(GL,CLK);
48
output GL;
49
input  CLK;
50
    wire GND;
51
    GND GND_1_net(.Y(GND));
52
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
53
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
54
endmodule
55
`timescale 1 ns/1 ns
56
module vl_gbuf ( i, o);
57
input i;
58
output o;
59
`ifdef SIM_GBUF
60
assign o=i;
61
`else
62
gbuf gbuf_i0 ( .CLK(i), .GL(o));
63
`endif
64
endmodule
65
 //ACTEL
66
// sync reset
67
// input active lo async reset, normally from external reset generetaor and/or switch
68
// output active high global reset sync with two DFFs 
69
`timescale 1 ns/100 ps
70
module vl_sync_rst ( rst_n_i, rst_o, clk);
71
input rst_n_i, clk;
72
output rst_o;
73
reg [0:1] tmp;
74
always @ (posedge clk or negedge rst_n_i)
75
if (!rst_n_i)
76
        tmp <= 2'b00;
77
else
78
        tmp <= {1'b1,tmp[0]};
79
vl_gbuf buf_i0( .i(tmp[1]), .o(rst_o));
80
endmodule
81
// vl_pll
82
`timescale 1 ns/100 ps
83
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
84
parameter index = 0;
85
parameter number_of_clk = 1;
86
parameter period_time_0 = 20;
87
parameter period_time_1 = 20;
88
parameter period_time_2 = 20;
89
parameter lock_delay = 2000;
90
input clk_i, rst_n_i;
91
output lock;
92
output reg [0:number_of_clk-1] clk_o;
93
output [0:number_of_clk-1] rst_o;
94
`ifdef SIM_PLL
95
always
96
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
97
generate if (number_of_clk > 1)
98
always
99
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
100
endgenerate
101
generate if (number_of_clk > 2)
102
always
103
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
104
endgenerate
105
genvar i;
106
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
107
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
108
end
109
endgenerate
110
assign #lock_delay lock = rst_n_i;
111
endmodule
112
`else
113
generate if (number_of_clk==1 & index==0) begin
114
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
115
end
116
endgenerate // index==0
117
generate if (number_of_clk==1 & index==1) begin
118
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
119
end
120
endgenerate // index==1
121
generate if (number_of_clk==1 & index==2) begin
122
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
123
end
124
endgenerate // index==2
125
generate if (number_of_clk==1 & index==3) begin
126
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
127
end
128
endgenerate // index==0
129
generate if (number_of_clk==2 & index==0) begin
130
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
131
end
132
endgenerate // index==0
133
generate if (number_of_clk==2 & index==1) begin
134
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
135
end
136
endgenerate // index==1
137
generate if (number_of_clk==2 & index==2) begin
138
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
139
end
140
endgenerate // index==2
141
generate if (number_of_clk==2 & index==3) begin
142
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
143
end
144
endgenerate // index==0
145
generate if (number_of_clk==3 & index==0) begin
146
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
147
end
148
endgenerate // index==0
149
generate if (number_of_clk==3 & index==1) begin
150
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
151
end
152
endgenerate // index==1
153
generate if (number_of_clk==3 & index==2) begin
154
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
155
end
156
endgenerate // index==2
157
generate if (number_of_clk==3 & index==3) begin
158
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
159
end
160
endgenerate // index==0
161
genvar i;
162
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
163
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
164
end
165
endgenerate
166
endmodule
167
`endif
168
 //actel
169
//////////////////////////////////////////////////////////////////////
170
////                                                              ////
171
////  Versatile library, registers                                ////
172
////                                                              ////
173
////  Description                                                 ////
174
////  Different type of registers                                 ////
175
////                                                              ////
176
////                                                              ////
177
////  To Do:                                                      ////
178
////   - add more different registers                             ////
179
////                                                              ////
180
////  Author(s):                                                  ////
181
////      - Michael Unneback, unneback@opencores.org              ////
182
////        ORSoC AB                                              ////
183
////                                                              ////
184
//////////////////////////////////////////////////////////////////////
185
////                                                              ////
186
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
187
////                                                              ////
188
//// This source file may be used and distributed without         ////
189
//// restriction provided that this copyright statement is not    ////
190
//// removed from the file and that any derivative work contains  ////
191
//// the original copyright notice and the associated disclaimer. ////
192
////                                                              ////
193
//// This source file is free software; you can redistribute it   ////
194
//// and/or modify it under the terms of the GNU Lesser General   ////
195
//// Public License as published by the Free Software Foundation; ////
196
//// either version 2.1 of the License, or (at your option) any   ////
197
//// later version.                                               ////
198
////                                                              ////
199
//// This source is distributed in the hope that it will be       ////
200
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
201
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
202
//// PURPOSE.  See the GNU Lesser General Public License for more ////
203
//// details.                                                     ////
204
////                                                              ////
205
//// You should have received a copy of the GNU Lesser General    ////
206
//// Public License along with this source; if not, download it   ////
207
//// from http://www.opencores.org/lgpl.shtml                     ////
208
////                                                              ////
209
//////////////////////////////////////////////////////////////////////
210
module dff ( d, q, clk, rst);
211
        parameter width = 1;
212
        parameter reset_value = 0;
213
        input [width-1:0] d;
214
        input clk, rst;
215
        output reg [width-1:0] q;
216
        always @ (posedge clk or posedge rst)
217
        if (rst)
218
                q <= reset_value;
219
        else
220
                q <= d;
221
endmodule
222
module dff_array ( d, q, clk, rst);
223
        parameter width = 1;
224
        parameter depth = 2;
225
        parameter reset_value = 1'b0;
226
        input [width-1:0] d;
227
        input clk, rst;
228
        output [width-1:0] q;
229
        reg  [0:depth-1] q_tmp [width-1:0];
230
        integer i;
231
        always @ (posedge clk or posedge rst)
232
        if (rst) begin
233
            for (i=0;i<depth;i=i+1)
234
                q_tmp[i] <= {width{reset_value}};
235
        end else begin
236
            q_tmp[0] <= d;
237
            for (i=1;i<depth;i=i+1)
238
                q_tmp[i] <= q_tmp[i-1];
239
        end
240
    assign q = q_tmp[depth-1];
241
endmodule
242
module dff_ce ( d, ce, q, clk, rst);
243
        parameter width = 1;
244
        parameter reset_value = 0;
245
        input [width-1:0] d;
246
        input ce, clk, rst;
247
        output reg [width-1:0] q;
248
        always @ (posedge clk or posedge rst)
249
        if (rst)
250
                q <= reset_value;
251
        else
252
                if (ce)
253
                        q <= d;
254
endmodule
255 8 unneback
module dff_ce_clear ( d, ce, clear, q, clk, rst);
256
        parameter width = 1;
257
        parameter reset_value = 0;
258
        input [width-1:0] d;
259 10 unneback
        input ce, clear, clk, rst;
260 8 unneback
        output reg [width-1:0] q;
261
        always @ (posedge clk or posedge rst)
262
        if (rst)
263
            q <= reset_value;
264
        else
265
            if (ce)
266
                if (clear)
267
                    q <= {width{1'b0}};
268
                else
269
                    q <= d;
270
endmodule
271 6 unneback
module dff_sr ( aclr, aset, clock, data, q);
272
    input         aclr;
273
    input         aset;
274
    input         clock;
275
    input         data;
276
    output reg    q;
277
   always @ (posedge clock or posedge aclr or posedge aset)
278
     if (aclr)
279
       q <= 1'b0;
280
     else if (aset)
281
       q <= 1'b1;
282
     else
283
       q <= data;
284
endmodule
285
// LATCH
286
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
287
module latch ( d, le, q, clk);
288
input d, le;
289
output q;
290
input clk;/*
291
   always @ (posedge direction_set or posedge direction_clr)
292
     if (direction_clr)
293
       direction <= going_empty;
294
     else
295
       direction <= going_full;*/
296
endmodule
297 15 unneback
module delay ( d, q, clk, rst);
298
parameter depth = 10;
299
input d;
300
output q;
301
input clk, rst;
302
reg [1:depth] dffs;
303
always @ (posedge clk or posedge rst)
304
if (rst)
305
    dffs <= {depth{1'b0}};
306
else
307
    dffs <= {d,dffs[1:depth-1]};
308
assign q = dffs[depth];
309
endmodule
310 6 unneback
//////////////////////////////////////////////////////////////////////
311
////                                                              ////
312
////  Versatile counter                                           ////
313
////                                                              ////
314
////  Description                                                 ////
315
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
316
////  counter                                                     ////
317
////                                                              ////
318
////  To Do:                                                      ////
319
////   - add LFSR with more taps                                  ////
320
////                                                              ////
321
////  Author(s):                                                  ////
322
////      - Michael Unneback, unneback@opencores.org              ////
323
////        ORSoC AB                                              ////
324
////                                                              ////
325
//////////////////////////////////////////////////////////////////////
326
////                                                              ////
327
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
328
////                                                              ////
329
//// This source file may be used and distributed without         ////
330
//// restriction provided that this copyright statement is not    ////
331
//// removed from the file and that any derivative work contains  ////
332
//// the original copyright notice and the associated disclaimer. ////
333
////                                                              ////
334
//// This source file is free software; you can redistribute it   ////
335
//// and/or modify it under the terms of the GNU Lesser General   ////
336
//// Public License as published by the Free Software Foundation; ////
337
//// either version 2.1 of the License, or (at your option) any   ////
338
//// later version.                                               ////
339
////                                                              ////
340
//// This source is distributed in the hope that it will be       ////
341
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
342
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
343
//// PURPOSE.  See the GNU Lesser General Public License for more ////
344
//// details.                                                     ////
345
////                                                              ////
346
//// You should have received a copy of the GNU Lesser General    ////
347
//// Public License along with this source; if not, download it   ////
348
//// from http://www.opencores.org/lgpl.shtml                     ////
349
////                                                              ////
350
//////////////////////////////////////////////////////////////////////
351
// binary counter
352
module cnt_bin_ce ( cke, q, rst, clk);
353
   parameter length = 4;
354
   input cke;
355
   output [length:1] q;
356
   input rst;
357
   input clk;
358
   parameter clear_value = 0;
359
   parameter set_value = 1;
360
   parameter wrap_value = 0;
361
   parameter level1_value = 15;
362
   reg  [length:1] qi;
363
   wire [length:1] q_next;
364
   assign q_next = qi + {{length-1{1'b0}},1'b1};
365
   always @ (posedge clk or posedge rst)
366
     if (rst)
367
       qi <= {length{1'b0}};
368
     else
369
     if (cke)
370
       qi <= q_next;
371
   assign q = qi;
372
endmodule
373
//////////////////////////////////////////////////////////////////////
374
////                                                              ////
375
////  Versatile counter                                           ////
376
////                                                              ////
377
////  Description                                                 ////
378
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
379
////  counter                                                     ////
380
////                                                              ////
381
////  To Do:                                                      ////
382
////   - add LFSR with more taps                                  ////
383
////                                                              ////
384
////  Author(s):                                                  ////
385
////      - Michael Unneback, unneback@opencores.org              ////
386
////        ORSoC AB                                              ////
387
////                                                              ////
388
//////////////////////////////////////////////////////////////////////
389
////                                                              ////
390
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
391
////                                                              ////
392
//// This source file may be used and distributed without         ////
393
//// restriction provided that this copyright statement is not    ////
394
//// removed from the file and that any derivative work contains  ////
395
//// the original copyright notice and the associated disclaimer. ////
396
////                                                              ////
397
//// This source file is free software; you can redistribute it   ////
398
//// and/or modify it under the terms of the GNU Lesser General   ////
399
//// Public License as published by the Free Software Foundation; ////
400
//// either version 2.1 of the License, or (at your option) any   ////
401
//// later version.                                               ////
402
////                                                              ////
403
//// This source is distributed in the hope that it will be       ////
404
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
405
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
406
//// PURPOSE.  See the GNU Lesser General Public License for more ////
407
//// details.                                                     ////
408
////                                                              ////
409
//// You should have received a copy of the GNU Lesser General    ////
410
//// Public License along with this source; if not, download it   ////
411
//// from http://www.opencores.org/lgpl.shtml                     ////
412
////                                                              ////
413
//////////////////////////////////////////////////////////////////////
414
// binary counter
415
module cnt_bin_ce_clear ( clear, cke, q, rst, clk);
416
   parameter length = 4;
417
   input clear;
418
   input cke;
419
   output [length:1] q;
420
   input rst;
421
   input clk;
422
   parameter clear_value = 0;
423
   parameter set_value = 1;
424
   parameter wrap_value = 0;
425
   parameter level1_value = 15;
426
   reg  [length:1] qi;
427
   wire [length:1] q_next;
428
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
429
   always @ (posedge clk or posedge rst)
430
     if (rst)
431
       qi <= {length{1'b0}};
432
     else
433
     if (cke)
434
       qi <= q_next;
435
   assign q = qi;
436
endmodule
437
//////////////////////////////////////////////////////////////////////
438
////                                                              ////
439
////  Versatile counter                                           ////
440
////                                                              ////
441
////  Description                                                 ////
442
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
443
////  counter                                                     ////
444
////                                                              ////
445
////  To Do:                                                      ////
446
////   - add LFSR with more taps                                  ////
447
////                                                              ////
448
////  Author(s):                                                  ////
449
////      - Michael Unneback, unneback@opencores.org              ////
450
////        ORSoC AB                                              ////
451
////                                                              ////
452
//////////////////////////////////////////////////////////////////////
453
////                                                              ////
454
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
455
////                                                              ////
456
//// This source file may be used and distributed without         ////
457
//// restriction provided that this copyright statement is not    ////
458
//// removed from the file and that any derivative work contains  ////
459
//// the original copyright notice and the associated disclaimer. ////
460
////                                                              ////
461
//// This source file is free software; you can redistribute it   ////
462
//// and/or modify it under the terms of the GNU Lesser General   ////
463
//// Public License as published by the Free Software Foundation; ////
464
//// either version 2.1 of the License, or (at your option) any   ////
465
//// later version.                                               ////
466
////                                                              ////
467
//// This source is distributed in the hope that it will be       ////
468
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
469
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
470
//// PURPOSE.  See the GNU Lesser General Public License for more ////
471
//// details.                                                     ////
472
////                                                              ////
473
//// You should have received a copy of the GNU Lesser General    ////
474
//// Public License along with this source; if not, download it   ////
475
//// from http://www.opencores.org/lgpl.shtml                     ////
476
////                                                              ////
477
//////////////////////////////////////////////////////////////////////
478
// binary counter
479
module cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
480
   parameter length = 4;
481
   input clear;
482
   input set;
483
   input cke;
484
   input rew;
485
   output [length:1] q;
486
   input rst;
487
   input clk;
488
   parameter clear_value = 0;
489
   parameter set_value = 1;
490
   parameter wrap_value = 0;
491
   parameter level1_value = 15;
492
   reg  [length:1] qi;
493
   wire  [length:1] q_next, q_next_fw, q_next_rew;
494
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
495
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
496
   assign q_next = rew ? q_next_rew : q_next_fw;
497
   always @ (posedge clk or posedge rst)
498
     if (rst)
499
       qi <= {length{1'b0}};
500
     else
501
     if (cke)
502
       qi <= q_next;
503
   assign q = qi;
504
endmodule
505
//////////////////////////////////////////////////////////////////////
506
////                                                              ////
507
////  Versatile counter                                           ////
508
////                                                              ////
509
////  Description                                                 ////
510
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
511
////  counter                                                     ////
512
////                                                              ////
513
////  To Do:                                                      ////
514
////   - add LFSR with more taps                                  ////
515
////                                                              ////
516
////  Author(s):                                                  ////
517
////      - Michael Unneback, unneback@opencores.org              ////
518
////        ORSoC AB                                              ////
519
////                                                              ////
520
//////////////////////////////////////////////////////////////////////
521
////                                                              ////
522
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
523
////                                                              ////
524
//// This source file may be used and distributed without         ////
525
//// restriction provided that this copyright statement is not    ////
526
//// removed from the file and that any derivative work contains  ////
527
//// the original copyright notice and the associated disclaimer. ////
528
////                                                              ////
529
//// This source file is free software; you can redistribute it   ////
530
//// and/or modify it under the terms of the GNU Lesser General   ////
531
//// Public License as published by the Free Software Foundation; ////
532
//// either version 2.1 of the License, or (at your option) any   ////
533
//// later version.                                               ////
534
////                                                              ////
535
//// This source is distributed in the hope that it will be       ////
536
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
537
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
538
//// PURPOSE.  See the GNU Lesser General Public License for more ////
539
//// details.                                                     ////
540
////                                                              ////
541
//// You should have received a copy of the GNU Lesser General    ////
542
//// Public License along with this source; if not, download it   ////
543
//// from http://www.opencores.org/lgpl.shtml                     ////
544
////                                                              ////
545
//////////////////////////////////////////////////////////////////////
546
// binary counter
547
module cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
548
   parameter length = 4;
549
   input cke;
550
   input rew;
551
   output reg level1;
552
   input rst;
553
   input clk;
554
   parameter clear_value = 0;
555
   parameter set_value = 1;
556
   parameter wrap_value = 1;
557
   parameter level1_value = 15;
558
   reg  [length:1] qi;
559
   wire  [length:1] q_next, q_next_fw, q_next_rew;
560
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
561
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
562
   assign q_next = rew ? q_next_rew : q_next_fw;
563
   always @ (posedge clk or posedge rst)
564
     if (rst)
565
       qi <= {length{1'b0}};
566
     else
567
     if (cke)
568
       qi <= q_next;
569
    always @ (posedge clk or posedge rst)
570
    if (rst)
571
        level1 <= 1'b0;
572
    else
573
    if (cke)
574
    if (q_next == level1_value)
575
        level1 <= 1'b1;
576
    else if (qi == level1_value & rew)
577
        level1 <= 1'b0;
578
endmodule
579
//////////////////////////////////////////////////////////////////////
580
////                                                              ////
581
////  Versatile counter                                           ////
582
////                                                              ////
583
////  Description                                                 ////
584
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
585
////  counter                                                     ////
586
////                                                              ////
587
////  To Do:                                                      ////
588
////   - add LFSR with more taps                                  ////
589
////                                                              ////
590
////  Author(s):                                                  ////
591
////      - Michael Unneback, unneback@opencores.org              ////
592
////        ORSoC AB                                              ////
593
////                                                              ////
594
//////////////////////////////////////////////////////////////////////
595
////                                                              ////
596
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
597
////                                                              ////
598
//// This source file may be used and distributed without         ////
599
//// restriction provided that this copyright statement is not    ////
600
//// removed from the file and that any derivative work contains  ////
601
//// the original copyright notice and the associated disclaimer. ////
602
////                                                              ////
603
//// This source file is free software; you can redistribute it   ////
604
//// and/or modify it under the terms of the GNU Lesser General   ////
605
//// Public License as published by the Free Software Foundation; ////
606
//// either version 2.1 of the License, or (at your option) any   ////
607
//// later version.                                               ////
608
////                                                              ////
609
//// This source is distributed in the hope that it will be       ////
610
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
611
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
612
//// PURPOSE.  See the GNU Lesser General Public License for more ////
613
//// details.                                                     ////
614
////                                                              ////
615
//// You should have received a copy of the GNU Lesser General    ////
616
//// Public License along with this source; if not, download it   ////
617
//// from http://www.opencores.org/lgpl.shtml                     ////
618
////                                                              ////
619
//////////////////////////////////////////////////////////////////////
620
// LFSR counter
621
module cnt_lfsr_zq ( zq, rst, clk);
622
   parameter length = 4;
623
   output reg zq;
624
   input rst;
625
   input clk;
626
   parameter clear_value = 0;
627
   parameter set_value = 1;
628
   parameter wrap_value = 8;
629
   parameter level1_value = 15;
630
   reg  [length:1] qi;
631
   reg lfsr_fb;
632
   wire [length:1] q_next;
633
   reg [32:1] polynom;
634
   integer i;
635
   always @ (qi)
636
   begin
637
        case (length)
638
         2: polynom = 32'b11;                               // 0x3
639
         3: polynom = 32'b110;                              // 0x6
640
         4: polynom = 32'b1100;                             // 0xC
641
         5: polynom = 32'b10100;                            // 0x14
642
         6: polynom = 32'b110000;                           // 0x30
643
         7: polynom = 32'b1100000;                          // 0x60
644
         8: polynom = 32'b10111000;                         // 0xb8
645
         9: polynom = 32'b100010000;                        // 0x110
646
        10: polynom = 32'b1001000000;                       // 0x240
647
        11: polynom = 32'b10100000000;                      // 0x500
648
        12: polynom = 32'b100000101001;                     // 0x829
649
        13: polynom = 32'b1000000001100;                    // 0x100C
650
        14: polynom = 32'b10000000010101;                   // 0x2015
651
        15: polynom = 32'b110000000000000;                  // 0x6000
652
        16: polynom = 32'b1101000000001000;                 // 0xD008
653
        17: polynom = 32'b10010000000000000;                // 0x12000
654
        18: polynom = 32'b100000010000000000;               // 0x20400
655
        19: polynom = 32'b1000000000000100011;              // 0x40023
656
        20: polynom = 32'b10000010000000000000;             // 0x82000
657
        21: polynom = 32'b101000000000000000000;            // 0x140000
658
        22: polynom = 32'b1100000000000000000000;           // 0x300000
659
        23: polynom = 32'b10000100000000000000000;          // 0x420000
660
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
661
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
662
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
663
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
664
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
665
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
666
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
667
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
668
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
669
        default: polynom = 32'b0;
670
        endcase
671
        lfsr_fb = qi[length];
672
        for (i=length-1; i>=1; i=i-1) begin
673
            if (polynom[i])
674
                lfsr_fb = lfsr_fb  ~^ qi[i];
675
        end
676
    end
677
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
678
   always @ (posedge clk or posedge rst)
679
     if (rst)
680
       qi <= {length{1'b0}};
681
     else
682
       qi <= q_next;
683
   always @ (posedge clk or posedge rst)
684
     if (rst)
685
       zq <= 1'b1;
686
     else
687
       zq <= q_next == {length{1'b0}};
688
endmodule
689
//////////////////////////////////////////////////////////////////////
690
////                                                              ////
691
////  Versatile counter                                           ////
692
////                                                              ////
693
////  Description                                                 ////
694
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
695
////  counter                                                     ////
696
////                                                              ////
697
////  To Do:                                                      ////
698
////   - add LFSR with more taps                                  ////
699
////                                                              ////
700
////  Author(s):                                                  ////
701
////      - Michael Unneback, unneback@opencores.org              ////
702
////        ORSoC AB                                              ////
703
////                                                              ////
704
//////////////////////////////////////////////////////////////////////
705
////                                                              ////
706
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
707
////                                                              ////
708
//// This source file may be used and distributed without         ////
709
//// restriction provided that this copyright statement is not    ////
710
//// removed from the file and that any derivative work contains  ////
711
//// the original copyright notice and the associated disclaimer. ////
712
////                                                              ////
713
//// This source file is free software; you can redistribute it   ////
714
//// and/or modify it under the terms of the GNU Lesser General   ////
715
//// Public License as published by the Free Software Foundation; ////
716
//// either version 2.1 of the License, or (at your option) any   ////
717
//// later version.                                               ////
718
////                                                              ////
719
//// This source is distributed in the hope that it will be       ////
720
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
721
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
722
//// PURPOSE.  See the GNU Lesser General Public License for more ////
723
//// details.                                                     ////
724
////                                                              ////
725
//// You should have received a copy of the GNU Lesser General    ////
726
//// Public License along with this source; if not, download it   ////
727
//// from http://www.opencores.org/lgpl.shtml                     ////
728
////                                                              ////
729
//////////////////////////////////////////////////////////////////////
730
// LFSR counter
731
module cnt_lfsr_ce_zq ( cke, zq, rst, clk);
732
   parameter length = 4;
733
   input cke;
734
   output reg zq;
735
   input rst;
736
   input clk;
737
   parameter clear_value = 0;
738
   parameter set_value = 1;
739
   parameter wrap_value = 8;
740
   parameter level1_value = 15;
741
   reg  [length:1] qi;
742
   reg lfsr_fb;
743
   wire [length:1] q_next;
744
   reg [32:1] polynom;
745
   integer i;
746
   always @ (qi)
747
   begin
748
        case (length)
749
         2: polynom = 32'b11;                               // 0x3
750
         3: polynom = 32'b110;                              // 0x6
751
         4: polynom = 32'b1100;                             // 0xC
752
         5: polynom = 32'b10100;                            // 0x14
753
         6: polynom = 32'b110000;                           // 0x30
754
         7: polynom = 32'b1100000;                          // 0x60
755
         8: polynom = 32'b10111000;                         // 0xb8
756
         9: polynom = 32'b100010000;                        // 0x110
757
        10: polynom = 32'b1001000000;                       // 0x240
758
        11: polynom = 32'b10100000000;                      // 0x500
759
        12: polynom = 32'b100000101001;                     // 0x829
760
        13: polynom = 32'b1000000001100;                    // 0x100C
761
        14: polynom = 32'b10000000010101;                   // 0x2015
762
        15: polynom = 32'b110000000000000;                  // 0x6000
763
        16: polynom = 32'b1101000000001000;                 // 0xD008
764
        17: polynom = 32'b10010000000000000;                // 0x12000
765
        18: polynom = 32'b100000010000000000;               // 0x20400
766
        19: polynom = 32'b1000000000000100011;              // 0x40023
767
        20: polynom = 32'b10000010000000000000;             // 0x82000
768
        21: polynom = 32'b101000000000000000000;            // 0x140000
769
        22: polynom = 32'b1100000000000000000000;           // 0x300000
770
        23: polynom = 32'b10000100000000000000000;          // 0x420000
771
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
772
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
773
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
774
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
775
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
776
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
777
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
778
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
779
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
780
        default: polynom = 32'b0;
781
        endcase
782
        lfsr_fb = qi[length];
783
        for (i=length-1; i>=1; i=i-1) begin
784
            if (polynom[i])
785
                lfsr_fb = lfsr_fb  ~^ qi[i];
786
        end
787
    end
788
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
789
   always @ (posedge clk or posedge rst)
790
     if (rst)
791
       qi <= {length{1'b0}};
792
     else
793
     if (cke)
794
       qi <= q_next;
795
   always @ (posedge clk or posedge rst)
796
     if (rst)
797
       zq <= 1'b1;
798
     else
799
     if (cke)
800
       zq <= q_next == {length{1'b0}};
801
endmodule
802
//////////////////////////////////////////////////////////////////////
803
////                                                              ////
804
////  Versatile counter                                           ////
805
////                                                              ////
806
////  Description                                                 ////
807
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
808
////  counter                                                     ////
809
////                                                              ////
810
////  To Do:                                                      ////
811
////   - add LFSR with more taps                                  ////
812
////                                                              ////
813
////  Author(s):                                                  ////
814
////      - Michael Unneback, unneback@opencores.org              ////
815
////        ORSoC AB                                              ////
816
////                                                              ////
817
//////////////////////////////////////////////////////////////////////
818
////                                                              ////
819
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
820
////                                                              ////
821
//// This source file may be used and distributed without         ////
822
//// restriction provided that this copyright statement is not    ////
823
//// removed from the file and that any derivative work contains  ////
824
//// the original copyright notice and the associated disclaimer. ////
825
////                                                              ////
826
//// This source file is free software; you can redistribute it   ////
827
//// and/or modify it under the terms of the GNU Lesser General   ////
828
//// Public License as published by the Free Software Foundation; ////
829
//// either version 2.1 of the License, or (at your option) any   ////
830
//// later version.                                               ////
831
////                                                              ////
832
//// This source is distributed in the hope that it will be       ////
833
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
834
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
835
//// PURPOSE.  See the GNU Lesser General Public License for more ////
836
//// details.                                                     ////
837
////                                                              ////
838
//// You should have received a copy of the GNU Lesser General    ////
839
//// Public License along with this source; if not, download it   ////
840
//// from http://www.opencores.org/lgpl.shtml                     ////
841
////                                                              ////
842
//////////////////////////////////////////////////////////////////////
843
// LFSR counter
844
module cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
845
   parameter length = 4;
846
   input cke;
847
   input rew;
848
   output reg level1;
849
   input rst;
850
   input clk;
851
   parameter clear_value = 0;
852
   parameter set_value = 1;
853
   parameter wrap_value = 8;
854
   parameter level1_value = 15;
855
   reg  [length:1] qi;
856
   reg lfsr_fb, lfsr_fb_rew;
857
   wire  [length:1] q_next, q_next_fw, q_next_rew;
858
   reg [32:1] polynom_rew;
859
   integer j;
860
   reg [32:1] polynom;
861
   integer i;
862
   always @ (qi)
863
   begin
864
        case (length)
865
         2: polynom = 32'b11;                               // 0x3
866
         3: polynom = 32'b110;                              // 0x6
867
         4: polynom = 32'b1100;                             // 0xC
868
         5: polynom = 32'b10100;                            // 0x14
869
         6: polynom = 32'b110000;                           // 0x30
870
         7: polynom = 32'b1100000;                          // 0x60
871
         8: polynom = 32'b10111000;                         // 0xb8
872
         9: polynom = 32'b100010000;                        // 0x110
873
        10: polynom = 32'b1001000000;                       // 0x240
874
        11: polynom = 32'b10100000000;                      // 0x500
875
        12: polynom = 32'b100000101001;                     // 0x829
876
        13: polynom = 32'b1000000001100;                    // 0x100C
877
        14: polynom = 32'b10000000010101;                   // 0x2015
878
        15: polynom = 32'b110000000000000;                  // 0x6000
879
        16: polynom = 32'b1101000000001000;                 // 0xD008
880
        17: polynom = 32'b10010000000000000;                // 0x12000
881
        18: polynom = 32'b100000010000000000;               // 0x20400
882
        19: polynom = 32'b1000000000000100011;              // 0x40023
883
        20: polynom = 32'b10000010000000000000;             // 0x82000
884
        21: polynom = 32'b101000000000000000000;            // 0x140000
885
        22: polynom = 32'b1100000000000000000000;           // 0x300000
886
        23: polynom = 32'b10000100000000000000000;          // 0x420000
887
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
888
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
889
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
890
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
891
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
892
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
893
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
894
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
895
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
896
        default: polynom = 32'b0;
897
        endcase
898
        lfsr_fb = qi[length];
899
        for (i=length-1; i>=1; i=i-1) begin
900
            if (polynom[i])
901
                lfsr_fb = lfsr_fb  ~^ qi[i];
902
        end
903
    end
904
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
905
   always @ (qi)
906
   begin
907
        case (length)
908
         2: polynom_rew = 32'b11;
909
         3: polynom_rew = 32'b110;
910
         4: polynom_rew = 32'b1100;
911
         5: polynom_rew = 32'b10100;
912
         6: polynom_rew = 32'b110000;
913
         7: polynom_rew = 32'b1100000;
914
         8: polynom_rew = 32'b10111000;
915
         9: polynom_rew = 32'b100010000;
916
        10: polynom_rew = 32'b1001000000;
917
        11: polynom_rew = 32'b10100000000;
918
        12: polynom_rew = 32'b100000101001;
919
        13: polynom_rew = 32'b1000000001100;
920
        14: polynom_rew = 32'b10000000010101;
921
        15: polynom_rew = 32'b110000000000000;
922
        16: polynom_rew = 32'b1101000000001000;
923
        17: polynom_rew = 32'b10010000000000000;
924
        18: polynom_rew = 32'b100000010000000000;
925
        19: polynom_rew = 32'b1000000000000100011;
926
        20: polynom_rew = 32'b10000010000000000000;
927
        21: polynom_rew = 32'b101000000000000000000;
928
        22: polynom_rew = 32'b1100000000000000000000;
929
        23: polynom_rew = 32'b10000100000000000000000;
930
        24: polynom_rew = 32'b111000010000000000000000;
931
        25: polynom_rew = 32'b1001000000000000000000000;
932
        26: polynom_rew = 32'b10000000000000000000100011;
933
        27: polynom_rew = 32'b100000000000000000000010011;
934
        28: polynom_rew = 32'b1100100000000000000000000000;
935
        29: polynom_rew = 32'b10100000000000000000000000000;
936
        30: polynom_rew = 32'b100000000000000000000000101001;
937
        31: polynom_rew = 32'b1001000000000000000000000000000;
938
        32: polynom_rew = 32'b10000000001000000000000000000011;
939
        default: polynom_rew = 32'b0;
940
        endcase
941
        // rotate left
942
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
943
        lfsr_fb_rew = qi[length];
944
        for (i=length-1; i>=1; i=i-1) begin
945
            if (polynom_rew[i])
946
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
947
        end
948
    end
949
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
950
   assign q_next = rew ? q_next_rew : q_next_fw;
951
   always @ (posedge clk or posedge rst)
952
     if (rst)
953
       qi <= {length{1'b0}};
954
     else
955
     if (cke)
956
       qi <= q_next;
957
    always @ (posedge clk or posedge rst)
958
    if (rst)
959
        level1 <= 1'b0;
960
    else
961
    if (cke)
962
    if (q_next == level1_value)
963
        level1 <= 1'b1;
964
    else if (qi == level1_value & rew)
965
        level1 <= 1'b0;
966
endmodule
967
//////////////////////////////////////////////////////////////////////
968
////                                                              ////
969
////  Versatile counter                                           ////
970
////                                                              ////
971
////  Description                                                 ////
972
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
973
////  counter                                                     ////
974
////                                                              ////
975
////  To Do:                                                      ////
976
////   - add LFSR with more taps                                  ////
977
////                                                              ////
978
////  Author(s):                                                  ////
979
////      - Michael Unneback, unneback@opencores.org              ////
980
////        ORSoC AB                                              ////
981
////                                                              ////
982
//////////////////////////////////////////////////////////////////////
983
////                                                              ////
984
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
985
////                                                              ////
986
//// This source file may be used and distributed without         ////
987
//// restriction provided that this copyright statement is not    ////
988
//// removed from the file and that any derivative work contains  ////
989
//// the original copyright notice and the associated disclaimer. ////
990
////                                                              ////
991
//// This source file is free software; you can redistribute it   ////
992
//// and/or modify it under the terms of the GNU Lesser General   ////
993
//// Public License as published by the Free Software Foundation; ////
994
//// either version 2.1 of the License, or (at your option) any   ////
995
//// later version.                                               ////
996
////                                                              ////
997
//// This source is distributed in the hope that it will be       ////
998
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
999
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1000
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1001
//// details.                                                     ////
1002
////                                                              ////
1003
//// You should have received a copy of the GNU Lesser General    ////
1004
//// Public License along with this source; if not, download it   ////
1005
//// from http://www.opencores.org/lgpl.shtml                     ////
1006
////                                                              ////
1007
//////////////////////////////////////////////////////////////////////
1008
// GRAY counter
1009
module cnt_gray ( q, rst, clk);
1010
   parameter length = 4;
1011
   output reg [length:1] q;
1012
   input rst;
1013
   input clk;
1014
   parameter clear_value = 0;
1015
   parameter set_value = 1;
1016
   parameter wrap_value = 8;
1017
   parameter level1_value = 15;
1018
   reg  [length:1] qi;
1019
   wire [length:1] q_next;
1020
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1021
   always @ (posedge clk or posedge rst)
1022
     if (rst)
1023
       qi <= {length{1'b0}};
1024
     else
1025
       qi <= q_next;
1026
   always @ (posedge clk or posedge rst)
1027
     if (rst)
1028
       q <= {length{1'b0}};
1029
     else
1030
         q <= (q_next>>1) ^ q_next;
1031
endmodule
1032
//////////////////////////////////////////////////////////////////////
1033
////                                                              ////
1034
////  Versatile counter                                           ////
1035
////                                                              ////
1036
////  Description                                                 ////
1037
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1038
////  counter                                                     ////
1039
////                                                              ////
1040
////  To Do:                                                      ////
1041
////   - add LFSR with more taps                                  ////
1042
////                                                              ////
1043
////  Author(s):                                                  ////
1044
////      - Michael Unneback, unneback@opencores.org              ////
1045
////        ORSoC AB                                              ////
1046
////                                                              ////
1047
//////////////////////////////////////////////////////////////////////
1048
////                                                              ////
1049
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1050
////                                                              ////
1051
//// This source file may be used and distributed without         ////
1052
//// restriction provided that this copyright statement is not    ////
1053
//// removed from the file and that any derivative work contains  ////
1054
//// the original copyright notice and the associated disclaimer. ////
1055
////                                                              ////
1056
//// This source file is free software; you can redistribute it   ////
1057
//// and/or modify it under the terms of the GNU Lesser General   ////
1058
//// Public License as published by the Free Software Foundation; ////
1059
//// either version 2.1 of the License, or (at your option) any   ////
1060
//// later version.                                               ////
1061
////                                                              ////
1062
//// This source is distributed in the hope that it will be       ////
1063
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1064
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1065
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1066
//// details.                                                     ////
1067
////                                                              ////
1068
//// You should have received a copy of the GNU Lesser General    ////
1069
//// Public License along with this source; if not, download it   ////
1070
//// from http://www.opencores.org/lgpl.shtml                     ////
1071
////                                                              ////
1072
//////////////////////////////////////////////////////////////////////
1073
// GRAY counter
1074
module cnt_gray_ce ( cke, q, rst, clk);
1075
   parameter length = 4;
1076
   input cke;
1077
   output reg [length:1] q;
1078
   input rst;
1079
   input clk;
1080
   parameter clear_value = 0;
1081
   parameter set_value = 1;
1082
   parameter wrap_value = 8;
1083
   parameter level1_value = 15;
1084
   reg  [length:1] qi;
1085
   wire [length:1] q_next;
1086
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1087
   always @ (posedge clk or posedge rst)
1088
     if (rst)
1089
       qi <= {length{1'b0}};
1090
     else
1091
     if (cke)
1092
       qi <= q_next;
1093
   always @ (posedge clk or posedge rst)
1094
     if (rst)
1095
       q <= {length{1'b0}};
1096
     else
1097
       if (cke)
1098
         q <= (q_next>>1) ^ q_next;
1099
endmodule
1100
//////////////////////////////////////////////////////////////////////
1101
////                                                              ////
1102
////  Versatile counter                                           ////
1103
////                                                              ////
1104
////  Description                                                 ////
1105
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1106
////  counter                                                     ////
1107
////                                                              ////
1108
////  To Do:                                                      ////
1109
////   - add LFSR with more taps                                  ////
1110
////                                                              ////
1111
////  Author(s):                                                  ////
1112
////      - Michael Unneback, unneback@opencores.org              ////
1113
////        ORSoC AB                                              ////
1114
////                                                              ////
1115
//////////////////////////////////////////////////////////////////////
1116
////                                                              ////
1117
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1118
////                                                              ////
1119
//// This source file may be used and distributed without         ////
1120
//// restriction provided that this copyright statement is not    ////
1121
//// removed from the file and that any derivative work contains  ////
1122
//// the original copyright notice and the associated disclaimer. ////
1123
////                                                              ////
1124
//// This source file is free software; you can redistribute it   ////
1125
//// and/or modify it under the terms of the GNU Lesser General   ////
1126
//// Public License as published by the Free Software Foundation; ////
1127
//// either version 2.1 of the License, or (at your option) any   ////
1128
//// later version.                                               ////
1129
////                                                              ////
1130
//// This source is distributed in the hope that it will be       ////
1131
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1132
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1133
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1134
//// details.                                                     ////
1135
////                                                              ////
1136
//// You should have received a copy of the GNU Lesser General    ////
1137
//// Public License along with this source; if not, download it   ////
1138
//// from http://www.opencores.org/lgpl.shtml                     ////
1139
////                                                              ////
1140
//////////////////////////////////////////////////////////////////////
1141
// GRAY counter
1142
module cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
1143
   parameter length = 4;
1144
   input cke;
1145
   output reg [length:1] q;
1146
   output [length:1] q_bin;
1147
   input rst;
1148
   input clk;
1149
   parameter clear_value = 0;
1150
   parameter set_value = 1;
1151
   parameter wrap_value = 8;
1152
   parameter level1_value = 15;
1153
   reg  [length:1] qi;
1154
   wire [length:1] q_next;
1155
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1156
   always @ (posedge clk or posedge rst)
1157
     if (rst)
1158
       qi <= {length{1'b0}};
1159
     else
1160
     if (cke)
1161
       qi <= q_next;
1162
   always @ (posedge clk or posedge rst)
1163
     if (rst)
1164
       q <= {length{1'b0}};
1165
     else
1166
       if (cke)
1167
         q <= (q_next>>1) ^ q_next;
1168
   assign q_bin = qi;
1169
endmodule
1170
//////////////////////////////////////////////////////////////////////
1171
////                                                              ////
1172
////  Versatile library, counters                                 ////
1173
////                                                              ////
1174
////  Description                                                 ////
1175
////  counters                                                    ////
1176
////                                                              ////
1177
////                                                              ////
1178
////  To Do:                                                      ////
1179
////   - add more counters                                        ////
1180
////                                                              ////
1181
////  Author(s):                                                  ////
1182
////      - Michael Unneback, unneback@opencores.org              ////
1183
////        ORSoC AB                                              ////
1184
////                                                              ////
1185
//////////////////////////////////////////////////////////////////////
1186
////                                                              ////
1187
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1188
////                                                              ////
1189
//// This source file may be used and distributed without         ////
1190
//// restriction provided that this copyright statement is not    ////
1191
//// removed from the file and that any derivative work contains  ////
1192
//// the original copyright notice and the associated disclaimer. ////
1193
////                                                              ////
1194
//// This source file is free software; you can redistribute it   ////
1195
//// and/or modify it under the terms of the GNU Lesser General   ////
1196
//// Public License as published by the Free Software Foundation; ////
1197
//// either version 2.1 of the License, or (at your option) any   ////
1198
//// later version.                                               ////
1199
////                                                              ////
1200
//// This source is distributed in the hope that it will be       ////
1201
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1202
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1203
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1204
//// details.                                                     ////
1205
////                                                              ////
1206
//// You should have received a copy of the GNU Lesser General    ////
1207
//// Public License along with this source; if not, download it   ////
1208
//// from http://www.opencores.org/lgpl.shtml                     ////
1209
////                                                              ////
1210
//////////////////////////////////////////////////////////////////////
1211
module cnt_shreg_wrap ( q, rst, clk);
1212
   parameter length = 4;
1213
   output reg [0:length-1] q;
1214
   input rst;
1215
   input clk;
1216
    always @ (posedge clk or posedge rst)
1217
    if (rst)
1218
        q <= {1'b1,{length-1{1'b0}}};
1219
    else
1220
        q <= {q[length-1],q[0:length-2]};
1221
endmodule
1222
module cnt_shreg_ce_wrap ( cke, q, rst, clk);
1223
   parameter length = 4;
1224
   input cke;
1225
   output reg [0:length-1] q;
1226
   input rst;
1227
   input clk;
1228
    always @ (posedge clk or posedge rst)
1229
    if (rst)
1230
        q <= {1'b1,{length-1{1'b0}}};
1231
    else
1232
        if (cke)
1233
            q <= {q[length-1],q[0:length-2]};
1234
endmodule
1235
module cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1236
   parameter length = 4;
1237
   input cke, clear;
1238
   output reg [0:length-1] q;
1239
   input rst;
1240
   input clk;
1241
    always @ (posedge clk or posedge rst)
1242
    if (rst)
1243
        q <= {1'b1,{length-1{1'b0}}};
1244
    else
1245
        if (cke)
1246
            if (clear)
1247
                q <= {1'b1,{length-1{1'b0}}};
1248
            else
1249
                q <= q >> 1;
1250
endmodule
1251
module cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
1252
   parameter length = 4;
1253
   input cke, clear;
1254
   output reg [0:length-1] q;
1255
   input rst;
1256
   input clk;
1257
    always @ (posedge clk or posedge rst)
1258
    if (rst)
1259
        q <= {1'b1,{length-1{1'b0}}};
1260
    else
1261
        if (cke)
1262
            if (clear)
1263
                q <= {1'b1,{length-1{1'b0}}};
1264
            else
1265
            q <= {q[length-1],q[0:length-2]};
1266
endmodule
1267
//////////////////////////////////////////////////////////////////////
1268
////                                                              ////
1269
////  Versatile library, memories                                 ////
1270
////                                                              ////
1271
////  Description                                                 ////
1272
////  memories                                                    ////
1273
////                                                              ////
1274
////                                                              ////
1275
////  To Do:                                                      ////
1276
////   - add more memory types                                    ////
1277
////                                                              ////
1278
////  Author(s):                                                  ////
1279
////      - Michael Unneback, unneback@opencores.org              ////
1280
////        ORSoC AB                                              ////
1281
////                                                              ////
1282
//////////////////////////////////////////////////////////////////////
1283
////                                                              ////
1284
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1285
////                                                              ////
1286
//// This source file may be used and distributed without         ////
1287
//// restriction provided that this copyright statement is not    ////
1288
//// removed from the file and that any derivative work contains  ////
1289
//// the original copyright notice and the associated disclaimer. ////
1290
////                                                              ////
1291
//// This source file is free software; you can redistribute it   ////
1292
//// and/or modify it under the terms of the GNU Lesser General   ////
1293
//// Public License as published by the Free Software Foundation; ////
1294
//// either version 2.1 of the License, or (at your option) any   ////
1295
//// later version.                                               ////
1296
////                                                              ////
1297
//// This source is distributed in the hope that it will be       ////
1298
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1299
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1300
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1301
//// details.                                                     ////
1302
////                                                              ////
1303
//// You should have received a copy of the GNU Lesser General    ////
1304
//// Public License along with this source; if not, download it   ////
1305
//// from http://www.opencores.org/lgpl.shtml                     ////
1306
////                                                              ////
1307
//////////////////////////////////////////////////////////////////////
1308
/// ROM
1309 7 unneback
module vl_rom_init ( adr, q, clk);
1310
   parameter data_width = 32;
1311
   parameter addr_width = 8;
1312
   input [(addr_width-1):0]       adr;
1313
   output reg [(data_width-1):0] q;
1314
   input                         clk;
1315
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
1316
   parameter memory_file = "vl_rom.vmem";
1317
   initial
1318
     begin
1319
        $readmemh(memory_file, rom);
1320
     end
1321
   always @ (posedge clk)
1322
     q <= rom[adr];
1323
endmodule
1324 14 unneback
/*
1325 7 unneback
module vl_rom ( adr, q, clk);
1326 6 unneback
parameter data_width = 32;
1327
parameter addr_width = 4;
1328
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
1329
    {32'h18000000},
1330
    {32'hA8200000},
1331
    {32'hA8200000},
1332
    {32'hA8200000},
1333
    {32'h44003000},
1334
    {32'h15000000},
1335
    {32'h15000000},
1336
    {32'h15000000},
1337
    {32'h15000000},
1338
    {32'h15000000},
1339
    {32'h15000000},
1340
    {32'h15000000},
1341
    {32'h15000000},
1342
    {32'h15000000},
1343
    {32'h15000000},
1344
    {32'h15000000}};
1345 7 unneback
input [addr_width-1:0] adr;
1346 6 unneback
output reg [data_width-1:0] q;
1347
input clk;
1348
always @ (posedge clk)
1349 7 unneback
    q <= data[adr];
1350 6 unneback
endmodule
1351 14 unneback
*/
1352 6 unneback
// Single port RAM
1353
module vl_ram ( d, adr, we, q, clk);
1354
   parameter data_width = 32;
1355
   parameter addr_width = 8;
1356
   input [(data_width-1):0]      d;
1357
   input [(addr_width-1):0]       adr;
1358
   input                         we;
1359 7 unneback
   output reg [(data_width-1):0] q;
1360 6 unneback
   input                         clk;
1361
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1362 7 unneback
   parameter init = 0;
1363
   parameter memory_file = "vl_ram.vmem";
1364
   generate if (init) begin : init_mem
1365
   initial
1366
     begin
1367
        $readmemh(memory_file, ram);
1368
     end
1369
   end
1370
   endgenerate
1371 6 unneback
   always @ (posedge clk)
1372
   begin
1373
   if (we)
1374
     ram[adr] <= d;
1375
   q <= ram[adr];
1376
   end
1377
endmodule
1378 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
1379
   parameter data_width = 32;
1380
   parameter addr_width = 8;
1381
   input [(data_width-1):0]      d;
1382
   input [(addr_width-1):0]       adr;
1383
   input [(addr_width/4)-1:0]    be;
1384
   input                         we;
1385
   output reg [(data_width-1):0] q;
1386
   input                         clk;
1387
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1388
   parameter init = 0;
1389
   parameter memory_file = "vl_ram.vmem";
1390
   generate if (init) begin : init_mem
1391
   initial
1392
     begin
1393
        $readmemh(memory_file, ram);
1394
     end
1395
   end
1396
   endgenerate
1397
   genvar i;
1398
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
1399
      always @ (posedge clk)
1400
      if (we & be[i])
1401
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
1402
   end
1403
   endgenerate
1404
   always @ (posedge clk)
1405
      q <= ram[adr];
1406
endmodule
1407 6 unneback
// Dual port RAM
1408
// ACTEL FPGA should not use logic to handle rw collision
1409 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1410 6 unneback
   parameter data_width = 32;
1411
   parameter addr_width = 8;
1412
   input [(data_width-1):0]      d_a;
1413
   input [(addr_width-1):0]       adr_a;
1414
   input [(addr_width-1):0]       adr_b;
1415
   input                         we_a;
1416
   output [(data_width-1):0]      q_b;
1417
   input                         clk_a, clk_b;
1418
   reg [(addr_width-1):0]         adr_b_reg;
1419
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1420 7 unneback
   parameter init = 0;
1421
   parameter memory_file = "vl_ram.vmem";
1422
   generate if (init) begin : init_mem
1423
   initial
1424
     begin
1425
        $readmemh(memory_file, ram);
1426
     end
1427
   end
1428
   endgenerate
1429 6 unneback
   always @ (posedge clk_a)
1430
   if (we_a)
1431
     ram[adr_a] <= d_a;
1432
   always @ (posedge clk_b)
1433
   adr_b_reg <= adr_b;
1434
   assign q_b = ram[adr_b_reg];
1435
endmodule
1436 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1437 6 unneback
   parameter data_width = 32;
1438
   parameter addr_width = 8;
1439
   input [(data_width-1):0]      d_a;
1440
   input [(addr_width-1):0]       adr_a;
1441
   input [(addr_width-1):0]       adr_b;
1442
   input                         we_a;
1443
   output [(data_width-1):0]      q_b;
1444
   output reg [(data_width-1):0] q_a;
1445
   input                         clk_a, clk_b;
1446
   reg [(data_width-1):0]         q_b;
1447
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1448 7 unneback
   parameter init = 0;
1449
   parameter memory_file = "vl_ram.vmem";
1450
   generate if (init) begin : init_mem
1451
   initial
1452
     begin
1453
        $readmemh(memory_file, ram);
1454
     end
1455
   end
1456
   endgenerate
1457 6 unneback
   always @ (posedge clk_a)
1458
     begin
1459
        q_a <= ram[adr_a];
1460
        if (we_a)
1461
             ram[adr_a] <= d_a;
1462
     end
1463
   always @ (posedge clk_b)
1464
          q_b <= ram[adr_b];
1465
endmodule
1466 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
1467 6 unneback
   parameter data_width = 32;
1468
   parameter addr_width = 8;
1469
   input [(data_width-1):0]      d_a;
1470
   input [(addr_width-1):0]       adr_a;
1471
   input [(addr_width-1):0]       adr_b;
1472
   input                         we_a;
1473
   output [(data_width-1):0]      q_b;
1474
   input [(data_width-1):0]       d_b;
1475
   output reg [(data_width-1):0] q_a;
1476
   input                         we_b;
1477
   input                         clk_a, clk_b;
1478
   reg [(data_width-1):0]         q_b;
1479
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1480 7 unneback
   parameter init = 0;
1481
   parameter memory_file = "vl_ram.vmem";
1482
   generate if (init) begin : init_mem
1483
   initial
1484
     begin
1485
        $readmemh(memory_file, ram);
1486
     end
1487
   end
1488
   endgenerate
1489 6 unneback
   always @ (posedge clk_a)
1490
     begin
1491
        q_a <= ram[adr_a];
1492
        if (we_a)
1493
             ram[adr_a] <= d_a;
1494
     end
1495
   always @ (posedge clk_b)
1496
     begin
1497
        q_b <= ram[adr_b];
1498
        if (we_b)
1499
          ram[adr_b] <= d_b;
1500
     end
1501
endmodule
1502
// Content addresable memory, CAM
1503
// FIFO
1504
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
1505 11 unneback
   parameter addr_width = 4;
1506
   parameter N = addr_width-1;
1507 6 unneback
   parameter Q1 = 2'b00;
1508
   parameter Q2 = 2'b01;
1509
   parameter Q3 = 2'b11;
1510
   parameter Q4 = 2'b10;
1511
   parameter going_empty = 1'b0;
1512
   parameter going_full  = 1'b1;
1513
   input [N:0]  wptr, rptr;
1514 14 unneback
   output       fifo_empty;
1515 6 unneback
   output       fifo_full;
1516
   input        wclk, rclk, rst;
1517
   wire direction;
1518
   reg  direction_set, direction_clr;
1519
   wire async_empty, async_full;
1520
   wire fifo_full2;
1521 14 unneback
   wire fifo_empty2;
1522 6 unneback
   // direction_set
1523
   always @ (wptr[N:N-1] or rptr[N:N-1])
1524
     case ({wptr[N:N-1],rptr[N:N-1]})
1525
       {Q1,Q2} : direction_set <= 1'b1;
1526
       {Q2,Q3} : direction_set <= 1'b1;
1527
       {Q3,Q4} : direction_set <= 1'b1;
1528
       {Q4,Q1} : direction_set <= 1'b1;
1529
       default : direction_set <= 1'b0;
1530
     endcase
1531
   // direction_clear
1532
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
1533
     if (rst)
1534
       direction_clr <= 1'b1;
1535
     else
1536
       case ({wptr[N:N-1],rptr[N:N-1]})
1537
         {Q2,Q1} : direction_clr <= 1'b1;
1538
         {Q3,Q2} : direction_clr <= 1'b1;
1539
         {Q4,Q3} : direction_clr <= 1'b1;
1540
         {Q1,Q4} : direction_clr <= 1'b1;
1541
         default : direction_clr <= 1'b0;
1542
       endcase
1543
    dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
1544
   assign async_empty = (wptr == rptr) && (direction==going_empty);
1545
   assign async_full  = (wptr == rptr) && (direction==going_full);
1546
    dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
1547
    dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
1548
/*
1549
   always @ (posedge wclk or posedge rst or posedge async_full)
1550
     if (rst)
1551
       {fifo_full, fifo_full2} <= 2'b00;
1552
     else if (async_full)
1553
       {fifo_full, fifo_full2} <= 2'b11;
1554
     else
1555
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
1556
*/
1557 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
1558 6 unneback
     if (async_empty)
1559
       {fifo_empty, fifo_empty2} <= 2'b11;
1560
     else
1561 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
1562
    dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
1563
    dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
1564 6 unneback
endmodule // async_comp
1565
module vl_fifo_1r1w_async (
1566
    d, wr, fifo_full, wr_clk, wr_rst,
1567
    q, rd, fifo_empty, rd_clk, rd_rst
1568
    );
1569
parameter data_width = 18;
1570
parameter addr_width = 4;
1571
// write side
1572
input  [data_width-1:0] d;
1573
input                   wr;
1574
output                  fifo_full;
1575
input                   wr_clk;
1576
input                   wr_rst;
1577
// read side
1578
output [data_width-1:0] q;
1579
input                   rd;
1580
output                  fifo_empty;
1581
input                   rd_clk;
1582
input                   rd_rst;
1583
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
1584
vl_fifo_1r1w_async (
1585
    d, wr, fifo_full, wr_clk, wr_rst,
1586
    q, rd, fifo_empty, rd_clk, rd_rst
1587
    );
1588 7 unneback
cnt_gray_ce_bin
1589 6 unneback
    # ( .length(addr_width))
1590
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
1591 7 unneback
cnt_gray_ce_bin
1592 6 unneback
    # (.length(addr_width))
1593
    fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
1594 7 unneback
vl_dpram_1r1w
1595 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
1596
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
1597
vl_fifo_cmp_async
1598
    # (.addr_width(addr_width))
1599
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
1600
endmodule
1601 8 unneback
module vl_fifo_2r2w_async (
1602 6 unneback
    // a side
1603
    a_d, a_wr, a_fifo_full,
1604
    a_q, a_rd, a_fifo_empty,
1605
    a_clk, a_rst,
1606
    // b side
1607
    b_d, b_wr, b_fifo_full,
1608
    b_q, b_rd, b_fifo_empty,
1609
    b_clk, b_rst
1610
    );
1611
parameter data_width = 18;
1612
parameter addr_width = 4;
1613
// a side
1614
input  [data_width-1:0] a_d;
1615
input                   a_wr;
1616
output                  a_fifo_full;
1617
output [data_width-1:0] a_q;
1618
input                   a_rd;
1619
output                  a_fifo_empty;
1620
input                   a_clk;
1621
input                   a_rst;
1622
// b side
1623
input  [data_width-1:0] b_d;
1624
input                   b_wr;
1625
output                  b_fifo_full;
1626
output [data_width-1:0] b_q;
1627
input                   b_rd;
1628
output                  b_fifo_empty;
1629
input                   b_clk;
1630
input                   b_rst;
1631
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1632
vl_fifo_1r1w_async_a (
1633
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
1634
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
1635
    );
1636
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1637
vl_fifo_1r1w_async_b (
1638
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
1639
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
1640
    );
1641
endmodule
1642 8 unneback
module vl_fifo_2r2w_async_simplex (
1643 6 unneback
    // a side
1644
    a_d, a_wr, a_fifo_full,
1645
    a_q, a_rd, a_fifo_empty,
1646
    a_clk, a_rst,
1647
    // b side
1648
    b_d, b_wr, b_fifo_full,
1649
    b_q, b_rd, b_fifo_empty,
1650
    b_clk, b_rst
1651
    );
1652
parameter data_width = 18;
1653
parameter addr_width = 4;
1654
// a side
1655
input  [data_width-1:0] a_d;
1656
input                   a_wr;
1657
output                  a_fifo_full;
1658
output [data_width-1:0] a_q;
1659
input                   a_rd;
1660
output                  a_fifo_empty;
1661
input                   a_clk;
1662
input                   a_rst;
1663
// b side
1664
input  [data_width-1:0] b_d;
1665
input                   b_wr;
1666
output                  b_fifo_full;
1667
output [data_width-1:0] b_q;
1668
input                   b_rd;
1669
output                  b_fifo_empty;
1670
input                   b_clk;
1671
input                   b_rst;
1672
// adr_gen
1673
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
1674
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
1675
// dpram
1676
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1677 7 unneback
cnt_gray_ce_bin
1678 6 unneback
    # ( .length(addr_width))
1679
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
1680 7 unneback
cnt_gray_ce_bin
1681 6 unneback
    # (.length(addr_width))
1682
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
1683 7 unneback
cnt_gray_ce_bin
1684 6 unneback
    # ( .length(addr_width))
1685
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
1686 7 unneback
cnt_gray_ce_bin
1687 6 unneback
    # (.length(addr_width))
1688
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
1689
// mux read or write adr to DPRAM
1690
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
1691
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
1692 11 unneback
vl_dpram_2r2w
1693 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
1694
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1695
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1696 11 unneback
vl_fifo_cmp_async
1697 6 unneback
    # (.addr_width(addr_width))
1698
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
1699 11 unneback
vl_fifo_cmp_async
1700 6 unneback
    # (.addr_width(addr_width))
1701
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
1702
endmodule
1703 12 unneback
//////////////////////////////////////////////////////////////////////
1704
////                                                              ////
1705
////  Versatile library, wishbone stuff                           ////
1706
////                                                              ////
1707
////  Description                                                 ////
1708
////  Wishbone compliant modules                                  ////
1709
////                                                              ////
1710
////                                                              ////
1711
////  To Do:                                                      ////
1712
////   -                                                          ////
1713
////                                                              ////
1714
////  Author(s):                                                  ////
1715
////      - Michael Unneback, unneback@opencores.org              ////
1716
////        ORSoC AB                                              ////
1717
////                                                              ////
1718
//////////////////////////////////////////////////////////////////////
1719
////                                                              ////
1720
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1721
////                                                              ////
1722
//// This source file may be used and distributed without         ////
1723
//// restriction provided that this copyright statement is not    ////
1724
//// removed from the file and that any derivative work contains  ////
1725
//// the original copyright notice and the associated disclaimer. ////
1726
////                                                              ////
1727
//// This source file is free software; you can redistribute it   ////
1728
//// and/or modify it under the terms of the GNU Lesser General   ////
1729
//// Public License as published by the Free Software Foundation; ////
1730
//// either version 2.1 of the License, or (at your option) any   ////
1731
//// later version.                                               ////
1732
////                                                              ////
1733
//// This source is distributed in the hope that it will be       ////
1734
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1735
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1736
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1737
//// details.                                                     ////
1738
////                                                              ////
1739
//// You should have received a copy of the GNU Lesser General    ////
1740
//// Public License along with this source; if not, download it   ////
1741
//// from http://www.opencores.org/lgpl.shtml                     ////
1742
////                                                              ////
1743
//////////////////////////////////////////////////////////////////////
1744
// async wb3 - wb3 bridge
1745
`timescale 1ns/1ns
1746
module wb3wb3_bridge (
1747
        // wishbone slave side
1748
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
1749
        // wishbone master side
1750
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
1751
input [31:0] wbs_dat_i;
1752
input [31:2] wbs_adr_i;
1753
input [3:0]  wbs_sel_i;
1754
input [1:0]  wbs_bte_i;
1755
input [2:0]  wbs_cti_i;
1756
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
1757
output [31:0] wbs_dat_o;
1758 14 unneback
output wbs_ack_o;
1759 12 unneback
input wbs_clk, wbs_rst;
1760
output [31:0] wbm_dat_o;
1761
output reg [31:2] wbm_adr_o;
1762
output [3:0]  wbm_sel_o;
1763
output reg [1:0]  wbm_bte_o;
1764
output reg [2:0]  wbm_cti_o;
1765 14 unneback
output reg wbm_we_o;
1766
output wbm_cyc_o;
1767 12 unneback
output wbm_stb_o;
1768
input [31:0]  wbm_dat_i;
1769
input wbm_ack_i;
1770
input wbm_clk, wbm_rst;
1771
parameter addr_width = 4;
1772
// bte
1773
parameter linear       = 2'b00;
1774
parameter wrap4        = 2'b01;
1775
parameter wrap8        = 2'b10;
1776
parameter wrap16       = 2'b11;
1777
// cti
1778
parameter classic      = 3'b000;
1779
parameter incburst     = 3'b010;
1780
parameter endofburst   = 3'b111;
1781
parameter wbs_adr  = 1'b0;
1782
parameter wbs_data = 1'b1;
1783
parameter wbm_adr0 = 2'b00;
1784
parameter wbm_adr1 = 2'b01;
1785
parameter wbm_data = 2'b10;
1786
reg [1:0] wbs_bte_reg;
1787
reg wbs;
1788
wire wbs_eoc_alert, wbm_eoc_alert;
1789
reg wbs_eoc, wbm_eoc;
1790
reg [1:0] wbm;
1791 14 unneback
wire [1:16] wbs_count, wbm_count;
1792 12 unneback
wire [35:0] a_d, a_q, b_d, b_q;
1793
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
1794
reg a_rd_reg;
1795
wire b_rd_adr, b_rd_data;
1796 14 unneback
wire b_rd_data_reg;
1797
wire [35:0] temp;
1798 12 unneback
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
1799
always @ (posedge wbs_clk or posedge wbs_rst)
1800
if (wbs_rst)
1801
        wbs_eoc <= 1'b0;
1802
else
1803
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
1804
                wbs_eoc <= wbs_bte_i==linear;
1805
        else if (wbs_eoc_alert & (a_rd | a_wr))
1806
                wbs_eoc <= 1'b1;
1807
cnt_shreg_ce_clear # ( .length(16))
1808
    cnt0 (
1809
        .cke(wbs_ack_o),
1810
        .clear(wbs_eoc),
1811
        .q(wbs_count),
1812
        .rst(wbs_rst),
1813
        .clk(wbs_clk));
1814
always @ (posedge wbs_clk or posedge wbs_rst)
1815
if (wbs_rst)
1816
        wbs <= wbs_adr;
1817
else
1818
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
1819
                wbs <= wbs_data;
1820
        else if (wbs_eoc & wbs_ack_o)
1821
                wbs <= wbs_adr;
1822
// wbs FIFO
1823
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
1824
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
1825
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
1826
              1'b0;
1827
assign a_rd = !a_fifo_empty;
1828
always @ (posedge wbs_clk or posedge wbs_rst)
1829
if (wbs_rst)
1830
        a_rd_reg <= 1'b0;
1831
else
1832
        a_rd_reg <= a_rd;
1833
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
1834
assign wbs_dat_o = a_q[35:4];
1835
always @ (posedge wbs_clk or posedge wbs_rst)
1836
if (wbs_rst)
1837 13 unneback
        wbs_bte_reg <= 2'b00;
1838 12 unneback
else
1839 13 unneback
        wbs_bte_reg <= wbs_bte_i;
1840 12 unneback
// wbm FIFO
1841
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
1842
always @ (posedge wbm_clk or posedge wbm_rst)
1843
if (wbm_rst)
1844
        wbm_eoc <= 1'b0;
1845
else
1846
        if (wbm==wbm_adr0 & !b_fifo_empty)
1847
                wbm_eoc <= b_q[4:3] == linear;
1848
        else if (wbm_eoc_alert & wbm_ack_i)
1849
                wbm_eoc <= 1'b1;
1850
always @ (posedge wbm_clk or posedge wbm_rst)
1851
if (wbm_rst)
1852
        wbm <= wbm_adr0;
1853
else
1854
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
1855
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
1856
        (wbm==wbm_adr1 & !wbm_we_o) |
1857
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
1858
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
1859
assign b_d = {wbm_dat_i,4'b1111};
1860
assign b_wr = !wbm_we_o & wbm_ack_i;
1861
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
1862
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
1863
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
1864
                   1'b0;
1865
assign b_rd = b_rd_adr | b_rd_data;
1866
dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
1867
dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
1868
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
1869
cnt_shreg_ce_clear # ( .length(16))
1870
    cnt1 (
1871
        .cke(wbm_ack_i),
1872
        .clear(wbm_eoc),
1873
        .q(wbm_count),
1874
        .rst(wbm_rst),
1875
        .clk(wbm_clk));
1876
assign wbm_cyc_o = wbm==wbm_data;
1877
assign wbm_stb_o = (wbm==wbm_data & wbm_we_o) ? !b_fifo_empty :
1878
                   (wbm==wbm_data) ? 1'b1 :
1879
                   1'b0;
1880
always @ (posedge wbm_clk or posedge wbm_rst)
1881
if (wbm_rst)
1882
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
1883
else begin
1884
        if (wbm==wbm_adr0 & !b_fifo_empty)
1885
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
1886
        else if (wbm_eoc_alert & wbm_ack_i)
1887
                wbm_cti_o <= endofburst;
1888
end
1889
//async_fifo_dw_simplex_top
1890
vl_fifo_2r2w_async_simplex
1891
# ( .data_width(36), .addr_width(addr_width))
1892
fifo (
1893
    // a side
1894
    .a_d(a_d),
1895
    .a_wr(a_wr),
1896
    .a_fifo_full(a_fifo_full),
1897
    .a_q(a_q),
1898
    .a_rd(a_rd),
1899
    .a_fifo_empty(a_fifo_empty),
1900
    .a_clk(wbs_clk),
1901
    .a_rst(wbs_rst),
1902
    // b side
1903
    .b_d(b_d),
1904
    .b_wr(b_wr),
1905
    .b_fifo_full(b_fifo_full),
1906
    .b_q(b_q),
1907
    .b_rd(b_rd),
1908
    .b_fifo_empty(b_fifo_empty),
1909
    .b_clk(wbm_clk),
1910
    .b_rst(wbm_rst)
1911
    );
1912
endmodule

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