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1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  Versatile library, clock and reset                          ////
4
////                                                              ////
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////  Description                                                 ////
6
////  Logic related to clock and reset                            ////
7
////                                                              ////
8
////                                                              ////
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////  To Do:                                                      ////
10
////   - add more different registers                             ////
11
////                                                              ////
12
////  Author(s):                                                  ////
13
////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
// Global buffer
43
// usage:
44
// use to enable global buffers for high fan out signals such as clock and reset
45
`timescale 1 ns/100 ps
46
// Version: 8.4 8.4.0.33
47
module gbuf(GL,CLK);
48
output GL;
49
input  CLK;
50
    wire GND;
51
    GND GND_1_net(.Y(GND));
52
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
53
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
54
endmodule
55
`timescale 1 ns/1 ns
56
module vl_gbuf ( i, o);
57
input i;
58
output o;
59
`ifdef SIM_GBUF
60
assign o=i;
61
`else
62
gbuf gbuf_i0 ( .CLK(i), .GL(o));
63
`endif
64
endmodule
65
 //ACTEL
66
// sync reset
67 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
68 6 unneback
// output active high global reset sync with two DFFs 
69
`timescale 1 ns/100 ps
70
module vl_sync_rst ( rst_n_i, rst_o, clk);
71
input rst_n_i, clk;
72
output rst_o;
73 18 unneback
reg [1:0] tmp;
74 6 unneback
always @ (posedge clk or negedge rst_n_i)
75
if (!rst_n_i)
76 17 unneback
        tmp <= 2'b11;
77 6 unneback
else
78 17 unneback
        tmp <= {1'b0,tmp[0]};
79
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
80 6 unneback
endmodule
81
// vl_pll
82 17 unneback
`timescale 1 ps/1 ps
83 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
84
parameter index = 0;
85
parameter number_of_clk = 1;
86 17 unneback
parameter period_time_0 = 20000;
87
parameter period_time_1 = 20000;
88
parameter period_time_2 = 20000;
89
parameter lock_delay = 2000000;
90 6 unneback
input clk_i, rst_n_i;
91
output lock;
92
output reg [0:number_of_clk-1] clk_o;
93
output [0:number_of_clk-1] rst_o;
94
`ifdef SIM_PLL
95
always
96
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
97
generate if (number_of_clk > 1)
98
always
99
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
100
endgenerate
101
generate if (number_of_clk > 2)
102
always
103
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
104
endgenerate
105
genvar i;
106
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
107
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
108
end
109
endgenerate
110
assign #lock_delay lock = rst_n_i;
111
endmodule
112
`else
113
generate if (number_of_clk==1 & index==0) begin
114
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
115
end
116
endgenerate // index==0
117
generate if (number_of_clk==1 & index==1) begin
118
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
119
end
120
endgenerate // index==1
121
generate if (number_of_clk==1 & index==2) begin
122
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
123
end
124
endgenerate // index==2
125
generate if (number_of_clk==1 & index==3) begin
126
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
127
end
128
endgenerate // index==0
129
generate if (number_of_clk==2 & index==0) begin
130
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
131
end
132
endgenerate // index==0
133
generate if (number_of_clk==2 & index==1) begin
134
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
135
end
136
endgenerate // index==1
137
generate if (number_of_clk==2 & index==2) begin
138
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
139
end
140
endgenerate // index==2
141
generate if (number_of_clk==2 & index==3) begin
142
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
143
end
144
endgenerate // index==0
145
generate if (number_of_clk==3 & index==0) begin
146
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
147
end
148
endgenerate // index==0
149
generate if (number_of_clk==3 & index==1) begin
150
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
151
end
152
endgenerate // index==1
153
generate if (number_of_clk==3 & index==2) begin
154
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
155
end
156
endgenerate // index==2
157
generate if (number_of_clk==3 & index==3) begin
158
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
159
end
160
endgenerate // index==0
161
genvar i;
162
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
163
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
164
end
165
endgenerate
166
endmodule
167
`endif
168
 //actel
169
//////////////////////////////////////////////////////////////////////
170
////                                                              ////
171
////  Versatile library, registers                                ////
172
////                                                              ////
173
////  Description                                                 ////
174
////  Different type of registers                                 ////
175
////                                                              ////
176
////                                                              ////
177
////  To Do:                                                      ////
178
////   - add more different registers                             ////
179
////                                                              ////
180
////  Author(s):                                                  ////
181
////      - Michael Unneback, unneback@opencores.org              ////
182
////        ORSoC AB                                              ////
183
////                                                              ////
184
//////////////////////////////////////////////////////////////////////
185
////                                                              ////
186
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
187
////                                                              ////
188
//// This source file may be used and distributed without         ////
189
//// restriction provided that this copyright statement is not    ////
190
//// removed from the file and that any derivative work contains  ////
191
//// the original copyright notice and the associated disclaimer. ////
192
////                                                              ////
193
//// This source file is free software; you can redistribute it   ////
194
//// and/or modify it under the terms of the GNU Lesser General   ////
195
//// Public License as published by the Free Software Foundation; ////
196
//// either version 2.1 of the License, or (at your option) any   ////
197
//// later version.                                               ////
198
////                                                              ////
199
//// This source is distributed in the hope that it will be       ////
200
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
201
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
202
//// PURPOSE.  See the GNU Lesser General Public License for more ////
203
//// details.                                                     ////
204
////                                                              ////
205
//// You should have received a copy of the GNU Lesser General    ////
206
//// Public License along with this source; if not, download it   ////
207
//// from http://www.opencores.org/lgpl.shtml                     ////
208
////                                                              ////
209
//////////////////////////////////////////////////////////////////////
210 18 unneback
module vl_dff ( d, q, clk, rst);
211 6 unneback
        parameter width = 1;
212
        parameter reset_value = 0;
213
        input [width-1:0] d;
214
        input clk, rst;
215
        output reg [width-1:0] q;
216
        always @ (posedge clk or posedge rst)
217
        if (rst)
218
                q <= reset_value;
219
        else
220
                q <= d;
221
endmodule
222 18 unneback
module vl_dff_array ( d, q, clk, rst);
223 6 unneback
        parameter width = 1;
224
        parameter depth = 2;
225
        parameter reset_value = 1'b0;
226
        input [width-1:0] d;
227
        input clk, rst;
228
        output [width-1:0] q;
229
        reg  [0:depth-1] q_tmp [width-1:0];
230
        integer i;
231
        always @ (posedge clk or posedge rst)
232
        if (rst) begin
233
            for (i=0;i<depth;i=i+1)
234
                q_tmp[i] <= {width{reset_value}};
235
        end else begin
236
            q_tmp[0] <= d;
237
            for (i=1;i<depth;i=i+1)
238
                q_tmp[i] <= q_tmp[i-1];
239
        end
240
    assign q = q_tmp[depth-1];
241
endmodule
242 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
243 6 unneback
        parameter width = 1;
244
        parameter reset_value = 0;
245
        input [width-1:0] d;
246
        input ce, clk, rst;
247
        output reg [width-1:0] q;
248
        always @ (posedge clk or posedge rst)
249
        if (rst)
250
                q <= reset_value;
251
        else
252
                if (ce)
253
                        q <= d;
254
endmodule
255 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
256 8 unneback
        parameter width = 1;
257
        parameter reset_value = 0;
258
        input [width-1:0] d;
259 10 unneback
        input ce, clear, clk, rst;
260 8 unneback
        output reg [width-1:0] q;
261
        always @ (posedge clk or posedge rst)
262
        if (rst)
263
            q <= reset_value;
264
        else
265
            if (ce)
266
                if (clear)
267
                    q <= {width{1'b0}};
268
                else
269
                    q <= d;
270
endmodule
271 18 unneback
module vl_dff_sr ( aclr, aset, clock, data, q);
272 6 unneback
    input         aclr;
273
    input         aset;
274
    input         clock;
275
    input         data;
276
    output reg    q;
277
   always @ (posedge clock or posedge aclr or posedge aset)
278
     if (aclr)
279
       q <= 1'b0;
280
     else if (aset)
281
       q <= 1'b1;
282
     else
283
       q <= data;
284
endmodule
285
// LATCH
286
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
287
module latch ( d, le, q, clk);
288
input d, le;
289
output q;
290
input clk;/*
291
   always @ (posedge direction_set or posedge direction_clr)
292
     if (direction_clr)
293
       direction <= going_empty;
294
     else
295
       direction <= going_full;*/
296
endmodule
297 18 unneback
module vl_shreg ( d, q, clk, rst);
298 17 unneback
parameter depth = 10;
299
input d;
300
output q;
301
input clk, rst;
302
reg [1:depth] dffs;
303
always @ (posedge clk or posedge rst)
304
if (rst)
305
    dffs <= {depth{1'b0}};
306
else
307
    dffs <= {d,dffs[1:depth-1]};
308
assign q = dffs[depth];
309
endmodule
310 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
311 17 unneback
parameter depth = 10;
312
input d, ce;
313
output q;
314
input clk, rst;
315
reg [1:depth] dffs;
316
always @ (posedge clk or posedge rst)
317
if (rst)
318
    dffs <= {depth{1'b0}};
319
else
320
    if (ce)
321
        dffs <= {d,dffs[1:depth-1]};
322
assign q = dffs[depth];
323
endmodule
324 18 unneback
module vl_delay ( d, q, clk, rst);
325 15 unneback
parameter depth = 10;
326
input d;
327
output q;
328
input clk, rst;
329
reg [1:depth] dffs;
330
always @ (posedge clk or posedge rst)
331
if (rst)
332
    dffs <= {depth{1'b0}};
333
else
334
    dffs <= {d,dffs[1:depth-1]};
335
assign q = dffs[depth];
336
endmodule
337 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
338 17 unneback
parameter depth = 10;
339
input d;
340
output q, emptyflag;
341
input clk, rst;
342
reg [1:depth] dffs;
343
always @ (posedge clk or posedge rst)
344
if (rst)
345
    dffs <= {depth{1'b0}};
346
else
347
    dffs <= {d,dffs[1:depth-1]};
348
assign q = dffs[depth];
349
assign emptyflag = !(|dffs);
350
endmodule
351 6 unneback
//////////////////////////////////////////////////////////////////////
352
////                                                              ////
353 18 unneback
////  Logic functions                                             ////
354
////                                                              ////
355
////  Description                                                 ////
356
////  Logic functions such as multiplexers                        ////
357
////                                                              ////
358
////                                                              ////
359
////  To Do:                                                      ////
360
////   -                                                          ////
361
////                                                              ////
362
////  Author(s):                                                  ////
363
////      - Michael Unneback, unneback@opencores.org              ////
364
////        ORSoC AB                                              ////
365
////                                                              ////
366
//////////////////////////////////////////////////////////////////////
367
////                                                              ////
368
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
369
////                                                              ////
370
//// This source file may be used and distributed without         ////
371
//// restriction provided that this copyright statement is not    ////
372
//// removed from the file and that any derivative work contains  ////
373
//// the original copyright notice and the associated disclaimer. ////
374
////                                                              ////
375
//// This source file is free software; you can redistribute it   ////
376
//// and/or modify it under the terms of the GNU Lesser General   ////
377
//// Public License as published by the Free Software Foundation; ////
378
//// either version 2.1 of the License, or (at your option) any   ////
379
//// later version.                                               ////
380
////                                                              ////
381
//// This source is distributed in the hope that it will be       ////
382
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
383
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
384
//// PURPOSE.  See the GNU Lesser General Public License for more ////
385
//// details.                                                     ////
386
////                                                              ////
387
//// You should have received a copy of the GNU Lesser General    ////
388
//// Public License along with this source; if not, download it   ////
389
//// from http://www.opencores.org/lgpl.shtml                     ////
390
////                                                              ////
391
//////////////////////////////////////////////////////////////////////
392
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
393
parameter width = 32;
394
parameter nr_of_ports = 4;
395
input [width-1:0] a3, a2, a1, a0;
396
input [nr_of_ports-1:0] sel;
397 22 unneback
output [width-1:0] dout;
398 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
399 18 unneback
integer i;
400
// and
401
assign tmp[0] = {width{sel[0]}} & a0;
402
assign tmp[1] = {width{sel[1]}} & a1;
403
assign tmp[2] = {width{sel[2]}} & a2;
404
assign tmp[3] = {width{sel[3]}} & a3;
405
// or
406
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
407
endmodule
408
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
409
parameter width = 32;
410
parameter nr_of_ports = 5;
411
input [width-1:0] a4, a3, a2, a1, a0;
412
input [nr_of_ports-1:0] sel;
413 22 unneback
output [width-1:0] dout;
414 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
415 18 unneback
integer i;
416
// and
417
assign tmp[0] = {width{sel[0]}} & a0;
418
assign tmp[1] = {width{sel[1]}} & a1;
419
assign tmp[2] = {width{sel[2]}} & a2;
420
assign tmp[3] = {width{sel[3]}} & a3;
421
assign tmp[4] = {width{sel[4]}} & a4;
422
// or
423
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
424
endmodule
425
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
426
parameter width = 32;
427
parameter nr_of_ports = 6;
428
input [width-1:0] a5, a4, a3, a2, a1, a0;
429
input [nr_of_ports-1:0] sel;
430 22 unneback
output [width-1:0] dout;
431 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
432 18 unneback
integer i;
433
// and
434
assign tmp[0] = {width{sel[0]}} & a0;
435
assign tmp[1] = {width{sel[1]}} & a1;
436
assign tmp[2] = {width{sel[2]}} & a2;
437
assign tmp[3] = {width{sel[3]}} & a3;
438
assign tmp[4] = {width{sel[4]}} & a4;
439
assign tmp[5] = {width{sel[5]}} & a5;
440
// or
441
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
442
endmodule
443
//////////////////////////////////////////////////////////////////////
444
////                                                              ////
445 6 unneback
////  Versatile counter                                           ////
446
////                                                              ////
447
////  Description                                                 ////
448
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
449
////  counter                                                     ////
450
////                                                              ////
451
////  To Do:                                                      ////
452
////   - add LFSR with more taps                                  ////
453
////                                                              ////
454
////  Author(s):                                                  ////
455
////      - Michael Unneback, unneback@opencores.org              ////
456
////        ORSoC AB                                              ////
457
////                                                              ////
458
//////////////////////////////////////////////////////////////////////
459
////                                                              ////
460
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
461
////                                                              ////
462
//// This source file may be used and distributed without         ////
463
//// restriction provided that this copyright statement is not    ////
464
//// removed from the file and that any derivative work contains  ////
465
//// the original copyright notice and the associated disclaimer. ////
466
////                                                              ////
467
//// This source file is free software; you can redistribute it   ////
468
//// and/or modify it under the terms of the GNU Lesser General   ////
469
//// Public License as published by the Free Software Foundation; ////
470
//// either version 2.1 of the License, or (at your option) any   ////
471
//// later version.                                               ////
472
////                                                              ////
473
//// This source is distributed in the hope that it will be       ////
474
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
475
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
476
//// PURPOSE.  See the GNU Lesser General Public License for more ////
477
//// details.                                                     ////
478
////                                                              ////
479
//// You should have received a copy of the GNU Lesser General    ////
480
//// Public License along with this source; if not, download it   ////
481
//// from http://www.opencores.org/lgpl.shtml                     ////
482
////                                                              ////
483
//////////////////////////////////////////////////////////////////////
484
// binary counter
485 22 unneback
module vl_cnt_bin ( q, rst, clk);
486
   parameter length = 4;
487
   output [length:1] q;
488
   input rst;
489
   input clk;
490
   parameter clear_value = 0;
491
   parameter set_value = 1;
492
   parameter wrap_value = 0;
493
   parameter level1_value = 15;
494
   reg  [length:1] qi;
495
   wire [length:1] q_next;
496
   assign q_next = qi + {{length-1{1'b0}},1'b1};
497
   always @ (posedge clk or posedge rst)
498
     if (rst)
499
       qi <= {length{1'b0}};
500
     else
501
       qi <= q_next;
502
   assign q = qi;
503
endmodule
504
//////////////////////////////////////////////////////////////////////
505
////                                                              ////
506
////  Versatile counter                                           ////
507
////                                                              ////
508
////  Description                                                 ////
509
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
510
////  counter                                                     ////
511
////                                                              ////
512
////  To Do:                                                      ////
513
////   - add LFSR with more taps                                  ////
514
////                                                              ////
515
////  Author(s):                                                  ////
516
////      - Michael Unneback, unneback@opencores.org              ////
517
////        ORSoC AB                                              ////
518
////                                                              ////
519
//////////////////////////////////////////////////////////////////////
520
////                                                              ////
521
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
522
////                                                              ////
523
//// This source file may be used and distributed without         ////
524
//// restriction provided that this copyright statement is not    ////
525
//// removed from the file and that any derivative work contains  ////
526
//// the original copyright notice and the associated disclaimer. ////
527
////                                                              ////
528
//// This source file is free software; you can redistribute it   ////
529
//// and/or modify it under the terms of the GNU Lesser General   ////
530
//// Public License as published by the Free Software Foundation; ////
531
//// either version 2.1 of the License, or (at your option) any   ////
532
//// later version.                                               ////
533
////                                                              ////
534
//// This source is distributed in the hope that it will be       ////
535
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
536
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
537
//// PURPOSE.  See the GNU Lesser General Public License for more ////
538
//// details.                                                     ////
539
////                                                              ////
540
//// You should have received a copy of the GNU Lesser General    ////
541
//// Public License along with this source; if not, download it   ////
542
//// from http://www.opencores.org/lgpl.shtml                     ////
543
////                                                              ////
544
//////////////////////////////////////////////////////////////////////
545
// binary counter
546
module vl_cnt_bin_clear ( clear, q, rst, clk);
547
   parameter length = 4;
548
   input clear;
549
   output [length:1] q;
550
   input rst;
551
   input clk;
552
   parameter clear_value = 0;
553
   parameter set_value = 1;
554
   parameter wrap_value = 0;
555
   parameter level1_value = 15;
556
   reg  [length:1] qi;
557
   wire [length:1] q_next;
558
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
559
   always @ (posedge clk or posedge rst)
560
     if (rst)
561
       qi <= {length{1'b0}};
562
     else
563
       qi <= q_next;
564
   assign q = qi;
565
endmodule
566
//////////////////////////////////////////////////////////////////////
567
////                                                              ////
568
////  Versatile counter                                           ////
569
////                                                              ////
570
////  Description                                                 ////
571
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
572
////  counter                                                     ////
573
////                                                              ////
574
////  To Do:                                                      ////
575
////   - add LFSR with more taps                                  ////
576
////                                                              ////
577
////  Author(s):                                                  ////
578
////      - Michael Unneback, unneback@opencores.org              ////
579
////        ORSoC AB                                              ////
580
////                                                              ////
581
//////////////////////////////////////////////////////////////////////
582
////                                                              ////
583
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
584
////                                                              ////
585
//// This source file may be used and distributed without         ////
586
//// restriction provided that this copyright statement is not    ////
587
//// removed from the file and that any derivative work contains  ////
588
//// the original copyright notice and the associated disclaimer. ////
589
////                                                              ////
590
//// This source file is free software; you can redistribute it   ////
591
//// and/or modify it under the terms of the GNU Lesser General   ////
592
//// Public License as published by the Free Software Foundation; ////
593
//// either version 2.1 of the License, or (at your option) any   ////
594
//// later version.                                               ////
595
////                                                              ////
596
//// This source is distributed in the hope that it will be       ////
597
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
598
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
599
//// PURPOSE.  See the GNU Lesser General Public License for more ////
600
//// details.                                                     ////
601
////                                                              ////
602
//// You should have received a copy of the GNU Lesser General    ////
603
//// Public License along with this source; if not, download it   ////
604
//// from http://www.opencores.org/lgpl.shtml                     ////
605
////                                                              ////
606
//////////////////////////////////////////////////////////////////////
607
// binary counter
608 18 unneback
module vl_cnt_bin_ce ( cke, q, rst, clk);
609 6 unneback
   parameter length = 4;
610
   input cke;
611
   output [length:1] q;
612
   input rst;
613
   input clk;
614
   parameter clear_value = 0;
615
   parameter set_value = 1;
616
   parameter wrap_value = 0;
617
   parameter level1_value = 15;
618
   reg  [length:1] qi;
619
   wire [length:1] q_next;
620
   assign q_next = qi + {{length-1{1'b0}},1'b1};
621
   always @ (posedge clk or posedge rst)
622
     if (rst)
623
       qi <= {length{1'b0}};
624
     else
625
     if (cke)
626
       qi <= q_next;
627
   assign q = qi;
628
endmodule
629
//////////////////////////////////////////////////////////////////////
630
////                                                              ////
631
////  Versatile counter                                           ////
632
////                                                              ////
633
////  Description                                                 ////
634
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
635
////  counter                                                     ////
636
////                                                              ////
637
////  To Do:                                                      ////
638
////   - add LFSR with more taps                                  ////
639
////                                                              ////
640
////  Author(s):                                                  ////
641
////      - Michael Unneback, unneback@opencores.org              ////
642
////        ORSoC AB                                              ////
643
////                                                              ////
644
//////////////////////////////////////////////////////////////////////
645
////                                                              ////
646
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
647
////                                                              ////
648
//// This source file may be used and distributed without         ////
649
//// restriction provided that this copyright statement is not    ////
650
//// removed from the file and that any derivative work contains  ////
651
//// the original copyright notice and the associated disclaimer. ////
652
////                                                              ////
653
//// This source file is free software; you can redistribute it   ////
654
//// and/or modify it under the terms of the GNU Lesser General   ////
655
//// Public License as published by the Free Software Foundation; ////
656
//// either version 2.1 of the License, or (at your option) any   ////
657
//// later version.                                               ////
658
////                                                              ////
659
//// This source is distributed in the hope that it will be       ////
660
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
661
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
662
//// PURPOSE.  See the GNU Lesser General Public License for more ////
663
//// details.                                                     ////
664
////                                                              ////
665
//// You should have received a copy of the GNU Lesser General    ////
666
//// Public License along with this source; if not, download it   ////
667
//// from http://www.opencores.org/lgpl.shtml                     ////
668
////                                                              ////
669
//////////////////////////////////////////////////////////////////////
670
// binary counter
671 18 unneback
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
672 6 unneback
   parameter length = 4;
673
   input clear;
674
   input cke;
675
   output [length:1] q;
676
   input rst;
677
   input clk;
678
   parameter clear_value = 0;
679
   parameter set_value = 1;
680
   parameter wrap_value = 0;
681
   parameter level1_value = 15;
682
   reg  [length:1] qi;
683
   wire [length:1] q_next;
684
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
685
   always @ (posedge clk or posedge rst)
686
     if (rst)
687
       qi <= {length{1'b0}};
688
     else
689
     if (cke)
690
       qi <= q_next;
691
   assign q = qi;
692
endmodule
693
//////////////////////////////////////////////////////////////////////
694
////                                                              ////
695
////  Versatile counter                                           ////
696
////                                                              ////
697
////  Description                                                 ////
698
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
699
////  counter                                                     ////
700
////                                                              ////
701
////  To Do:                                                      ////
702
////   - add LFSR with more taps                                  ////
703
////                                                              ////
704
////  Author(s):                                                  ////
705
////      - Michael Unneback, unneback@opencores.org              ////
706
////        ORSoC AB                                              ////
707
////                                                              ////
708
//////////////////////////////////////////////////////////////////////
709
////                                                              ////
710
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
711
////                                                              ////
712
//// This source file may be used and distributed without         ////
713
//// restriction provided that this copyright statement is not    ////
714
//// removed from the file and that any derivative work contains  ////
715
//// the original copyright notice and the associated disclaimer. ////
716
////                                                              ////
717
//// This source file is free software; you can redistribute it   ////
718
//// and/or modify it under the terms of the GNU Lesser General   ////
719
//// Public License as published by the Free Software Foundation; ////
720
//// either version 2.1 of the License, or (at your option) any   ////
721
//// later version.                                               ////
722
////                                                              ////
723
//// This source is distributed in the hope that it will be       ////
724
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
725
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
726
//// PURPOSE.  See the GNU Lesser General Public License for more ////
727
//// details.                                                     ////
728
////                                                              ////
729
//// You should have received a copy of the GNU Lesser General    ////
730
//// Public License along with this source; if not, download it   ////
731
//// from http://www.opencores.org/lgpl.shtml                     ////
732
////                                                              ////
733
//////////////////////////////////////////////////////////////////////
734
// binary counter
735 18 unneback
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
736 6 unneback
   parameter length = 4;
737
   input clear;
738
   input set;
739
   input cke;
740
   input rew;
741
   output [length:1] q;
742
   input rst;
743
   input clk;
744
   parameter clear_value = 0;
745
   parameter set_value = 1;
746
   parameter wrap_value = 0;
747
   parameter level1_value = 15;
748
   reg  [length:1] qi;
749
   wire  [length:1] q_next, q_next_fw, q_next_rew;
750
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
751
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
752
   assign q_next = rew ? q_next_rew : q_next_fw;
753
   always @ (posedge clk or posedge rst)
754
     if (rst)
755
       qi <= {length{1'b0}};
756
     else
757
     if (cke)
758
       qi <= q_next;
759
   assign q = qi;
760
endmodule
761
//////////////////////////////////////////////////////////////////////
762
////                                                              ////
763
////  Versatile counter                                           ////
764
////                                                              ////
765
////  Description                                                 ////
766
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
767
////  counter                                                     ////
768
////                                                              ////
769
////  To Do:                                                      ////
770
////   - add LFSR with more taps                                  ////
771
////                                                              ////
772
////  Author(s):                                                  ////
773
////      - Michael Unneback, unneback@opencores.org              ////
774
////        ORSoC AB                                              ////
775
////                                                              ////
776
//////////////////////////////////////////////////////////////////////
777
////                                                              ////
778
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
779
////                                                              ////
780
//// This source file may be used and distributed without         ////
781
//// restriction provided that this copyright statement is not    ////
782
//// removed from the file and that any derivative work contains  ////
783
//// the original copyright notice and the associated disclaimer. ////
784
////                                                              ////
785
//// This source file is free software; you can redistribute it   ////
786
//// and/or modify it under the terms of the GNU Lesser General   ////
787
//// Public License as published by the Free Software Foundation; ////
788
//// either version 2.1 of the License, or (at your option) any   ////
789
//// later version.                                               ////
790
////                                                              ////
791
//// This source is distributed in the hope that it will be       ////
792
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
793
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
794
//// PURPOSE.  See the GNU Lesser General Public License for more ////
795
//// details.                                                     ////
796
////                                                              ////
797
//// You should have received a copy of the GNU Lesser General    ////
798
//// Public License along with this source; if not, download it   ////
799
//// from http://www.opencores.org/lgpl.shtml                     ////
800
////                                                              ////
801
//////////////////////////////////////////////////////////////////////
802
// binary counter
803 18 unneback
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
804 6 unneback
   parameter length = 4;
805
   input cke;
806
   input rew;
807
   output reg level1;
808
   input rst;
809
   input clk;
810
   parameter clear_value = 0;
811
   parameter set_value = 1;
812
   parameter wrap_value = 1;
813
   parameter level1_value = 15;
814
   reg  [length:1] qi;
815
   wire  [length:1] q_next, q_next_fw, q_next_rew;
816
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
817
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
818
   assign q_next = rew ? q_next_rew : q_next_fw;
819
   always @ (posedge clk or posedge rst)
820
     if (rst)
821
       qi <= {length{1'b0}};
822
     else
823
     if (cke)
824
       qi <= q_next;
825
    always @ (posedge clk or posedge rst)
826
    if (rst)
827
        level1 <= 1'b0;
828
    else
829
    if (cke)
830
    if (q_next == level1_value)
831
        level1 <= 1'b1;
832
    else if (qi == level1_value & rew)
833
        level1 <= 1'b0;
834
endmodule
835
//////////////////////////////////////////////////////////////////////
836
////                                                              ////
837
////  Versatile counter                                           ////
838
////                                                              ////
839
////  Description                                                 ////
840
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
841
////  counter                                                     ////
842
////                                                              ////
843
////  To Do:                                                      ////
844
////   - add LFSR with more taps                                  ////
845
////                                                              ////
846
////  Author(s):                                                  ////
847
////      - Michael Unneback, unneback@opencores.org              ////
848
////        ORSoC AB                                              ////
849
////                                                              ////
850
//////////////////////////////////////////////////////////////////////
851
////                                                              ////
852
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
853
////                                                              ////
854
//// This source file may be used and distributed without         ////
855
//// restriction provided that this copyright statement is not    ////
856
//// removed from the file and that any derivative work contains  ////
857
//// the original copyright notice and the associated disclaimer. ////
858
////                                                              ////
859
//// This source file is free software; you can redistribute it   ////
860
//// and/or modify it under the terms of the GNU Lesser General   ////
861
//// Public License as published by the Free Software Foundation; ////
862
//// either version 2.1 of the License, or (at your option) any   ////
863
//// later version.                                               ////
864
////                                                              ////
865
//// This source is distributed in the hope that it will be       ////
866
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
867
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
868
//// PURPOSE.  See the GNU Lesser General Public License for more ////
869
//// details.                                                     ////
870
////                                                              ////
871
//// You should have received a copy of the GNU Lesser General    ////
872
//// Public License along with this source; if not, download it   ////
873
//// from http://www.opencores.org/lgpl.shtml                     ////
874
////                                                              ////
875
//////////////////////////////////////////////////////////////////////
876
// LFSR counter
877 18 unneback
module vl_cnt_lfsr_zq ( zq, rst, clk);
878 6 unneback
   parameter length = 4;
879
   output reg zq;
880
   input rst;
881
   input clk;
882
   parameter clear_value = 0;
883
   parameter set_value = 1;
884
   parameter wrap_value = 8;
885
   parameter level1_value = 15;
886
   reg  [length:1] qi;
887
   reg lfsr_fb;
888
   wire [length:1] q_next;
889
   reg [32:1] polynom;
890
   integer i;
891
   always @ (qi)
892
   begin
893
        case (length)
894
         2: polynom = 32'b11;                               // 0x3
895
         3: polynom = 32'b110;                              // 0x6
896
         4: polynom = 32'b1100;                             // 0xC
897
         5: polynom = 32'b10100;                            // 0x14
898
         6: polynom = 32'b110000;                           // 0x30
899
         7: polynom = 32'b1100000;                          // 0x60
900
         8: polynom = 32'b10111000;                         // 0xb8
901
         9: polynom = 32'b100010000;                        // 0x110
902
        10: polynom = 32'b1001000000;                       // 0x240
903
        11: polynom = 32'b10100000000;                      // 0x500
904
        12: polynom = 32'b100000101001;                     // 0x829
905
        13: polynom = 32'b1000000001100;                    // 0x100C
906
        14: polynom = 32'b10000000010101;                   // 0x2015
907
        15: polynom = 32'b110000000000000;                  // 0x6000
908
        16: polynom = 32'b1101000000001000;                 // 0xD008
909
        17: polynom = 32'b10010000000000000;                // 0x12000
910
        18: polynom = 32'b100000010000000000;               // 0x20400
911
        19: polynom = 32'b1000000000000100011;              // 0x40023
912
        20: polynom = 32'b10000010000000000000;             // 0x82000
913
        21: polynom = 32'b101000000000000000000;            // 0x140000
914
        22: polynom = 32'b1100000000000000000000;           // 0x300000
915
        23: polynom = 32'b10000100000000000000000;          // 0x420000
916
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
917
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
918
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
919
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
920
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
921
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
922
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
923
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
924
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
925
        default: polynom = 32'b0;
926
        endcase
927
        lfsr_fb = qi[length];
928
        for (i=length-1; i>=1; i=i-1) begin
929
            if (polynom[i])
930
                lfsr_fb = lfsr_fb  ~^ qi[i];
931
        end
932
    end
933
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
934
   always @ (posedge clk or posedge rst)
935
     if (rst)
936
       qi <= {length{1'b0}};
937
     else
938
       qi <= q_next;
939
   always @ (posedge clk or posedge rst)
940
     if (rst)
941
       zq <= 1'b1;
942
     else
943
       zq <= q_next == {length{1'b0}};
944
endmodule
945
//////////////////////////////////////////////////////////////////////
946
////                                                              ////
947
////  Versatile counter                                           ////
948
////                                                              ////
949
////  Description                                                 ////
950
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
951
////  counter                                                     ////
952
////                                                              ////
953
////  To Do:                                                      ////
954
////   - add LFSR with more taps                                  ////
955
////                                                              ////
956
////  Author(s):                                                  ////
957
////      - Michael Unneback, unneback@opencores.org              ////
958
////        ORSoC AB                                              ////
959
////                                                              ////
960
//////////////////////////////////////////////////////////////////////
961
////                                                              ////
962
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
963
////                                                              ////
964
//// This source file may be used and distributed without         ////
965
//// restriction provided that this copyright statement is not    ////
966
//// removed from the file and that any derivative work contains  ////
967
//// the original copyright notice and the associated disclaimer. ////
968
////                                                              ////
969
//// This source file is free software; you can redistribute it   ////
970
//// and/or modify it under the terms of the GNU Lesser General   ////
971
//// Public License as published by the Free Software Foundation; ////
972
//// either version 2.1 of the License, or (at your option) any   ////
973
//// later version.                                               ////
974
////                                                              ////
975
//// This source is distributed in the hope that it will be       ////
976
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
977
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
978
//// PURPOSE.  See the GNU Lesser General Public License for more ////
979
//// details.                                                     ////
980
////                                                              ////
981
//// You should have received a copy of the GNU Lesser General    ////
982
//// Public License along with this source; if not, download it   ////
983
//// from http://www.opencores.org/lgpl.shtml                     ////
984
////                                                              ////
985
//////////////////////////////////////////////////////////////////////
986
// LFSR counter
987 18 unneback
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
988 6 unneback
   parameter length = 4;
989
   input cke;
990
   output reg zq;
991
   input rst;
992
   input clk;
993
   parameter clear_value = 0;
994
   parameter set_value = 1;
995
   parameter wrap_value = 8;
996
   parameter level1_value = 15;
997
   reg  [length:1] qi;
998
   reg lfsr_fb;
999
   wire [length:1] q_next;
1000
   reg [32:1] polynom;
1001
   integer i;
1002
   always @ (qi)
1003
   begin
1004
        case (length)
1005
         2: polynom = 32'b11;                               // 0x3
1006
         3: polynom = 32'b110;                              // 0x6
1007
         4: polynom = 32'b1100;                             // 0xC
1008
         5: polynom = 32'b10100;                            // 0x14
1009
         6: polynom = 32'b110000;                           // 0x30
1010
         7: polynom = 32'b1100000;                          // 0x60
1011
         8: polynom = 32'b10111000;                         // 0xb8
1012
         9: polynom = 32'b100010000;                        // 0x110
1013
        10: polynom = 32'b1001000000;                       // 0x240
1014
        11: polynom = 32'b10100000000;                      // 0x500
1015
        12: polynom = 32'b100000101001;                     // 0x829
1016
        13: polynom = 32'b1000000001100;                    // 0x100C
1017
        14: polynom = 32'b10000000010101;                   // 0x2015
1018
        15: polynom = 32'b110000000000000;                  // 0x6000
1019
        16: polynom = 32'b1101000000001000;                 // 0xD008
1020
        17: polynom = 32'b10010000000000000;                // 0x12000
1021
        18: polynom = 32'b100000010000000000;               // 0x20400
1022
        19: polynom = 32'b1000000000000100011;              // 0x40023
1023
        20: polynom = 32'b10000010000000000000;             // 0x82000
1024
        21: polynom = 32'b101000000000000000000;            // 0x140000
1025
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1026
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1027
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1028
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1029
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1030
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1031
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1032
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1033
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1034
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1035
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1036
        default: polynom = 32'b0;
1037
        endcase
1038
        lfsr_fb = qi[length];
1039
        for (i=length-1; i>=1; i=i-1) begin
1040
            if (polynom[i])
1041
                lfsr_fb = lfsr_fb  ~^ qi[i];
1042
        end
1043
    end
1044
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1045
   always @ (posedge clk or posedge rst)
1046
     if (rst)
1047
       qi <= {length{1'b0}};
1048
     else
1049
     if (cke)
1050
       qi <= q_next;
1051
   always @ (posedge clk or posedge rst)
1052
     if (rst)
1053
       zq <= 1'b1;
1054
     else
1055
     if (cke)
1056
       zq <= q_next == {length{1'b0}};
1057
endmodule
1058
//////////////////////////////////////////////////////////////////////
1059
////                                                              ////
1060
////  Versatile counter                                           ////
1061
////                                                              ////
1062
////  Description                                                 ////
1063
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1064
////  counter                                                     ////
1065
////                                                              ////
1066
////  To Do:                                                      ////
1067
////   - add LFSR with more taps                                  ////
1068
////                                                              ////
1069
////  Author(s):                                                  ////
1070
////      - Michael Unneback, unneback@opencores.org              ////
1071
////        ORSoC AB                                              ////
1072
////                                                              ////
1073
//////////////////////////////////////////////////////////////////////
1074
////                                                              ////
1075
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1076
////                                                              ////
1077
//// This source file may be used and distributed without         ////
1078
//// restriction provided that this copyright statement is not    ////
1079
//// removed from the file and that any derivative work contains  ////
1080
//// the original copyright notice and the associated disclaimer. ////
1081
////                                                              ////
1082
//// This source file is free software; you can redistribute it   ////
1083
//// and/or modify it under the terms of the GNU Lesser General   ////
1084
//// Public License as published by the Free Software Foundation; ////
1085
//// either version 2.1 of the License, or (at your option) any   ////
1086
//// later version.                                               ////
1087
////                                                              ////
1088
//// This source is distributed in the hope that it will be       ////
1089
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1090
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1091
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1092
//// details.                                                     ////
1093
////                                                              ////
1094
//// You should have received a copy of the GNU Lesser General    ////
1095
//// Public License along with this source; if not, download it   ////
1096
//// from http://www.opencores.org/lgpl.shtml                     ////
1097
////                                                              ////
1098
//////////////////////////////////////////////////////////////////////
1099
// LFSR counter
1100 22 unneback
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk);
1101
   parameter length = 4;
1102
   input cke;
1103
   output [length:1] q;
1104
   output reg zq;
1105
   input rst;
1106
   input clk;
1107
   parameter clear_value = 0;
1108
   parameter set_value = 1;
1109
   parameter wrap_value = 8;
1110
   parameter level1_value = 15;
1111
   reg  [length:1] qi;
1112
   reg lfsr_fb;
1113
   wire [length:1] q_next;
1114
   reg [32:1] polynom;
1115
   integer i;
1116
   always @ (qi)
1117
   begin
1118
        case (length)
1119
         2: polynom = 32'b11;                               // 0x3
1120
         3: polynom = 32'b110;                              // 0x6
1121
         4: polynom = 32'b1100;                             // 0xC
1122
         5: polynom = 32'b10100;                            // 0x14
1123
         6: polynom = 32'b110000;                           // 0x30
1124
         7: polynom = 32'b1100000;                          // 0x60
1125
         8: polynom = 32'b10111000;                         // 0xb8
1126
         9: polynom = 32'b100010000;                        // 0x110
1127
        10: polynom = 32'b1001000000;                       // 0x240
1128
        11: polynom = 32'b10100000000;                      // 0x500
1129
        12: polynom = 32'b100000101001;                     // 0x829
1130
        13: polynom = 32'b1000000001100;                    // 0x100C
1131
        14: polynom = 32'b10000000010101;                   // 0x2015
1132
        15: polynom = 32'b110000000000000;                  // 0x6000
1133
        16: polynom = 32'b1101000000001000;                 // 0xD008
1134
        17: polynom = 32'b10010000000000000;                // 0x12000
1135
        18: polynom = 32'b100000010000000000;               // 0x20400
1136
        19: polynom = 32'b1000000000000100011;              // 0x40023
1137
        20: polynom = 32'b10000010000000000000;             // 0x82000
1138
        21: polynom = 32'b101000000000000000000;            // 0x140000
1139
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1140
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1141
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1142
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1143
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1144
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1145
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1146
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1147
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1148
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1149
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1150
        default: polynom = 32'b0;
1151
        endcase
1152
        lfsr_fb = qi[length];
1153
        for (i=length-1; i>=1; i=i-1) begin
1154
            if (polynom[i])
1155
                lfsr_fb = lfsr_fb  ~^ qi[i];
1156
        end
1157
    end
1158
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1159
   always @ (posedge clk or posedge rst)
1160
     if (rst)
1161
       qi <= {length{1'b0}};
1162
     else
1163
     if (cke)
1164
       qi <= q_next;
1165
   assign q = qi;
1166
   always @ (posedge clk or posedge rst)
1167
     if (rst)
1168
       zq <= 1'b1;
1169
     else
1170
     if (cke)
1171
       zq <= q_next == {length{1'b0}};
1172
endmodule
1173
//////////////////////////////////////////////////////////////////////
1174
////                                                              ////
1175
////  Versatile counter                                           ////
1176
////                                                              ////
1177
////  Description                                                 ////
1178
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1179
////  counter                                                     ////
1180
////                                                              ////
1181
////  To Do:                                                      ////
1182
////   - add LFSR with more taps                                  ////
1183
////                                                              ////
1184
////  Author(s):                                                  ////
1185
////      - Michael Unneback, unneback@opencores.org              ////
1186
////        ORSoC AB                                              ////
1187
////                                                              ////
1188
//////////////////////////////////////////////////////////////////////
1189
////                                                              ////
1190
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1191
////                                                              ////
1192
//// This source file may be used and distributed without         ////
1193
//// restriction provided that this copyright statement is not    ////
1194
//// removed from the file and that any derivative work contains  ////
1195
//// the original copyright notice and the associated disclaimer. ////
1196
////                                                              ////
1197
//// This source file is free software; you can redistribute it   ////
1198
//// and/or modify it under the terms of the GNU Lesser General   ////
1199
//// Public License as published by the Free Software Foundation; ////
1200
//// either version 2.1 of the License, or (at your option) any   ////
1201
//// later version.                                               ////
1202
////                                                              ////
1203
//// This source is distributed in the hope that it will be       ////
1204
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1205
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1206
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1207
//// details.                                                     ////
1208
////                                                              ////
1209
//// You should have received a copy of the GNU Lesser General    ////
1210
//// Public License along with this source; if not, download it   ////
1211
//// from http://www.opencores.org/lgpl.shtml                     ////
1212
////                                                              ////
1213
//////////////////////////////////////////////////////////////////////
1214
// LFSR counter
1215 18 unneback
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
1216 6 unneback
   parameter length = 4;
1217
   input cke;
1218
   input rew;
1219
   output reg level1;
1220
   input rst;
1221
   input clk;
1222
   parameter clear_value = 0;
1223
   parameter set_value = 1;
1224
   parameter wrap_value = 8;
1225
   parameter level1_value = 15;
1226
   reg  [length:1] qi;
1227
   reg lfsr_fb, lfsr_fb_rew;
1228
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1229
   reg [32:1] polynom_rew;
1230
   integer j;
1231
   reg [32:1] polynom;
1232
   integer i;
1233
   always @ (qi)
1234
   begin
1235
        case (length)
1236
         2: polynom = 32'b11;                               // 0x3
1237
         3: polynom = 32'b110;                              // 0x6
1238
         4: polynom = 32'b1100;                             // 0xC
1239
         5: polynom = 32'b10100;                            // 0x14
1240
         6: polynom = 32'b110000;                           // 0x30
1241
         7: polynom = 32'b1100000;                          // 0x60
1242
         8: polynom = 32'b10111000;                         // 0xb8
1243
         9: polynom = 32'b100010000;                        // 0x110
1244
        10: polynom = 32'b1001000000;                       // 0x240
1245
        11: polynom = 32'b10100000000;                      // 0x500
1246
        12: polynom = 32'b100000101001;                     // 0x829
1247
        13: polynom = 32'b1000000001100;                    // 0x100C
1248
        14: polynom = 32'b10000000010101;                   // 0x2015
1249
        15: polynom = 32'b110000000000000;                  // 0x6000
1250
        16: polynom = 32'b1101000000001000;                 // 0xD008
1251
        17: polynom = 32'b10010000000000000;                // 0x12000
1252
        18: polynom = 32'b100000010000000000;               // 0x20400
1253
        19: polynom = 32'b1000000000000100011;              // 0x40023
1254
        20: polynom = 32'b10000010000000000000;             // 0x82000
1255
        21: polynom = 32'b101000000000000000000;            // 0x140000
1256
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1257
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1258
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1259
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1260
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1261
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1262
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1263
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1264
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1265
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1266
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1267
        default: polynom = 32'b0;
1268
        endcase
1269
        lfsr_fb = qi[length];
1270
        for (i=length-1; i>=1; i=i-1) begin
1271
            if (polynom[i])
1272
                lfsr_fb = lfsr_fb  ~^ qi[i];
1273
        end
1274
    end
1275
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1276
   always @ (qi)
1277
   begin
1278
        case (length)
1279
         2: polynom_rew = 32'b11;
1280
         3: polynom_rew = 32'b110;
1281
         4: polynom_rew = 32'b1100;
1282
         5: polynom_rew = 32'b10100;
1283
         6: polynom_rew = 32'b110000;
1284
         7: polynom_rew = 32'b1100000;
1285
         8: polynom_rew = 32'b10111000;
1286
         9: polynom_rew = 32'b100010000;
1287
        10: polynom_rew = 32'b1001000000;
1288
        11: polynom_rew = 32'b10100000000;
1289
        12: polynom_rew = 32'b100000101001;
1290
        13: polynom_rew = 32'b1000000001100;
1291
        14: polynom_rew = 32'b10000000010101;
1292
        15: polynom_rew = 32'b110000000000000;
1293
        16: polynom_rew = 32'b1101000000001000;
1294
        17: polynom_rew = 32'b10010000000000000;
1295
        18: polynom_rew = 32'b100000010000000000;
1296
        19: polynom_rew = 32'b1000000000000100011;
1297
        20: polynom_rew = 32'b10000010000000000000;
1298
        21: polynom_rew = 32'b101000000000000000000;
1299
        22: polynom_rew = 32'b1100000000000000000000;
1300
        23: polynom_rew = 32'b10000100000000000000000;
1301
        24: polynom_rew = 32'b111000010000000000000000;
1302
        25: polynom_rew = 32'b1001000000000000000000000;
1303
        26: polynom_rew = 32'b10000000000000000000100011;
1304
        27: polynom_rew = 32'b100000000000000000000010011;
1305
        28: polynom_rew = 32'b1100100000000000000000000000;
1306
        29: polynom_rew = 32'b10100000000000000000000000000;
1307
        30: polynom_rew = 32'b100000000000000000000000101001;
1308
        31: polynom_rew = 32'b1001000000000000000000000000000;
1309
        32: polynom_rew = 32'b10000000001000000000000000000011;
1310
        default: polynom_rew = 32'b0;
1311
        endcase
1312
        // rotate left
1313
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
1314
        lfsr_fb_rew = qi[length];
1315
        for (i=length-1; i>=1; i=i-1) begin
1316
            if (polynom_rew[i])
1317
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
1318
        end
1319
    end
1320
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
1321
   assign q_next = rew ? q_next_rew : q_next_fw;
1322
   always @ (posedge clk or posedge rst)
1323
     if (rst)
1324
       qi <= {length{1'b0}};
1325
     else
1326
     if (cke)
1327
       qi <= q_next;
1328
    always @ (posedge clk or posedge rst)
1329
    if (rst)
1330
        level1 <= 1'b0;
1331
    else
1332
    if (cke)
1333
    if (q_next == level1_value)
1334
        level1 <= 1'b1;
1335
    else if (qi == level1_value & rew)
1336
        level1 <= 1'b0;
1337
endmodule
1338
//////////////////////////////////////////////////////////////////////
1339
////                                                              ////
1340
////  Versatile counter                                           ////
1341
////                                                              ////
1342
////  Description                                                 ////
1343
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1344
////  counter                                                     ////
1345
////                                                              ////
1346
////  To Do:                                                      ////
1347
////   - add LFSR with more taps                                  ////
1348
////                                                              ////
1349
////  Author(s):                                                  ////
1350
////      - Michael Unneback, unneback@opencores.org              ////
1351
////        ORSoC AB                                              ////
1352
////                                                              ////
1353
//////////////////////////////////////////////////////////////////////
1354
////                                                              ////
1355
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1356
////                                                              ////
1357
//// This source file may be used and distributed without         ////
1358
//// restriction provided that this copyright statement is not    ////
1359
//// removed from the file and that any derivative work contains  ////
1360
//// the original copyright notice and the associated disclaimer. ////
1361
////                                                              ////
1362
//// This source file is free software; you can redistribute it   ////
1363
//// and/or modify it under the terms of the GNU Lesser General   ////
1364
//// Public License as published by the Free Software Foundation; ////
1365
//// either version 2.1 of the License, or (at your option) any   ////
1366
//// later version.                                               ////
1367
////                                                              ////
1368
//// This source is distributed in the hope that it will be       ////
1369
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1370
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1371
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1372
//// details.                                                     ////
1373
////                                                              ////
1374
//// You should have received a copy of the GNU Lesser General    ////
1375
//// Public License along with this source; if not, download it   ////
1376
//// from http://www.opencores.org/lgpl.shtml                     ////
1377
////                                                              ////
1378
//////////////////////////////////////////////////////////////////////
1379
// GRAY counter
1380 18 unneback
module vl_cnt_gray ( q, rst, clk);
1381 6 unneback
   parameter length = 4;
1382
   output reg [length:1] q;
1383
   input rst;
1384
   input clk;
1385
   parameter clear_value = 0;
1386
   parameter set_value = 1;
1387
   parameter wrap_value = 8;
1388
   parameter level1_value = 15;
1389
   reg  [length:1] qi;
1390
   wire [length:1] q_next;
1391
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1392
   always @ (posedge clk or posedge rst)
1393
     if (rst)
1394
       qi <= {length{1'b0}};
1395
     else
1396
       qi <= q_next;
1397
   always @ (posedge clk or posedge rst)
1398
     if (rst)
1399
       q <= {length{1'b0}};
1400
     else
1401
         q <= (q_next>>1) ^ q_next;
1402
endmodule
1403
//////////////////////////////////////////////////////////////////////
1404
////                                                              ////
1405
////  Versatile counter                                           ////
1406
////                                                              ////
1407
////  Description                                                 ////
1408
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1409
////  counter                                                     ////
1410
////                                                              ////
1411
////  To Do:                                                      ////
1412
////   - add LFSR with more taps                                  ////
1413
////                                                              ////
1414
////  Author(s):                                                  ////
1415
////      - Michael Unneback, unneback@opencores.org              ////
1416
////        ORSoC AB                                              ////
1417
////                                                              ////
1418
//////////////////////////////////////////////////////////////////////
1419
////                                                              ////
1420
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1421
////                                                              ////
1422
//// This source file may be used and distributed without         ////
1423
//// restriction provided that this copyright statement is not    ////
1424
//// removed from the file and that any derivative work contains  ////
1425
//// the original copyright notice and the associated disclaimer. ////
1426
////                                                              ////
1427
//// This source file is free software; you can redistribute it   ////
1428
//// and/or modify it under the terms of the GNU Lesser General   ////
1429
//// Public License as published by the Free Software Foundation; ////
1430
//// either version 2.1 of the License, or (at your option) any   ////
1431
//// later version.                                               ////
1432
////                                                              ////
1433
//// This source is distributed in the hope that it will be       ////
1434
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1435
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1436
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1437
//// details.                                                     ////
1438
////                                                              ////
1439
//// You should have received a copy of the GNU Lesser General    ////
1440
//// Public License along with this source; if not, download it   ////
1441
//// from http://www.opencores.org/lgpl.shtml                     ////
1442
////                                                              ////
1443
//////////////////////////////////////////////////////////////////////
1444
// GRAY counter
1445 18 unneback
module vl_cnt_gray_ce ( cke, q, rst, clk);
1446 6 unneback
   parameter length = 4;
1447
   input cke;
1448
   output reg [length:1] q;
1449
   input rst;
1450
   input clk;
1451
   parameter clear_value = 0;
1452
   parameter set_value = 1;
1453
   parameter wrap_value = 8;
1454
   parameter level1_value = 15;
1455
   reg  [length:1] qi;
1456
   wire [length:1] q_next;
1457
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1458
   always @ (posedge clk or posedge rst)
1459
     if (rst)
1460
       qi <= {length{1'b0}};
1461
     else
1462
     if (cke)
1463
       qi <= q_next;
1464
   always @ (posedge clk or posedge rst)
1465
     if (rst)
1466
       q <= {length{1'b0}};
1467
     else
1468
       if (cke)
1469
         q <= (q_next>>1) ^ q_next;
1470
endmodule
1471
//////////////////////////////////////////////////////////////////////
1472
////                                                              ////
1473
////  Versatile counter                                           ////
1474
////                                                              ////
1475
////  Description                                                 ////
1476
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1477
////  counter                                                     ////
1478
////                                                              ////
1479
////  To Do:                                                      ////
1480
////   - add LFSR with more taps                                  ////
1481
////                                                              ////
1482
////  Author(s):                                                  ////
1483
////      - Michael Unneback, unneback@opencores.org              ////
1484
////        ORSoC AB                                              ////
1485
////                                                              ////
1486
//////////////////////////////////////////////////////////////////////
1487
////                                                              ////
1488
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1489
////                                                              ////
1490
//// This source file may be used and distributed without         ////
1491
//// restriction provided that this copyright statement is not    ////
1492
//// removed from the file and that any derivative work contains  ////
1493
//// the original copyright notice and the associated disclaimer. ////
1494
////                                                              ////
1495
//// This source file is free software; you can redistribute it   ////
1496
//// and/or modify it under the terms of the GNU Lesser General   ////
1497
//// Public License as published by the Free Software Foundation; ////
1498
//// either version 2.1 of the License, or (at your option) any   ////
1499
//// later version.                                               ////
1500
////                                                              ////
1501
//// This source is distributed in the hope that it will be       ////
1502
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1503
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1504
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1505
//// details.                                                     ////
1506
////                                                              ////
1507
//// You should have received a copy of the GNU Lesser General    ////
1508
//// Public License along with this source; if not, download it   ////
1509
//// from http://www.opencores.org/lgpl.shtml                     ////
1510
////                                                              ////
1511
//////////////////////////////////////////////////////////////////////
1512
// GRAY counter
1513 18 unneback
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
1514 6 unneback
   parameter length = 4;
1515
   input cke;
1516
   output reg [length:1] q;
1517
   output [length:1] q_bin;
1518
   input rst;
1519
   input clk;
1520
   parameter clear_value = 0;
1521
   parameter set_value = 1;
1522
   parameter wrap_value = 8;
1523
   parameter level1_value = 15;
1524
   reg  [length:1] qi;
1525
   wire [length:1] q_next;
1526
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1527
   always @ (posedge clk or posedge rst)
1528
     if (rst)
1529
       qi <= {length{1'b0}};
1530
     else
1531
     if (cke)
1532
       qi <= q_next;
1533
   always @ (posedge clk or posedge rst)
1534
     if (rst)
1535
       q <= {length{1'b0}};
1536
     else
1537
       if (cke)
1538
         q <= (q_next>>1) ^ q_next;
1539
   assign q_bin = qi;
1540
endmodule
1541
//////////////////////////////////////////////////////////////////////
1542
////                                                              ////
1543
////  Versatile library, counters                                 ////
1544
////                                                              ////
1545
////  Description                                                 ////
1546
////  counters                                                    ////
1547
////                                                              ////
1548
////                                                              ////
1549
////  To Do:                                                      ////
1550
////   - add more counters                                        ////
1551
////                                                              ////
1552
////  Author(s):                                                  ////
1553
////      - Michael Unneback, unneback@opencores.org              ////
1554
////        ORSoC AB                                              ////
1555
////                                                              ////
1556
//////////////////////////////////////////////////////////////////////
1557
////                                                              ////
1558
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1559
////                                                              ////
1560
//// This source file may be used and distributed without         ////
1561
//// restriction provided that this copyright statement is not    ////
1562
//// removed from the file and that any derivative work contains  ////
1563
//// the original copyright notice and the associated disclaimer. ////
1564
////                                                              ////
1565
//// This source file is free software; you can redistribute it   ////
1566
//// and/or modify it under the terms of the GNU Lesser General   ////
1567
//// Public License as published by the Free Software Foundation; ////
1568
//// either version 2.1 of the License, or (at your option) any   ////
1569
//// later version.                                               ////
1570
////                                                              ////
1571
//// This source is distributed in the hope that it will be       ////
1572
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1573
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1574
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1575
//// details.                                                     ////
1576
////                                                              ////
1577
//// You should have received a copy of the GNU Lesser General    ////
1578
//// Public License along with this source; if not, download it   ////
1579
//// from http://www.opencores.org/lgpl.shtml                     ////
1580
////                                                              ////
1581
//////////////////////////////////////////////////////////////////////
1582 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
1583 6 unneback
   parameter length = 4;
1584
   output reg [0:length-1] q;
1585
   input rst;
1586
   input clk;
1587
    always @ (posedge clk or posedge rst)
1588
    if (rst)
1589
        q <= {1'b1,{length-1{1'b0}}};
1590
    else
1591
        q <= {q[length-1],q[0:length-2]};
1592
endmodule
1593 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
1594 6 unneback
   parameter length = 4;
1595
   input cke;
1596
   output reg [0:length-1] q;
1597
   input rst;
1598
   input clk;
1599
    always @ (posedge clk or posedge rst)
1600
    if (rst)
1601
        q <= {1'b1,{length-1{1'b0}}};
1602
    else
1603
        if (cke)
1604
            q <= {q[length-1],q[0:length-2]};
1605
endmodule
1606 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1607 6 unneback
   parameter length = 4;
1608
   input cke, clear;
1609
   output reg [0:length-1] q;
1610
   input rst;
1611
   input clk;
1612
    always @ (posedge clk or posedge rst)
1613
    if (rst)
1614
        q <= {1'b1,{length-1{1'b0}}};
1615
    else
1616
        if (cke)
1617
            if (clear)
1618
                q <= {1'b1,{length-1{1'b0}}};
1619
            else
1620
                q <= q >> 1;
1621
endmodule
1622 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
1623 6 unneback
   parameter length = 4;
1624
   input cke, clear;
1625
   output reg [0:length-1] q;
1626
   input rst;
1627
   input clk;
1628
    always @ (posedge clk or posedge rst)
1629
    if (rst)
1630
        q <= {1'b1,{length-1{1'b0}}};
1631
    else
1632
        if (cke)
1633
            if (clear)
1634
                q <= {1'b1,{length-1{1'b0}}};
1635
            else
1636
            q <= {q[length-1],q[0:length-2]};
1637
endmodule
1638
//////////////////////////////////////////////////////////////////////
1639
////                                                              ////
1640
////  Versatile library, memories                                 ////
1641
////                                                              ////
1642
////  Description                                                 ////
1643
////  memories                                                    ////
1644
////                                                              ////
1645
////                                                              ////
1646
////  To Do:                                                      ////
1647
////   - add more memory types                                    ////
1648
////                                                              ////
1649
////  Author(s):                                                  ////
1650
////      - Michael Unneback, unneback@opencores.org              ////
1651
////        ORSoC AB                                              ////
1652
////                                                              ////
1653
//////////////////////////////////////////////////////////////////////
1654
////                                                              ////
1655
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1656
////                                                              ////
1657
//// This source file may be used and distributed without         ////
1658
//// restriction provided that this copyright statement is not    ////
1659
//// removed from the file and that any derivative work contains  ////
1660
//// the original copyright notice and the associated disclaimer. ////
1661
////                                                              ////
1662
//// This source file is free software; you can redistribute it   ////
1663
//// and/or modify it under the terms of the GNU Lesser General   ////
1664
//// Public License as published by the Free Software Foundation; ////
1665
//// either version 2.1 of the License, or (at your option) any   ////
1666
//// later version.                                               ////
1667
////                                                              ////
1668
//// This source is distributed in the hope that it will be       ////
1669
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1670
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1671
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1672
//// details.                                                     ////
1673
////                                                              ////
1674
//// You should have received a copy of the GNU Lesser General    ////
1675
//// Public License along with this source; if not, download it   ////
1676
//// from http://www.opencores.org/lgpl.shtml                     ////
1677
////                                                              ////
1678
//////////////////////////////////////////////////////////////////////
1679
/// ROM
1680 7 unneback
module vl_rom_init ( adr, q, clk);
1681
   parameter data_width = 32;
1682
   parameter addr_width = 8;
1683
   input [(addr_width-1):0]       adr;
1684
   output reg [(data_width-1):0] q;
1685
   input                         clk;
1686
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
1687
   parameter memory_file = "vl_rom.vmem";
1688
   initial
1689
     begin
1690
        $readmemh(memory_file, rom);
1691
     end
1692
   always @ (posedge clk)
1693
     q <= rom[adr];
1694
endmodule
1695 14 unneback
/*
1696 7 unneback
module vl_rom ( adr, q, clk);
1697 6 unneback
parameter data_width = 32;
1698
parameter addr_width = 4;
1699
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
1700
    {32'h18000000},
1701
    {32'hA8200000},
1702
    {32'hA8200000},
1703
    {32'hA8200000},
1704
    {32'h44003000},
1705
    {32'h15000000},
1706
    {32'h15000000},
1707
    {32'h15000000},
1708
    {32'h15000000},
1709
    {32'h15000000},
1710
    {32'h15000000},
1711
    {32'h15000000},
1712
    {32'h15000000},
1713
    {32'h15000000},
1714
    {32'h15000000},
1715
    {32'h15000000}};
1716 7 unneback
input [addr_width-1:0] adr;
1717 6 unneback
output reg [data_width-1:0] q;
1718
input clk;
1719
always @ (posedge clk)
1720 7 unneback
    q <= data[adr];
1721 6 unneback
endmodule
1722 14 unneback
*/
1723 6 unneback
// Single port RAM
1724
module vl_ram ( d, adr, we, q, clk);
1725
   parameter data_width = 32;
1726
   parameter addr_width = 8;
1727
   input [(data_width-1):0]      d;
1728
   input [(addr_width-1):0]       adr;
1729
   input                         we;
1730 7 unneback
   output reg [(data_width-1):0] q;
1731 6 unneback
   input                         clk;
1732
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1733 7 unneback
   parameter init = 0;
1734
   parameter memory_file = "vl_ram.vmem";
1735
   generate if (init) begin : init_mem
1736
   initial
1737
     begin
1738
        $readmemh(memory_file, ram);
1739
     end
1740
   end
1741
   endgenerate
1742 6 unneback
   always @ (posedge clk)
1743
   begin
1744
   if (we)
1745
     ram[adr] <= d;
1746
   q <= ram[adr];
1747
   end
1748
endmodule
1749 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
1750
   parameter data_width = 32;
1751
   parameter addr_width = 8;
1752
   input [(data_width-1):0]      d;
1753
   input [(addr_width-1):0]       adr;
1754
   input [(addr_width/4)-1:0]    be;
1755
   input                         we;
1756
   output reg [(data_width-1):0] q;
1757
   input                         clk;
1758
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1759
   parameter init = 0;
1760
   parameter memory_file = "vl_ram.vmem";
1761
   generate if (init) begin : init_mem
1762
   initial
1763
     begin
1764
        $readmemh(memory_file, ram);
1765
     end
1766
   end
1767
   endgenerate
1768
   genvar i;
1769
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
1770
      always @ (posedge clk)
1771
      if (we & be[i])
1772
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
1773
   end
1774
   endgenerate
1775
   always @ (posedge clk)
1776
      q <= ram[adr];
1777
endmodule
1778 6 unneback
// Dual port RAM
1779
// ACTEL FPGA should not use logic to handle rw collision
1780 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1781 6 unneback
   parameter data_width = 32;
1782
   parameter addr_width = 8;
1783
   input [(data_width-1):0]      d_a;
1784
   input [(addr_width-1):0]       adr_a;
1785
   input [(addr_width-1):0]       adr_b;
1786
   input                         we_a;
1787
   output [(data_width-1):0]      q_b;
1788
   input                         clk_a, clk_b;
1789
   reg [(addr_width-1):0]         adr_b_reg;
1790
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1791 7 unneback
   parameter init = 0;
1792
   parameter memory_file = "vl_ram.vmem";
1793
   generate if (init) begin : init_mem
1794
   initial
1795
     begin
1796
        $readmemh(memory_file, ram);
1797
     end
1798
   end
1799
   endgenerate
1800 6 unneback
   always @ (posedge clk_a)
1801
   if (we_a)
1802
     ram[adr_a] <= d_a;
1803
   always @ (posedge clk_b)
1804
   adr_b_reg <= adr_b;
1805
   assign q_b = ram[adr_b_reg];
1806
endmodule
1807 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1808 6 unneback
   parameter data_width = 32;
1809
   parameter addr_width = 8;
1810
   input [(data_width-1):0]      d_a;
1811
   input [(addr_width-1):0]       adr_a;
1812
   input [(addr_width-1):0]       adr_b;
1813
   input                         we_a;
1814
   output [(data_width-1):0]      q_b;
1815
   output reg [(data_width-1):0] q_a;
1816
   input                         clk_a, clk_b;
1817
   reg [(data_width-1):0]         q_b;
1818
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1819 7 unneback
   parameter init = 0;
1820
   parameter memory_file = "vl_ram.vmem";
1821
   generate if (init) begin : init_mem
1822
   initial
1823
     begin
1824
        $readmemh(memory_file, ram);
1825
     end
1826
   end
1827
   endgenerate
1828 6 unneback
   always @ (posedge clk_a)
1829
     begin
1830
        q_a <= ram[adr_a];
1831
        if (we_a)
1832
             ram[adr_a] <= d_a;
1833
     end
1834
   always @ (posedge clk_b)
1835
          q_b <= ram[adr_b];
1836
endmodule
1837 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
1838 6 unneback
   parameter data_width = 32;
1839
   parameter addr_width = 8;
1840
   input [(data_width-1):0]      d_a;
1841
   input [(addr_width-1):0]       adr_a;
1842
   input [(addr_width-1):0]       adr_b;
1843
   input                         we_a;
1844
   output [(data_width-1):0]      q_b;
1845
   input [(data_width-1):0]       d_b;
1846
   output reg [(data_width-1):0] q_a;
1847
   input                         we_b;
1848
   input                         clk_a, clk_b;
1849
   reg [(data_width-1):0]         q_b;
1850
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1851 7 unneback
   parameter init = 0;
1852
   parameter memory_file = "vl_ram.vmem";
1853
   generate if (init) begin : init_mem
1854
   initial
1855
     begin
1856
        $readmemh(memory_file, ram);
1857
     end
1858
   end
1859
   endgenerate
1860 6 unneback
   always @ (posedge clk_a)
1861
     begin
1862
        q_a <= ram[adr_a];
1863
        if (we_a)
1864
             ram[adr_a] <= d_a;
1865
     end
1866
   always @ (posedge clk_b)
1867
     begin
1868
        q_b <= ram[adr_b];
1869
        if (we_b)
1870
          ram[adr_b] <= d_b;
1871
     end
1872
endmodule
1873
// Content addresable memory, CAM
1874
// FIFO
1875
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
1876 11 unneback
   parameter addr_width = 4;
1877
   parameter N = addr_width-1;
1878 6 unneback
   parameter Q1 = 2'b00;
1879
   parameter Q2 = 2'b01;
1880
   parameter Q3 = 2'b11;
1881
   parameter Q4 = 2'b10;
1882
   parameter going_empty = 1'b0;
1883
   parameter going_full  = 1'b1;
1884
   input [N:0]  wptr, rptr;
1885 14 unneback
   output       fifo_empty;
1886 6 unneback
   output       fifo_full;
1887
   input        wclk, rclk, rst;
1888
   wire direction;
1889
   reg  direction_set, direction_clr;
1890
   wire async_empty, async_full;
1891
   wire fifo_full2;
1892 14 unneback
   wire fifo_empty2;
1893 6 unneback
   // direction_set
1894
   always @ (wptr[N:N-1] or rptr[N:N-1])
1895
     case ({wptr[N:N-1],rptr[N:N-1]})
1896
       {Q1,Q2} : direction_set <= 1'b1;
1897
       {Q2,Q3} : direction_set <= 1'b1;
1898
       {Q3,Q4} : direction_set <= 1'b1;
1899
       {Q4,Q1} : direction_set <= 1'b1;
1900
       default : direction_set <= 1'b0;
1901
     endcase
1902
   // direction_clear
1903
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
1904
     if (rst)
1905
       direction_clr <= 1'b1;
1906
     else
1907
       case ({wptr[N:N-1],rptr[N:N-1]})
1908
         {Q2,Q1} : direction_clr <= 1'b1;
1909
         {Q3,Q2} : direction_clr <= 1'b1;
1910
         {Q4,Q3} : direction_clr <= 1'b1;
1911
         {Q1,Q4} : direction_clr <= 1'b1;
1912
         default : direction_clr <= 1'b0;
1913
       endcase
1914 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
1915 6 unneback
   assign async_empty = (wptr == rptr) && (direction==going_empty);
1916
   assign async_full  = (wptr == rptr) && (direction==going_full);
1917 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
1918
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
1919 6 unneback
/*
1920
   always @ (posedge wclk or posedge rst or posedge async_full)
1921
     if (rst)
1922
       {fifo_full, fifo_full2} <= 2'b00;
1923
     else if (async_full)
1924
       {fifo_full, fifo_full2} <= 2'b11;
1925
     else
1926
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
1927
*/
1928 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
1929 6 unneback
     if (async_empty)
1930
       {fifo_empty, fifo_empty2} <= 2'b11;
1931
     else
1932 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
1933 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
1934
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
1935 6 unneback
endmodule // async_comp
1936
module vl_fifo_1r1w_async (
1937
    d, wr, fifo_full, wr_clk, wr_rst,
1938
    q, rd, fifo_empty, rd_clk, rd_rst
1939
    );
1940
parameter data_width = 18;
1941
parameter addr_width = 4;
1942
// write side
1943
input  [data_width-1:0] d;
1944
input                   wr;
1945
output                  fifo_full;
1946
input                   wr_clk;
1947
input                   wr_rst;
1948
// read side
1949
output [data_width-1:0] q;
1950
input                   rd;
1951
output                  fifo_empty;
1952
input                   rd_clk;
1953
input                   rd_rst;
1954
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
1955 21 unneback
/*
1956 6 unneback
vl_fifo_1r1w_async (
1957
    d, wr, fifo_full, wr_clk, wr_rst,
1958
    q, rd, fifo_empty, rd_clk, rd_rst
1959
    );
1960 21 unneback
*/
1961 18 unneback
vl_cnt_gray_ce_bin
1962 6 unneback
    # ( .length(addr_width))
1963
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
1964 18 unneback
vl_cnt_gray_ce_bin
1965 6 unneback
    # (.length(addr_width))
1966
    fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
1967 7 unneback
vl_dpram_1r1w
1968 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
1969
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
1970
vl_fifo_cmp_async
1971
    # (.addr_width(addr_width))
1972
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
1973
endmodule
1974 8 unneback
module vl_fifo_2r2w_async (
1975 6 unneback
    // a side
1976
    a_d, a_wr, a_fifo_full,
1977
    a_q, a_rd, a_fifo_empty,
1978
    a_clk, a_rst,
1979
    // b side
1980
    b_d, b_wr, b_fifo_full,
1981
    b_q, b_rd, b_fifo_empty,
1982
    b_clk, b_rst
1983
    );
1984
parameter data_width = 18;
1985
parameter addr_width = 4;
1986
// a side
1987
input  [data_width-1:0] a_d;
1988
input                   a_wr;
1989
output                  a_fifo_full;
1990
output [data_width-1:0] a_q;
1991
input                   a_rd;
1992
output                  a_fifo_empty;
1993
input                   a_clk;
1994
input                   a_rst;
1995
// b side
1996
input  [data_width-1:0] b_d;
1997
input                   b_wr;
1998
output                  b_fifo_full;
1999
output [data_width-1:0] b_q;
2000
input                   b_rd;
2001
output                  b_fifo_empty;
2002
input                   b_clk;
2003
input                   b_rst;
2004
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
2005
vl_fifo_1r1w_async_a (
2006
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
2007
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
2008
    );
2009
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
2010
vl_fifo_1r1w_async_b (
2011
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
2012
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
2013
    );
2014
endmodule
2015 8 unneback
module vl_fifo_2r2w_async_simplex (
2016 6 unneback
    // a side
2017
    a_d, a_wr, a_fifo_full,
2018
    a_q, a_rd, a_fifo_empty,
2019
    a_clk, a_rst,
2020
    // b side
2021
    b_d, b_wr, b_fifo_full,
2022
    b_q, b_rd, b_fifo_empty,
2023
    b_clk, b_rst
2024
    );
2025
parameter data_width = 18;
2026
parameter addr_width = 4;
2027
// a side
2028
input  [data_width-1:0] a_d;
2029
input                   a_wr;
2030
output                  a_fifo_full;
2031
output [data_width-1:0] a_q;
2032
input                   a_rd;
2033
output                  a_fifo_empty;
2034
input                   a_clk;
2035
input                   a_rst;
2036
// b side
2037
input  [data_width-1:0] b_d;
2038
input                   b_wr;
2039
output                  b_fifo_full;
2040
output [data_width-1:0] b_q;
2041
input                   b_rd;
2042
output                  b_fifo_empty;
2043
input                   b_clk;
2044
input                   b_rst;
2045
// adr_gen
2046
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
2047
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
2048
// dpram
2049
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
2050 18 unneback
vl_cnt_gray_ce_bin
2051 6 unneback
    # ( .length(addr_width))
2052
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
2053 18 unneback
vl_cnt_gray_ce_bin
2054 6 unneback
    # (.length(addr_width))
2055
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
2056 18 unneback
vl_cnt_gray_ce_bin
2057 6 unneback
    # ( .length(addr_width))
2058
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
2059 18 unneback
vl_cnt_gray_ce_bin
2060 6 unneback
    # (.length(addr_width))
2061
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
2062
// mux read or write adr to DPRAM
2063
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
2064
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
2065 11 unneback
vl_dpram_2r2w
2066 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
2067
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
2068
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
2069 11 unneback
vl_fifo_cmp_async
2070 6 unneback
    # (.addr_width(addr_width))
2071
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
2072 11 unneback
vl_fifo_cmp_async
2073 6 unneback
    # (.addr_width(addr_width))
2074
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
2075
endmodule
2076 12 unneback
//////////////////////////////////////////////////////////////////////
2077
////                                                              ////
2078
////  Versatile library, wishbone stuff                           ////
2079
////                                                              ////
2080
////  Description                                                 ////
2081
////  Wishbone compliant modules                                  ////
2082
////                                                              ////
2083
////                                                              ////
2084
////  To Do:                                                      ////
2085
////   -                                                          ////
2086
////                                                              ////
2087
////  Author(s):                                                  ////
2088
////      - Michael Unneback, unneback@opencores.org              ////
2089
////        ORSoC AB                                              ////
2090
////                                                              ////
2091
//////////////////////////////////////////////////////////////////////
2092
////                                                              ////
2093
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2094
////                                                              ////
2095
//// This source file may be used and distributed without         ////
2096
//// restriction provided that this copyright statement is not    ////
2097
//// removed from the file and that any derivative work contains  ////
2098
//// the original copyright notice and the associated disclaimer. ////
2099
////                                                              ////
2100
//// This source file is free software; you can redistribute it   ////
2101
//// and/or modify it under the terms of the GNU Lesser General   ////
2102
//// Public License as published by the Free Software Foundation; ////
2103
//// either version 2.1 of the License, or (at your option) any   ////
2104
//// later version.                                               ////
2105
////                                                              ////
2106
//// This source is distributed in the hope that it will be       ////
2107
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2108
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2109
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2110
//// details.                                                     ////
2111
////                                                              ////
2112
//// You should have received a copy of the GNU Lesser General    ////
2113
//// Public License along with this source; if not, download it   ////
2114
//// from http://www.opencores.org/lgpl.shtml                     ////
2115
////                                                              ////
2116
//////////////////////////////////////////////////////////////////////
2117
// async wb3 - wb3 bridge
2118
`timescale 1ns/1ns
2119 18 unneback
module vl_wb3wb3_bridge (
2120 12 unneback
        // wishbone slave side
2121
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
2122
        // wishbone master side
2123
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
2124
input [31:0] wbs_dat_i;
2125
input [31:2] wbs_adr_i;
2126
input [3:0]  wbs_sel_i;
2127
input [1:0]  wbs_bte_i;
2128
input [2:0]  wbs_cti_i;
2129
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
2130
output [31:0] wbs_dat_o;
2131 14 unneback
output wbs_ack_o;
2132 12 unneback
input wbs_clk, wbs_rst;
2133
output [31:0] wbm_dat_o;
2134
output reg [31:2] wbm_adr_o;
2135
output [3:0]  wbm_sel_o;
2136
output reg [1:0]  wbm_bte_o;
2137
output reg [2:0]  wbm_cti_o;
2138 14 unneback
output reg wbm_we_o;
2139
output wbm_cyc_o;
2140 12 unneback
output wbm_stb_o;
2141
input [31:0]  wbm_dat_i;
2142
input wbm_ack_i;
2143
input wbm_clk, wbm_rst;
2144
parameter addr_width = 4;
2145
// bte
2146
parameter linear       = 2'b00;
2147
parameter wrap4        = 2'b01;
2148
parameter wrap8        = 2'b10;
2149
parameter wrap16       = 2'b11;
2150
// cti
2151
parameter classic      = 3'b000;
2152
parameter incburst     = 3'b010;
2153
parameter endofburst   = 3'b111;
2154
parameter wbs_adr  = 1'b0;
2155
parameter wbs_data = 1'b1;
2156
parameter wbm_adr0 = 2'b00;
2157
parameter wbm_adr1 = 2'b01;
2158
parameter wbm_data = 2'b10;
2159
reg [1:0] wbs_bte_reg;
2160
reg wbs;
2161
wire wbs_eoc_alert, wbm_eoc_alert;
2162
reg wbs_eoc, wbm_eoc;
2163
reg [1:0] wbm;
2164 14 unneback
wire [1:16] wbs_count, wbm_count;
2165 12 unneback
wire [35:0] a_d, a_q, b_d, b_q;
2166
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
2167
reg a_rd_reg;
2168
wire b_rd_adr, b_rd_data;
2169 14 unneback
wire b_rd_data_reg;
2170
wire [35:0] temp;
2171 12 unneback
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
2172
always @ (posedge wbs_clk or posedge wbs_rst)
2173
if (wbs_rst)
2174
        wbs_eoc <= 1'b0;
2175
else
2176
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
2177
                wbs_eoc <= wbs_bte_i==linear;
2178
        else if (wbs_eoc_alert & (a_rd | a_wr))
2179
                wbs_eoc <= 1'b1;
2180 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
2181 12 unneback
    cnt0 (
2182
        .cke(wbs_ack_o),
2183
        .clear(wbs_eoc),
2184
        .q(wbs_count),
2185
        .rst(wbs_rst),
2186
        .clk(wbs_clk));
2187
always @ (posedge wbs_clk or posedge wbs_rst)
2188
if (wbs_rst)
2189
        wbs <= wbs_adr;
2190
else
2191
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
2192
                wbs <= wbs_data;
2193
        else if (wbs_eoc & wbs_ack_o)
2194
                wbs <= wbs_adr;
2195
// wbs FIFO
2196
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
2197
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
2198
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
2199
              1'b0;
2200
assign a_rd = !a_fifo_empty;
2201
always @ (posedge wbs_clk or posedge wbs_rst)
2202
if (wbs_rst)
2203
        a_rd_reg <= 1'b0;
2204
else
2205
        a_rd_reg <= a_rd;
2206
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
2207
assign wbs_dat_o = a_q[35:4];
2208
always @ (posedge wbs_clk or posedge wbs_rst)
2209
if (wbs_rst)
2210 13 unneback
        wbs_bte_reg <= 2'b00;
2211 12 unneback
else
2212 13 unneback
        wbs_bte_reg <= wbs_bte_i;
2213 12 unneback
// wbm FIFO
2214
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
2215
always @ (posedge wbm_clk or posedge wbm_rst)
2216
if (wbm_rst)
2217
        wbm_eoc <= 1'b0;
2218
else
2219
        if (wbm==wbm_adr0 & !b_fifo_empty)
2220
                wbm_eoc <= b_q[4:3] == linear;
2221
        else if (wbm_eoc_alert & wbm_ack_i)
2222
                wbm_eoc <= 1'b1;
2223
always @ (posedge wbm_clk or posedge wbm_rst)
2224
if (wbm_rst)
2225
        wbm <= wbm_adr0;
2226
else
2227
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
2228
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
2229
        (wbm==wbm_adr1 & !wbm_we_o) |
2230
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
2231
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
2232
assign b_d = {wbm_dat_i,4'b1111};
2233
assign b_wr = !wbm_we_o & wbm_ack_i;
2234
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
2235
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
2236
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
2237
                   1'b0;
2238
assign b_rd = b_rd_adr | b_rd_data;
2239 18 unneback
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
2240
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
2241 12 unneback
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
2242 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
2243 12 unneback
    cnt1 (
2244
        .cke(wbm_ack_i),
2245
        .clear(wbm_eoc),
2246
        .q(wbm_count),
2247
        .rst(wbm_rst),
2248
        .clk(wbm_clk));
2249
assign wbm_cyc_o = wbm==wbm_data;
2250
assign wbm_stb_o = (wbm==wbm_data & wbm_we_o) ? !b_fifo_empty :
2251
                   (wbm==wbm_data) ? 1'b1 :
2252
                   1'b0;
2253
always @ (posedge wbm_clk or posedge wbm_rst)
2254
if (wbm_rst)
2255
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
2256
else begin
2257
        if (wbm==wbm_adr0 & !b_fifo_empty)
2258
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
2259
        else if (wbm_eoc_alert & wbm_ack_i)
2260
                wbm_cti_o <= endofburst;
2261
end
2262
//async_fifo_dw_simplex_top
2263
vl_fifo_2r2w_async_simplex
2264
# ( .data_width(36), .addr_width(addr_width))
2265
fifo (
2266
    // a side
2267
    .a_d(a_d),
2268
    .a_wr(a_wr),
2269
    .a_fifo_full(a_fifo_full),
2270
    .a_q(a_q),
2271
    .a_rd(a_rd),
2272
    .a_fifo_empty(a_fifo_empty),
2273
    .a_clk(wbs_clk),
2274
    .a_rst(wbs_rst),
2275
    // b side
2276
    .b_d(b_d),
2277
    .b_wr(b_wr),
2278
    .b_fifo_full(b_fifo_full),
2279
    .b_q(b_q),
2280
    .b_rd(b_rd),
2281
    .b_fifo_empty(b_fifo_empty),
2282
    .b_clk(wbm_clk),
2283
    .b_rst(wbm_rst)
2284
    );
2285
endmodule
2286 17 unneback
// WB ROM
2287 18 unneback
module vl_wb_boot_rom (
2288 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
2289 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
2290
    parameter adr_hi = 31;
2291
    parameter adr_lo = 28;
2292
    parameter adr_sel = 4'hf;
2293
    parameter addr_width = 5;
2294 17 unneback
`ifndef BOOT_ROM
2295
`define BOOT_ROM "boot_rom.v"
2296
`endif
2297 18 unneback
    input [adr_hi:2]    wb_adr_i;
2298
    input               wb_stb_i;
2299
    input               wb_cyc_i;
2300
    output [31:0]        wb_dat_o;
2301
    output              wb_ack_o;
2302
    output              hit_o;
2303
    input               wb_clk;
2304
    input               wb_rst;
2305
    wire hit;
2306
    reg [31:0] wb_dat;
2307
    reg wb_ack;
2308
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
2309 17 unneback
always @ (posedge wb_clk or posedge wb_rst)
2310
    if (wb_rst)
2311 18 unneback
        wb_dat <= 32'h15000000;
2312 17 unneback
    else
2313 18 unneback
         case (wb_adr_i[addr_width-1:2])
2314 17 unneback
`include `BOOT_ROM
2315
           /*
2316
            // Zero r0 and jump to 0x00000100
2317 18 unneback
 
2318
            1 : wb_dat <= 32'hA8200000;
2319
            2 : wb_dat <= 32'hA8C00100;
2320
            3 : wb_dat <= 32'h44003000;
2321
            4 : wb_dat <= 32'h15000000;
2322 17 unneback
            */
2323
           default:
2324 18 unneback
             wb_dat <= 32'h00000000;
2325 17 unneback
         endcase // case (wb_adr_i)
2326
always @ (posedge wb_clk or posedge wb_rst)
2327
    if (wb_rst)
2328 18 unneback
        wb_ack <= 1'b0;
2329 17 unneback
    else
2330 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
2331
assign hit_o = hit;
2332
assign wb_dat_o = wb_dat & {32{wb_ack}};
2333
assign wb_ack_o = wb_ack;
2334 17 unneback
endmodule
2335 18 unneback
//////////////////////////////////////////////////////////////////////
2336
////                                                              ////
2337
////  Arithmetic functions                                        ////
2338
////                                                              ////
2339
////  Description                                                 ////
2340
////  Arithmetic functions for ALU and DSP                        ////
2341
////                                                              ////
2342
////                                                              ////
2343
////  To Do:                                                      ////
2344
////   -                                                          ////
2345
////                                                              ////
2346
////  Author(s):                                                  ////
2347
////      - Michael Unneback, unneback@opencores.org              ////
2348
////        ORSoC AB                                              ////
2349
////                                                              ////
2350
//////////////////////////////////////////////////////////////////////
2351
////                                                              ////
2352
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2353
////                                                              ////
2354
//// This source file may be used and distributed without         ////
2355
//// restriction provided that this copyright statement is not    ////
2356
//// removed from the file and that any derivative work contains  ////
2357
//// the original copyright notice and the associated disclaimer. ////
2358
////                                                              ////
2359
//// This source file is free software; you can redistribute it   ////
2360
//// and/or modify it under the terms of the GNU Lesser General   ////
2361
//// Public License as published by the Free Software Foundation; ////
2362
//// either version 2.1 of the License, or (at your option) any   ////
2363
//// later version.                                               ////
2364
////                                                              ////
2365
//// This source is distributed in the hope that it will be       ////
2366
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2367
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2368
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2369
//// details.                                                     ////
2370
////                                                              ////
2371
//// You should have received a copy of the GNU Lesser General    ////
2372
//// Public License along with this source; if not, download it   ////
2373
//// from http://www.opencores.org/lgpl.shtml                     ////
2374
////                                                              ////
2375
//////////////////////////////////////////////////////////////////////
2376
// signed multiplication
2377
module vl_mults (a,b,p);
2378
parameter operand_a_width = 18;
2379
parameter operand_b_width = 18;
2380
parameter result_hi = 35;
2381
parameter result_lo = 0;
2382
input [operand_a_width-1:0] a;
2383
input [operand_b_width-1:0] b;
2384
output [result_hi:result_lo] p;
2385
wire signed [operand_a_width-1:0] ai;
2386
wire signed [operand_b_width-1:0] bi;
2387
wire signed [operand_a_width+operand_b_width-1:0] result;
2388
    assign ai = a;
2389
    assign bi = b;
2390
    assign result = ai * bi;
2391
    assign p = result[result_hi:result_lo];
2392
endmodule
2393
module vl_mults18x18 (a,b,p);
2394
input [17:0] a,b;
2395
output [35:0] p;
2396
vl_mult
2397
    # (.operand_a_width(18), .operand_b_width(18))
2398
    mult0 (.a(a), .b(b), .p(p));
2399
endmodule
2400
// unsigned multiplication
2401
module vl_mult (a,b,p);
2402
parameter operand_a_width = 18;
2403
parameter operand_b_width = 18;
2404
parameter result_hi = 35;
2405
parameter result_lo = 0;
2406
input [operand_a_width-1:0] a;
2407
input [operand_b_width-1:0] b;
2408
output [result_hi:result_hi] p;
2409
wire [operand_a_width+operand_b_width-1:0] result;
2410
    assign result = a * b;
2411
    assign p = result[result_hi:result_lo];
2412
endmodule
2413
// shift unit
2414
// supporting the following shift functions
2415
//   SLL
2416
//   SRL
2417
//   SRA
2418
module vl_shift_unit_32( din, s, dout, opcode);
2419
input [31:0] din; // data in operand
2420
input [4:0] s; // shift operand
2421
input [1:0] opcode;
2422
output [31:0] dout;
2423
parameter opcode_sll = 2'b00;
2424
//parameter opcode_srl = 2'b01;
2425
parameter opcode_sra = 2'b10;
2426
//parameter opcode_ror = 2'b11;
2427
wire sll, sra;
2428
assign sll = opcode == opcode_sll;
2429
assign sra = opcode == opcode_sra;
2430
wire [15:1] s1;
2431
wire [3:0] sign;
2432
wire [7:0] tmp [0:3];
2433
// first stage is multiplier based
2434
// shift operand as fractional 8.7
2435
assign s1[15] = sll & s[2:0]==3'd7;
2436
assign s1[14] = sll & s[2:0]==3'd6;
2437
assign s1[13] = sll & s[2:0]==3'd5;
2438
assign s1[12] = sll & s[2:0]==3'd4;
2439
assign s1[11] = sll & s[2:0]==3'd3;
2440
assign s1[10] = sll & s[2:0]==3'd2;
2441
assign s1[ 9] = sll & s[2:0]==3'd1;
2442
assign s1[ 8] = s[2:0]==3'd0;
2443
assign s1[ 7] = !sll & s[2:0]==3'd1;
2444
assign s1[ 6] = !sll & s[2:0]==3'd2;
2445
assign s1[ 5] = !sll & s[2:0]==3'd3;
2446
assign s1[ 4] = !sll & s[2:0]==3'd4;
2447
assign s1[ 3] = !sll & s[2:0]==3'd5;
2448
assign s1[ 2] = !sll & s[2:0]==3'd6;
2449
assign s1[ 1] = !sll & s[2:0]==3'd7;
2450
assign sign[3] = din[31] & sra;
2451
assign sign[2] = sign[3] & (&din[31:24]);
2452
assign sign[1] = sign[2] & (&din[23:16]);
2453
assign sign[0] = sign[1] & (&din[15:8]);
2454
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
2455
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
2456
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
2457
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
2458
// second stage is multiplexer based
2459
// shift on byte level
2460
// mux byte 3
2461
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
2462
                     (sll & s[4:3]==2'b01) ? tmp[2] :
2463
                     (sll & s[4:3]==2'b10) ? tmp[1] :
2464
                     (sll & s[4:3]==2'b11) ? tmp[0] :
2465
                     {8{sign[3]}};
2466
// mux byte 2
2467
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
2468
                     (sll & s[4:3]==2'b01) ? tmp[1] :
2469
                     (sll & s[4:3]==2'b10) ? tmp[0] :
2470
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
2471
                     (s[4:3]==2'b01) ? tmp[3] :
2472
                     {8{sign[3]}};
2473
// mux byte 1
2474
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
2475
                     (sll & s[4:3]==2'b01) ? tmp[0] :
2476
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
2477
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
2478
                     (s[4:3]==2'b01) ? tmp[2] :
2479
                     (s[4:3]==2'b10) ? tmp[3] :
2480
                     {8{sign[3]}};
2481
// mux byte 0
2482
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
2483
                     (sll) ?  {8{1'b0}}:
2484
                     (s[4:3]==2'b01) ? tmp[1] :
2485
                     (s[4:3]==2'b10) ? tmp[2] :
2486
                     tmp