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1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  Versatile library, clock and reset                          ////
4
////                                                              ////
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////  Description                                                 ////
6
////  Logic related to clock and reset                            ////
7
////                                                              ////
8
////                                                              ////
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////  To Do:                                                      ////
10
////   - add more different registers                             ////
11
////                                                              ////
12
////  Author(s):                                                  ////
13
////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
// Global buffer
43
// usage:
44
// use to enable global buffers for high fan out signals such as clock and reset
45
`timescale 1 ns/100 ps
46
// Version: 8.4 8.4.0.33
47
module gbuf(GL,CLK);
48
output GL;
49
input  CLK;
50
    wire GND;
51
    GND GND_1_net(.Y(GND));
52
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
53
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
54
endmodule
55
`timescale 1 ns/1 ns
56
module vl_gbuf ( i, o);
57
input i;
58
output o;
59
`ifdef SIM_GBUF
60
assign o=i;
61
`else
62
gbuf gbuf_i0 ( .CLK(i), .GL(o));
63
`endif
64
endmodule
65
 //ACTEL
66
// sync reset
67 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
68 6 unneback
// output active high global reset sync with two DFFs 
69
`timescale 1 ns/100 ps
70
module vl_sync_rst ( rst_n_i, rst_o, clk);
71
input rst_n_i, clk;
72
output rst_o;
73 18 unneback
reg [1:0] tmp;
74 6 unneback
always @ (posedge clk or negedge rst_n_i)
75
if (!rst_n_i)
76 17 unneback
        tmp <= 2'b11;
77 6 unneback
else
78 17 unneback
        tmp <= {1'b0,tmp[0]};
79
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
80 6 unneback
endmodule
81
// vl_pll
82 17 unneback
`timescale 1 ps/1 ps
83 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
84
parameter index = 0;
85
parameter number_of_clk = 1;
86 17 unneback
parameter period_time_0 = 20000;
87
parameter period_time_1 = 20000;
88
parameter period_time_2 = 20000;
89
parameter lock_delay = 2000000;
90 6 unneback
input clk_i, rst_n_i;
91
output lock;
92
output reg [0:number_of_clk-1] clk_o;
93
output [0:number_of_clk-1] rst_o;
94
`ifdef SIM_PLL
95
always
96
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
97
generate if (number_of_clk > 1)
98
always
99
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
100
endgenerate
101
generate if (number_of_clk > 2)
102
always
103
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
104
endgenerate
105
genvar i;
106
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
107
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
108
end
109
endgenerate
110
assign #lock_delay lock = rst_n_i;
111
endmodule
112
`else
113
generate if (number_of_clk==1 & index==0) begin
114
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
115
end
116
endgenerate // index==0
117
generate if (number_of_clk==1 & index==1) begin
118
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
119
end
120
endgenerate // index==1
121
generate if (number_of_clk==1 & index==2) begin
122
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
123
end
124
endgenerate // index==2
125
generate if (number_of_clk==1 & index==3) begin
126
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
127
end
128
endgenerate // index==0
129
generate if (number_of_clk==2 & index==0) begin
130
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
131
end
132
endgenerate // index==0
133
generate if (number_of_clk==2 & index==1) begin
134
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
135
end
136
endgenerate // index==1
137
generate if (number_of_clk==2 & index==2) begin
138
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
139
end
140
endgenerate // index==2
141
generate if (number_of_clk==2 & index==3) begin
142
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
143
end
144
endgenerate // index==0
145
generate if (number_of_clk==3 & index==0) begin
146
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
147
end
148
endgenerate // index==0
149
generate if (number_of_clk==3 & index==1) begin
150
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
151
end
152
endgenerate // index==1
153
generate if (number_of_clk==3 & index==2) begin
154
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
155
end
156
endgenerate // index==2
157
generate if (number_of_clk==3 & index==3) begin
158
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
159
end
160
endgenerate // index==0
161
genvar i;
162
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
163
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
164
end
165
endgenerate
166
endmodule
167
`endif
168
 //actel
169
//////////////////////////////////////////////////////////////////////
170
////                                                              ////
171
////  Versatile library, registers                                ////
172
////                                                              ////
173
////  Description                                                 ////
174
////  Different type of registers                                 ////
175
////                                                              ////
176
////                                                              ////
177
////  To Do:                                                      ////
178
////   - add more different registers                             ////
179
////                                                              ////
180
////  Author(s):                                                  ////
181
////      - Michael Unneback, unneback@opencores.org              ////
182
////        ORSoC AB                                              ////
183
////                                                              ////
184
//////////////////////////////////////////////////////////////////////
185
////                                                              ////
186
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
187
////                                                              ////
188
//// This source file may be used and distributed without         ////
189
//// restriction provided that this copyright statement is not    ////
190
//// removed from the file and that any derivative work contains  ////
191
//// the original copyright notice and the associated disclaimer. ////
192
////                                                              ////
193
//// This source file is free software; you can redistribute it   ////
194
//// and/or modify it under the terms of the GNU Lesser General   ////
195
//// Public License as published by the Free Software Foundation; ////
196
//// either version 2.1 of the License, or (at your option) any   ////
197
//// later version.                                               ////
198
////                                                              ////
199
//// This source is distributed in the hope that it will be       ////
200
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
201
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
202
//// PURPOSE.  See the GNU Lesser General Public License for more ////
203
//// details.                                                     ////
204
////                                                              ////
205
//// You should have received a copy of the GNU Lesser General    ////
206
//// Public License along with this source; if not, download it   ////
207
//// from http://www.opencores.org/lgpl.shtml                     ////
208
////                                                              ////
209
//////////////////////////////////////////////////////////////////////
210 18 unneback
module vl_dff ( d, q, clk, rst);
211 6 unneback
        parameter width = 1;
212
        parameter reset_value = 0;
213
        input [width-1:0] d;
214
        input clk, rst;
215
        output reg [width-1:0] q;
216
        always @ (posedge clk or posedge rst)
217
        if (rst)
218
                q <= reset_value;
219
        else
220
                q <= d;
221
endmodule
222 18 unneback
module vl_dff_array ( d, q, clk, rst);
223 6 unneback
        parameter width = 1;
224
        parameter depth = 2;
225
        parameter reset_value = 1'b0;
226
        input [width-1:0] d;
227
        input clk, rst;
228
        output [width-1:0] q;
229
        reg  [0:depth-1] q_tmp [width-1:0];
230
        integer i;
231
        always @ (posedge clk or posedge rst)
232
        if (rst) begin
233
            for (i=0;i<depth;i=i+1)
234
                q_tmp[i] <= {width{reset_value}};
235
        end else begin
236
            q_tmp[0] <= d;
237
            for (i=1;i<depth;i=i+1)
238
                q_tmp[i] <= q_tmp[i-1];
239
        end
240
    assign q = q_tmp[depth-1];
241
endmodule
242 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
243 6 unneback
        parameter width = 1;
244
        parameter reset_value = 0;
245
        input [width-1:0] d;
246
        input ce, clk, rst;
247
        output reg [width-1:0] q;
248
        always @ (posedge clk or posedge rst)
249
        if (rst)
250
                q <= reset_value;
251
        else
252
                if (ce)
253
                        q <= d;
254
endmodule
255 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
256 8 unneback
        parameter width = 1;
257
        parameter reset_value = 0;
258
        input [width-1:0] d;
259 10 unneback
        input ce, clear, clk, rst;
260 8 unneback
        output reg [width-1:0] q;
261
        always @ (posedge clk or posedge rst)
262
        if (rst)
263
            q <= reset_value;
264
        else
265
            if (ce)
266
                if (clear)
267
                    q <= {width{1'b0}};
268
                else
269
                    q <= d;
270
endmodule
271 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
272
        parameter width = 1;
273
        parameter reset_value = 0;
274
        input [width-1:0] d;
275
        input ce, set, clk, rst;
276
        output reg [width-1:0] q;
277
        always @ (posedge clk or posedge rst)
278
        if (rst)
279
            q <= reset_value;
280
        else
281
            if (ce)
282
                if (set)
283
                    q <= {width{1'b1}};
284
                else
285
                    q <= d;
286
endmodule
287 18 unneback
module vl_dff_sr ( aclr, aset, clock, data, q);
288 6 unneback
    input         aclr;
289
    input         aset;
290
    input         clock;
291
    input         data;
292
    output reg    q;
293
   always @ (posedge clock or posedge aclr or posedge aset)
294
     if (aclr)
295
       q <= 1'b0;
296
     else if (aset)
297
       q <= 1'b1;
298
     else
299
       q <= data;
300
endmodule
301
// LATCH
302
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
303
module latch ( d, le, q, clk);
304
input d, le;
305
output q;
306
input clk;/*
307
   always @ (posedge direction_set or posedge direction_clr)
308
     if (direction_clr)
309
       direction <= going_empty;
310
     else
311
       direction <= going_full;*/
312
endmodule
313 18 unneback
module vl_shreg ( d, q, clk, rst);
314 17 unneback
parameter depth = 10;
315
input d;
316
output q;
317
input clk, rst;
318
reg [1:depth] dffs;
319
always @ (posedge clk or posedge rst)
320
if (rst)
321
    dffs <= {depth{1'b0}};
322
else
323
    dffs <= {d,dffs[1:depth-1]};
324
assign q = dffs[depth];
325
endmodule
326 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
327 17 unneback
parameter depth = 10;
328
input d, ce;
329
output q;
330
input clk, rst;
331
reg [1:depth] dffs;
332
always @ (posedge clk or posedge rst)
333
if (rst)
334
    dffs <= {depth{1'b0}};
335
else
336
    if (ce)
337
        dffs <= {d,dffs[1:depth-1]};
338
assign q = dffs[depth];
339
endmodule
340 18 unneback
module vl_delay ( d, q, clk, rst);
341 15 unneback
parameter depth = 10;
342
input d;
343
output q;
344
input clk, rst;
345
reg [1:depth] dffs;
346
always @ (posedge clk or posedge rst)
347
if (rst)
348
    dffs <= {depth{1'b0}};
349
else
350
    dffs <= {d,dffs[1:depth-1]};
351
assign q = dffs[depth];
352
endmodule
353 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
354 17 unneback
parameter depth = 10;
355
input d;
356
output q, emptyflag;
357
input clk, rst;
358
reg [1:depth] dffs;
359
always @ (posedge clk or posedge rst)
360
if (rst)
361
    dffs <= {depth{1'b0}};
362
else
363
    dffs <= {d,dffs[1:depth-1]};
364
assign q = dffs[depth];
365
assign emptyflag = !(|dffs);
366
endmodule
367 6 unneback
//////////////////////////////////////////////////////////////////////
368
////                                                              ////
369 18 unneback
////  Logic functions                                             ////
370
////                                                              ////
371
////  Description                                                 ////
372
////  Logic functions such as multiplexers                        ////
373
////                                                              ////
374
////                                                              ////
375
////  To Do:                                                      ////
376
////   -                                                          ////
377
////                                                              ////
378
////  Author(s):                                                  ////
379
////      - Michael Unneback, unneback@opencores.org              ////
380
////        ORSoC AB                                              ////
381
////                                                              ////
382
//////////////////////////////////////////////////////////////////////
383
////                                                              ////
384
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
385
////                                                              ////
386
//// This source file may be used and distributed without         ////
387
//// restriction provided that this copyright statement is not    ////
388
//// removed from the file and that any derivative work contains  ////
389
//// the original copyright notice and the associated disclaimer. ////
390
////                                                              ////
391
//// This source file is free software; you can redistribute it   ////
392
//// and/or modify it under the terms of the GNU Lesser General   ////
393
//// Public License as published by the Free Software Foundation; ////
394
//// either version 2.1 of the License, or (at your option) any   ////
395
//// later version.                                               ////
396
////                                                              ////
397
//// This source is distributed in the hope that it will be       ////
398
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
399
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
400
//// PURPOSE.  See the GNU Lesser General Public License for more ////
401
//// details.                                                     ////
402
////                                                              ////
403
//// You should have received a copy of the GNU Lesser General    ////
404
//// Public License along with this source; if not, download it   ////
405
//// from http://www.opencores.org/lgpl.shtml                     ////
406
////                                                              ////
407
//////////////////////////////////////////////////////////////////////
408
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
409
parameter width = 32;
410
parameter nr_of_ports = 4;
411
input [width-1:0] a3, a2, a1, a0;
412
input [nr_of_ports-1:0] sel;
413 22 unneback
output [width-1:0] dout;
414 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
415 18 unneback
integer i;
416
// and
417
assign tmp[0] = {width{sel[0]}} & a0;
418
assign tmp[1] = {width{sel[1]}} & a1;
419
assign tmp[2] = {width{sel[2]}} & a2;
420
assign tmp[3] = {width{sel[3]}} & a3;
421
// or
422
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
423
endmodule
424
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
425
parameter width = 32;
426
parameter nr_of_ports = 5;
427
input [width-1:0] a4, a3, a2, a1, a0;
428
input [nr_of_ports-1:0] sel;
429 22 unneback
output [width-1:0] dout;
430 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
431 18 unneback
integer i;
432
// and
433
assign tmp[0] = {width{sel[0]}} & a0;
434
assign tmp[1] = {width{sel[1]}} & a1;
435
assign tmp[2] = {width{sel[2]}} & a2;
436
assign tmp[3] = {width{sel[3]}} & a3;
437
assign tmp[4] = {width{sel[4]}} & a4;
438
// or
439
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
440
endmodule
441
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
442
parameter width = 32;
443
parameter nr_of_ports = 6;
444
input [width-1:0] a5, a4, a3, a2, a1, a0;
445
input [nr_of_ports-1:0] sel;
446 22 unneback
output [width-1:0] dout;
447 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
448 18 unneback
integer i;
449
// and
450
assign tmp[0] = {width{sel[0]}} & a0;
451
assign tmp[1] = {width{sel[1]}} & a1;
452
assign tmp[2] = {width{sel[2]}} & a2;
453
assign tmp[3] = {width{sel[3]}} & a3;
454
assign tmp[4] = {width{sel[4]}} & a4;
455
assign tmp[5] = {width{sel[5]}} & a5;
456
// or
457
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
458
endmodule
459
//////////////////////////////////////////////////////////////////////
460
////                                                              ////
461 6 unneback
////  Versatile counter                                           ////
462
////                                                              ////
463
////  Description                                                 ////
464
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
465
////  counter                                                     ////
466
////                                                              ////
467
////  To Do:                                                      ////
468
////   - add LFSR with more taps                                  ////
469
////                                                              ////
470
////  Author(s):                                                  ////
471
////      - Michael Unneback, unneback@opencores.org              ////
472
////        ORSoC AB                                              ////
473
////                                                              ////
474
//////////////////////////////////////////////////////////////////////
475
////                                                              ////
476
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
477
////                                                              ////
478
//// This source file may be used and distributed without         ////
479
//// restriction provided that this copyright statement is not    ////
480
//// removed from the file and that any derivative work contains  ////
481
//// the original copyright notice and the associated disclaimer. ////
482
////                                                              ////
483
//// This source file is free software; you can redistribute it   ////
484
//// and/or modify it under the terms of the GNU Lesser General   ////
485
//// Public License as published by the Free Software Foundation; ////
486
//// either version 2.1 of the License, or (at your option) any   ////
487
//// later version.                                               ////
488
////                                                              ////
489
//// This source is distributed in the hope that it will be       ////
490
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
491
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
492
//// PURPOSE.  See the GNU Lesser General Public License for more ////
493
//// details.                                                     ////
494
////                                                              ////
495
//// You should have received a copy of the GNU Lesser General    ////
496
//// Public License along with this source; if not, download it   ////
497
//// from http://www.opencores.org/lgpl.shtml                     ////
498
////                                                              ////
499
//////////////////////////////////////////////////////////////////////
500
// binary counter
501 22 unneback
module vl_cnt_bin ( q, rst, clk);
502
   parameter length = 4;
503
   output [length:1] q;
504
   input rst;
505
   input clk;
506
   parameter clear_value = 0;
507
   parameter set_value = 1;
508
   parameter wrap_value = 0;
509
   parameter level1_value = 15;
510
   reg  [length:1] qi;
511
   wire [length:1] q_next;
512
   assign q_next = qi + {{length-1{1'b0}},1'b1};
513
   always @ (posedge clk or posedge rst)
514
     if (rst)
515
       qi <= {length{1'b0}};
516
     else
517
       qi <= q_next;
518
   assign q = qi;
519
endmodule
520
//////////////////////////////////////////////////////////////////////
521
////                                                              ////
522
////  Versatile counter                                           ////
523
////                                                              ////
524
////  Description                                                 ////
525
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
526
////  counter                                                     ////
527
////                                                              ////
528
////  To Do:                                                      ////
529
////   - add LFSR with more taps                                  ////
530
////                                                              ////
531
////  Author(s):                                                  ////
532
////      - Michael Unneback, unneback@opencores.org              ////
533
////        ORSoC AB                                              ////
534
////                                                              ////
535
//////////////////////////////////////////////////////////////////////
536
////                                                              ////
537
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
538
////                                                              ////
539
//// This source file may be used and distributed without         ////
540
//// restriction provided that this copyright statement is not    ////
541
//// removed from the file and that any derivative work contains  ////
542
//// the original copyright notice and the associated disclaimer. ////
543
////                                                              ////
544
//// This source file is free software; you can redistribute it   ////
545
//// and/or modify it under the terms of the GNU Lesser General   ////
546
//// Public License as published by the Free Software Foundation; ////
547
//// either version 2.1 of the License, or (at your option) any   ////
548
//// later version.                                               ////
549
////                                                              ////
550
//// This source is distributed in the hope that it will be       ////
551
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
552
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
553
//// PURPOSE.  See the GNU Lesser General Public License for more ////
554
//// details.                                                     ////
555
////                                                              ////
556
//// You should have received a copy of the GNU Lesser General    ////
557
//// Public License along with this source; if not, download it   ////
558
//// from http://www.opencores.org/lgpl.shtml                     ////
559
////                                                              ////
560
//////////////////////////////////////////////////////////////////////
561
// binary counter
562
module vl_cnt_bin_clear ( clear, q, rst, clk);
563
   parameter length = 4;
564
   input clear;
565
   output [length:1] q;
566
   input rst;
567
   input clk;
568
   parameter clear_value = 0;
569
   parameter set_value = 1;
570
   parameter wrap_value = 0;
571
   parameter level1_value = 15;
572
   reg  [length:1] qi;
573
   wire [length:1] q_next;
574
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
575
   always @ (posedge clk or posedge rst)
576
     if (rst)
577
       qi <= {length{1'b0}};
578
     else
579
       qi <= q_next;
580
   assign q = qi;
581
endmodule
582
//////////////////////////////////////////////////////////////////////
583
////                                                              ////
584
////  Versatile counter                                           ////
585
////                                                              ////
586
////  Description                                                 ////
587
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
588
////  counter                                                     ////
589
////                                                              ////
590
////  To Do:                                                      ////
591
////   - add LFSR with more taps                                  ////
592
////                                                              ////
593
////  Author(s):                                                  ////
594
////      - Michael Unneback, unneback@opencores.org              ////
595
////        ORSoC AB                                              ////
596
////                                                              ////
597
//////////////////////////////////////////////////////////////////////
598
////                                                              ////
599
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
600
////                                                              ////
601
//// This source file may be used and distributed without         ////
602
//// restriction provided that this copyright statement is not    ////
603
//// removed from the file and that any derivative work contains  ////
604
//// the original copyright notice and the associated disclaimer. ////
605
////                                                              ////
606
//// This source file is free software; you can redistribute it   ////
607
//// and/or modify it under the terms of the GNU Lesser General   ////
608
//// Public License as published by the Free Software Foundation; ////
609
//// either version 2.1 of the License, or (at your option) any   ////
610
//// later version.                                               ////
611
////                                                              ////
612
//// This source is distributed in the hope that it will be       ////
613
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
614
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
615
//// PURPOSE.  See the GNU Lesser General Public License for more ////
616
//// details.                                                     ////
617
////                                                              ////
618
//// You should have received a copy of the GNU Lesser General    ////
619
//// Public License along with this source; if not, download it   ////
620
//// from http://www.opencores.org/lgpl.shtml                     ////
621
////                                                              ////
622
//////////////////////////////////////////////////////////////////////
623
// binary counter
624 18 unneback
module vl_cnt_bin_ce ( cke, q, rst, clk);
625 6 unneback
   parameter length = 4;
626
   input cke;
627
   output [length:1] q;
628
   input rst;
629
   input clk;
630
   parameter clear_value = 0;
631
   parameter set_value = 1;
632
   parameter wrap_value = 0;
633
   parameter level1_value = 15;
634
   reg  [length:1] qi;
635
   wire [length:1] q_next;
636
   assign q_next = qi + {{length-1{1'b0}},1'b1};
637
   always @ (posedge clk or posedge rst)
638
     if (rst)
639
       qi <= {length{1'b0}};
640
     else
641
     if (cke)
642
       qi <= q_next;
643
   assign q = qi;
644
endmodule
645
//////////////////////////////////////////////////////////////////////
646
////                                                              ////
647
////  Versatile counter                                           ////
648
////                                                              ////
649
////  Description                                                 ////
650
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
651
////  counter                                                     ////
652
////                                                              ////
653
////  To Do:                                                      ////
654
////   - add LFSR with more taps                                  ////
655
////                                                              ////
656
////  Author(s):                                                  ////
657
////      - Michael Unneback, unneback@opencores.org              ////
658
////        ORSoC AB                                              ////
659
////                                                              ////
660
//////////////////////////////////////////////////////////////////////
661
////                                                              ////
662
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
663
////                                                              ////
664
//// This source file may be used and distributed without         ////
665
//// restriction provided that this copyright statement is not    ////
666
//// removed from the file and that any derivative work contains  ////
667
//// the original copyright notice and the associated disclaimer. ////
668
////                                                              ////
669
//// This source file is free software; you can redistribute it   ////
670
//// and/or modify it under the terms of the GNU Lesser General   ////
671
//// Public License as published by the Free Software Foundation; ////
672
//// either version 2.1 of the License, or (at your option) any   ////
673
//// later version.                                               ////
674
////                                                              ////
675
//// This source is distributed in the hope that it will be       ////
676
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
677
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
678
//// PURPOSE.  See the GNU Lesser General Public License for more ////
679
//// details.                                                     ////
680
////                                                              ////
681
//// You should have received a copy of the GNU Lesser General    ////
682
//// Public License along with this source; if not, download it   ////
683
//// from http://www.opencores.org/lgpl.shtml                     ////
684
////                                                              ////
685
//////////////////////////////////////////////////////////////////////
686
// binary counter
687 18 unneback
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
688 6 unneback
   parameter length = 4;
689
   input clear;
690
   input cke;
691
   output [length:1] q;
692
   input rst;
693
   input clk;
694
   parameter clear_value = 0;
695
   parameter set_value = 1;
696
   parameter wrap_value = 0;
697
   parameter level1_value = 15;
698
   reg  [length:1] qi;
699
   wire [length:1] q_next;
700
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
701
   always @ (posedge clk or posedge rst)
702
     if (rst)
703
       qi <= {length{1'b0}};
704
     else
705
     if (cke)
706
       qi <= q_next;
707
   assign q = qi;
708
endmodule
709
//////////////////////////////////////////////////////////////////////
710
////                                                              ////
711
////  Versatile counter                                           ////
712
////                                                              ////
713
////  Description                                                 ////
714
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
715
////  counter                                                     ////
716
////                                                              ////
717
////  To Do:                                                      ////
718
////   - add LFSR with more taps                                  ////
719
////                                                              ////
720
////  Author(s):                                                  ////
721
////      - Michael Unneback, unneback@opencores.org              ////
722
////        ORSoC AB                                              ////
723
////                                                              ////
724
//////////////////////////////////////////////////////////////////////
725
////                                                              ////
726
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
727
////                                                              ////
728
//// This source file may be used and distributed without         ////
729
//// restriction provided that this copyright statement is not    ////
730
//// removed from the file and that any derivative work contains  ////
731
//// the original copyright notice and the associated disclaimer. ////
732
////                                                              ////
733
//// This source file is free software; you can redistribute it   ////
734
//// and/or modify it under the terms of the GNU Lesser General   ////
735
//// Public License as published by the Free Software Foundation; ////
736
//// either version 2.1 of the License, or (at your option) any   ////
737
//// later version.                                               ////
738
////                                                              ////
739
//// This source is distributed in the hope that it will be       ////
740
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
741
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
742
//// PURPOSE.  See the GNU Lesser General Public License for more ////
743
//// details.                                                     ////
744
////                                                              ////
745
//// You should have received a copy of the GNU Lesser General    ////
746
//// Public License along with this source; if not, download it   ////
747
//// from http://www.opencores.org/lgpl.shtml                     ////
748
////                                                              ////
749
//////////////////////////////////////////////////////////////////////
750
// binary counter
751 18 unneback
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
752 6 unneback
   parameter length = 4;
753
   input clear;
754
   input set;
755
   input cke;
756
   input rew;
757
   output [length:1] q;
758
   input rst;
759
   input clk;
760
   parameter clear_value = 0;
761
   parameter set_value = 1;
762
   parameter wrap_value = 0;
763
   parameter level1_value = 15;
764
   reg  [length:1] qi;
765
   wire  [length:1] q_next, q_next_fw, q_next_rew;
766
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
767
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
768
   assign q_next = rew ? q_next_rew : q_next_fw;
769
   always @ (posedge clk or posedge rst)
770
     if (rst)
771
       qi <= {length{1'b0}};
772
     else
773
     if (cke)
774
       qi <= q_next;
775
   assign q = qi;
776
endmodule
777
//////////////////////////////////////////////////////////////////////
778
////                                                              ////
779
////  Versatile counter                                           ////
780
////                                                              ////
781
////  Description                                                 ////
782
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
783
////  counter                                                     ////
784
////                                                              ////
785
////  To Do:                                                      ////
786
////   - add LFSR with more taps                                  ////
787
////                                                              ////
788
////  Author(s):                                                  ////
789
////      - Michael Unneback, unneback@opencores.org              ////
790
////        ORSoC AB                                              ////
791
////                                                              ////
792
//////////////////////////////////////////////////////////////////////
793
////                                                              ////
794
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
795
////                                                              ////
796
//// This source file may be used and distributed without         ////
797
//// restriction provided that this copyright statement is not    ////
798
//// removed from the file and that any derivative work contains  ////
799
//// the original copyright notice and the associated disclaimer. ////
800
////                                                              ////
801
//// This source file is free software; you can redistribute it   ////
802
//// and/or modify it under the terms of the GNU Lesser General   ////
803
//// Public License as published by the Free Software Foundation; ////
804
//// either version 2.1 of the License, or (at your option) any   ////
805
//// later version.                                               ////
806
////                                                              ////
807
//// This source is distributed in the hope that it will be       ////
808
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
809
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
810
//// PURPOSE.  See the GNU Lesser General Public License for more ////
811
//// details.                                                     ////
812
////                                                              ////
813
//// You should have received a copy of the GNU Lesser General    ////
814
//// Public License along with this source; if not, download it   ////
815
//// from http://www.opencores.org/lgpl.shtml                     ////
816
////                                                              ////
817
//////////////////////////////////////////////////////////////////////
818
// binary counter
819 18 unneback
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
820 6 unneback
   parameter length = 4;
821
   input cke;
822
   input rew;
823
   output reg level1;
824
   input rst;
825
   input clk;
826
   parameter clear_value = 0;
827
   parameter set_value = 1;
828
   parameter wrap_value = 1;
829
   parameter level1_value = 15;
830
   reg  [length:1] qi;
831
   wire  [length:1] q_next, q_next_fw, q_next_rew;
832
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
833
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
834
   assign q_next = rew ? q_next_rew : q_next_fw;
835
   always @ (posedge clk or posedge rst)
836
     if (rst)
837
       qi <= {length{1'b0}};
838
     else
839
     if (cke)
840
       qi <= q_next;
841
    always @ (posedge clk or posedge rst)
842
    if (rst)
843
        level1 <= 1'b0;
844
    else
845
    if (cke)
846
    if (q_next == level1_value)
847
        level1 <= 1'b1;
848
    else if (qi == level1_value & rew)
849
        level1 <= 1'b0;
850
endmodule
851
//////////////////////////////////////////////////////////////////////
852
////                                                              ////
853
////  Versatile counter                                           ////
854
////                                                              ////
855
////  Description                                                 ////
856
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
857
////  counter                                                     ////
858
////                                                              ////
859
////  To Do:                                                      ////
860
////   - add LFSR with more taps                                  ////
861
////                                                              ////
862
////  Author(s):                                                  ////
863
////      - Michael Unneback, unneback@opencores.org              ////
864
////        ORSoC AB                                              ////
865
////                                                              ////
866
//////////////////////////////////////////////////////////////////////
867
////                                                              ////
868
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
869
////                                                              ////
870
//// This source file may be used and distributed without         ////
871
//// restriction provided that this copyright statement is not    ////
872
//// removed from the file and that any derivative work contains  ////
873
//// the original copyright notice and the associated disclaimer. ////
874
////                                                              ////
875
//// This source file is free software; you can redistribute it   ////
876
//// and/or modify it under the terms of the GNU Lesser General   ////
877
//// Public License as published by the Free Software Foundation; ////
878
//// either version 2.1 of the License, or (at your option) any   ////
879
//// later version.                                               ////
880
////                                                              ////
881
//// This source is distributed in the hope that it will be       ////
882
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
883
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
884
//// PURPOSE.  See the GNU Lesser General Public License for more ////
885
//// details.                                                     ////
886
////                                                              ////
887
//// You should have received a copy of the GNU Lesser General    ////
888
//// Public License along with this source; if not, download it   ////
889
//// from http://www.opencores.org/lgpl.shtml                     ////
890
////                                                              ////
891
//////////////////////////////////////////////////////////////////////
892 25 unneback
// binary counter
893
module vl_cnt_bin_ce_rew_zq_l1 ( cke, rew, zq, level1, rst, clk);
894
   parameter length = 4;
895
   input cke;
896
   input rew;
897
   output reg zq;
898
   output reg level1;
899
   input rst;
900
   input clk;
901
   parameter clear_value = 0;
902
   parameter set_value = 1;
903
   parameter wrap_value = 1;
904
   parameter level1_value = 15;
905
   reg  [length:1] qi;
906
   wire  [length:1] q_next, q_next_fw, q_next_rew;
907
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
908
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
909
   assign q_next = rew ? q_next_rew : q_next_fw;
910
   always @ (posedge clk or posedge rst)
911
     if (rst)
912
       qi <= {length{1'b0}};
913
     else
914
     if (cke)
915
       qi <= q_next;
916
   always @ (posedge clk or posedge rst)
917
     if (rst)
918
       zq <= 1'b1;
919
     else
920
     if (cke)
921
       zq <= q_next == {length{1'b0}};
922
    always @ (posedge clk or posedge rst)
923
    if (rst)
924
        level1 <= 1'b0;
925
    else
926
    if (cke)
927
    if (q_next == level1_value)
928
        level1 <= 1'b1;
929
    else if (qi == level1_value & rew)
930
        level1 <= 1'b0;
931
endmodule
932
//////////////////////////////////////////////////////////////////////
933
////                                                              ////
934
////  Versatile counter                                           ////
935
////                                                              ////
936
////  Description                                                 ////
937
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
938
////  counter                                                     ////
939
////                                                              ////
940
////  To Do:                                                      ////
941
////   - add LFSR with more taps                                  ////
942
////                                                              ////
943
////  Author(s):                                                  ////
944
////      - Michael Unneback, unneback@opencores.org              ////
945
////        ORSoC AB                                              ////
946
////                                                              ////
947
//////////////////////////////////////////////////////////////////////
948
////                                                              ////
949
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
950
////                                                              ////
951
//// This source file may be used and distributed without         ////
952
//// restriction provided that this copyright statement is not    ////
953
//// removed from the file and that any derivative work contains  ////
954
//// the original copyright notice and the associated disclaimer. ////
955
////                                                              ////
956
//// This source file is free software; you can redistribute it   ////
957
//// and/or modify it under the terms of the GNU Lesser General   ////
958
//// Public License as published by the Free Software Foundation; ////
959
//// either version 2.1 of the License, or (at your option) any   ////
960
//// later version.                                               ////
961
////                                                              ////
962
//// This source is distributed in the hope that it will be       ////
963
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
964
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
965
//// PURPOSE.  See the GNU Lesser General Public License for more ////
966
//// details.                                                     ////
967
////                                                              ////
968
//// You should have received a copy of the GNU Lesser General    ////
969
//// Public License along with this source; if not, download it   ////
970
//// from http://www.opencores.org/lgpl.shtml                     ////
971
////                                                              ////
972
//////////////////////////////////////////////////////////////////////
973
// binary counter
974
module vl_cnt_bin_ce_rew_q_zq_l1 ( cke, rew, q, zq, level1, rst, clk);
975
   parameter length = 4;
976
   input cke;
977
   input rew;
978
   output [length:1] q;
979
   output reg zq;
980
   output reg level1;
981
   input rst;
982
   input clk;
983
   parameter clear_value = 0;
984
   parameter set_value = 1;
985
   parameter wrap_value = 1;
986
   parameter level1_value = 15;
987
   reg  [length:1] qi;
988
   wire  [length:1] q_next, q_next_fw, q_next_rew;
989
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
990
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
991
   assign q_next = rew ? q_next_rew : q_next_fw;
992
   always @ (posedge clk or posedge rst)
993
     if (rst)
994
       qi <= {length{1'b0}};
995
     else
996
     if (cke)
997
       qi <= q_next;
998
   assign q = qi;
999
   always @ (posedge clk or posedge rst)
1000
     if (rst)
1001
       zq <= 1'b1;
1002
     else
1003
     if (cke)
1004
       zq <= q_next == {length{1'b0}};
1005
    always @ (posedge clk or posedge rst)
1006
    if (rst)
1007
        level1 <= 1'b0;
1008
    else
1009
    if (cke)
1010
    if (q_next == level1_value)
1011
        level1 <= 1'b1;
1012
    else if (qi == level1_value & rew)
1013
        level1 <= 1'b0;
1014
endmodule
1015
//////////////////////////////////////////////////////////////////////
1016
////                                                              ////
1017
////  Versatile counter                                           ////
1018
////                                                              ////
1019
////  Description                                                 ////
1020
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1021
////  counter                                                     ////
1022
////                                                              ////
1023
////  To Do:                                                      ////
1024
////   - add LFSR with more taps                                  ////
1025
////                                                              ////
1026
////  Author(s):                                                  ////
1027
////      - Michael Unneback, unneback@opencores.org              ////
1028
////        ORSoC AB                                              ////
1029
////                                                              ////
1030
//////////////////////////////////////////////////////////////////////
1031
////                                                              ////
1032
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1033
////                                                              ////
1034
//// This source file may be used and distributed without         ////
1035
//// restriction provided that this copyright statement is not    ////
1036
//// removed from the file and that any derivative work contains  ////
1037
//// the original copyright notice and the associated disclaimer. ////
1038
////                                                              ////
1039
//// This source file is free software; you can redistribute it   ////
1040
//// and/or modify it under the terms of the GNU Lesser General   ////
1041
//// Public License as published by the Free Software Foundation; ////
1042
//// either version 2.1 of the License, or (at your option) any   ////
1043
//// later version.                                               ////
1044
////                                                              ////
1045
//// This source is distributed in the hope that it will be       ////
1046
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1047
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1048
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1049
//// details.                                                     ////
1050
////                                                              ////
1051
//// You should have received a copy of the GNU Lesser General    ////
1052
//// Public License along with this source; if not, download it   ////
1053
//// from http://www.opencores.org/lgpl.shtml                     ////
1054
////                                                              ////
1055
//////////////////////////////////////////////////////////////////////
1056 6 unneback
// LFSR counter
1057 18 unneback
module vl_cnt_lfsr_zq ( zq, rst, clk);
1058 6 unneback
   parameter length = 4;
1059
   output reg zq;
1060
   input rst;
1061
   input clk;
1062
   parameter clear_value = 0;
1063
   parameter set_value = 1;
1064
   parameter wrap_value = 8;
1065
   parameter level1_value = 15;
1066
   reg  [length:1] qi;
1067
   reg lfsr_fb;
1068
   wire [length:1] q_next;
1069
   reg [32:1] polynom;
1070
   integer i;
1071
   always @ (qi)
1072
   begin
1073
        case (length)
1074
         2: polynom = 32'b11;                               // 0x3
1075
         3: polynom = 32'b110;                              // 0x6
1076
         4: polynom = 32'b1100;                             // 0xC
1077
         5: polynom = 32'b10100;                            // 0x14
1078
         6: polynom = 32'b110000;                           // 0x30
1079
         7: polynom = 32'b1100000;                          // 0x60
1080
         8: polynom = 32'b10111000;                         // 0xb8
1081
         9: polynom = 32'b100010000;                        // 0x110
1082
        10: polynom = 32'b1001000000;                       // 0x240
1083
        11: polynom = 32'b10100000000;                      // 0x500
1084
        12: polynom = 32'b100000101001;                     // 0x829
1085
        13: polynom = 32'b1000000001100;                    // 0x100C
1086
        14: polynom = 32'b10000000010101;                   // 0x2015
1087
        15: polynom = 32'b110000000000000;                  // 0x6000
1088
        16: polynom = 32'b1101000000001000;                 // 0xD008
1089
        17: polynom = 32'b10010000000000000;                // 0x12000
1090
        18: polynom = 32'b100000010000000000;               // 0x20400
1091
        19: polynom = 32'b1000000000000100011;              // 0x40023
1092
        20: polynom = 32'b10000010000000000000;             // 0x82000
1093
        21: polynom = 32'b101000000000000000000;            // 0x140000
1094
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1095
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1096
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1097
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1098
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1099
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1100
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1101
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1102
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1103
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1104
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1105
        default: polynom = 32'b0;
1106
        endcase
1107
        lfsr_fb = qi[length];
1108
        for (i=length-1; i>=1; i=i-1) begin
1109
            if (polynom[i])
1110
                lfsr_fb = lfsr_fb  ~^ qi[i];
1111
        end
1112
    end
1113
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1114
   always @ (posedge clk or posedge rst)
1115
     if (rst)
1116
       qi <= {length{1'b0}};
1117
     else
1118
       qi <= q_next;
1119
   always @ (posedge clk or posedge rst)
1120
     if (rst)
1121
       zq <= 1'b1;
1122
     else
1123
       zq <= q_next == {length{1'b0}};
1124
endmodule
1125
//////////////////////////////////////////////////////////////////////
1126
////                                                              ////
1127
////  Versatile counter                                           ////
1128
////                                                              ////
1129
////  Description                                                 ////
1130
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1131
////  counter                                                     ////
1132
////                                                              ////
1133
////  To Do:                                                      ////
1134
////   - add LFSR with more taps                                  ////
1135
////                                                              ////
1136
////  Author(s):                                                  ////
1137
////      - Michael Unneback, unneback@opencores.org              ////
1138
////        ORSoC AB                                              ////
1139
////                                                              ////
1140
//////////////////////////////////////////////////////////////////////
1141
////                                                              ////
1142
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1143
////                                                              ////
1144
//// This source file may be used and distributed without         ////
1145
//// restriction provided that this copyright statement is not    ////
1146
//// removed from the file and that any derivative work contains  ////
1147
//// the original copyright notice and the associated disclaimer. ////
1148
////                                                              ////
1149
//// This source file is free software; you can redistribute it   ////
1150
//// and/or modify it under the terms of the GNU Lesser General   ////
1151
//// Public License as published by the Free Software Foundation; ////
1152
//// either version 2.1 of the License, or (at your option) any   ////
1153
//// later version.                                               ////
1154
////                                                              ////
1155
//// This source is distributed in the hope that it will be       ////
1156
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1157
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1158
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1159
//// details.                                                     ////
1160
////                                                              ////
1161
//// You should have received a copy of the GNU Lesser General    ////
1162
//// Public License along with this source; if not, download it   ////
1163
//// from http://www.opencores.org/lgpl.shtml                     ////
1164
////                                                              ////
1165
//////////////////////////////////////////////////////////////////////
1166
// LFSR counter
1167 18 unneback
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
1168 6 unneback
   parameter length = 4;
1169
   input cke;
1170
   output reg zq;
1171
   input rst;
1172
   input clk;
1173
   parameter clear_value = 0;
1174
   parameter set_value = 1;
1175
   parameter wrap_value = 8;
1176
   parameter level1_value = 15;
1177
   reg  [length:1] qi;
1178
   reg lfsr_fb;
1179
   wire [length:1] q_next;
1180
   reg [32:1] polynom;
1181
   integer i;
1182
   always @ (qi)
1183
   begin
1184
        case (length)
1185
         2: polynom = 32'b11;                               // 0x3
1186
         3: polynom = 32'b110;                              // 0x6
1187
         4: polynom = 32'b1100;                             // 0xC
1188
         5: polynom = 32'b10100;                            // 0x14
1189
         6: polynom = 32'b110000;                           // 0x30
1190
         7: polynom = 32'b1100000;                          // 0x60
1191
         8: polynom = 32'b10111000;                         // 0xb8
1192
         9: polynom = 32'b100010000;                        // 0x110
1193
        10: polynom = 32'b1001000000;                       // 0x240
1194
        11: polynom = 32'b10100000000;                      // 0x500
1195
        12: polynom = 32'b100000101001;                     // 0x829
1196
        13: polynom = 32'b1000000001100;                    // 0x100C
1197
        14: polynom = 32'b10000000010101;                   // 0x2015
1198
        15: polynom = 32'b110000000000000;                  // 0x6000
1199
        16: polynom = 32'b1101000000001000;                 // 0xD008
1200
        17: polynom = 32'b10010000000000000;                // 0x12000
1201
        18: polynom = 32'b100000010000000000;               // 0x20400
1202
        19: polynom = 32'b1000000000000100011;              // 0x40023
1203
        20: polynom = 32'b10000010000000000000;             // 0x82000
1204
        21: polynom = 32'b101000000000000000000;            // 0x140000
1205
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1206
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1207
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1208
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1209
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1210
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1211
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1212
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1213
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1214
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1215
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1216
        default: polynom = 32'b0;
1217
        endcase
1218
        lfsr_fb = qi[length];
1219
        for (i=length-1; i>=1; i=i-1) begin
1220
            if (polynom[i])
1221
                lfsr_fb = lfsr_fb  ~^ qi[i];
1222
        end
1223
    end
1224
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1225
   always @ (posedge clk or posedge rst)
1226
     if (rst)
1227
       qi <= {length{1'b0}};
1228
     else
1229
     if (cke)
1230
       qi <= q_next;
1231
   always @ (posedge clk or posedge rst)
1232
     if (rst)
1233
       zq <= 1'b1;
1234
     else
1235
     if (cke)
1236
       zq <= q_next == {length{1'b0}};
1237
endmodule
1238
//////////////////////////////////////////////////////////////////////
1239
////                                                              ////
1240
////  Versatile counter                                           ////
1241
////                                                              ////
1242
////  Description                                                 ////
1243
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1244
////  counter                                                     ////
1245
////                                                              ////
1246
////  To Do:                                                      ////
1247
////   - add LFSR with more taps                                  ////
1248
////                                                              ////
1249
////  Author(s):                                                  ////
1250
////      - Michael Unneback, unneback@opencores.org              ////
1251
////        ORSoC AB                                              ////
1252
////                                                              ////
1253
//////////////////////////////////////////////////////////////////////
1254
////                                                              ////
1255
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1256
////                                                              ////
1257
//// This source file may be used and distributed without         ////
1258
//// restriction provided that this copyright statement is not    ////
1259
//// removed from the file and that any derivative work contains  ////
1260
//// the original copyright notice and the associated disclaimer. ////
1261
////                                                              ////
1262
//// This source file is free software; you can redistribute it   ////
1263
//// and/or modify it under the terms of the GNU Lesser General   ////
1264
//// Public License as published by the Free Software Foundation; ////
1265
//// either version 2.1 of the License, or (at your option) any   ////
1266
//// later version.                                               ////
1267
////                                                              ////
1268
//// This source is distributed in the hope that it will be       ////
1269
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1270
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1271
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1272
//// details.                                                     ////
1273
////                                                              ////
1274
//// You should have received a copy of the GNU Lesser General    ////
1275
//// Public License along with this source; if not, download it   ////
1276
//// from http://www.opencores.org/lgpl.shtml                     ////
1277
////                                                              ////
1278
//////////////////////////////////////////////////////////////////////
1279
// LFSR counter
1280 27 unneback
module vl_cnt_lfsr_ce_q ( cke, q, rst, clk);
1281
   parameter length = 4;
1282
   input cke;
1283
   output [length:1] q;
1284
   input rst;
1285
   input clk;
1286
   parameter clear_value = 0;
1287
   parameter set_value = 1;
1288
   parameter wrap_value = 8;
1289
   parameter level1_value = 15;
1290
   reg  [length:1] qi;
1291
   reg lfsr_fb;
1292
   wire [length:1] q_next;
1293
   reg [32:1] polynom;
1294
   integer i;
1295
   always @ (qi)
1296
   begin
1297
        case (length)
1298
         2: polynom = 32'b11;                               // 0x3
1299
         3: polynom = 32'b110;                              // 0x6
1300
         4: polynom = 32'b1100;                             // 0xC
1301
         5: polynom = 32'b10100;                            // 0x14
1302
         6: polynom = 32'b110000;                           // 0x30
1303
         7: polynom = 32'b1100000;                          // 0x60
1304
         8: polynom = 32'b10111000;                         // 0xb8
1305
         9: polynom = 32'b100010000;                        // 0x110
1306
        10: polynom = 32'b1001000000;                       // 0x240
1307
        11: polynom = 32'b10100000000;                      // 0x500
1308
        12: polynom = 32'b100000101001;                     // 0x829
1309
        13: polynom = 32'b1000000001100;                    // 0x100C
1310
        14: polynom = 32'b10000000010101;                   // 0x2015
1311
        15: polynom = 32'b110000000000000;                  // 0x6000
1312
        16: polynom = 32'b1101000000001000;                 // 0xD008
1313
        17: polynom = 32'b10010000000000000;                // 0x12000
1314
        18: polynom = 32'b100000010000000000;               // 0x20400
1315
        19: polynom = 32'b1000000000000100011;              // 0x40023
1316
        20: polynom = 32'b10000010000000000000;             // 0x82000
1317
        21: polynom = 32'b101000000000000000000;            // 0x140000
1318
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1319
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1320
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1321
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1322
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1323
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1324
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1325
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1326
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1327
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1328
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1329
        default: polynom = 32'b0;
1330
        endcase
1331
        lfsr_fb = qi[length];
1332
        for (i=length-1; i>=1; i=i-1) begin
1333
            if (polynom[i])
1334
                lfsr_fb = lfsr_fb  ~^ qi[i];
1335
        end
1336
    end
1337
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1338
   always @ (posedge clk or posedge rst)
1339
     if (rst)
1340
       qi <= {length{1'b0}};
1341
     else
1342
     if (cke)
1343
       qi <= q_next;
1344
   assign q = qi;
1345
endmodule
1346
//////////////////////////////////////////////////////////////////////
1347
////                                                              ////
1348
////  Versatile counter                                           ////
1349
////                                                              ////
1350
////  Description                                                 ////
1351
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1352
////  counter                                                     ////
1353
////                                                              ////
1354
////  To Do:                                                      ////
1355
////   - add LFSR with more taps                                  ////
1356
////                                                              ////
1357
////  Author(s):                                                  ////
1358
////      - Michael Unneback, unneback@opencores.org              ////
1359
////        ORSoC AB                                              ////
1360
////                                                              ////
1361
//////////////////////////////////////////////////////////////////////
1362
////                                                              ////
1363
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1364
////                                                              ////
1365
//// This source file may be used and distributed without         ////
1366
//// restriction provided that this copyright statement is not    ////
1367
//// removed from the file and that any derivative work contains  ////
1368
//// the original copyright notice and the associated disclaimer. ////
1369
////                                                              ////
1370
//// This source file is free software; you can redistribute it   ////
1371
//// and/or modify it under the terms of the GNU Lesser General   ////
1372
//// Public License as published by the Free Software Foundation; ////
1373
//// either version 2.1 of the License, or (at your option) any   ////
1374
//// later version.                                               ////
1375
////                                                              ////
1376
//// This source is distributed in the hope that it will be       ////
1377
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1378
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1379
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1380
//// details.                                                     ////
1381
////                                                              ////
1382
//// You should have received a copy of the GNU Lesser General    ////
1383
//// Public License along with this source; if not, download it   ////
1384
//// from http://www.opencores.org/lgpl.shtml                     ////
1385
////                                                              ////
1386
//////////////////////////////////////////////////////////////////////
1387
// LFSR counter
1388
module vl_cnt_lfsr_ce_clear_q ( clear, cke, q, rst, clk);
1389
   parameter length = 4;
1390
   input clear;
1391
   input cke;
1392
   output [length:1] q;
1393
   input rst;
1394
   input clk;
1395
   parameter clear_value = 0;
1396
   parameter set_value = 1;
1397
   parameter wrap_value = 8;
1398
   parameter level1_value = 15;
1399
   reg  [length:1] qi;
1400
   reg lfsr_fb;
1401
   wire [length:1] q_next;
1402
   reg [32:1] polynom;
1403
   integer i;
1404
   always @ (qi)
1405
   begin
1406
        case (length)
1407
         2: polynom = 32'b11;                               // 0x3
1408
         3: polynom = 32'b110;                              // 0x6
1409
         4: polynom = 32'b1100;                             // 0xC
1410
         5: polynom = 32'b10100;                            // 0x14
1411
         6: polynom = 32'b110000;                           // 0x30
1412
         7: polynom = 32'b1100000;                          // 0x60
1413
         8: polynom = 32'b10111000;                         // 0xb8
1414
         9: polynom = 32'b100010000;                        // 0x110
1415
        10: polynom = 32'b1001000000;                       // 0x240
1416
        11: polynom = 32'b10100000000;                      // 0x500
1417
        12: polynom = 32'b100000101001;                     // 0x829
1418
        13: polynom = 32'b1000000001100;                    // 0x100C
1419
        14: polynom = 32'b10000000010101;                   // 0x2015
1420
        15: polynom = 32'b110000000000000;                  // 0x6000
1421
        16: polynom = 32'b1101000000001000;                 // 0xD008
1422
        17: polynom = 32'b10010000000000000;                // 0x12000
1423
        18: polynom = 32'b100000010000000000;               // 0x20400
1424
        19: polynom = 32'b1000000000000100011;              // 0x40023
1425
        20: polynom = 32'b10000010000000000000;             // 0x82000
1426
        21: polynom = 32'b101000000000000000000;            // 0x140000
1427
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1428
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1429
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1430
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1431
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1432
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1433
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1434
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1435
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1436
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1437
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1438
        default: polynom = 32'b0;
1439
        endcase
1440
        lfsr_fb = qi[length];
1441
        for (i=length-1; i>=1; i=i-1) begin
1442
            if (polynom[i])
1443
                lfsr_fb = lfsr_fb  ~^ qi[i];
1444
        end
1445
    end
1446
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1447
   always @ (posedge clk or posedge rst)
1448
     if (rst)
1449
       qi <= {length{1'b0}};
1450
     else
1451
     if (cke)
1452
       qi <= q_next;
1453
   assign q = qi;
1454
endmodule
1455
//////////////////////////////////////////////////////////////////////
1456
////                                                              ////
1457
////  Versatile counter                                           ////
1458
////                                                              ////
1459
////  Description                                                 ////
1460
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1461
////  counter                                                     ////
1462
////                                                              ////
1463
////  To Do:                                                      ////
1464
////   - add LFSR with more taps                                  ////
1465
////                                                              ////
1466
////  Author(s):                                                  ////
1467
////      - Michael Unneback, unneback@opencores.org              ////
1468
////        ORSoC AB                                              ////
1469
////                                                              ////
1470
//////////////////////////////////////////////////////////////////////
1471
////                                                              ////
1472
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1473
////                                                              ////
1474
//// This source file may be used and distributed without         ////
1475
//// restriction provided that this copyright statement is not    ////
1476
//// removed from the file and that any derivative work contains  ////
1477
//// the original copyright notice and the associated disclaimer. ////
1478
////                                                              ////
1479
//// This source file is free software; you can redistribute it   ////
1480
//// and/or modify it under the terms of the GNU Lesser General   ////
1481
//// Public License as published by the Free Software Foundation; ////
1482
//// either version 2.1 of the License, or (at your option) any   ////
1483
//// later version.                                               ////
1484
////                                                              ////
1485
//// This source is distributed in the hope that it will be       ////
1486
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1487
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1488
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1489
//// details.                                                     ////
1490
////                                                              ////
1491
//// You should have received a copy of the GNU Lesser General    ////
1492
//// Public License along with this source; if not, download it   ////
1493
//// from http://www.opencores.org/lgpl.shtml                     ////
1494
////                                                              ////
1495
//////////////////////////////////////////////////////////////////////
1496
// LFSR counter
1497 22 unneback
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk);
1498
   parameter length = 4;
1499
   input cke;
1500
   output [length:1] q;
1501
   output reg zq;
1502
   input rst;
1503
   input clk;
1504
   parameter clear_value = 0;
1505
   parameter set_value = 1;
1506
   parameter wrap_value = 8;
1507
   parameter level1_value = 15;
1508
   reg  [length:1] qi;
1509
   reg lfsr_fb;
1510
   wire [length:1] q_next;
1511
   reg [32:1] polynom;
1512
   integer i;
1513
   always @ (qi)
1514
   begin
1515
        case (length)
1516
         2: polynom = 32'b11;                               // 0x3
1517
         3: polynom = 32'b110;                              // 0x6
1518
         4: polynom = 32'b1100;                             // 0xC
1519
         5: polynom = 32'b10100;                            // 0x14
1520
         6: polynom = 32'b110000;                           // 0x30
1521
         7: polynom = 32'b1100000;                          // 0x60
1522
         8: polynom = 32'b10111000;                         // 0xb8
1523
         9: polynom = 32'b100010000;                        // 0x110
1524
        10: polynom = 32'b1001000000;                       // 0x240
1525
        11: polynom = 32'b10100000000;                      // 0x500
1526
        12: polynom = 32'b100000101001;                     // 0x829
1527
        13: polynom = 32'b1000000001100;                    // 0x100C
1528
        14: polynom = 32'b10000000010101;                   // 0x2015
1529
        15: polynom = 32'b110000000000000;                  // 0x6000
1530
        16: polynom = 32'b1101000000001000;                 // 0xD008
1531
        17: polynom = 32'b10010000000000000;                // 0x12000
1532
        18: polynom = 32'b100000010000000000;               // 0x20400
1533
        19: polynom = 32'b1000000000000100011;              // 0x40023
1534
        20: polynom = 32'b10000010000000000000;             // 0x82000
1535
        21: polynom = 32'b101000000000000000000;            // 0x140000
1536
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1537
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1538
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1539
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1540
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1541
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1542
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1543
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1544
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1545
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1546
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1547
        default: polynom = 32'b0;
1548
        endcase
1549
        lfsr_fb = qi[length];
1550
        for (i=length-1; i>=1; i=i-1) begin
1551
            if (polynom[i])
1552
                lfsr_fb = lfsr_fb  ~^ qi[i];
1553
        end
1554
    end
1555
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1556
   always @ (posedge clk or posedge rst)
1557
     if (rst)
1558
       qi <= {length{1'b0}};
1559
     else
1560
     if (cke)
1561
       qi <= q_next;
1562
   assign q = qi;
1563
   always @ (posedge clk or posedge rst)
1564
     if (rst)
1565
       zq <= 1'b1;
1566
     else
1567
     if (cke)
1568
       zq <= q_next == {length{1'b0}};
1569
endmodule
1570
//////////////////////////////////////////////////////////////////////
1571
////                                                              ////
1572
////  Versatile counter                                           ////
1573
////                                                              ////
1574
////  Description                                                 ////
1575
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1576
////  counter                                                     ////
1577
////                                                              ////
1578
////  To Do:                                                      ////
1579
////   - add LFSR with more taps                                  ////
1580
////                                                              ////
1581
////  Author(s):                                                  ////
1582
////      - Michael Unneback, unneback@opencores.org              ////
1583
////        ORSoC AB                                              ////
1584
////                                                              ////
1585
//////////////////////////////////////////////////////////////////////
1586
////                                                              ////
1587
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1588
////                                                              ////
1589
//// This source file may be used and distributed without         ////
1590
//// restriction provided that this copyright statement is not    ////
1591
//// removed from the file and that any derivative work contains  ////
1592
//// the original copyright notice and the associated disclaimer. ////
1593
////                                                              ////
1594
//// This source file is free software; you can redistribute it   ////
1595
//// and/or modify it under the terms of the GNU Lesser General   ////
1596
//// Public License as published by the Free Software Foundation; ////
1597
//// either version 2.1 of the License, or (at your option) any   ////
1598
//// later version.                                               ////
1599
////                                                              ////
1600
//// This source is distributed in the hope that it will be       ////
1601
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1602
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1603
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1604
//// details.                                                     ////
1605
////                                                              ////
1606
//// You should have received a copy of the GNU Lesser General    ////
1607
//// Public License along with this source; if not, download it   ////
1608
//// from http://www.opencores.org/lgpl.shtml                     ////
1609
////                                                              ////
1610
//////////////////////////////////////////////////////////////////////
1611
// LFSR counter
1612 18 unneback
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
1613 6 unneback
   parameter length = 4;
1614
   input cke;
1615
   input rew;
1616
   output reg level1;
1617
   input rst;
1618
   input clk;
1619
   parameter clear_value = 0;
1620
   parameter set_value = 1;
1621
   parameter wrap_value = 8;
1622
   parameter level1_value = 15;
1623
   reg  [length:1] qi;
1624
   reg lfsr_fb, lfsr_fb_rew;
1625
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1626
   reg [32:1] polynom_rew;
1627
   integer j;
1628
   reg [32:1] polynom;
1629
   integer i;
1630
   always @ (qi)
1631
   begin
1632
        case (length)
1633
         2: polynom = 32'b11;                               // 0x3
1634
         3: polynom = 32'b110;                              // 0x6
1635
         4: polynom = 32'b1100;                             // 0xC
1636
         5: polynom = 32'b10100;                            // 0x14
1637
         6: polynom = 32'b110000;                           // 0x30
1638
         7: polynom = 32'b1100000;                          // 0x60
1639
         8: polynom = 32'b10111000;                         // 0xb8
1640
         9: polynom = 32'b100010000;                        // 0x110
1641
        10: polynom = 32'b1001000000;                       // 0x240
1642
        11: polynom = 32'b10100000000;                      // 0x500
1643
        12: polynom = 32'b100000101001;                     // 0x829
1644
        13: polynom = 32'b1000000001100;                    // 0x100C
1645
        14: polynom = 32'b10000000010101;                   // 0x2015
1646
        15: polynom = 32'b110000000000000;                  // 0x6000
1647
        16: polynom = 32'b1101000000001000;                 // 0xD008
1648
        17: polynom = 32'b10010000000000000;                // 0x12000
1649
        18: polynom = 32'b100000010000000000;               // 0x20400
1650
        19: polynom = 32'b1000000000000100011;              // 0x40023
1651
        20: polynom = 32'b10000010000000000000;             // 0x82000
1652
        21: polynom = 32'b101000000000000000000;            // 0x140000
1653
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1654
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1655
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1656
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1657
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1658
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1659
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1660
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1661
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1662
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1663
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1664
        default: polynom = 32'b0;
1665
        endcase
1666
        lfsr_fb = qi[length];
1667
        for (i=length-1; i>=1; i=i-1) begin
1668
            if (polynom[i])
1669
                lfsr_fb = lfsr_fb  ~^ qi[i];
1670
        end
1671
    end
1672
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1673
   always @ (qi)
1674
   begin
1675
        case (length)
1676
         2: polynom_rew = 32'b11;
1677
         3: polynom_rew = 32'b110;
1678
         4: polynom_rew = 32'b1100;
1679
         5: polynom_rew = 32'b10100;
1680
         6: polynom_rew = 32'b110000;
1681
         7: polynom_rew = 32'b1100000;
1682
         8: polynom_rew = 32'b10111000;
1683
         9: polynom_rew = 32'b100010000;
1684
        10: polynom_rew = 32'b1001000000;
1685
        11: polynom_rew = 32'b10100000000;
1686
        12: polynom_rew = 32'b100000101001;
1687
        13: polynom_rew = 32'b1000000001100;
1688
        14: polynom_rew = 32'b10000000010101;
1689
        15: polynom_rew = 32'b110000000000000;
1690
        16: polynom_rew = 32'b1101000000001000;
1691
        17: polynom_rew = 32'b10010000000000000;
1692
        18: polynom_rew = 32'b100000010000000000;
1693
        19: polynom_rew = 32'b1000000000000100011;
1694
        20: polynom_rew = 32'b10000010000000000000;
1695
        21: polynom_rew = 32'b101000000000000000000;
1696
        22: polynom_rew = 32'b1100000000000000000000;
1697
        23: polynom_rew = 32'b10000100000000000000000;
1698
        24: polynom_rew = 32'b111000010000000000000000;
1699
        25: polynom_rew = 32'b1001000000000000000000000;
1700
        26: polynom_rew = 32'b10000000000000000000100011;
1701
        27: polynom_rew = 32'b100000000000000000000010011;
1702
        28: polynom_rew = 32'b1100100000000000000000000000;
1703
        29: polynom_rew = 32'b10100000000000000000000000000;
1704
        30: polynom_rew = 32'b100000000000000000000000101001;
1705
        31: polynom_rew = 32'b1001000000000000000000000000000;
1706
        32: polynom_rew = 32'b10000000001000000000000000000011;
1707
        default: polynom_rew = 32'b0;
1708
        endcase
1709
        // rotate left
1710
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
1711
        lfsr_fb_rew = qi[length];
1712
        for (i=length-1; i>=1; i=i-1) begin
1713
            if (polynom_rew[i])
1714
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
1715
        end
1716
    end
1717
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
1718
   assign q_next = rew ? q_next_rew : q_next_fw;
1719
   always @ (posedge clk or posedge rst)
1720
     if (rst)
1721
       qi <= {length{1'b0}};
1722
     else
1723
     if (cke)
1724
       qi <= q_next;
1725
    always @ (posedge clk or posedge rst)
1726
    if (rst)
1727
        level1 <= 1'b0;
1728
    else
1729
    if (cke)
1730
    if (q_next == level1_value)
1731
        level1 <= 1'b1;
1732
    else if (qi == level1_value & rew)
1733
        level1 <= 1'b0;
1734
endmodule
1735
//////////////////////////////////////////////////////////////////////
1736
////                                                              ////
1737
////  Versatile counter                                           ////
1738
////                                                              ////
1739
////  Description                                                 ////
1740
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1741
////  counter                                                     ////
1742
////                                                              ////
1743
////  To Do:                                                      ////
1744
////   - add LFSR with more taps                                  ////
1745
////                                                              ////
1746
////  Author(s):                                                  ////
1747
////      - Michael Unneback, unneback@opencores.org              ////
1748
////        ORSoC AB                                              ////
1749
////                                                              ////
1750
//////////////////////////////////////////////////////////////////////
1751
////                                                              ////
1752
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1753
////                                                              ////
1754
//// This source file may be used and distributed without         ////
1755
//// restriction provided that this copyright statement is not    ////
1756
//// removed from the file and that any derivative work contains  ////
1757
//// the original copyright notice and the associated disclaimer. ////
1758
////                                                              ////
1759
//// This source file is free software; you can redistribute it   ////
1760
//// and/or modify it under the terms of the GNU Lesser General   ////
1761
//// Public License as published by the Free Software Foundation; ////
1762
//// either version 2.1 of the License, or (at your option) any   ////
1763
//// later version.                                               ////
1764
////                                                              ////
1765
//// This source is distributed in the hope that it will be       ////
1766
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1767
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1768
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1769
//// details.                                                     ////
1770
////                                                              ////
1771
//// You should have received a copy of the GNU Lesser General    ////
1772
//// Public License along with this source; if not, download it   ////
1773
//// from http://www.opencores.org/lgpl.shtml                     ////
1774
////                                                              ////
1775
//////////////////////////////////////////////////////////////////////
1776
// GRAY counter
1777 18 unneback
module vl_cnt_gray ( q, rst, clk);
1778 6 unneback
   parameter length = 4;
1779
   output reg [length:1] q;
1780
   input rst;
1781
   input clk;
1782
   parameter clear_value = 0;
1783
   parameter set_value = 1;
1784
   parameter wrap_value = 8;
1785
   parameter level1_value = 15;
1786
   reg  [length:1] qi;
1787
   wire [length:1] q_next;
1788
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1789
   always @ (posedge clk or posedge rst)
1790
     if (rst)
1791
       qi <= {length{1'b0}};
1792
     else
1793
       qi <= q_next;
1794
   always @ (posedge clk or posedge rst)
1795
     if (rst)
1796
       q <= {length{1'b0}};
1797
     else
1798
         q <= (q_next>>1) ^ q_next;
1799
endmodule
1800
//////////////////////////////////////////////////////////////////////
1801
////                                                              ////
1802
////  Versatile counter                                           ////
1803
////                                                              ////
1804
////  Description                                                 ////
1805
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1806
////  counter                                                     ////
1807
////                                                              ////
1808
////  To Do:                                                      ////
1809
////   - add LFSR with more taps                                  ////
1810
////                                                              ////
1811
////  Author(s):                                                  ////
1812
////      - Michael Unneback, unneback@opencores.org              ////
1813
////        ORSoC AB                                              ////
1814
////                                                              ////
1815
//////////////////////////////////////////////////////////////////////
1816
////                                                              ////
1817
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1818
////                                                              ////
1819
//// This source file may be used and distributed without         ////
1820
//// restriction provided that this copyright statement is not    ////
1821
//// removed from the file and that any derivative work contains  ////
1822
//// the original copyright notice and the associated disclaimer. ////
1823
////                                                              ////
1824
//// This source file is free software; you can redistribute it   ////
1825
//// and/or modify it under the terms of the GNU Lesser General   ////
1826
//// Public License as published by the Free Software Foundation; ////
1827
//// either version 2.1 of the License, or (at your option) any   ////
1828
//// later version.                                               ////
1829
////                                                              ////
1830
//// This source is distributed in the hope that it will be       ////
1831
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1832
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1833
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1834
//// details.                                                     ////
1835
////                                                              ////
1836
//// You should have received a copy of the GNU Lesser General    ////
1837
//// Public License along with this source; if not, download it   ////
1838
//// from http://www.opencores.org/lgpl.shtml                     ////
1839
////                                                              ////
1840
//////////////////////////////////////////////////////////////////////
1841
// GRAY counter
1842 18 unneback
module vl_cnt_gray_ce ( cke, q, rst, clk);
1843 6 unneback
   parameter length = 4;
1844
   input cke;
1845
   output reg [length:1] q;
1846
   input rst;
1847
   input clk;
1848
   parameter clear_value = 0;
1849
   parameter set_value = 1;
1850
   parameter wrap_value = 8;
1851
   parameter level1_value = 15;
1852
   reg  [length:1] qi;
1853
   wire [length:1] q_next;
1854
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1855
   always @ (posedge clk or posedge rst)
1856
     if (rst)
1857
       qi <= {length{1'b0}};
1858
     else
1859
     if (cke)
1860
       qi <= q_next;
1861
   always @ (posedge clk or posedge rst)
1862
     if (rst)
1863
       q <= {length{1'b0}};
1864
     else
1865
       if (cke)
1866
         q <= (q_next>>1) ^ q_next;
1867
endmodule
1868
//////////////////////////////////////////////////////////////////////
1869
////                                                              ////
1870
////  Versatile counter                                           ////
1871
////                                                              ////
1872
////  Description                                                 ////
1873
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1874
////  counter                                                     ////
1875
////                                                              ////
1876
////  To Do:                                                      ////
1877
////   - add LFSR with more taps                                  ////
1878
////                                                              ////
1879
////  Author(s):                                                  ////
1880
////      - Michael Unneback, unneback@opencores.org              ////
1881
////        ORSoC AB                                              ////
1882
////                                                              ////
1883
//////////////////////////////////////////////////////////////////////
1884
////                                                              ////
1885
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1886
////                                                              ////
1887
//// This source file may be used and distributed without         ////
1888
//// restriction provided that this copyright statement is not    ////
1889
//// removed from the file and that any derivative work contains  ////
1890
//// the original copyright notice and the associated disclaimer. ////
1891
////                                                              ////
1892
//// This source file is free software; you can redistribute it   ////
1893
//// and/or modify it under the terms of the GNU Lesser General   ////
1894
//// Public License as published by the Free Software Foundation; ////
1895
//// either version 2.1 of the License, or (at your option) any   ////
1896
//// later version.                                               ////
1897
////                                                              ////
1898
//// This source is distributed in the hope that it will be       ////
1899
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1900
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1901
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1902
//// details.                                                     ////
1903
////                                                              ////
1904
//// You should have received a copy of the GNU Lesser General    ////
1905
//// Public License along with this source; if not, download it   ////
1906
//// from http://www.opencores.org/lgpl.shtml                     ////
1907
////                                                              ////
1908
//////////////////////////////////////////////////////////////////////
1909
// GRAY counter
1910 18 unneback
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
1911 6 unneback
   parameter length = 4;
1912
   input cke;
1913
   output reg [length:1] q;
1914
   output [length:1] q_bin;
1915
   input rst;
1916
   input clk;
1917
   parameter clear_value = 0;
1918
   parameter set_value = 1;
1919
   parameter wrap_value = 8;
1920
   parameter level1_value = 15;
1921
   reg  [length:1] qi;
1922
   wire [length:1] q_next;
1923
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1924
   always @ (posedge clk or posedge rst)
1925
     if (rst)
1926
       qi <= {length{1'b0}};
1927
     else
1928
     if (cke)
1929
       qi <= q_next;
1930
   always @ (posedge clk or posedge rst)
1931
     if (rst)
1932
       q <= {length{1'b0}};
1933
     else
1934
       if (cke)
1935
         q <= (q_next>>1) ^ q_next;
1936
   assign q_bin = qi;
1937
endmodule
1938
//////////////////////////////////////////////////////////////////////
1939
////                                                              ////
1940
////  Versatile library, counters                                 ////
1941
////                                                              ////
1942
////  Description                                                 ////
1943
////  counters                                                    ////
1944
////                                                              ////
1945
////                                                              ////
1946
////  To Do:                                                      ////
1947
////   - add more counters                                        ////
1948
////                                                              ////
1949
////  Author(s):                                                  ////
1950
////      - Michael Unneback, unneback@opencores.org              ////
1951
////        ORSoC AB                                              ////
1952
////                                                              ////
1953
//////////////////////////////////////////////////////////////////////
1954
////                                                              ////
1955
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1956
////                                                              ////
1957
//// This source file may be used and distributed without         ////
1958
//// restriction provided that this copyright statement is not    ////
1959
//// removed from the file and that any derivative work contains  ////
1960
//// the original copyright notice and the associated disclaimer. ////
1961
////                                                              ////
1962
//// This source file is free software; you can redistribute it   ////
1963
//// and/or modify it under the terms of the GNU Lesser General   ////
1964
//// Public License as published by the Free Software Foundation; ////
1965
//// either version 2.1 of the License, or (at your option) any   ////
1966
//// later version.                                               ////
1967
////                                                              ////
1968
//// This source is distributed in the hope that it will be       ////
1969
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1970
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1971
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1972
//// details.                                                     ////
1973
////                                                              ////
1974
//// You should have received a copy of the GNU Lesser General    ////
1975
//// Public License along with this source; if not, download it   ////
1976
//// from http://www.opencores.org/lgpl.shtml                     ////
1977
////                                                              ////
1978
//////////////////////////////////////////////////////////////////////
1979 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
1980 6 unneback
   parameter length = 4;
1981
   output reg [0:length-1] q;
1982
   input rst;
1983
   input clk;
1984
    always @ (posedge clk or posedge rst)
1985
    if (rst)
1986
        q <= {1'b1,{length-1{1'b0}}};
1987
    else
1988
        q <= {q[length-1],q[0:length-2]};
1989
endmodule
1990 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
1991 6 unneback
   parameter length = 4;
1992
   input cke;
1993
   output reg [0:length-1] q;
1994
   input rst;
1995
   input clk;
1996
    always @ (posedge clk or posedge rst)
1997
    if (rst)
1998
        q <= {1'b1,{length-1{1'b0}}};
1999
    else
2000
        if (cke)
2001
            q <= {q[length-1],q[0:length-2]};
2002
endmodule
2003 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
2004 6 unneback
   parameter length = 4;
2005
   input cke, clear;
2006
   output reg [0:length-1] q;
2007
   input rst;
2008
   input clk;
2009
    always @ (posedge clk or posedge rst)
2010
    if (rst)
2011
        q <= {1'b1,{length-1{1'b0}}};
2012
    else
2013
        if (cke)
2014
            if (clear)
2015
                q <= {1'b1,{length-1{1'b0}}};
2016
            else
2017
                q <= q >> 1;
2018
endmodule
2019 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
2020 6 unneback
   parameter length = 4;
2021
   input cke, clear;
2022
   output reg [0:length-1] q;
2023
   input rst;
2024
   input clk;
2025
    always @ (posedge clk or posedge rst)
2026
    if (rst)
2027
        q <= {1'b1,{length-1{1'b0}}};
2028
    else
2029
        if (cke)
2030
            if (clear)
2031
                q <= {1'b1,{length-1{1'b0}}};
2032
            else
2033
            q <= {q[length-1],q[0:length-2]};
2034
endmodule
2035
//////////////////////////////////////////////////////////////////////
2036
////                                                              ////
2037
////  Versatile library, memories                                 ////
2038
////                                                              ////
2039
////  Description                                                 ////
2040
////  memories                                                    ////
2041
////                                                              ////
2042
////                                                              ////
2043
////  To Do:                                                      ////
2044
////   - add more memory types                                    ////
2045
////                                                              ////
2046
////  Author(s):                                                  ////
2047
////      - Michael Unneback, unneback@opencores.org              ////
2048
////        ORSoC AB                                              ////
2049
////                                                              ////
2050
//////////////////////////////////////////////////////////////////////
2051
////                                                              ////
2052
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2053
////                                                              ////
2054
//// This source file may be used and distributed without         ////
2055
//// restriction provided that this copyright statement is not    ////
2056
//// removed from the file and that any derivative work contains  ////
2057
//// the original copyright notice and the associated disclaimer. ////
2058
////                                                              ////
2059
//// This source file is free software; you can redistribute it   ////
2060
//// and/or modify it under the terms of the GNU Lesser General   ////
2061
//// Public License as published by the Free Software Foundation; ////
2062
//// either version 2.1 of the License, or (at your option) any   ////
2063
//// later version.                                               ////
2064
////                                                              ////
2065
//// This source is distributed in the hope that it will be       ////
2066
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2067
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2068
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2069
//// details.                                                     ////
2070
////                                                              ////
2071
//// You should have received a copy of the GNU Lesser General    ////
2072
//// Public License along with this source; if not, download it   ////
2073
//// from http://www.opencores.org/lgpl.shtml                     ////
2074
////                                                              ////
2075
//////////////////////////////////////////////////////////////////////
2076
/// ROM
2077 7 unneback
module vl_rom_init ( adr, q, clk);
2078
   parameter data_width = 32;
2079
   parameter addr_width = 8;
2080
   input [(addr_width-1):0]       adr;
2081
   output reg [(data_width-1):0] q;
2082
   input                         clk;
2083
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
2084
   parameter memory_file = "vl_rom.vmem";
2085
   initial
2086
     begin
2087
        $readmemh(memory_file, rom);
2088
     end
2089
   always @ (posedge clk)
2090
     q <= rom[adr];
2091
endmodule
2092 14 unneback
/*
2093 7 unneback
module vl_rom ( adr, q, clk);
2094 6 unneback
parameter data_width = 32;
2095
parameter addr_width = 4;
2096
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
2097
    {32'h18000000},
2098
    {32'hA8200000},
2099
    {32'hA8200000},
2100
    {32'hA8200000},
2101
    {32'h44003000},
2102
    {32'h15000000},
2103
    {32'h15000000},
2104
    {32'h15000000},
2105
    {32'h15000000},
2106
    {32'h15000000},
2107
    {32'h15000000},
2108
    {32'h15000000},
2109
    {32'h15000000},
2110
    {32'h15000000},
2111
    {32'h15000000},
2112
    {32'h15000000}};
2113 7 unneback
input [addr_width-1:0] adr;
2114 6 unneback
output reg [data_width-1:0] q;
2115
input clk;
2116
always @ (posedge clk)
2117 7 unneback
    q <= data[adr];
2118 6 unneback
endmodule
2119 14 unneback
*/
2120 6 unneback
// Single port RAM
2121
module vl_ram ( d, adr, we, q, clk);
2122
   parameter data_width = 32;
2123
   parameter addr_width = 8;
2124
   input [(data_width-1):0]      d;
2125
   input [(addr_width-1):0]       adr;
2126
   input                         we;
2127 7 unneback
   output reg [(data_width-1):0] q;
2128 6 unneback
   input                         clk;
2129
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
2130 7 unneback
   parameter init = 0;
2131
   parameter memory_file = "vl_ram.vmem";
2132
   generate if (init) begin : init_mem
2133
   initial
2134
     begin
2135
        $readmemh(memory_file, ram);
2136
     end
2137
   end
2138
   endgenerate
2139 6 unneback
   always @ (posedge clk)
2140
   begin
2141
   if (we)
2142
     ram[adr] <= d;
2143
   q <= ram[adr];
2144
   end
2145
endmodule
2146 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
2147
   parameter data_width = 32;
2148
   parameter addr_width = 8;
2149
   input [(data_width-1):0]      d;
2150
   input [(addr_width-1):0]       adr;
2151
   input [(addr_width/4)-1:0]    be;
2152
   input                         we;
2153
   output reg [(data_width-1):0] q;
2154
   input                         clk;
2155
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
2156
   parameter init = 0;
2157
   parameter memory_file = "vl_ram.vmem";
2158
   generate if (init) begin : init_mem
2159
   initial
2160
     begin
2161
        $readmemh(memory_file, ram);
2162
     end
2163
   end
2164
   endgenerate
2165
   genvar i;
2166
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
2167
      always @ (posedge clk)
2168
      if (we & be[i])
2169
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
2170
   end
2171
   endgenerate
2172
   always @ (posedge clk)
2173
      q <= ram[adr];
2174
endmodule
2175 6 unneback
// Dual port RAM
2176
// ACTEL FPGA should not use logic to handle rw collision
2177 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
2178 6 unneback
   parameter data_width = 32;
2179
   parameter addr_width = 8;
2180
   input [(data_width-1):0]      d_a;
2181
   input [(addr_width-1):0]       adr_a;
2182
   input [(addr_width-1):0]       adr_b;
2183
   input                         we_a;
2184
   output [(data_width-1):0]      q_b;
2185
   input                         clk_a, clk_b;
2186
   reg [(addr_width-1):0]         adr_b_reg;
2187
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
2188 7 unneback
   parameter init = 0;
2189
   parameter memory_file = "vl_ram.vmem";
2190
   generate if (init) begin : init_mem
2191
   initial
2192
     begin
2193
        $readmemh(memory_file, ram);
2194
     end
2195
   end
2196
   endgenerate
2197 6 unneback
   always @ (posedge clk_a)
2198
   if (we_a)
2199
     ram[adr_a] <= d_a;
2200
   always @ (posedge clk_b)
2201
   adr_b_reg <= adr_b;
2202
   assign q_b = ram[adr_b_reg];
2203
endmodule
2204 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
2205 6 unneback
   parameter data_width = 32;
2206
   parameter addr_width = 8;
2207
   input [(data_width-1):0]      d_a;
2208
   input [(addr_width-1):0]       adr_a;
2209
   input [(addr_width-1):0]       adr_b;
2210
   input                         we_a;
2211
   output [(data_width-1):0]      q_b;
2212
   output reg [(data_width-1):0] q_a;
2213
   input                         clk_a, clk_b;
2214
   reg [(data_width-1):0]         q_b;
2215
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
2216 7 unneback
   parameter init = 0;
2217
   parameter memory_file = "vl_ram.vmem";
2218
   generate if (init) begin : init_mem
2219
   initial
2220
     begin
2221
        $readmemh(memory_file, ram);
2222
     end
2223
   end
2224
   endgenerate
2225 6 unneback
   always @ (posedge clk_a)
2226
     begin
2227
        q_a <= ram[adr_a];
2228
        if (we_a)
2229
             ram[adr_a] <= d_a;
2230
     end
2231
   always @ (posedge clk_b)
2232
          q_b <= ram[adr_b];
2233
endmodule
2234 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
2235 6 unneback
   parameter data_width = 32;
2236
   parameter addr_width = 8;
2237
   input [(data_width-1):0]      d_a;
2238
   input [(addr_width-1):0]       adr_a;
2239
   input [(addr_width-1):0]       adr_b;
2240
   input                         we_a;
2241
   output [(data_width-1):0]      q_b;
2242
   input [(data_width-1):0]       d_b;
2243
   output reg [(data_width-1):0] q_a;
2244
   input                         we_b;
2245
   input                         clk_a, clk_b;
2246
   reg [(data_width-1):0]         q_b;
2247
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
2248 7 unneback
   parameter init = 0;
2249
   parameter memory_file = "vl_ram.vmem";
2250
   generate if (init) begin : init_mem
2251
   initial
2252
     begin
2253
        $readmemh(memory_file, ram);
2254
     end
2255
   end
2256
   endgenerate
2257 6 unneback
   always @ (posedge clk_a)
2258
     begin
2259
        q_a <= ram[adr_a];
2260
        if (we_a)
2261
             ram[adr_a] <= d_a;
2262
     end
2263
   always @ (posedge clk_b)
2264
     begin
2265
        q_b <= ram[adr_b];
2266
        if (we_b)
2267
          ram[adr_b] <= d_b;
2268
     end
2269
endmodule
2270
// Content addresable memory, CAM
2271
// FIFO
2272 25 unneback
module vl_fifo_1r1w_fill_level_sync (
2273
    d, wr, fifo_full,
2274
    q, rd, fifo_empty,
2275
    fill_level,
2276
    clk, rst
2277
    );
2278
parameter data_width = 18;
2279
parameter addr_width = 4;
2280
// write side
2281
input  [data_width-1:0] d;
2282
input                   wr;
2283
output                  fifo_full;
2284
// read side
2285
output [data_width-1:0] q;
2286
input                   rd;
2287
output                  fifo_empty;
2288
// common
2289
output [addr_width:0]   fill_level;
2290
input rst, clk;
2291
wire [addr_width:1] wadr, radr;
2292
vl_cnt_bin_ce
2293
    # ( .length(addr_width))
2294
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
2295
vl_cnt_bin_ce
2296
    # (.length(addr_width))
2297
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
2298
vl_dpram_1r1w
2299
    # (.data_width(data_width), .addr_width(addr_width))
2300
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
2301
vl_cnt_bin_ce_rew_zq_l1
2302 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
2303 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
2304
endmodule
2305 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
2306
// RAM is supposed to be larger than the two FIFOs
2307
// LFSR counters used adr pointers
2308
module vl_fifo_2r2w_sync_simplex (
2309
    // a side
2310
    a_d, a_wr, a_fifo_full,
2311
    a_q, a_rd, a_fifo_empty,
2312
    a_fill_level,
2313
    // b side
2314
    b_d, b_wr, b_fifo_full,
2315
    b_q, b_rd, b_fifo_empty,
2316
    b_fill_level,
2317
    // common
2318
    clk, rst
2319
    );
2320
parameter data_width = 8;
2321
parameter addr_width = 5;
2322
parameter fifo_full_level = (1<<addr_width)-1;
2323
// a side
2324
input  [data_width-1:0] a_d;
2325
input                   a_wr;
2326
output                  a_fifo_full;
2327
output [data_width-1:0] a_q;
2328
input                   a_rd;
2329
output                  a_fifo_empty;
2330
output [addr_width-1:0] a_fill_level;
2331
// b side
2332
input  [data_width-1:0] b_d;
2333
input                   b_wr;
2334
output                  b_fifo_full;
2335
output [data_width-1:0] b_q;
2336
input                   b_rd;
2337
output                  b_fifo_empty;
2338
output [addr_width-1:0] b_fill_level;
2339
input                   clk;
2340
input                   rst;
2341
// adr_gen
2342
wire [addr_width:1] a_wadr, a_radr;
2343
wire [addr_width:1] b_wadr, b_radr;
2344
// dpram
2345
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
2346
vl_cnt_lfsr_ce
2347
    # ( .length(addr_width))
2348
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
2349
vl_cnt_lfsr_ce
2350
    # (.length(addr_width))
2351
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
2352
vl_cnt_lfsr_ce
2353
    # ( .length(addr_width))
2354
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
2355
vl_cnt_lfsr_ce
2356
    # (.length(addr_width))
2357
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
2358
// mux read or write adr to DPRAM
2359
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
2360
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
2361
vl_dpram_2r2w
2362
    # (.data_width(data_width), .addr_width(addr_width+1))
2363
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
2364
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
2365
vl_cnt_bin_ce_rew_zq_l1
2366 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
2367 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
2368
vl_cnt_bin_ce_rew_zq_l1
2369 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
2370 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
2371
endmodule
2372 6 unneback
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
2373 11 unneback
   parameter addr_width = 4;
2374
   parameter N = addr_width-1;
2375 6 unneback
   parameter Q1 = 2'b00;
2376
   parameter Q2 = 2'b01;
2377
   parameter Q3 = 2'b11;
2378
   parameter Q4 = 2'b10;
2379
   parameter going_empty = 1'b0;
2380
   parameter going_full  = 1'b1;
2381
   input [N:0]  wptr, rptr;
2382 14 unneback
   output       fifo_empty;
2383 6 unneback
   output       fifo_full;
2384
   input        wclk, rclk, rst;
2385
   wire direction;
2386
   reg  direction_set, direction_clr;
2387
   wire async_empty, async_full;
2388
   wire fifo_full2;
2389 14 unneback
   wire fifo_empty2;
2390 6 unneback
   // direction_set
2391
   always @ (wptr[N:N-1] or rptr[N:N-1])
2392
     case ({wptr[N:N-1],rptr[N:N-1]})
2393
       {Q1,Q2} : direction_set <= 1'b1;
2394
       {Q2,Q3} : direction_set <= 1'b1;
2395
       {Q3,Q4} : direction_set <= 1'b1;
2396
       {Q4,Q1} : direction_set <= 1'b1;
2397
       default : direction_set <= 1'b0;
2398
     endcase
2399
   // direction_clear
2400
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
2401
     if (rst)
2402
       direction_clr <= 1'b1;
2403
     else
2404
       case ({wptr[N:N-1],rptr[N:N-1]})
2405
         {Q2,Q1} : direction_clr <= 1'b1;
2406
         {Q3,Q2} : direction_clr <= 1'b1;
2407
         {Q4,Q3} : direction_clr <= 1'b1;
2408
         {Q1,Q4} : direction_clr <= 1'b1;
2409
         default : direction_clr <= 1'b0;
2410
       endcase
2411 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
2412 6 unneback
   assign async_empty = (wptr == rptr) && (direction==going_empty);
2413
   assign async_full  = (wptr == rptr) && (direction==going_full);
2414 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
2415
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
2416 6 unneback
/*
2417
   always @ (posedge wclk or posedge rst or posedge async_full)
2418
     if (rst)
2419
       {fifo_full, fifo_full2} <= 2'b00;
2420
     else if (async_full)
2421
       {fifo_full, fifo_full2} <= 2'b11;
2422
     else
2423
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
2424
*/
2425 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
2426 6 unneback
     if (async_empty)
2427
       {fifo_empty, fifo_empty2} <= 2'b11;
2428
     else
2429 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
2430 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
2431
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
2432 27 unneback
endmodule // async_compb
2433 6 unneback
module vl_fifo_1r1w_async (
2434
    d, wr, fifo_full, wr_clk, wr_rst,
2435
    q, rd, fifo_empty, rd_clk, rd_rst
2436
    );
2437
parameter data_width = 18;
2438
parameter addr_width = 4;
2439
// write side
2440
input  [data_width-1:0] d;
2441
input                   wr;
2442
output                  fifo_full;
2443
input                   wr_clk;
2444
input                   wr_rst;
2445
// read side
2446
output [data_width-1:0] q;
2447
input                   rd;
2448
output                  fifo_empty;
2449
input                   rd_clk;
2450
input                   rd_rst;
2451
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
2452 18 unneback
vl_cnt_gray_ce_bin
2453 6 unneback
    # ( .length(addr_width))
2454
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
2455 18 unneback
vl_cnt_gray_ce_bin
2456 6 unneback
    # (.length(addr_width))
2457 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
2458 7 unneback
vl_dpram_1r1w
2459 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
2460
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
2461
vl_fifo_cmp_async
2462
    # (.addr_width(addr_width))
2463
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
2464
endmodule
2465 8 unneback
module vl_fifo_2r2w_async (
2466 6 unneback
    // a side
2467
    a_d, a_wr, a_fifo_full,
2468
    a_q, a_rd, a_fifo_empty,
2469
    a_clk, a_rst,
2470
    // b side
2471
    b_d, b_wr, b_fifo_full,
2472
    b_q, b_rd, b_fifo_empty,
2473
    b_clk, b_rst
2474
    );
2475
parameter data_width = 18;
2476
parameter addr_width = 4;
2477
// a side
2478
input  [data_width-1:0] a_d;
2479
input                   a_wr;
2480
output                  a_fifo_full;
2481
output [data_width-1:0] a_q;
2482
input                   a_rd;
2483
output                  a_fifo_empty;
2484
input                   a_clk;
2485
input                   a_rst;
2486
// b side
2487
input  [data_width-1:0] b_d;
2488
input                   b_wr;
2489
output                  b_fifo_full;
2490
output [data_width-1:0] b_q;
2491
input                   b_rd;
2492
output                  b_fifo_empty;
2493
input                   b_clk;
2494
input                   b_rst;
2495
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
2496
vl_fifo_1r1w_async_a (
2497
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
2498
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
2499
    );
2500
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
2501
vl_fifo_1r1w_async_b (
2502
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
2503
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
2504
    );
2505
endmodule
2506 8 unneback
module vl_fifo_2r2w_async_simplex (
2507 6 unneback
    // a side
2508
    a_d, a_wr, a_fifo_full,
2509
    a_q, a_rd, a_fifo_empty,
2510
    a_clk, a_rst,
2511
    // b side
2512
    b_d, b_wr, b_fifo_full,
2513
    b_q, b_rd, b_fifo_empty,
2514
    b_clk, b_rst
2515
    );
2516
parameter data_width = 18;
2517
parameter addr_width = 4;
2518
// a side
2519
input  [data_width-1:0] a_d;
2520
input                   a_wr;
2521
output                  a_fifo_full;
2522
output [data_width-1:0] a_q;
2523
input                   a_rd;
2524
output                  a_fifo_empty;
2525
input                   a_clk;
2526
input                   a_rst;
2527
// b side
2528
input  [data_width-1:0] b_d;
2529
input                   b_wr;
2530
output                  b_fifo_full;
2531
output [data_width-1:0] b_q;
2532
input                   b_rd;
2533
output                  b_fifo_empty;
2534
input                   b_clk;
2535
input                   b_rst;
2536
// adr_gen
2537
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
2538
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
2539
// dpram
2540
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
2541 18 unneback
vl_cnt_gray_ce_bin
2542 6 unneback
    # ( .length(addr_width))
2543
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
2544 18 unneback
vl_cnt_gray_ce_bin
2545 6 unneback
    # (.length(addr_width))
2546
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
2547 18 unneback
vl_cnt_gray_ce_bin
2548 6 unneback
    # ( .length(addr_width))
2549
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
2550 18 unneback
vl_cnt_gray_ce_bin
2551 6 unneback
    # (.length(addr_width))
2552
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
2553
// mux read or write adr to DPRAM
2554
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
2555
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
2556 11 unneback
vl_dpram_2r2w
2557 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
2558
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
2559
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
2560 11 unneback
vl_fifo_cmp_async