Subversion Repositories versatile_library

//////////////////////////////////////////////////////////////////////

////                                                              ////

////  Versatile library, clock and reset                          ////

////                                                              ////

////  Description                                                 ////

////  Logic related to clock and reset                            ////

////                                                              ////

////                                                              ////

////  To Do:                                                      ////

////   - add more different registers                             ////

////                                                              ////

////  Author(s):                                                  ////

////      - Michael Unneback, unneback@opencores.org              ////

////        ORSoC AB                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

// Global buffer

// usage:

// use to enable global buffers for high fan out signals such as clock and reset

`timescale 1 ns/100 ps

// Version: 8.4 8.4.0.33

module gbuf(GL,CLK);

output GL;

input  CLK;

    wire GND;

    GND GND_1_net(.Y(GND));

    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),

        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;

endmodule

`timescale 1 ns/1 ns

module vl_gbuf ( i, o);

input i;

output o;

`ifdef SIM_GBUF

assign o=i;

`else

gbuf gbuf_i0 ( .CLK(i), .GL(o));

`endif

endmodule

 //ACTEL

// sync reset

// input active lo async reset, normally from external reset generator and/or switch

// output active high global reset sync with two DFFs 

`timescale 1 ns/100 ps

module vl_sync_rst ( rst_n_i, rst_o, clk);

input rst_n_i, clk;

output rst_o;

reg [1:0] tmp;

always @ (posedge clk or negedge rst_n_i)

if (!rst_n_i)

        tmp <= 2'b11;

else

        tmp <= {1'b0,tmp[0]};

vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));

endmodule

// vl_pll

`timescale 1 ps/1 ps

module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);

parameter index = 0;

parameter number_of_clk = 1;

parameter period_time_0 = 20000;

parameter period_time_1 = 20000;

parameter period_time_2 = 20000;

parameter lock_delay = 2000000;

input clk_i, rst_n_i;

output lock;

output reg [0:number_of_clk-1] clk_o;

output [0:number_of_clk-1] rst_o;

`ifdef SIM_PLL

always

     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];

generate if (number_of_clk > 1)

always

     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];

endgenerate

generate if (number_of_clk > 2)

always

     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];

endgenerate

genvar i;

generate for (i=0;i<number_of_clk;i=i+1) begin: clock

     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));

end

endgenerate

assign #lock_delay lock = rst_n_i;

endmodule

`else

generate if (number_of_clk==1 & index==0) begin

        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));

end

endgenerate // index==0

generate if (number_of_clk==1 & index==1) begin

        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));

end

endgenerate // index==1

generate if (number_of_clk==1 & index==2) begin

        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));

end

endgenerate // index==2

generate if (number_of_clk==1 & index==3) begin

        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));

end

endgenerate // index==0

generate if (number_of_clk==2 & index==0) begin

        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));

end

endgenerate // index==0

generate if (number_of_clk==2 & index==1) begin

        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));

end

endgenerate // index==1

generate if (number_of_clk==2 & index==2) begin

        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));

end

endgenerate // index==2

generate if (number_of_clk==2 & index==3) begin

        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));

end

endgenerate // index==0

generate if (number_of_clk==3 & index==0) begin

        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));

end

endgenerate // index==0

generate if (number_of_clk==3 & index==1) begin

        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));

end

endgenerate // index==1

generate if (number_of_clk==3 & index==2) begin

        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));

end

endgenerate // index==2

generate if (number_of_clk==3 & index==3) begin

        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));

end

endgenerate // index==0

genvar i;

generate for (i=0;i<number_of_clk;i=i+1) begin: clock

        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));

end

endgenerate

endmodule

`endif

 //actel

//////////////////////////////////////////////////////////////////////

////                                                              ////

////  Versatile library, registers                                ////

////                                                              ////

////  Description                                                 ////

////  Different type of registers                                 ////

////                                                              ////

////                                                              ////

////  To Do:                                                      ////

////   - add more different registers                             ////

////                                                              ////

////  Author(s):                                                  ////

////      - Michael Unneback, unneback@opencores.org              ////

////        ORSoC AB                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

module vl_dff ( d, q, clk, rst);

        parameter width = 1;

        parameter reset_value = 0;

        input [width-1:0] d;

        input clk, rst;

        output reg [width-1:0] q;

        always @ (posedge clk or posedge rst)

        if (rst)

                q <= reset_value;

        else

                q <= d;

endmodule

module vl_dff_array ( d, q, clk, rst);

        parameter width = 1;

        parameter depth = 2;

        parameter reset_value = 1'b0;

        input [width-1:0] d;

        input clk, rst;

        output [width-1:0] q;

        reg  [0:depth-1] q_tmp [width-1:0];

        integer i;

        always @ (posedge clk or posedge rst)

        if (rst) begin

            for (i=0;i<depth;i=i+1)

                q_tmp[i] <= {width{reset_value}};

        end else begin

            q_tmp[0] <= d;

            for (i=1;i<depth;i=i+1)

                q_tmp[i] <= q_tmp[i-1];

        end

    assign q = q_tmp[depth-1];

endmodule

module vl_dff_ce ( d, ce, q, clk, rst);

        parameter width = 1;

        parameter reset_value = 0;

        input [width-1:0] d;

        input ce, clk, rst;

        output reg [width-1:0] q;

        always @ (posedge clk or posedge rst)

        if (rst)

                q <= reset_value;

        else

                if (ce)

                        q <= d;

endmodule

module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);

        parameter width = 1;

        parameter reset_value = 0;

        input [width-1:0] d;

        input ce, clear, clk, rst;

        output reg [width-1:0] q;

        always @ (posedge clk or posedge rst)

        if (rst)

            q <= reset_value;

        else

            if (ce)

                if (clear)

                    q <= {width{1'b0}};

                else

                    q <= d;

endmodule

module vl_dff_ce_set ( d, ce, set, q, clk, rst);

        parameter width = 1;

        parameter reset_value = 0;

        input [width-1:0] d;

        input ce, set, clk, rst;

        output reg [width-1:0] q;

        always @ (posedge clk or posedge rst)

        if (rst)

            q <= reset_value;

        else

            if (ce)

                if (set)

                    q <= {width{1'b1}};

                else

                    q <= d;

endmodule

module vl_spr ( sp, r, q, clk, rst);

        parameter width = 1;

        parameter reset_value = 0;

        input sp, r;

        output reg q;

        input clk, rst;

        always @ (posedge clk or posedge rst)

        if (rst)

            q <= reset_value;

        else

            if (sp)

                q <= 1'b1;

            else if (r)

                q <= 1'b0;

endmodule

module vl_srp ( s, rp, q, clk, rst);

        parameter width = 1;

        parameter reset_value = 0;

        input s, rp;

        output reg q;

        input clk, rst;

        always @ (posedge clk or posedge rst)

        if (rst)

            q <= reset_value;

        else

            if (rp)

                q <= 1'b0;

            else if (s)

                q <= 1'b1;

endmodule

module vl_dff_sr ( aclr, aset, clock, data, q);

    input         aclr;

    input         aset;

    input         clock;

    input         data;

    output reg    q;

   always @ (posedge clock or posedge aclr or posedge aset)

     if (aclr)

       q <= 1'b0;

     else if (aset)

       q <= 1'b1;

     else

       q <= data;

endmodule

// LATCH

// For targtes not supporting LATCH use dff_sr with clk=1 and data=1

module latch ( d, le, q, clk);

input d, le;

output q;

input clk;/*

   always @ (posedge direction_set or posedge direction_clr)

     if (direction_clr)

       direction <= going_empty;

     else

       direction <= going_full;*/

endmodule

module vl_shreg ( d, q, clk, rst);

parameter depth = 10;

input d;

output q;

input clk, rst;

reg [1:depth] dffs;

always @ (posedge clk or posedge rst)

if (rst)

    dffs <= {depth{1'b0}};

else

    dffs <= {d,dffs[1:depth-1]};

assign q = dffs[depth];

endmodule

module vl_shreg_ce ( d, ce, q, clk, rst);

parameter depth = 10;

input d, ce;

output q;

input clk, rst;

reg [1:depth] dffs;

always @ (posedge clk or posedge rst)

if (rst)

    dffs <= {depth{1'b0}};

else

    if (ce)

        dffs <= {d,dffs[1:depth-1]};

assign q = dffs[depth];

endmodule

module vl_delay ( d, q, clk, rst);

parameter depth = 10;

input d;

output q;

input clk, rst;

reg [1:depth] dffs;

always @ (posedge clk or posedge rst)

if (rst)

    dffs <= {depth{1'b0}};

else

    dffs <= {d,dffs[1:depth-1]};

assign q = dffs[depth];

endmodule

module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);

parameter depth = 10;

input d;

output q, emptyflag;

input clk, rst;

reg [1:depth] dffs;

always @ (posedge clk or posedge rst)

if (rst)

    dffs <= {depth{1'b0}};

else

    dffs <= {d,dffs[1:depth-1]};

assign q = dffs[depth];

assign emptyflag = !(|dffs);

endmodule

//////////////////////////////////////////////////////////////////////

////                                                              ////

////  Logic functions                                             ////

////                                                              ////

////  Description                                                 ////

////  Logic functions such as multiplexers                        ////

////                                                              ////

////                                                              ////

////  To Do:                                                      ////

////   -                                                          ////

////                                                              ////

////  Author(s):                                                  ////

////      - Michael Unneback, unneback@opencores.org              ////

////        ORSoC AB                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);

parameter width = 32;

parameter nr_of_ports = 4;

input [width-1:0] a3, a2, a1, a0;

input [nr_of_ports-1:0] sel;

output [width-1:0] dout;

wire [width-1:0] tmp [nr_of_ports-1:0];

integer i;

// and

assign tmp[0] = {width{sel[0]}} & a0;

assign tmp[1] = {width{sel[1]}} & a1;

assign tmp[2] = {width{sel[2]}} & a2;

assign tmp[3] = {width{sel[3]}} & a3;

// or

assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];

endmodule

module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);

parameter width = 32;

parameter nr_of_ports = 5;

input [width-1:0] a4, a3, a2, a1, a0;

input [nr_of_ports-1:0] sel;

output [width-1:0] dout;

wire [width-1:0] tmp [nr_of_ports-1:0];

integer i;

// and

assign tmp[0] = {width{sel[0]}} & a0;

assign tmp[1] = {width{sel[1]}} & a1;

assign tmp[2] = {width{sel[2]}} & a2;

assign tmp[3] = {width{sel[3]}} & a3;

assign tmp[4] = {width{sel[4]}} & a4;

// or

assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];

endmodule

module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);

parameter width = 32;

parameter nr_of_ports = 6;

input [width-1:0] a5, a4, a3, a2, a1, a0;

input [nr_of_ports-1:0] sel;

output [width-1:0] dout;

wire [width-1:0] tmp [nr_of_ports-1:0];

integer i;

// and

assign tmp[0] = {width{sel[0]}} & a0;

assign tmp[1] = {width{sel[1]}} & a1;

assign tmp[2] = {width{sel[2]}} & a2;

assign tmp[3] = {width{sel[3]}} & a3;

assign tmp[4] = {width{sel[4]}} & a4;

assign tmp[5] = {width{sel[5]}} & a5;

// or

assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];

endmodule

//////////////////////////////////////////////////////////////////////

////                                                              ////

////  Versatile counter                                           ////

////                                                              ////

////  Description                                                 ////

////  Versatile counter, a reconfigurable binary, gray or LFSR    ////

////  counter                                                     ////

////                                                              ////

////  To Do:                                                      ////

////   - add LFSR with more taps                                  ////

////                                                              ////

////  Author(s):                                                  ////

////      - Michael Unneback, unneback@opencores.org              ////

////        ORSoC AB                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

// binary counter

module vl_cnt_bin ( q, rst, clk);

   parameter length = 4;

   output [length:1] q;

   input rst;

   input clk;

   parameter clear_value = 0;

   parameter set_value = 1;

   parameter wrap_value = 0;

   parameter level1_value = 15;

   reg  [length:1] qi;

   wire [length:1] q_next;

   assign q_next = qi + {{length-1{1'b0}},1'b1};

   always @ (posedge clk or posedge rst)

     if (rst)

       qi <= {length{1'b0}};

     else

       qi <= q_next;

   assign q = qi;

endmodule

//////////////////////////////////////////////////////////////////////

////                                                              ////

////  Versatile counter                                           ////

////                                                              ////

////  Description                                                 ////

////  Versatile counter, a reconfigurable binary, gray or LFSR    ////

////  counter                                                     ////

////                                                              ////

////  To Do:                                                      ////

////   - add LFSR with more taps                                  ////

////                                                              ////

////  Author(s):                                                  ////

////      - Michael Unneback, unneback@opencores.org              ////

////        ORSoC AB                                              ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

////                                                              ////

//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////

////                                                              ////

//// This source file may be used and distributed without         ////

//// restriction provided that this copyright statement is not    ////

//// removed from the file and that any derivative work contains  ////

//// the original copyright notice and the associated disclaimer. ////

////                                                              ////

//// This source file is free software; you can redistribute it   ////

//// and/or modify it under the terms of the GNU Lesser General   ////

//// Public License as published by the Free Software Foundation; ////

//// either version 2.1 of the License, or (at your option) any   ////

//// later version.                                               ////

////                                                              ////

//// This source is distributed in the hope that it will be       ////

//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////

//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////

//// PURPOSE.  See the GNU Lesser General Public License for more ////

//// details.                                                     ////

////                                                              ////

//// You should have received a copy of the GNU Lesser General    ////

//// Public License along with this source; if not, download it   ////

//// from http://www.opencores.org/lgpl.shtml                     ////

////                                                              ////

//////////////////////////////////////////////////////////////////////

// binary counter

module vl_cnt_bin_clear ( clear, q, rst, clk);

   parameter length = 4;

   input clear;

   output [length:1] q;