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1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  Versatile library, clock and reset                          ////
4
////                                                              ////
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////  Description                                                 ////
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////  Logic related to clock and reset                            ////
7
////                                                              ////
8
////                                                              ////
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////  To Do:                                                      ////
10
////   - add more different registers                             ////
11
////                                                              ////
12
////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
// Global buffer
43
// usage:
44
// use to enable global buffers for high fan out signals such as clock and reset
45
`timescale 1 ns/100 ps
46
// Version: 8.4 8.4.0.33
47
module gbuf(GL,CLK);
48
output GL;
49
input  CLK;
50
    wire GND;
51
    GND GND_1_net(.Y(GND));
52
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
53
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
54
endmodule
55
`timescale 1 ns/1 ns
56
module vl_gbuf ( i, o);
57
input i;
58
output o;
59
`ifdef SIM_GBUF
60
assign o=i;
61
`else
62
gbuf gbuf_i0 ( .CLK(i), .GL(o));
63
`endif
64
endmodule
65
 //ACTEL
66
// sync reset
67 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
68 6 unneback
// output active high global reset sync with two DFFs 
69
`timescale 1 ns/100 ps
70
module vl_sync_rst ( rst_n_i, rst_o, clk);
71
input rst_n_i, clk;
72
output rst_o;
73 18 unneback
reg [1:0] tmp;
74 6 unneback
always @ (posedge clk or negedge rst_n_i)
75
if (!rst_n_i)
76 17 unneback
        tmp <= 2'b11;
77 6 unneback
else
78 17 unneback
        tmp <= {1'b0,tmp[0]};
79
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
80 6 unneback
endmodule
81
// vl_pll
82 17 unneback
`timescale 1 ps/1 ps
83 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
84
parameter index = 0;
85
parameter number_of_clk = 1;
86 17 unneback
parameter period_time_0 = 20000;
87
parameter period_time_1 = 20000;
88
parameter period_time_2 = 20000;
89
parameter lock_delay = 2000000;
90 6 unneback
input clk_i, rst_n_i;
91
output lock;
92
output reg [0:number_of_clk-1] clk_o;
93
output [0:number_of_clk-1] rst_o;
94
`ifdef SIM_PLL
95
always
96
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
97
generate if (number_of_clk > 1)
98
always
99
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
100
endgenerate
101
generate if (number_of_clk > 2)
102
always
103
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
104
endgenerate
105
genvar i;
106
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
107
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
108
end
109
endgenerate
110
assign #lock_delay lock = rst_n_i;
111
endmodule
112
`else
113
generate if (number_of_clk==1 & index==0) begin
114
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
115
end
116
endgenerate // index==0
117
generate if (number_of_clk==1 & index==1) begin
118
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
119
end
120
endgenerate // index==1
121
generate if (number_of_clk==1 & index==2) begin
122
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
123
end
124
endgenerate // index==2
125
generate if (number_of_clk==1 & index==3) begin
126
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
127
end
128
endgenerate // index==0
129
generate if (number_of_clk==2 & index==0) begin
130
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
131
end
132
endgenerate // index==0
133
generate if (number_of_clk==2 & index==1) begin
134
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
135
end
136
endgenerate // index==1
137
generate if (number_of_clk==2 & index==2) begin
138
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
139
end
140
endgenerate // index==2
141
generate if (number_of_clk==2 & index==3) begin
142
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
143
end
144
endgenerate // index==0
145
generate if (number_of_clk==3 & index==0) begin
146
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
147
end
148
endgenerate // index==0
149
generate if (number_of_clk==3 & index==1) begin
150
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
151
end
152
endgenerate // index==1
153
generate if (number_of_clk==3 & index==2) begin
154
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
155
end
156
endgenerate // index==2
157
generate if (number_of_clk==3 & index==3) begin
158
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
159
end
160
endgenerate // index==0
161
genvar i;
162
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
163
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
164
end
165
endgenerate
166
endmodule
167
`endif
168
 //actel
169
//////////////////////////////////////////////////////////////////////
170
////                                                              ////
171
////  Versatile library, registers                                ////
172
////                                                              ////
173
////  Description                                                 ////
174
////  Different type of registers                                 ////
175
////                                                              ////
176
////                                                              ////
177
////  To Do:                                                      ////
178
////   - add more different registers                             ////
179
////                                                              ////
180
////  Author(s):                                                  ////
181
////      - Michael Unneback, unneback@opencores.org              ////
182
////        ORSoC AB                                              ////
183
////                                                              ////
184
//////////////////////////////////////////////////////////////////////
185
////                                                              ////
186
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
187
////                                                              ////
188
//// This source file may be used and distributed without         ////
189
//// restriction provided that this copyright statement is not    ////
190
//// removed from the file and that any derivative work contains  ////
191
//// the original copyright notice and the associated disclaimer. ////
192
////                                                              ////
193
//// This source file is free software; you can redistribute it   ////
194
//// and/or modify it under the terms of the GNU Lesser General   ////
195
//// Public License as published by the Free Software Foundation; ////
196
//// either version 2.1 of the License, or (at your option) any   ////
197
//// later version.                                               ////
198
////                                                              ////
199
//// This source is distributed in the hope that it will be       ////
200
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
201
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
202
//// PURPOSE.  See the GNU Lesser General Public License for more ////
203
//// details.                                                     ////
204
////                                                              ////
205
//// You should have received a copy of the GNU Lesser General    ////
206
//// Public License along with this source; if not, download it   ////
207
//// from http://www.opencores.org/lgpl.shtml                     ////
208
////                                                              ////
209
//////////////////////////////////////////////////////////////////////
210 18 unneback
module vl_dff ( d, q, clk, rst);
211 6 unneback
        parameter width = 1;
212
        parameter reset_value = 0;
213
        input [width-1:0] d;
214
        input clk, rst;
215
        output reg [width-1:0] q;
216
        always @ (posedge clk or posedge rst)
217
        if (rst)
218
                q <= reset_value;
219
        else
220
                q <= d;
221
endmodule
222 18 unneback
module vl_dff_array ( d, q, clk, rst);
223 6 unneback
        parameter width = 1;
224
        parameter depth = 2;
225
        parameter reset_value = 1'b0;
226
        input [width-1:0] d;
227
        input clk, rst;
228
        output [width-1:0] q;
229
        reg  [0:depth-1] q_tmp [width-1:0];
230
        integer i;
231
        always @ (posedge clk or posedge rst)
232
        if (rst) begin
233
            for (i=0;i<depth;i=i+1)
234
                q_tmp[i] <= {width{reset_value}};
235
        end else begin
236
            q_tmp[0] <= d;
237
            for (i=1;i<depth;i=i+1)
238
                q_tmp[i] <= q_tmp[i-1];
239
        end
240
    assign q = q_tmp[depth-1];
241
endmodule
242 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
243 6 unneback
        parameter width = 1;
244
        parameter reset_value = 0;
245
        input [width-1:0] d;
246
        input ce, clk, rst;
247
        output reg [width-1:0] q;
248
        always @ (posedge clk or posedge rst)
249
        if (rst)
250
                q <= reset_value;
251
        else
252
                if (ce)
253
                        q <= d;
254
endmodule
255 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
256 8 unneback
        parameter width = 1;
257
        parameter reset_value = 0;
258
        input [width-1:0] d;
259 10 unneback
        input ce, clear, clk, rst;
260 8 unneback
        output reg [width-1:0] q;
261
        always @ (posedge clk or posedge rst)
262
        if (rst)
263
            q <= reset_value;
264
        else
265
            if (ce)
266
                if (clear)
267
                    q <= {width{1'b0}};
268
                else
269
                    q <= d;
270
endmodule
271 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
272
        parameter width = 1;
273
        parameter reset_value = 0;
274
        input [width-1:0] d;
275
        input ce, set, clk, rst;
276
        output reg [width-1:0] q;
277
        always @ (posedge clk or posedge rst)
278
        if (rst)
279
            q <= reset_value;
280
        else
281
            if (ce)
282
                if (set)
283
                    q <= {width{1'b1}};
284
                else
285
                    q <= d;
286
endmodule
287 29 unneback
module vl_spr ( sp, r, q, clk, rst);
288
        parameter width = 1;
289
        parameter reset_value = 0;
290
        input sp, r;
291
        output reg q;
292
        input clk, rst;
293
        always @ (posedge clk or posedge rst)
294
        if (rst)
295
            q <= reset_value;
296
        else
297
            if (sp)
298
                q <= 1'b1;
299
            else if (r)
300
                q <= 1'b0;
301
endmodule
302
module vl_srp ( s, rp, q, clk, rst);
303
        parameter width = 1;
304
        parameter reset_value = 0;
305
        input s, rp;
306
        output reg q;
307
        input clk, rst;
308
        always @ (posedge clk or posedge rst)
309
        if (rst)
310
            q <= reset_value;
311
        else
312
            if (rp)
313
                q <= 1'b0;
314
            else if (s)
315
                q <= 1'b1;
316
endmodule
317 18 unneback
module vl_dff_sr ( aclr, aset, clock, data, q);
318 6 unneback
    input         aclr;
319
    input         aset;
320
    input         clock;
321
    input         data;
322
    output reg    q;
323
   always @ (posedge clock or posedge aclr or posedge aset)
324
     if (aclr)
325
       q <= 1'b0;
326
     else if (aset)
327
       q <= 1'b1;
328
     else
329
       q <= data;
330
endmodule
331
// LATCH
332
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
333
module latch ( d, le, q, clk);
334
input d, le;
335
output q;
336
input clk;/*
337
   always @ (posedge direction_set or posedge direction_clr)
338
     if (direction_clr)
339
       direction <= going_empty;
340
     else
341
       direction <= going_full;*/
342
endmodule
343 18 unneback
module vl_shreg ( d, q, clk, rst);
344 17 unneback
parameter depth = 10;
345
input d;
346
output q;
347
input clk, rst;
348
reg [1:depth] dffs;
349
always @ (posedge clk or posedge rst)
350
if (rst)
351
    dffs <= {depth{1'b0}};
352
else
353
    dffs <= {d,dffs[1:depth-1]};
354
assign q = dffs[depth];
355
endmodule
356 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
357 17 unneback
parameter depth = 10;
358
input d, ce;
359
output q;
360
input clk, rst;
361
reg [1:depth] dffs;
362
always @ (posedge clk or posedge rst)
363
if (rst)
364
    dffs <= {depth{1'b0}};
365
else
366
    if (ce)
367
        dffs <= {d,dffs[1:depth-1]};
368
assign q = dffs[depth];
369
endmodule
370 18 unneback
module vl_delay ( d, q, clk, rst);
371 15 unneback
parameter depth = 10;
372
input d;
373
output q;
374
input clk, rst;
375
reg [1:depth] dffs;
376
always @ (posedge clk or posedge rst)
377
if (rst)
378
    dffs <= {depth{1'b0}};
379
else
380
    dffs <= {d,dffs[1:depth-1]};
381
assign q = dffs[depth];
382
endmodule
383 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
384 17 unneback
parameter depth = 10;
385
input d;
386
output q, emptyflag;
387
input clk, rst;
388
reg [1:depth] dffs;
389
always @ (posedge clk or posedge rst)
390
if (rst)
391
    dffs <= {depth{1'b0}};
392
else
393
    dffs <= {d,dffs[1:depth-1]};
394
assign q = dffs[depth];
395
assign emptyflag = !(|dffs);
396
endmodule
397 6 unneback
//////////////////////////////////////////////////////////////////////
398
////                                                              ////
399 18 unneback
////  Logic functions                                             ////
400
////                                                              ////
401
////  Description                                                 ////
402
////  Logic functions such as multiplexers                        ////
403
////                                                              ////
404
////                                                              ////
405
////  To Do:                                                      ////
406
////   -                                                          ////
407
////                                                              ////
408
////  Author(s):                                                  ////
409
////      - Michael Unneback, unneback@opencores.org              ////
410
////        ORSoC AB                                              ////
411
////                                                              ////
412
//////////////////////////////////////////////////////////////////////
413
////                                                              ////
414
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
415
////                                                              ////
416
//// This source file may be used and distributed without         ////
417
//// restriction provided that this copyright statement is not    ////
418
//// removed from the file and that any derivative work contains  ////
419
//// the original copyright notice and the associated disclaimer. ////
420
////                                                              ////
421
//// This source file is free software; you can redistribute it   ////
422
//// and/or modify it under the terms of the GNU Lesser General   ////
423
//// Public License as published by the Free Software Foundation; ////
424
//// either version 2.1 of the License, or (at your option) any   ////
425
//// later version.                                               ////
426
////                                                              ////
427
//// This source is distributed in the hope that it will be       ////
428
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
429
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
430
//// PURPOSE.  See the GNU Lesser General Public License for more ////
431
//// details.                                                     ////
432
////                                                              ////
433
//// You should have received a copy of the GNU Lesser General    ////
434
//// Public License along with this source; if not, download it   ////
435
//// from http://www.opencores.org/lgpl.shtml                     ////
436
////                                                              ////
437
//////////////////////////////////////////////////////////////////////
438
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
439
parameter width = 32;
440
parameter nr_of_ports = 4;
441
input [width-1:0] a3, a2, a1, a0;
442
input [nr_of_ports-1:0] sel;
443 22 unneback
output [width-1:0] dout;
444 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
445 18 unneback
integer i;
446
// and
447
assign tmp[0] = {width{sel[0]}} & a0;
448
assign tmp[1] = {width{sel[1]}} & a1;
449
assign tmp[2] = {width{sel[2]}} & a2;
450
assign tmp[3] = {width{sel[3]}} & a3;
451
// or
452
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
453
endmodule
454
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
455
parameter width = 32;
456
parameter nr_of_ports = 5;
457
input [width-1:0] a4, a3, a2, a1, a0;
458
input [nr_of_ports-1:0] sel;
459 22 unneback
output [width-1:0] dout;
460 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
461 18 unneback
integer i;
462
// and
463
assign tmp[0] = {width{sel[0]}} & a0;
464
assign tmp[1] = {width{sel[1]}} & a1;
465
assign tmp[2] = {width{sel[2]}} & a2;
466
assign tmp[3] = {width{sel[3]}} & a3;
467
assign tmp[4] = {width{sel[4]}} & a4;
468
// or
469
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
470
endmodule
471
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
472
parameter width = 32;
473
parameter nr_of_ports = 6;
474
input [width-1:0] a5, a4, a3, a2, a1, a0;
475
input [nr_of_ports-1:0] sel;
476 22 unneback
output [width-1:0] dout;
477 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
478 18 unneback
integer i;
479
// and
480
assign tmp[0] = {width{sel[0]}} & a0;
481
assign tmp[1] = {width{sel[1]}} & a1;
482
assign tmp[2] = {width{sel[2]}} & a2;
483
assign tmp[3] = {width{sel[3]}} & a3;
484
assign tmp[4] = {width{sel[4]}} & a4;
485
assign tmp[5] = {width{sel[5]}} & a5;
486
// or
487
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
488
endmodule
489
//////////////////////////////////////////////////////////////////////
490
////                                                              ////
491 6 unneback
////  Versatile counter                                           ////
492
////                                                              ////
493
////  Description                                                 ////
494
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
495
////  counter                                                     ////
496
////                                                              ////
497
////  To Do:                                                      ////
498
////   - add LFSR with more taps                                  ////
499
////                                                              ////
500
////  Author(s):                                                  ////
501
////      - Michael Unneback, unneback@opencores.org              ////
502
////        ORSoC AB                                              ////
503
////                                                              ////
504
//////////////////////////////////////////////////////////////////////
505
////                                                              ////
506
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
507
////                                                              ////
508
//// This source file may be used and distributed without         ////
509
//// restriction provided that this copyright statement is not    ////
510
//// removed from the file and that any derivative work contains  ////
511
//// the original copyright notice and the associated disclaimer. ////
512
////                                                              ////
513
//// This source file is free software; you can redistribute it   ////
514
//// and/or modify it under the terms of the GNU Lesser General   ////
515
//// Public License as published by the Free Software Foundation; ////
516
//// either version 2.1 of the License, or (at your option) any   ////
517
//// later version.                                               ////
518
////                                                              ////
519
//// This source is distributed in the hope that it will be       ////
520
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
521
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
522
//// PURPOSE.  See the GNU Lesser General Public License for more ////
523
//// details.                                                     ////
524
////                                                              ////
525
//// You should have received a copy of the GNU Lesser General    ////
526
//// Public License along with this source; if not, download it   ////
527
//// from http://www.opencores.org/lgpl.shtml                     ////
528
////                                                              ////
529
//////////////////////////////////////////////////////////////////////
530
// binary counter
531 22 unneback
module vl_cnt_bin ( q, rst, clk);
532
   parameter length = 4;
533
   output [length:1] q;
534
   input rst;
535
   input clk;
536
   parameter clear_value = 0;
537
   parameter set_value = 1;
538
   parameter wrap_value = 0;
539
   parameter level1_value = 15;
540
   reg  [length:1] qi;
541
   wire [length:1] q_next;
542
   assign q_next = qi + {{length-1{1'b0}},1'b1};
543
   always @ (posedge clk or posedge rst)
544
     if (rst)
545
       qi <= {length{1'b0}};
546
     else
547
       qi <= q_next;
548
   assign q = qi;
549
endmodule
550
//////////////////////////////////////////////////////////////////////
551
////                                                              ////
552
////  Versatile counter                                           ////
553
////                                                              ////
554
////  Description                                                 ////
555
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
556
////  counter                                                     ////
557
////                                                              ////
558
////  To Do:                                                      ////
559
////   - add LFSR with more taps                                  ////
560
////                                                              ////
561
////  Author(s):                                                  ////
562
////      - Michael Unneback, unneback@opencores.org              ////
563
////        ORSoC AB                                              ////
564
////                                                              ////
565
//////////////////////////////////////////////////////////////////////
566
////                                                              ////
567
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
568
////                                                              ////
569
//// This source file may be used and distributed without         ////
570
//// restriction provided that this copyright statement is not    ////
571
//// removed from the file and that any derivative work contains  ////
572
//// the original copyright notice and the associated disclaimer. ////
573
////                                                              ////
574
//// This source file is free software; you can redistribute it   ////
575
//// and/or modify it under the terms of the GNU Lesser General   ////
576
//// Public License as published by the Free Software Foundation; ////
577
//// either version 2.1 of the License, or (at your option) any   ////
578
//// later version.                                               ////
579
////                                                              ////
580
//// This source is distributed in the hope that it will be       ////
581
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
582
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
583
//// PURPOSE.  See the GNU Lesser General Public License for more ////
584
//// details.                                                     ////
585
////                                                              ////
586
//// You should have received a copy of the GNU Lesser General    ////
587
//// Public License along with this source; if not, download it   ////
588
//// from http://www.opencores.org/lgpl.shtml                     ////
589
////                                                              ////
590
//////////////////////////////////////////////////////////////////////
591
// binary counter
592
module vl_cnt_bin_clear ( clear, q, rst, clk);
593
   parameter length = 4;
594
   input clear;
595
   output [length:1] q;
596
   input rst;
597
   input clk;
598
   parameter clear_value = 0;
599
   parameter set_value = 1;
600
   parameter wrap_value = 0;
601
   parameter level1_value = 15;
602
   reg  [length:1] qi;
603
   wire [length:1] q_next;
604
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
605
   always @ (posedge clk or posedge rst)
606
     if (rst)
607
       qi <= {length{1'b0}};
608
     else
609
       qi <= q_next;
610
   assign q = qi;
611
endmodule
612
//////////////////////////////////////////////////////////////////////
613
////                                                              ////
614
////  Versatile counter                                           ////
615
////                                                              ////
616
////  Description                                                 ////
617
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
618
////  counter                                                     ////
619
////                                                              ////
620
////  To Do:                                                      ////
621
////   - add LFSR with more taps                                  ////
622
////                                                              ////
623
////  Author(s):                                                  ////
624
////      - Michael Unneback, unneback@opencores.org              ////
625
////        ORSoC AB                                              ////
626
////                                                              ////
627
//////////////////////////////////////////////////////////////////////
628
////                                                              ////
629
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
630
////                                                              ////
631
//// This source file may be used and distributed without         ////
632
//// restriction provided that this copyright statement is not    ////
633
//// removed from the file and that any derivative work contains  ////
634
//// the original copyright notice and the associated disclaimer. ////
635
////                                                              ////
636
//// This source file is free software; you can redistribute it   ////
637
//// and/or modify it under the terms of the GNU Lesser General   ////
638
//// Public License as published by the Free Software Foundation; ////
639
//// either version 2.1 of the License, or (at your option) any   ////
640
//// later version.                                               ////
641
////                                                              ////
642
//// This source is distributed in the hope that it will be       ////
643
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
644
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
645
//// PURPOSE.  See the GNU Lesser General Public License for more ////
646
//// details.                                                     ////
647
////                                                              ////
648
//// You should have received a copy of the GNU Lesser General    ////
649
//// Public License along with this source; if not, download it   ////
650
//// from http://www.opencores.org/lgpl.shtml                     ////
651
////                                                              ////
652
//////////////////////////////////////////////////////////////////////
653
// binary counter
654 18 unneback
module vl_cnt_bin_ce ( cke, q, rst, clk);
655 6 unneback
   parameter length = 4;
656
   input cke;
657
   output [length:1] q;
658
   input rst;
659
   input clk;
660
   parameter clear_value = 0;
661
   parameter set_value = 1;
662
   parameter wrap_value = 0;
663
   parameter level1_value = 15;
664
   reg  [length:1] qi;
665
   wire [length:1] q_next;
666
   assign q_next = qi + {{length-1{1'b0}},1'b1};
667
   always @ (posedge clk or posedge rst)
668
     if (rst)
669
       qi <= {length{1'b0}};
670
     else
671
     if (cke)
672
       qi <= q_next;
673
   assign q = qi;
674
endmodule
675
//////////////////////////////////////////////////////////////////////
676
////                                                              ////
677
////  Versatile counter                                           ////
678
////                                                              ////
679
////  Description                                                 ////
680
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
681
////  counter                                                     ////
682
////                                                              ////
683
////  To Do:                                                      ////
684
////   - add LFSR with more taps                                  ////
685
////                                                              ////
686
////  Author(s):                                                  ////
687
////      - Michael Unneback, unneback@opencores.org              ////
688
////        ORSoC AB                                              ////
689
////                                                              ////
690
//////////////////////////////////////////////////////////////////////
691
////                                                              ////
692
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
693
////                                                              ////
694
//// This source file may be used and distributed without         ////
695
//// restriction provided that this copyright statement is not    ////
696
//// removed from the file and that any derivative work contains  ////
697
//// the original copyright notice and the associated disclaimer. ////
698
////                                                              ////
699
//// This source file is free software; you can redistribute it   ////
700
//// and/or modify it under the terms of the GNU Lesser General   ////
701
//// Public License as published by the Free Software Foundation; ////
702
//// either version 2.1 of the License, or (at your option) any   ////
703
//// later version.                                               ////
704
////                                                              ////
705
//// This source is distributed in the hope that it will be       ////
706
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
707
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
708
//// PURPOSE.  See the GNU Lesser General Public License for more ////
709
//// details.                                                     ////
710
////                                                              ////
711
//// You should have received a copy of the GNU Lesser General    ////
712
//// Public License along with this source; if not, download it   ////
713
//// from http://www.opencores.org/lgpl.shtml                     ////
714
////                                                              ////
715
//////////////////////////////////////////////////////////////////////
716
// binary counter
717 18 unneback
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
718 6 unneback
   parameter length = 4;
719
   input clear;
720
   input cke;
721
   output [length:1] q;
722
   input rst;
723
   input clk;
724
   parameter clear_value = 0;
725
   parameter set_value = 1;
726
   parameter wrap_value = 0;
727
   parameter level1_value = 15;
728
   reg  [length:1] qi;
729
   wire [length:1] q_next;
730
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
731
   always @ (posedge clk or posedge rst)
732
     if (rst)
733
       qi <= {length{1'b0}};
734
     else
735
     if (cke)
736
       qi <= q_next;
737
   assign q = qi;
738
endmodule
739
//////////////////////////////////////////////////////////////////////
740
////                                                              ////
741
////  Versatile counter                                           ////
742
////                                                              ////
743
////  Description                                                 ////
744
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
745
////  counter                                                     ////
746
////                                                              ////
747
////  To Do:                                                      ////
748
////   - add LFSR with more taps                                  ////
749
////                                                              ////
750
////  Author(s):                                                  ////
751
////      - Michael Unneback, unneback@opencores.org              ////
752
////        ORSoC AB                                              ////
753
////                                                              ////
754
//////////////////////////////////////////////////////////////////////
755
////                                                              ////
756
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
757
////                                                              ////
758
//// This source file may be used and distributed without         ////
759
//// restriction provided that this copyright statement is not    ////
760
//// removed from the file and that any derivative work contains  ////
761
//// the original copyright notice and the associated disclaimer. ////
762
////                                                              ////
763
//// This source file is free software; you can redistribute it   ////
764
//// and/or modify it under the terms of the GNU Lesser General   ////
765
//// Public License as published by the Free Software Foundation; ////
766
//// either version 2.1 of the License, or (at your option) any   ////
767
//// later version.                                               ////
768
////                                                              ////
769
//// This source is distributed in the hope that it will be       ////
770
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
771
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
772
//// PURPOSE.  See the GNU Lesser General Public License for more ////
773
//// details.                                                     ////
774
////                                                              ////
775
//// You should have received a copy of the GNU Lesser General    ////
776
//// Public License along with this source; if not, download it   ////
777
//// from http://www.opencores.org/lgpl.shtml                     ////
778
////                                                              ////
779
//////////////////////////////////////////////////////////////////////
780
// binary counter
781 29 unneback
module vl_cnt_bin_ce_clear_l1_l2 ( clear, cke, q, level1, level2, rst, clk);
782
   parameter length = 4;
783
   input clear;
784
   input cke;
785
   output [length:1] q;
786
   output reg level1;
787
   output reg level2;
788
   input rst;
789
   input clk;
790
   parameter clear_value = 0;
791
   parameter set_value = 1;
792
   parameter wrap_value = 7;
793
   parameter level1_value = 15;
794
   wire rew;
795
   assign rew=1'b0;
796
   reg  [length:1] qi;
797
   wire [length:1] q_next;
798
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
799
   always @ (posedge clk or posedge rst)
800
     if (rst)
801
       qi <= {length{1'b0}};
802
     else
803
     if (cke)
804
       qi <= q_next;
805
   assign q = qi;
806
    always @ (posedge clk or posedge rst)
807
    if (rst)
808
        level1 <= 1'b0;
809
    else
810
    if (cke)
811
    if (clear)
812
        level1 <= 1'b0;
813
    else if (q_next == level1_value)
814
        level1 <= 1'b1;
815
    else if (qi == level1_value & rew)
816
        level1 <= 1'b0;
817
    always @ (posedge clk or posedge rst)
818
    if (rst)
819
        level2 <= 1'b0;
820
    else
821
    if (cke)
822
    if (clear)
823
        level2 <= 1'b0;
824
    else if (q_next == level2_value)
825
        level2 <= 1'b1;
826
    else if (qi == level2_value & rew)
827
        level2 <= 1'b0;
828
endmodule
829
//////////////////////////////////////////////////////////////////////
830
////                                                              ////
831
////  Versatile counter                                           ////
832
////                                                              ////
833
////  Description                                                 ////
834
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
835
////  counter                                                     ////
836
////                                                              ////
837
////  To Do:                                                      ////
838
////   - add LFSR with more taps                                  ////
839
////                                                              ////
840
////  Author(s):                                                  ////
841
////      - Michael Unneback, unneback@opencores.org              ////
842
////        ORSoC AB                                              ////
843
////                                                              ////
844
//////////////////////////////////////////////////////////////////////
845
////                                                              ////
846
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
847
////                                                              ////
848
//// This source file may be used and distributed without         ////
849
//// restriction provided that this copyright statement is not    ////
850
//// removed from the file and that any derivative work contains  ////
851
//// the original copyright notice and the associated disclaimer. ////
852
////                                                              ////
853
//// This source file is free software; you can redistribute it   ////
854
//// and/or modify it under the terms of the GNU Lesser General   ////
855
//// Public License as published by the Free Software Foundation; ////
856
//// either version 2.1 of the License, or (at your option) any   ////
857
//// later version.                                               ////
858
////                                                              ////
859
//// This source is distributed in the hope that it will be       ////
860
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
861
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
862
//// PURPOSE.  See the GNU Lesser General Public License for more ////
863
//// details.                                                     ////
864
////                                                              ////
865
//// You should have received a copy of the GNU Lesser General    ////
866
//// Public License along with this source; if not, download it   ////
867
//// from http://www.opencores.org/lgpl.shtml                     ////
868
////                                                              ////
869
//////////////////////////////////////////////////////////////////////
870
// binary counter
871 18 unneback
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
872 6 unneback
   parameter length = 4;
873
   input clear;
874
   input set;
875
   input cke;
876
   input rew;
877
   output [length:1] q;
878
   input rst;
879
   input clk;
880
   parameter clear_value = 0;
881
   parameter set_value = 1;
882
   parameter wrap_value = 0;
883
   parameter level1_value = 15;
884
   reg  [length:1] qi;
885
   wire  [length:1] q_next, q_next_fw, q_next_rew;
886
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
887
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
888
   assign q_next = rew ? q_next_rew : q_next_fw;
889
   always @ (posedge clk or posedge rst)
890
     if (rst)
891
       qi <= {length{1'b0}};
892
     else
893
     if (cke)
894
       qi <= q_next;
895
   assign q = qi;
896
endmodule
897
//////////////////////////////////////////////////////////////////////
898
////                                                              ////
899
////  Versatile counter                                           ////
900
////                                                              ////
901
////  Description                                                 ////
902
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
903
////  counter                                                     ////
904
////                                                              ////
905
////  To Do:                                                      ////
906
////   - add LFSR with more taps                                  ////
907
////                                                              ////
908
////  Author(s):                                                  ////
909
////      - Michael Unneback, unneback@opencores.org              ////
910
////        ORSoC AB                                              ////
911
////                                                              ////
912
//////////////////////////////////////////////////////////////////////
913
////                                                              ////
914
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
915
////                                                              ////
916
//// This source file may be used and distributed without         ////
917
//// restriction provided that this copyright statement is not    ////
918
//// removed from the file and that any derivative work contains  ////
919
//// the original copyright notice and the associated disclaimer. ////
920
////                                                              ////
921
//// This source file is free software; you can redistribute it   ////
922
//// and/or modify it under the terms of the GNU Lesser General   ////
923
//// Public License as published by the Free Software Foundation; ////
924
//// either version 2.1 of the License, or (at your option) any   ////
925
//// later version.                                               ////
926
////                                                              ////
927
//// This source is distributed in the hope that it will be       ////
928
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
929
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
930
//// PURPOSE.  See the GNU Lesser General Public License for more ////
931
//// details.                                                     ////
932
////                                                              ////
933
//// You should have received a copy of the GNU Lesser General    ////
934
//// Public License along with this source; if not, download it   ////
935
//// from http://www.opencores.org/lgpl.shtml                     ////
936
////                                                              ////
937
//////////////////////////////////////////////////////////////////////
938
// binary counter
939 18 unneback
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
940 6 unneback
   parameter length = 4;
941
   input cke;
942
   input rew;
943
   output reg level1;
944
   input rst;
945
   input clk;
946
   parameter clear_value = 0;
947
   parameter set_value = 1;
948
   parameter wrap_value = 1;
949
   parameter level1_value = 15;
950 29 unneback
   wire clear;
951
   assign clear=1'b0;
952 6 unneback
   reg  [length:1] qi;
953
   wire  [length:1] q_next, q_next_fw, q_next_rew;
954
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
955
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
956
   assign q_next = rew ? q_next_rew : q_next_fw;
957
   always @ (posedge clk or posedge rst)
958
     if (rst)
959
       qi <= {length{1'b0}};
960
     else
961
     if (cke)
962
       qi <= q_next;
963
    always @ (posedge clk or posedge rst)
964
    if (rst)
965
        level1 <= 1'b0;
966
    else
967
    if (cke)
968 29 unneback
    if (clear)
969
        level1 <= 1'b0;
970
    else if (q_next == level1_value)
971 6 unneback
        level1 <= 1'b1;
972
    else if (qi == level1_value & rew)
973
        level1 <= 1'b0;
974
endmodule
975
//////////////////////////////////////////////////////////////////////
976
////                                                              ////
977
////  Versatile counter                                           ////
978
////                                                              ////
979
////  Description                                                 ////
980
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
981
////  counter                                                     ////
982
////                                                              ////
983
////  To Do:                                                      ////
984
////   - add LFSR with more taps                                  ////
985
////                                                              ////
986
////  Author(s):                                                  ////
987
////      - Michael Unneback, unneback@opencores.org              ////
988
////        ORSoC AB                                              ////
989
////                                                              ////
990
//////////////////////////////////////////////////////////////////////
991
////                                                              ////
992
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
993
////                                                              ////
994
//// This source file may be used and distributed without         ////
995
//// restriction provided that this copyright statement is not    ////
996
//// removed from the file and that any derivative work contains  ////
997
//// the original copyright notice and the associated disclaimer. ////
998
////                                                              ////
999
//// This source file is free software; you can redistribute it   ////
1000
//// and/or modify it under the terms of the GNU Lesser General   ////
1001
//// Public License as published by the Free Software Foundation; ////
1002
//// either version 2.1 of the License, or (at your option) any   ////
1003
//// later version.                                               ////
1004
////                                                              ////
1005
//// This source is distributed in the hope that it will be       ////
1006
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1007
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1008
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1009
//// details.                                                     ////
1010
////                                                              ////
1011
//// You should have received a copy of the GNU Lesser General    ////
1012
//// Public License along with this source; if not, download it   ////
1013
//// from http://www.opencores.org/lgpl.shtml                     ////
1014
////                                                              ////
1015
//////////////////////////////////////////////////////////////////////
1016 25 unneback
// binary counter
1017
module vl_cnt_bin_ce_rew_zq_l1 ( cke, rew, zq, level1, rst, clk);
1018
   parameter length = 4;
1019
   input cke;
1020
   input rew;
1021
   output reg zq;
1022
   output reg level1;
1023
   input rst;
1024
   input clk;
1025
   parameter clear_value = 0;
1026
   parameter set_value = 1;
1027
   parameter wrap_value = 1;
1028
   parameter level1_value = 15;
1029 29 unneback
   wire clear;
1030
   assign clear=1'b0;
1031 25 unneback
   reg  [length:1] qi;
1032
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1033
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1034
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1035
   assign q_next = rew ? q_next_rew : q_next_fw;
1036
   always @ (posedge clk or posedge rst)
1037
     if (rst)
1038
       qi <= {length{1'b0}};
1039
     else
1040
     if (cke)
1041
       qi <= q_next;
1042
   always @ (posedge clk or posedge rst)
1043
     if (rst)
1044
       zq <= 1'b1;
1045
     else
1046
     if (cke)
1047
       zq <= q_next == {length{1'b0}};
1048
    always @ (posedge clk or posedge rst)
1049
    if (rst)
1050
        level1 <= 1'b0;
1051
    else
1052
    if (cke)
1053 29 unneback
    if (clear)
1054
        level1 <= 1'b0;
1055
    else if (q_next == level1_value)
1056 25 unneback
        level1 <= 1'b1;
1057
    else if (qi == level1_value & rew)
1058
        level1 <= 1'b0;
1059
endmodule
1060
//////////////////////////////////////////////////////////////////////
1061
////                                                              ////
1062
////  Versatile counter                                           ////
1063
////                                                              ////
1064
////  Description                                                 ////
1065
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1066
////  counter                                                     ////
1067
////                                                              ////
1068
////  To Do:                                                      ////
1069
////   - add LFSR with more taps                                  ////
1070
////                                                              ////
1071
////  Author(s):                                                  ////
1072
////      - Michael Unneback, unneback@opencores.org              ////
1073
////        ORSoC AB                                              ////
1074
////                                                              ////
1075
//////////////////////////////////////////////////////////////////////
1076
////                                                              ////
1077
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1078
////                                                              ////
1079
//// This source file may be used and distributed without         ////
1080
//// restriction provided that this copyright statement is not    ////
1081
//// removed from the file and that any derivative work contains  ////
1082
//// the original copyright notice and the associated disclaimer. ////
1083
////                                                              ////
1084
//// This source file is free software; you can redistribute it   ////
1085
//// and/or modify it under the terms of the GNU Lesser General   ////
1086
//// Public License as published by the Free Software Foundation; ////
1087
//// either version 2.1 of the License, or (at your option) any   ////
1088
//// later version.                                               ////
1089
////                                                              ////
1090
//// This source is distributed in the hope that it will be       ////
1091
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1092
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1093
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1094
//// details.                                                     ////
1095
////                                                              ////
1096
//// You should have received a copy of the GNU Lesser General    ////
1097
//// Public License along with this source; if not, download it   ////
1098
//// from http://www.opencores.org/lgpl.shtml                     ////
1099
////                                                              ////
1100
//////////////////////////////////////////////////////////////////////
1101
// binary counter
1102
module vl_cnt_bin_ce_rew_q_zq_l1 ( cke, rew, q, zq, level1, rst, clk);
1103
   parameter length = 4;
1104
   input cke;
1105
   input rew;
1106
   output [length:1] q;
1107
   output reg zq;
1108
   output reg level1;
1109
   input rst;
1110
   input clk;
1111
   parameter clear_value = 0;
1112
   parameter set_value = 1;
1113
   parameter wrap_value = 1;
1114
   parameter level1_value = 15;
1115 29 unneback
   wire clear;
1116
   assign clear=1'b0;
1117 25 unneback
   reg  [length:1] qi;
1118
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1119
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1120
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1121
   assign q_next = rew ? q_next_rew : q_next_fw;
1122
   always @ (posedge clk or posedge rst)
1123
     if (rst)
1124
       qi <= {length{1'b0}};
1125
     else
1126
     if (cke)
1127
       qi <= q_next;
1128
   assign q = qi;
1129
   always @ (posedge clk or posedge rst)
1130
     if (rst)
1131
       zq <= 1'b1;
1132
     else
1133
     if (cke)
1134
       zq <= q_next == {length{1'b0}};
1135
    always @ (posedge clk or posedge rst)
1136
    if (rst)
1137
        level1 <= 1'b0;
1138
    else
1139
    if (cke)
1140 29 unneback
    if (clear)
1141
        level1 <= 1'b0;
1142
    else if (q_next == level1_value)
1143 25 unneback
        level1 <= 1'b1;
1144
    else if (qi == level1_value & rew)
1145
        level1 <= 1'b0;
1146
endmodule
1147
//////////////////////////////////////////////////////////////////////
1148
////                                                              ////
1149
////  Versatile counter                                           ////
1150
////                                                              ////
1151
////  Description                                                 ////
1152
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1153
////  counter                                                     ////
1154
////                                                              ////
1155
////  To Do:                                                      ////
1156
////   - add LFSR with more taps                                  ////
1157
////                                                              ////
1158
////  Author(s):                                                  ////
1159
////      - Michael Unneback, unneback@opencores.org              ////
1160
////        ORSoC AB                                              ////
1161
////                                                              ////
1162
//////////////////////////////////////////////////////////////////////
1163
////                                                              ////
1164
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1165
////                                                              ////
1166
//// This source file may be used and distributed without         ////
1167
//// restriction provided that this copyright statement is not    ////
1168
//// removed from the file and that any derivative work contains  ////
1169
//// the original copyright notice and the associated disclaimer. ////
1170
////                                                              ////
1171
//// This source file is free software; you can redistribute it   ////
1172
//// and/or modify it under the terms of the GNU Lesser General   ////
1173
//// Public License as published by the Free Software Foundation; ////
1174
//// either version 2.1 of the License, or (at your option) any   ////
1175
//// later version.                                               ////
1176
////                                                              ////
1177
//// This source is distributed in the hope that it will be       ////
1178
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1179
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1180
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1181
//// details.                                                     ////
1182
////                                                              ////
1183
//// You should have received a copy of the GNU Lesser General    ////
1184
//// Public License along with this source; if not, download it   ////
1185
//// from http://www.opencores.org/lgpl.shtml                     ////
1186
////                                                              ////
1187
//////////////////////////////////////////////////////////////////////
1188 6 unneback
// LFSR counter
1189 18 unneback
module vl_cnt_lfsr_zq ( zq, rst, clk);
1190 6 unneback
   parameter length = 4;
1191
   output reg zq;
1192
   input rst;
1193
   input clk;
1194
   parameter clear_value = 0;
1195
   parameter set_value = 1;
1196
   parameter wrap_value = 8;
1197
   parameter level1_value = 15;
1198
   reg  [length:1] qi;
1199
   reg lfsr_fb;
1200
   wire [length:1] q_next;
1201
   reg [32:1] polynom;
1202
   integer i;
1203
   always @ (qi)
1204
   begin
1205
        case (length)
1206
         2: polynom = 32'b11;                               // 0x3
1207
         3: polynom = 32'b110;                              // 0x6
1208
         4: polynom = 32'b1100;                             // 0xC
1209
         5: polynom = 32'b10100;                            // 0x14
1210
         6: polynom = 32'b110000;                           // 0x30
1211
         7: polynom = 32'b1100000;                          // 0x60
1212
         8: polynom = 32'b10111000;                         // 0xb8
1213
         9: polynom = 32'b100010000;                        // 0x110
1214
        10: polynom = 32'b1001000000;                       // 0x240
1215
        11: polynom = 32'b10100000000;                      // 0x500
1216
        12: polynom = 32'b100000101001;                     // 0x829
1217
        13: polynom = 32'b1000000001100;                    // 0x100C
1218
        14: polynom = 32'b10000000010101;                   // 0x2015
1219
        15: polynom = 32'b110000000000000;                  // 0x6000
1220
        16: polynom = 32'b1101000000001000;                 // 0xD008
1221
        17: polynom = 32'b10010000000000000;                // 0x12000
1222
        18: polynom = 32'b100000010000000000;               // 0x20400
1223
        19: polynom = 32'b1000000000000100011;              // 0x40023
1224
        20: polynom = 32'b10000010000000000000;             // 0x82000
1225
        21: polynom = 32'b101000000000000000000;            // 0x140000
1226
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1227
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1228
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1229
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1230
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1231
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1232
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1233
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1234
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1235
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1236
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1237
        default: polynom = 32'b0;
1238
        endcase
1239
        lfsr_fb = qi[length];
1240
        for (i=length-1; i>=1; i=i-1) begin
1241
            if (polynom[i])
1242
                lfsr_fb = lfsr_fb  ~^ qi[i];
1243
        end
1244
    end
1245
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1246
   always @ (posedge clk or posedge rst)
1247
     if (rst)
1248
       qi <= {length{1'b0}};
1249
     else
1250
       qi <= q_next;
1251
   always @ (posedge clk or posedge rst)
1252
     if (rst)
1253
       zq <= 1'b1;
1254
     else
1255
       zq <= q_next == {length{1'b0}};
1256
endmodule
1257
//////////////////////////////////////////////////////////////////////
1258
////                                                              ////
1259
////  Versatile counter                                           ////
1260
////                                                              ////
1261
////  Description                                                 ////
1262
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1263
////  counter                                                     ////
1264
////                                                              ////
1265
////  To Do:                                                      ////
1266
////   - add LFSR with more taps                                  ////
1267
////                                                              ////
1268
////  Author(s):                                                  ////
1269
////      - Michael Unneback, unneback@opencores.org              ////
1270
////        ORSoC AB                                              ////
1271
////                                                              ////
1272
//////////////////////////////////////////////////////////////////////
1273
////                                                              ////
1274
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1275
////                                                              ////
1276
//// This source file may be used and distributed without         ////
1277
//// restriction provided that this copyright statement is not    ////
1278
//// removed from the file and that any derivative work contains  ////
1279
//// the original copyright notice and the associated disclaimer. ////
1280
////                                                              ////
1281
//// This source file is free software; you can redistribute it   ////
1282
//// and/or modify it under the terms of the GNU Lesser General   ////
1283
//// Public License as published by the Free Software Foundation; ////
1284
//// either version 2.1 of the License, or (at your option) any   ////
1285
//// later version.                                               ////
1286
////                                                              ////
1287
//// This source is distributed in the hope that it will be       ////
1288
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1289
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1290
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1291
//// details.                                                     ////
1292
////                                                              ////
1293
//// You should have received a copy of the GNU Lesser General    ////
1294
//// Public License along with this source; if not, download it   ////
1295
//// from http://www.opencores.org/lgpl.shtml                     ////
1296
////                                                              ////
1297
//////////////////////////////////////////////////////////////////////
1298
// LFSR counter
1299 18 unneback
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
1300 6 unneback
   parameter length = 4;
1301
   input cke;
1302
   output reg zq;
1303
   input rst;
1304
   input clk;
1305
   parameter clear_value = 0;
1306
   parameter set_value = 1;
1307
   parameter wrap_value = 8;
1308
   parameter level1_value = 15;
1309
   reg  [length:1] qi;
1310
   reg lfsr_fb;
1311
   wire [length:1] q_next;
1312
   reg [32:1] polynom;
1313
   integer i;
1314
   always @ (qi)
1315
   begin
1316
        case (length)
1317
         2: polynom = 32'b11;                               // 0x3
1318
         3: polynom = 32'b110;                              // 0x6
1319
         4: polynom = 32'b1100;                             // 0xC
1320
         5: polynom = 32'b10100;                            // 0x14
1321
         6: polynom = 32'b110000;                           // 0x30
1322
         7: polynom = 32'b1100000;                          // 0x60
1323
         8: polynom = 32'b10111000;                         // 0xb8
1324
         9: polynom = 32'b100010000;                        // 0x110
1325
        10: polynom = 32'b1001000000;                       // 0x240
1326
        11: polynom = 32'b10100000000;                      // 0x500
1327
        12: polynom = 32'b100000101001;                     // 0x829
1328
        13: polynom = 32'b1000000001100;                    // 0x100C
1329
        14: polynom = 32'b10000000010101;                   // 0x2015
1330
        15: polynom = 32'b110000000000000;                  // 0x6000
1331
        16: polynom = 32'b1101000000001000;                 // 0xD008
1332
        17: polynom = 32'b10010000000000000;                // 0x12000
1333
        18: polynom = 32'b100000010000000000;               // 0x20400
1334
        19: polynom = 32'b1000000000000100011;              // 0x40023
1335
        20: polynom = 32'b10000010000000000000;             // 0x82000
1336
        21: polynom = 32'b101000000000000000000;            // 0x140000
1337
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1338
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1339
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1340
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1341
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1342
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1343
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1344
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1345
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1346
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1347
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1348
        default: polynom = 32'b0;
1349
        endcase
1350
        lfsr_fb = qi[length];
1351
        for (i=length-1; i>=1; i=i-1) begin
1352
            if (polynom[i])
1353
                lfsr_fb = lfsr_fb  ~^ qi[i];
1354
        end
1355
    end
1356
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1357
   always @ (posedge clk or posedge rst)
1358
     if (rst)
1359
       qi <= {length{1'b0}};
1360
     else
1361
     if (cke)
1362
       qi <= q_next;
1363
   always @ (posedge clk or posedge rst)
1364
     if (rst)
1365
       zq <= 1'b1;
1366
     else
1367
     if (cke)
1368
       zq <= q_next == {length{1'b0}};
1369
endmodule
1370
//////////////////////////////////////////////////////////////////////
1371
////                                                              ////
1372
////  Versatile counter                                           ////
1373
////                                                              ////
1374
////  Description                                                 ////
1375
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1376
////  counter                                                     ////
1377
////                                                              ////
1378
////  To Do:                                                      ////
1379
////   - add LFSR with more taps                                  ////
1380
////                                                              ////
1381
////  Author(s):                                                  ////
1382
////      - Michael Unneback, unneback@opencores.org              ////
1383
////        ORSoC AB                                              ////
1384
////                                                              ////
1385
//////////////////////////////////////////////////////////////////////
1386
////                                                              ////
1387
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1388
////                                                              ////
1389
//// This source file may be used and distributed without         ////
1390
//// restriction provided that this copyright statement is not    ////
1391
//// removed from the file and that any derivative work contains  ////
1392
//// the original copyright notice and the associated disclaimer. ////
1393
////                                                              ////
1394
//// This source file is free software; you can redistribute it   ////
1395
//// and/or modify it under the terms of the GNU Lesser General   ////
1396
//// Public License as published by the Free Software Foundation; ////
1397
//// either version 2.1 of the License, or (at your option) any   ////
1398
//// later version.                                               ////
1399
////                                                              ////
1400
//// This source is distributed in the hope that it will be       ////
1401
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1402
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1403
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1404
//// details.                                                     ////
1405
////                                                              ////
1406
//// You should have received a copy of the GNU Lesser General    ////
1407
//// Public License along with this source; if not, download it   ////
1408
//// from http://www.opencores.org/lgpl.shtml                     ////
1409
////                                                              ////
1410
//////////////////////////////////////////////////////////////////////
1411
// LFSR counter
1412 27 unneback
module vl_cnt_lfsr_ce_q ( cke, q, rst, clk);
1413
   parameter length = 4;
1414
   input cke;
1415
   output [length:1] q;
1416
   input rst;
1417
   input clk;
1418
   parameter clear_value = 0;
1419
   parameter set_value = 1;
1420
   parameter wrap_value = 8;
1421
   parameter level1_value = 15;
1422
   reg  [length:1] qi;
1423
   reg lfsr_fb;
1424
   wire [length:1] q_next;
1425
   reg [32:1] polynom;
1426
   integer i;
1427
   always @ (qi)
1428
   begin
1429
        case (length)
1430
         2: polynom = 32'b11;                               // 0x3
1431
         3: polynom = 32'b110;                              // 0x6
1432
         4: polynom = 32'b1100;                             // 0xC
1433
         5: polynom = 32'b10100;                            // 0x14
1434
         6: polynom = 32'b110000;                           // 0x30
1435
         7: polynom = 32'b1100000;                          // 0x60
1436
         8: polynom = 32'b10111000;                         // 0xb8
1437
         9: polynom = 32'b100010000;                        // 0x110
1438
        10: polynom = 32'b1001000000;                       // 0x240
1439
        11: polynom = 32'b10100000000;                      // 0x500
1440
        12: polynom = 32'b100000101001;                     // 0x829
1441
        13: polynom = 32'b1000000001100;                    // 0x100C
1442
        14: polynom = 32'b10000000010101;                   // 0x2015
1443
        15: polynom = 32'b110000000000000;                  // 0x6000
1444
        16: polynom = 32'b1101000000001000;                 // 0xD008
1445
        17: polynom = 32'b10010000000000000;                // 0x12000
1446
        18: polynom = 32'b100000010000000000;               // 0x20400
1447
        19: polynom = 32'b1000000000000100011;              // 0x40023
1448
        20: polynom = 32'b10000010000000000000;             // 0x82000
1449
        21: polynom = 32'b101000000000000000000;            // 0x140000
1450
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1451
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1452
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1453
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1454
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1455
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1456
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1457
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1458
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1459
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1460
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1461
        default: polynom = 32'b0;
1462
        endcase
1463
        lfsr_fb = qi[length];
1464
        for (i=length-1; i>=1; i=i-1) begin
1465
            if (polynom[i])
1466
                lfsr_fb = lfsr_fb  ~^ qi[i];
1467
        end
1468
    end
1469
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1470
   always @ (posedge clk or posedge rst)
1471
     if (rst)
1472
       qi <= {length{1'b0}};
1473
     else
1474
     if (cke)
1475
       qi <= q_next;
1476
   assign q = qi;
1477
endmodule
1478
//////////////////////////////////////////////////////////////////////
1479
////                                                              ////
1480
////  Versatile counter                                           ////
1481
////                                                              ////
1482
////  Description                                                 ////
1483
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1484
////  counter                                                     ////
1485
////                                                              ////
1486
////  To Do:                                                      ////
1487
////   - add LFSR with more taps                                  ////
1488
////                                                              ////
1489
////  Author(s):                                                  ////
1490
////      - Michael Unneback, unneback@opencores.org              ////
1491
////        ORSoC AB                                              ////
1492
////                                                              ////
1493
//////////////////////////////////////////////////////////////////////
1494
////                                                              ////
1495
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1496
////                                                              ////
1497
//// This source file may be used and distributed without         ////
1498
//// restriction provided that this copyright statement is not    ////
1499
//// removed from the file and that any derivative work contains  ////
1500
//// the original copyright notice and the associated disclaimer. ////
1501
////                                                              ////
1502
//// This source file is free software; you can redistribute it   ////
1503
//// and/or modify it under the terms of the GNU Lesser General   ////
1504
//// Public License as published by the Free Software Foundation; ////
1505
//// either version 2.1 of the License, or (at your option) any   ////
1506
//// later version.                                               ////
1507
////                                                              ////
1508
//// This source is distributed in the hope that it will be       ////
1509
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1510
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1511
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1512
//// details.                                                     ////
1513
////                                                              ////
1514
//// You should have received a copy of the GNU Lesser General    ////
1515
//// Public License along with this source; if not, download it   ////
1516
//// from http://www.opencores.org/lgpl.shtml                     ////
1517
////                                                              ////
1518
//////////////////////////////////////////////////////////////////////
1519
// LFSR counter
1520
module vl_cnt_lfsr_ce_clear_q ( clear, cke, q, rst, clk);
1521
   parameter length = 4;
1522
   input clear;
1523
   input cke;
1524
   output [length:1] q;
1525
   input rst;
1526
   input clk;
1527
   parameter clear_value = 0;
1528
   parameter set_value = 1;
1529
   parameter wrap_value = 8;
1530
   parameter level1_value = 15;
1531
   reg  [length:1] qi;
1532
   reg lfsr_fb;
1533
   wire [length:1] q_next;
1534
   reg [32:1] polynom;
1535
   integer i;
1536
   always @ (qi)
1537
   begin
1538
        case (length)
1539
         2: polynom = 32'b11;                               // 0x3
1540
         3: polynom = 32'b110;                              // 0x6
1541
         4: polynom = 32'b1100;                             // 0xC
1542
         5: polynom = 32'b10100;                            // 0x14
1543
         6: polynom = 32'b110000;                           // 0x30
1544
         7: polynom = 32'b1100000;                          // 0x60
1545
         8: polynom = 32'b10111000;                         // 0xb8
1546
         9: polynom = 32'b100010000;                        // 0x110
1547
        10: polynom = 32'b1001000000;                       // 0x240
1548
        11: polynom = 32'b10100000000;                      // 0x500
1549
        12: polynom = 32'b100000101001;                     // 0x829
1550
        13: polynom = 32'b1000000001100;                    // 0x100C
1551
        14: polynom = 32'b10000000010101;                   // 0x2015
1552
        15: polynom = 32'b110000000000000;                  // 0x6000
1553
        16: polynom = 32'b1101000000001000;                 // 0xD008
1554
        17: polynom = 32'b10010000000000000;                // 0x12000
1555
        18: polynom = 32'b100000010000000000;               // 0x20400
1556
        19: polynom = 32'b1000000000000100011;              // 0x40023
1557
        20: polynom = 32'b10000010000000000000;             // 0x82000
1558
        21: polynom = 32'b101000000000000000000;            // 0x140000
1559
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1560
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1561
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1562
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1563
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1564
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1565
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1566
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1567
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1568
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1569
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1570
        default: polynom = 32'b0;
1571
        endcase
1572
        lfsr_fb = qi[length];
1573
        for (i=length-1; i>=1; i=i-1) begin
1574
            if (polynom[i])
1575
                lfsr_fb = lfsr_fb  ~^ qi[i];
1576
        end
1577
    end
1578
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1579
   always @ (posedge clk or posedge rst)
1580
     if (rst)
1581
       qi <= {length{1'b0}};
1582
     else
1583
     if (cke)
1584
       qi <= q_next;
1585
   assign q = qi;
1586
endmodule
1587
//////////////////////////////////////////////////////////////////////
1588
////                                                              ////
1589
////  Versatile counter                                           ////
1590
////                                                              ////
1591
////  Description                                                 ////
1592
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1593
////  counter                                                     ////
1594
////                                                              ////
1595
////  To Do:                                                      ////
1596
////   - add LFSR with more taps                                  ////
1597
////                                                              ////
1598
////  Author(s):                                                  ////
1599
////      - Michael Unneback, unneback@opencores.org              ////
1600
////        ORSoC AB                                              ////
1601
////                                                              ////
1602
//////////////////////////////////////////////////////////////////////
1603
////                                                              ////
1604
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1605
////                                                              ////
1606
//// This source file may be used and distributed without         ////
1607
//// restriction provided that this copyright statement is not    ////
1608
//// removed from the file and that any derivative work contains  ////
1609
//// the original copyright notice and the associated disclaimer. ////
1610
////                                                              ////
1611
//// This source file is free software; you can redistribute it   ////
1612
//// and/or modify it under the terms of the GNU Lesser General   ////
1613
//// Public License as published by the Free Software Foundation; ////
1614
//// either version 2.1 of the License, or (at your option) any   ////
1615
//// later version.                                               ////
1616
////                                                              ////
1617
//// This source is distributed in the hope that it will be       ////
1618
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1619
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1620
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1621
//// details.                                                     ////
1622
////                                                              ////
1623
//// You should have received a copy of the GNU Lesser General    ////
1624
//// Public License along with this source; if not, download it   ////
1625
//// from http://www.opencores.org/lgpl.shtml                     ////
1626
////                                                              ////
1627
//////////////////////////////////////////////////////////////////////
1628
// LFSR counter
1629 22 unneback
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk);
1630
   parameter length = 4;
1631
   input cke;
1632
   output [length:1] q;
1633
   output reg zq;
1634
   input rst;
1635
   input clk;
1636
   parameter clear_value = 0;
1637
   parameter set_value = 1;
1638
   parameter wrap_value = 8;
1639
   parameter level1_value = 15;
1640
   reg  [length:1] qi;
1641
   reg lfsr_fb;
1642
   wire [length:1] q_next;
1643
   reg [32:1] polynom;
1644
   integer i;
1645
   always @ (qi)
1646
   begin
1647
        case (length)
1648
         2: polynom = 32'b11;                               // 0x3
1649
         3: polynom = 32'b110;                              // 0x6
1650
         4: polynom = 32'b1100;                             // 0xC
1651
         5: polynom = 32'b10100;                            // 0x14
1652
         6: polynom = 32'b110000;                           // 0x30
1653
         7: polynom = 32'b1100000;                          // 0x60
1654
         8: polynom = 32'b10111000;                         // 0xb8
1655
         9: polynom = 32'b100010000;                        // 0x110
1656
        10: polynom = 32'b1001000000;                       // 0x240
1657
        11: polynom = 32'b10100000000;                      // 0x500
1658
        12: polynom = 32'b100000101001;                     // 0x829
1659
        13: polynom = 32'b1000000001100;                    // 0x100C
1660
        14: polynom = 32'b10000000010101;                   // 0x2015
1661
        15: polynom = 32'b110000000000000;                  // 0x6000
1662
        16: polynom = 32'b1101000000001000;                 // 0xD008
1663
        17: polynom = 32'b10010000000000000;                // 0x12000
1664
        18: polynom = 32'b100000010000000000;               // 0x20400
1665
        19: polynom = 32'b1000000000000100011;              // 0x40023
1666
        20: polynom = 32'b10000010000000000000;             // 0x82000
1667
        21: polynom = 32'b101000000000000000000;            // 0x140000
1668
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1669
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1670
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1671
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1672
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1673
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1674
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1675
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1676
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1677
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1678
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1679
        default: polynom = 32'b0;
1680
        endcase
1681
        lfsr_fb = qi[length];
1682
        for (i=length-1; i>=1; i=i-1) begin
1683
            if (polynom[i])
1684
                lfsr_fb = lfsr_fb  ~^ qi[i];
1685
        end
1686
    end
1687
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1688
   always @ (posedge clk or posedge rst)
1689
     if (rst)
1690
       qi <= {length{1'b0}};
1691
     else
1692
     if (cke)
1693
       qi <= q_next;
1694
   assign q = qi;
1695
   always @ (posedge clk or posedge rst)
1696
     if (rst)
1697
       zq <= 1'b1;
1698
     else
1699
     if (cke)
1700
       zq <= q_next == {length{1'b0}};
1701
endmodule
1702
//////////////////////////////////////////////////////////////////////
1703
////                                                              ////
1704
////  Versatile counter                                           ////
1705
////                                                              ////
1706
////  Description                                                 ////
1707
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1708
////  counter                                                     ////
1709
////                                                              ////
1710
////  To Do:                                                      ////
1711
////   - add LFSR with more taps                                  ////
1712
////                                                              ////
1713
////  Author(s):                                                  ////
1714
////      - Michael Unneback, unneback@opencores.org              ////
1715
////        ORSoC AB                                              ////
1716
////                                                              ////
1717
//////////////////////////////////////////////////////////////////////
1718
////                                                              ////
1719
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1720
////                                                              ////
1721
//// This source file may be used and distributed without         ////
1722
//// restriction provided that this copyright statement is not    ////
1723
//// removed from the file and that any derivative work contains  ////
1724
//// the original copyright notice and the associated disclaimer. ////
1725
////                                                              ////
1726
//// This source file is free software; you can redistribute it   ////
1727
//// and/or modify it under the terms of the GNU Lesser General   ////
1728
//// Public License as published by the Free Software Foundation; ////
1729
//// either version 2.1 of the License, or (at your option) any   ////
1730
//// later version.                                               ////
1731
////                                                              ////
1732
//// This source is distributed in the hope that it will be       ////
1733
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1734
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1735
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1736
//// details.                                                     ////
1737
////                                                              ////
1738
//// You should have received a copy of the GNU Lesser General    ////
1739
//// Public License along with this source; if not, download it   ////
1740
//// from http://www.opencores.org/lgpl.shtml                     ////
1741
////                                                              ////
1742
//////////////////////////////////////////////////////////////////////
1743
// LFSR counter
1744 18 unneback
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
1745 6 unneback
   parameter length = 4;
1746
   input cke;
1747
   input rew;
1748
   output reg level1;
1749
   input rst;
1750
   input clk;
1751
   parameter clear_value = 0;
1752
   parameter set_value = 1;
1753
   parameter wrap_value = 8;
1754
   parameter level1_value = 15;
1755 29 unneback
   wire clear;
1756
   assign clear=1'b0;
1757 6 unneback
   reg  [length:1] qi;
1758
   reg lfsr_fb, lfsr_fb_rew;
1759
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1760
   reg [32:1] polynom_rew;
1761
   integer j;
1762
   reg [32:1] polynom;
1763
   integer i;
1764
   always @ (qi)
1765
   begin
1766
        case (length)
1767
         2: polynom = 32'b11;                               // 0x3
1768
         3: polynom = 32'b110;                              // 0x6
1769
         4: polynom = 32'b1100;                             // 0xC
1770
         5: polynom = 32'b10100;                            // 0x14
1771
         6: polynom = 32'b110000;                           // 0x30
1772
         7: polynom = 32'b1100000;                          // 0x60
1773
         8: polynom = 32'b10111000;                         // 0xb8
1774
         9: polynom = 32'b100010000;                        // 0x110
1775
        10: polynom = 32'b1001000000;                       // 0x240
1776
        11: polynom = 32'b10100000000;                      // 0x500
1777
        12: polynom = 32'b100000101001;                     // 0x829
1778
        13: polynom = 32'b1000000001100;                    // 0x100C
1779
        14: polynom = 32'b10000000010101;                   // 0x2015
1780
        15: polynom = 32'b110000000000000;                  // 0x6000
1781
        16: polynom = 32'b1101000000001000;                 // 0xD008
1782
        17: polynom = 32'b10010000000000000;                // 0x12000
1783
        18: polynom = 32'b100000010000000000;               // 0x20400
1784
        19: polynom = 32'b1000000000000100011;              // 0x40023
1785
        20: polynom = 32'b10000010000000000000;             // 0x82000
1786
        21: polynom = 32'b101000000000000000000;            // 0x140000
1787
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1788
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1789
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1790
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1791
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1792
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1793
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1794
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1795
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1796
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1797
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1798
        default: polynom = 32'b0;
1799
        endcase
1800
        lfsr_fb = qi[length];
1801
        for (i=length-1; i>=1; i=i-1) begin
1802
            if (polynom[i])
1803
                lfsr_fb = lfsr_fb  ~^ qi[i];
1804
        end
1805
    end
1806
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1807
   always @ (qi)
1808
   begin
1809
        case (length)
1810
         2: polynom_rew = 32'b11;
1811
         3: polynom_rew = 32'b110;
1812
         4: polynom_rew = 32'b1100;
1813
         5: polynom_rew = 32'b10100;
1814
         6: polynom_rew = 32'b110000;
1815
         7: polynom_rew = 32'b1100000;
1816
         8: polynom_rew = 32'b10111000;
1817
         9: polynom_rew = 32'b100010000;
1818
        10: polynom_rew = 32'b1001000000;
1819
        11: polynom_rew = 32'b10100000000;
1820
        12: polynom_rew = 32'b100000101001;
1821
        13: polynom_rew = 32'b1000000001100;
1822
        14: polynom_rew = 32'b10000000010101;
1823
        15: polynom_rew = 32'b110000000000000;
1824
        16: polynom_rew = 32'b1101000000001000;
1825
        17: polynom_rew = 32'b10010000000000000;
1826
        18: polynom_rew = 32'b100000010000000000;
1827
        19: polynom_rew = 32'b1000000000000100011;
1828
        20: polynom_rew = 32'b10000010000000000000;
1829
        21: polynom_rew = 32'b101000000000000000000;
1830
        22: polynom_rew = 32'b1100000000000000000000;
1831
        23: polynom_rew = 32'b10000100000000000000000;
1832
        24: polynom_rew = 32'b111000010000000000000000;
1833
        25: polynom_rew = 32'b1001000000000000000000000;
1834
        26: polynom_rew = 32'b10000000000000000000100011;
1835
        27: polynom_rew = 32'b100000000000000000000010011;
1836
        28: polynom_rew = 32'b1100100000000000000000000000;
1837
        29: polynom_rew = 32'b10100000000000000000000000000;
1838
        30: polynom_rew = 32'b100000000000000000000000101001;
1839
        31: polynom_rew = 32'b1001000000000000000000000000000;
1840
        32: polynom_rew = 32'b10000000001000000000000000000011;
1841
        default: polynom_rew = 32'b0;
1842
        endcase
1843
        // rotate left
1844
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
1845
        lfsr_fb_rew = qi[length];
1846
        for (i=length-1; i>=1; i=i-1) begin
1847
            if (polynom_rew[i])
1848
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
1849
        end
1850
    end
1851
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
1852
   assign q_next = rew ? q_next_rew : q_next_fw;
1853
   always @ (posedge clk or posedge rst)
1854
     if (rst)
1855
       qi <= {length{1'b0}};
1856
     else
1857
     if (cke)
1858
       qi <= q_next;
1859
    always @ (posedge clk or posedge rst)
1860
    if (rst)
1861
        level1 <= 1'b0;
1862
    else
1863
    if (cke)
1864 29 unneback
    if (clear)
1865
        level1 <= 1'b0;
1866
    else if (q_next == level1_value)
1867 6 unneback
        level1 <= 1'b1;
1868
    else if (qi == level1_value & rew)
1869
        level1 <= 1'b0;
1870
endmodule
1871
//////////////////////////////////////////////////////////////////////
1872
////                                                              ////
1873
////  Versatile counter                                           ////
1874
////                                                              ////
1875
////  Description                                                 ////
1876
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1877
////  counter                                                     ////
1878
////                                                              ////
1879
////  To Do:                                                      ////
1880
////   - add LFSR with more taps                                  ////
1881
////                                                              ////
1882
////  Author(s):                                                  ////
1883
////      - Michael Unneback, unneback@opencores.org              ////
1884
////        ORSoC AB                                              ////
1885
////                                                              ////
1886
//////////////////////////////////////////////////////////////////////
1887
////                                                              ////
1888
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1889
////                                                              ////
1890
//// This source file may be used and distributed without         ////
1891
//// restriction provided that this copyright statement is not    ////
1892
//// removed from the file and that any derivative work contains  ////
1893
//// the original copyright notice and the associated disclaimer. ////
1894
////                                                              ////
1895
//// This source file is free software; you can redistribute it   ////
1896
//// and/or modify it under the terms of the GNU Lesser General   ////
1897
//// Public License as published by the Free Software Foundation; ////
1898
//// either version 2.1 of the License, or (at your option) any   ////
1899
//// later version.                                               ////
1900
////                                                              ////
1901
//// This source is distributed in the hope that it will be       ////
1902
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1903
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1904
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1905
//// details.                                                     ////
1906
////                                                              ////
1907
//// You should have received a copy of the GNU Lesser General    ////
1908
//// Public License along with this source; if not, download it   ////
1909
//// from http://www.opencores.org/lgpl.shtml                     ////
1910
////                                                              ////
1911
//////////////////////////////////////////////////////////////////////
1912
// GRAY counter
1913 18 unneback
module vl_cnt_gray ( q, rst, clk);
1914 6 unneback
   parameter length = 4;
1915
   output reg [length:1] q;
1916
   input rst;
1917
   input clk;
1918
   parameter clear_value = 0;
1919
   parameter set_value = 1;
1920
   parameter wrap_value = 8;
1921
   parameter level1_value = 15;
1922
   reg  [length:1] qi;
1923
   wire [length:1] q_next;
1924
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1925
   always @ (posedge clk or posedge rst)
1926
     if (rst)
1927
       qi <= {length{1'b0}};
1928
     else
1929
       qi <= q_next;
1930
   always @ (posedge clk or posedge rst)
1931
     if (rst)
1932
       q <= {length{1'b0}};
1933
     else
1934
         q <= (q_next>>1) ^ q_next;
1935
endmodule
1936
//////////////////////////////////////////////////////////////////////
1937
////                                                              ////
1938
////  Versatile counter                                           ////
1939
////                                                              ////
1940
////  Description                                                 ////
1941
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1942
////  counter                                                     ////
1943
////                                                              ////
1944
////  To Do:                                                      ////
1945
////   - add LFSR with more taps                                  ////
1946
////                                                              ////
1947
////  Author(s):                                                  ////
1948
////      - Michael Unneback, unneback@opencores.org              ////
1949
////        ORSoC AB                                              ////
1950
////                                                              ////
1951
//////////////////////////////////////////////////////////////////////
1952
////                                                              ////
1953
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1954
////                                                              ////
1955
//// This source file may be used and distributed without         ////
1956
//// restriction provided that this copyright statement is not    ////
1957
//// removed from the file and that any derivative work contains  ////
1958
//// the original copyright notice and the associated disclaimer. ////
1959
////                                                              ////
1960
//// This source file is free software; you can redistribute it   ////
1961
//// and/or modify it under the terms of the GNU Lesser General   ////
1962
//// Public License as published by the Free Software Foundation; ////
1963
//// either version 2.1 of the License, or (at your option) any   ////
1964
//// later version.                                               ////
1965
////                                                              ////
1966
//// This source is distributed in the hope that it will be       ////
1967
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1968
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1969
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1970
//// details.                                                     ////
1971
////                                                              ////
1972
//// You should have received a copy of the GNU Lesser General    ////
1973
//// Public License along with this source; if not, download it   ////
1974
//// from http://www.opencores.org/lgpl.shtml                     ////
1975
////                                                              ////
1976
//////////////////////////////////////////////////////////////////////
1977
// GRAY counter
1978 18 unneback
module vl_cnt_gray_ce ( cke, q, rst, clk);
1979 6 unneback
   parameter length = 4;
1980
   input cke;
1981
   output reg [length:1] q;
1982
   input rst;
1983
   input clk;
1984
   parameter clear_value = 0;
1985
   parameter set_value = 1;
1986
   parameter wrap_value = 8;
1987
   parameter level1_value = 15;
1988
   reg  [length:1] qi;
1989
   wire [length:1] q_next;
1990
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1991
   always @ (posedge clk or posedge rst)
1992
     if (rst)
1993
       qi <= {length{1'b0}};
1994
     else
1995
     if (cke)
1996
       qi <= q_next;
1997
   always @ (posedge clk or posedge rst)
1998
     if (rst)
1999
       q <= {length{1'b0}};
2000
     else
2001
       if (cke)
2002
         q <= (q_next>>1) ^ q_next;
2003
endmodule
2004
//////////////////////////////////////////////////////////////////////
2005
////                                                              ////
2006
////  Versatile counter                                           ////
2007
////                                                              ////
2008
////  Description                                                 ////
2009
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2010
////  counter                                                     ////
2011
////                                                              ////
2012
////  To Do:                                                      ////
2013
////   - add LFSR with more taps                                  ////
2014
////                                                              ////
2015
////  Author(s):                                                  ////
2016
////      - Michael Unneback, unneback@opencores.org              ////
2017
////        ORSoC AB                                              ////
2018
////                                                              ////
2019
//////////////////////////////////////////////////////////////////////
2020
////                                                              ////
2021
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2022
////                                                              ////
2023
//// This source file may be used and distributed without         ////
2024
//// restriction provided that this copyright statement is not    ////
2025
//// removed from the file and that any derivative work contains  ////
2026
//// the original copyright notice and the associated disclaimer. ////
2027
////                                                              ////
2028
//// This source file is free software; you can redistribute it   ////
2029
//// and/or modify it under the terms of the GNU Lesser General   ////
2030
//// Public License as published by the Free Software Foundation; ////
2031
//// either version 2.1 of the License, or (at your option) any   ////
2032
//// later version.                                               ////
2033
////                                                              ////
2034
//// This source is distributed in the hope that it will be       ////
2035
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2036
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2037
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2038
//// details.                                                     ////
2039
////                                                              ////
2040
//// You should have received a copy of the GNU Lesser General    ////
2041
//// Public License along with this source; if not, download it   ////
2042
//// from http://www.opencores.org/lgpl.shtml                     ////
2043
////                                                              ////
2044
//////////////////////////////////////////////////////////////////////
2045
// GRAY counter
2046 18 unneback
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
2047 6 unneback
   parameter length = 4;
2048
   input cke;
2049
   output reg [length:1] q;
2050
   output [length:1] q_bin;
2051
   input rst;
2052
   input clk;
2053
   parameter clear_value = 0;
2054
   parameter set_value = 1;
2055
   parameter wrap_value = 8;
2056
   parameter level1_value = 15;
2057
   reg  [length:1] qi;
2058
   wire [length:1] q_next;
2059
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2060
   always @ (posedge clk or posedge rst)
2061
     if (rst)
2062
       qi <= {length{1'b0}};
2063
     else
2064
     if (cke)
2065
       qi <= q_next;
2066
   always @ (posedge clk or posedge rst)
2067
     if (rst)
2068
       q <= {length{1'b0}};
2069
     else
2070
       if (cke)
2071
         q <= (q_next>>1) ^ q_next;
2072
   assign q_bin = qi;
2073
endmodule
2074
//////////////////////////////////////////////////////////////////////
2075
////                                                              ////
2076
////  Versatile library, counters                                 ////
2077
////                                                              ////
2078
////  Description                                                 ////
2079
////  counters                                                    ////
2080
////                                                              ////
2081
////                                                              ////
2082
////  To Do:                                                      ////
2083
////   - add more counters                                        ////
2084
////                                                              ////
2085
////  Author(s):                                                  ////
2086
////      - Michael Unneback, unneback@opencores.org              ////
2087
////        ORSoC AB                                              ////
2088
////                                                              ////
2089
//////////////////////////////////////////////////////////////////////
2090
////                                                              ////
2091
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2092
////                                                              ////
2093
//// This source file may be used and distributed without         ////
2094
//// restriction provided that this copyright statement is not    ////
2095
//// removed from the file and that any derivative work contains  ////
2096
//// the original copyright notice and the associated disclaimer. ////
2097
////                                                              ////
2098
//// This source file is free software; you can redistribute it   ////
2099
//// and/or modify it under the terms of the GNU Lesser General   ////
2100
//// Public License as published by the Free Software Foundation; ////
2101
//// either version 2.1 of the License, or (at your option) any   ////
2102
//// later version.                                               ////
2103
////                                                              ////
2104
//// This source is distributed in the hope that it will be       ////
2105
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2106
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2107
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2108
//// details.                                                     ////
2109
////                                                              ////
2110
//// You should have received a copy of the GNU Lesser General    ////
2111
//// Public License along with this source; if not, download it   ////
2112
//// from http://www.opencores.org/lgpl.shtml                     ////
2113
////                                                              ////
2114
//////////////////////////////////////////////////////////////////////
2115 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
2116 6 unneback
   parameter length = 4;
2117
   output reg [0:length-1] q;
2118
   input rst;
2119
   input clk;
2120
    always @ (posedge clk or posedge rst)
2121
    if (rst)
2122
        q <= {1'b1,{length-1{1'b0}}};
2123
    else
2124
        q <= {q[length-1],q[0:length-2]};
2125
endmodule
2126 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
2127 6 unneback
   parameter length = 4;
2128
   input cke;
2129
   output reg [0:length-1] q;
2130
   input rst;
2131
   input clk;
2132
    always @ (posedge clk or posedge rst)
2133
    if (rst)
2134
        q <= {1'b1,{length-1{1'b0}}};
2135
    else
2136
        if (cke)
2137
            q <= {q[length-1],q[0:length-2]};
2138
endmodule
2139 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
2140 6 unneback
   parameter length = 4;
2141
   input cke, clear;
2142
   output reg [0:length-1] q;
2143
   input rst;
2144
   input clk;
2145
    always @ (posedge clk or posedge rst)
2146
    if (rst)
2147
        q <= {1'b1,{length-1{1'b0}}};
2148
    else
2149
        if (cke)
2150
            if (clear)
2151
                q <= {1'b1,{length-1{1'b0}}};
2152
            else
2153
                q <= q >> 1;
2154
endmodule
2155 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
2156 6 unneback
   parameter length = 4;
2157
   input cke, clear;
2158
   output reg [0:length-1] q;
2159
   input rst;
2160
   input clk;
2161
    always @ (posedge clk or posedge rst)
2162
    if (rst)
2163
        q <= {1'b1,{length-1{1'b0}}};
2164
    else
2165
        if (cke)
2166
            if (clear)
2167
                q <= {1'b1,{length-1{1'b0}}};
2168
            else
2169
            q <= {q[length-1],q[0:length-2]};
2170
endmodule
2171
//////////////////////////////////////////////////////////////////////
2172
////                                                              ////
2173
////  Versatile library, memories                                 ////
2174
////                                                              ////
2175
////  Description                                                 ////
2176
////  memories                                                    ////
2177
////                                                              ////
2178
////                                                              ////
2179
////  To Do:                                                      ////
2180
////   - add more memory types                                    ////
2181
////                                                              ////
2182
////  Author(s):                                                  ////
2183
////      - Michael Unneback, unneback@opencores.org              ////
2184
////        ORSoC AB                                              ////
2185
////                                                              ////
2186
//////////////////////////////////////////////////////////////////////
2187
////                                                              ////
2188
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2189
////                                                              ////
2190
//// This source file may be used and distributed without         ////
2191
//// restriction provided that this copyright statement is not    ////
2192
//// removed from the file and that any derivative work contains  ////
2193
//// the original copyright notice and the associated disclaimer. ////
2194
////                                                              ////
2195
//// This source file is free software; you can redistribute it   ////
2196
//// and/or modify it under the terms of the GNU Lesser General   ////
2197
//// Public License as published by the Free Software Foundation; ////
2198
//// either version 2.1 of the License, or (at your option) any   ////
2199
//// later version.                                               ////
2200
////                                                              ////
2201
//// This source is distributed in the hope that it will be       ////
2202
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2203
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2204
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2205
//// details.                                                     ////
2206
////                                                              ////
2207
//// You should have received a copy of the GNU Lesser General    ////
2208
//// Public License along with this source; if not, download it   ////
2209
//// from http://www.opencores.org/lgpl.shtml                     ////
2210
////                                                              ////
2211
//////////////////////////////////////////////////////////////////////
2212
/// ROM
2213 7 unneback
module vl_rom_init ( adr, q, clk);
2214
   parameter data_width = 32;
2215
   parameter addr_width = 8;
2216
   input [(addr_width-1):0]       adr;
2217
   output reg [(data_width-1):0] q;
2218
   input                         clk;
2219
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
2220
   parameter memory_file = "vl_rom.vmem";
2221
   initial
2222
     begin
2223
        $readmemh(memory_file, rom);
2224
     end
2225
   always @ (posedge clk)
2226
     q <= rom[adr];
2227
endmodule
2228 14 unneback
/*
2229 7 unneback
module vl_rom ( adr, q, clk);
2230 6 unneback
parameter data_width = 32;
2231
parameter addr_width = 4;
2232
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
2233
    {32'h18000000},
2234
    {32'hA8200000},
2235
    {32'hA8200000},
2236
    {32'hA8200000},
2237
    {32'h44003000},
2238
    {32'h15000000},
2239
    {32'h15000000},
2240
    {32'h15000000},
2241
    {32'h15000000},
2242
    {32'h15000000},
2243
    {32'h15000000},
2244
    {32'h15000000},
2245
    {32'h15000000},
2246
    {32'h15000000},
2247
    {32'h15000000},
2248
    {32'h15000000}};
2249 7 unneback
input [addr_width-1:0] adr;
2250 6 unneback
output reg [data_width-1:0] q;
2251
input clk;
2252
always @ (posedge clk)
2253 7 unneback
    q <= data[adr];
2254 6 unneback
endmodule
2255 14 unneback
*/
2256 6 unneback
// Single port RAM
2257
module vl_ram ( d, adr, we, q, clk);
2258
   parameter data_width = 32;
2259
   parameter addr_width = 8;
2260
   input [(data_width-1):0]      d;
2261
   input [(addr_width-1):0]       adr;
2262
   input                         we;
2263 7 unneback
   output reg [(data_width-1):0] q;
2264 6 unneback
   input                         clk;
2265
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
2266 7 unneback
   parameter init = 0;
2267
   parameter memory_file = "vl_ram.vmem";
2268
   generate if (init) begin : init_mem
2269
   initial
2270
     begin
2271
        $readmemh(memory_file, ram);
2272
     end
2273
   end
2274
   endgenerate
2275 6 unneback
   always @ (posedge clk)
2276
   begin
2277
   if (we)
2278
     ram[adr] <= d;
2279
   q <= ram[adr];
2280
   end
2281
endmodule
2282 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
2283
   parameter data_width = 32;
2284
   parameter addr_width = 8;
2285
   input [(data_width-1):0]      d;
2286
   input [(addr_width-1):0]       adr;
2287
   input [(addr_width/4)-1:0]    be;
2288
   input                         we;
2289
   output reg [(data_width-1):0] q;
2290
   input                         clk;
2291
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
2292
   parameter init = 0;
2293
   parameter memory_file = "vl_ram.vmem";
2294
   generate if (init) begin : init_mem
2295
   initial
2296
     begin
2297
        $readmemh(memory_file, ram);
2298
     end
2299
   end
2300
   endgenerate
2301
   genvar i;
2302
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
2303
      always @ (posedge clk)
2304
      if (we & be[i])
2305
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
2306
   end
2307
   endgenerate
2308
   always @ (posedge clk)
2309
      q <= ram[adr];
2310
endmodule
2311 6 unneback
// Dual port RAM
2312
// ACTEL FPGA should not use logic to handle rw collision
2313 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
2314 6 unneback
   parameter data_width = 32;
2315
   parameter addr_width = 8;
2316
   input [(data_width-1):0]      d_a;
2317
   input [(addr_width-1):0]       adr_a;
2318
   input [(addr_width-1):0]       adr_b;
2319
   input                         we_a;
2320
   output [(data_width-1):0]      q_b;
2321
   input                         clk_a, clk_b;
2322
   reg [(addr_width-1):0]         adr_b_reg;
2323
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
2324 7 unneback
   parameter init = 0;
2325
   parameter memory_file = "vl_ram.vmem";
2326
   generate if (init) begin : init_mem
2327
   initial
2328
     begin
2329
        $readmemh(memory_file, ram);
2330
     end
2331
   end
2332
   endgenerate
2333 6 unneback
   always @ (posedge clk_a)
2334
   if (we_a)
2335
     ram[adr_a] <= d_a;
2336
   always @ (posedge clk_b)
2337
   adr_b_reg <= adr_b;
2338
   assign q_b = ram[adr_b_reg];
2339
endmodule
2340 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
2341 6 unneback
   parameter data_width = 32;
2342
   parameter addr_width = 8;
2343
   input [(data_width-1):0]      d_a;
2344
   input [(addr_width-1):0]       adr_a;
2345
   input [(addr_width-1):0]       adr_b;
2346
   input                         we_a;
2347
   output [(data_width-1):0]      q_b;
2348
   output reg [(data_width-1):0] q_a;
2349
   input                         clk_a, clk_b;
2350
   reg [(data_width-1):0]         q_b;
2351
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
2352 7 unneback
   parameter init = 0;
2353
   parameter memory_file = "vl_ram.vmem";
2354
   generate if (init) begin : init_mem
2355
   initial
2356
     begin
2357
        $readmemh(memory_file, ram);
2358
     end
2359
   end
2360
   endgenerate
2361 6 unneback
   always @ (posedge clk_a)
2362
     begin
2363
        q_a <= ram[adr_a];
2364
        if (we_a)
2365
             ram[adr_a] <= d_a;
2366
     end
2367
   always @ (posedge clk_b)
2368
          q_b <= ram[adr_b];
2369
endmodule
2370 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
2371 6 unneback
   parameter data_width = 32;
2372
   parameter addr_width = 8;
2373
   input [(data_width-1):0]      d_a;
2374
   input [(addr_width-1):0]       adr_a;
2375
   input [(addr_width-1):0]       adr_b;
2376
   input                         we_a;
2377
   output [(data_width-1):0]      q_b;
2378
   input [(data_width-1):0]       d_b;
2379
   output reg [(data_width-1):0] q_a;
2380
   input                         we_b;
2381
   input                         clk_a, clk_b;
2382
   reg [(data_width-1):0]         q_b;
2383
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
2384 7 unneback
   parameter init = 0;
2385
   parameter memory_file = "vl_ram.vmem";
2386
   generate if (init) begin : init_mem
2387
   initial
2388
     begin
2389
        $readmemh(memory_file, ram);
2390
     end
2391
   end
2392
   endgenerate
2393 6 unneback
   always @ (posedge clk_a)
2394
     begin
2395
        q_a <= ram[adr_a];
2396
        if (we_a)
2397
             ram[adr_a] <= d_a;
2398
     end
2399
   always @ (posedge clk_b)
2400
     begin
2401
        q_b <= ram[adr_b];
2402
        if (we_b)
2403
          ram[adr_b] <= d_b;
2404
     end
2405
endmodule
2406
// Content addresable memory, CAM
2407
// FIFO
2408 25 unneback
module vl_fifo_1r1w_fill_level_sync (
2409
    d, wr, fifo_full,
2410
    q, rd, fifo_empty,
2411
    fill_level,
2412
    clk, rst
2413
    );
2414
parameter data_width = 18;
2415
parameter addr_width = 4;
2416
// write side
2417
input  [data_width-1:0] d;
2418
input                   wr;
2419
output                  fifo_full;
2420
// read side
2421
output [data_width-1:0] q;
2422
input                   rd;
2423
output                  fifo_empty;
2424
// common
2425
output [addr_width:0]   fill_level;
2426
input rst, clk;
2427
wire [addr_width:1] wadr, radr;
2428
vl_cnt_bin_ce
2429
    # ( .length(addr_width))
2430
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
2431
vl_cnt_bin_ce
2432
    # (.length(addr_width))
2433
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
2434
vl_dpram_1r1w
2435
    # (.data_width(data_width), .addr_width(addr_width))
2436
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
2437
vl_cnt_bin_ce_rew_zq_l1
2438 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
2439 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
2440
endmodule
2441 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
2442
// RAM is supposed to be larger than the two FIFOs
2443
// LFSR counters used adr pointers
2444
module vl_fifo_2r2w_sync_simplex (
2445
    // a side
2446
    a_d, a_wr, a_fifo_full,
2447
    a_q, a_rd, a_fifo_empty,
2448
    a_fill_level,
2449
    // b side
2450
    b_d, b_wr, b_fifo_full,
2451
    b_q, b_rd, b_fifo_empty,
2452
    b_fill_level,
2453
    // common
2454
    clk, rst
2455
    );
2456
parameter data_width = 8;
2457
parameter addr_width = 5;
2458
parameter fifo_full_level = (1<<addr_width)-1;
2459
// a side
2460
input  [data_width-1:0] a_d;
2461
input                   a_wr;
2462
output                  a_fifo_full;
2463
output [data_width-1:0] a_q;
2464
input                   a_rd;
2465
output                  a_fifo_empty;
2466
output [addr_width-1:0] a_fill_level;
2467
// b side
2468
input  [data_width-1:0] b_d;
2469
input                   b_wr;
2470
output                  b_fifo_full;
2471
output [data_width-1:0] b_q;
2472
input                   b_rd;
2473
output                  b_fifo_empty;
2474
output [addr_width-1:0] b_fill_level;
2475
input                   clk;
2476
input                   rst;
2477
// adr_gen
2478
wire [addr_width:1] a_wadr, a_radr;
2479
wire [addr_width:1] b_wadr, b_radr;
2480
// dpram
2481
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
2482
vl_cnt_lfsr_ce
2483
    # ( .length(addr_width))
2484
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
2485
vl_cnt_lfsr_ce
2486
    # (.length(addr_width))
2487
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
2488
vl_cnt_lfsr_ce
2489
    # ( .length(addr_width))
2490
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
2491
vl_cnt_lfsr_ce
2492
    # (.length(addr_width))
2493
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
2494
// mux read or write adr to DPRAM
2495
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
2496
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
2497
vl_dpram_2r2w
2498
    # (.data_width(data_width), .addr_width(addr_width+1))
2499
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
2500
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
2501
vl_cnt_bin_ce_rew_zq_l1
2502 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
2503 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
2504
vl_cnt_bin_ce_rew_zq_l1
2505 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
2506 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
2507
endmodule
2508 6 unneback
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
2509 11 unneback
   parameter addr_width = 4;
2510
   parameter N = addr_width-1;
2511 6 unneback
   parameter Q1 = 2'b00;
2512
   parameter Q2 = 2'b01;
2513
   parameter Q3 = 2'b11;
2514
   parameter Q4 = 2'b10;
2515
   parameter going_empty = 1'b0;
2516
   parameter going_full  = 1'b1;
2517
   input [N:0]  wptr, rptr;
2518 14 unneback
   output       fifo_empty;
2519 6 unneback
   output       fifo_full;
2520
   input        wclk, rclk, rst;
2521
   wire direction;
2522
   reg  direction_set, direction_clr;
2523
   wire async_empty, async_full;
2524
   wire fifo_full2;
2525 14 unneback
   wire fifo_empty2;
2526 6 unneback
   // direction_set
2527
   always @ (wptr[N:N-1] or rptr[N:N-1])
2528
     case ({wptr[N:N-1],rptr[N:N-1]})
2529
       {Q1,Q2} : direction_set <= 1'b1;
2530
       {Q2,Q3} : direction_set <= 1'b1;
2531
       {Q3,Q4} : direction_set <= 1'b1;
2532
       {Q4,Q1} : direction_set <= 1'b1;
2533
       default : direction_set <= 1'b0;
2534
     endcase
2535
   // direction_clear
2536
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
2537
     if (rst)
2538
       direction_clr <= 1'b1;
2539
     else
2540
       case ({wptr[N:N-1],rptr[N:N-1]})
2541
         {Q2,Q1} : direction_clr <= 1'b1;
2542
         {Q3,Q2} : direction_clr <= 1'b1;
2543
         {Q4,Q3} : direction_clr <= 1'b1;
2544
         {Q1,Q4} : direction_clr <= 1'b1;
2545
         default : direction_clr <= 1'b0;
2546
       endcase
2547 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
2548 6 unneback
   assign async_empty = (wptr == rptr) && (direction==going_empty);
2549
   assign async_full  = (wptr == rptr) && (direction==going_full);
2550 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
2551
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
2552 6 unneback
/*
2553
   always @ (posedge wclk or posedge rst or posedge async_full)
2554
     if (rst)
2555
       {fifo_full, fifo_full2} <= 2'b00;
2556
     else if (async_full)
2557
       {fifo_full, fifo_full2} <= 2'b11;
2558
     else
2559
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
2560
*/
2561 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
2562 6 unneback
     if (async_empty)
2563
       {fifo_empty, fifo_empty2} <= 2'b11;
2564
     else
2565 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
2566 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
2567
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
2568 27 unneback
endmodule // async_compb
2569 6 unneback
module vl_fifo_1r1w_async (
2570
    d, wr, fifo_full, wr_clk, wr_rst,
2571
    q, rd, fifo_empty, rd_clk, rd_rst
2572
    );
2573
parameter data_width = 18;
2574
parameter addr_width = 4;
2575
// write side
2576
input  [data_width-1:0] d;
2577
input                   wr;
2578
output                  fifo_full;
2579
input                   wr_clk;
2580
input                   wr_rst;
2581
// read side
2582
output [data_width-1:0] q;
2583
input                   rd;
2584
output                  fifo_empty;
2585
input                   rd_clk;
2586
input                   rd_rst;
2587
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin