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1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  Versatile library, clock and reset                          ////
4
////                                                              ////
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////  Description                                                 ////
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////  Logic related to clock and reset                            ////
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////                                                              ////
8
////                                                              ////
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////  To Do:                                                      ////
10
////   - add more different registers                             ////
11
////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
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////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
// Global buffer
43
// usage:
44
// use to enable global buffers for high fan out signals such as clock and reset
45
`timescale 1 ns/100 ps
46
// Version: 8.4 8.4.0.33
47
module gbuf(GL,CLK);
48
output GL;
49
input  CLK;
50
    wire GND;
51
    GND GND_1_net(.Y(GND));
52
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
53
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
54
endmodule
55
`timescale 1 ns/1 ns
56
module vl_gbuf ( i, o);
57
input i;
58
output o;
59
`ifdef SIM_GBUF
60
assign o=i;
61
`else
62
gbuf gbuf_i0 ( .CLK(i), .GL(o));
63
`endif
64
endmodule
65
 //ACTEL
66
// sync reset
67 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
68 6 unneback
// output active high global reset sync with two DFFs 
69
`timescale 1 ns/100 ps
70
module vl_sync_rst ( rst_n_i, rst_o, clk);
71
input rst_n_i, clk;
72
output rst_o;
73 18 unneback
reg [1:0] tmp;
74 6 unneback
always @ (posedge clk or negedge rst_n_i)
75
if (!rst_n_i)
76 17 unneback
        tmp <= 2'b11;
77 6 unneback
else
78 33 unneback
        tmp <= {1'b0,tmp[1]};
79 17 unneback
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
80 6 unneback
endmodule
81
// vl_pll
82 32 unneback
///////////////////////////////////////////////////////////////////////////////
83 17 unneback
`timescale 1 ps/1 ps
84 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
85
parameter index = 0;
86
parameter number_of_clk = 1;
87 17 unneback
parameter period_time_0 = 20000;
88
parameter period_time_1 = 20000;
89
parameter period_time_2 = 20000;
90
parameter lock_delay = 2000000;
91 6 unneback
input clk_i, rst_n_i;
92
output lock;
93
output reg [0:number_of_clk-1] clk_o;
94
output [0:number_of_clk-1] rst_o;
95
`ifdef SIM_PLL
96
always
97
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
98
generate if (number_of_clk > 1)
99
always
100
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
101
endgenerate
102
generate if (number_of_clk > 2)
103
always
104
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
105
endgenerate
106
genvar i;
107
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
108
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
109
end
110
endgenerate
111
assign #lock_delay lock = rst_n_i;
112
endmodule
113
`else
114
generate if (number_of_clk==1 & index==0) begin
115
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
116
end
117
endgenerate // index==0
118
generate if (number_of_clk==1 & index==1) begin
119
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
120
end
121
endgenerate // index==1
122
generate if (number_of_clk==1 & index==2) begin
123
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
124
end
125
endgenerate // index==2
126
generate if (number_of_clk==1 & index==3) begin
127
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
128
end
129
endgenerate // index==0
130
generate if (number_of_clk==2 & index==0) begin
131
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
132
end
133
endgenerate // index==0
134
generate if (number_of_clk==2 & index==1) begin
135
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
136
end
137
endgenerate // index==1
138
generate if (number_of_clk==2 & index==2) begin
139
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
140
end
141
endgenerate // index==2
142
generate if (number_of_clk==2 & index==3) begin
143
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
144
end
145
endgenerate // index==0
146
generate if (number_of_clk==3 & index==0) begin
147
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
148
end
149
endgenerate // index==0
150
generate if (number_of_clk==3 & index==1) begin
151
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
152
end
153
endgenerate // index==1
154
generate if (number_of_clk==3 & index==2) begin
155
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
156
end
157
endgenerate // index==2
158
generate if (number_of_clk==3 & index==3) begin
159
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
160
end
161
endgenerate // index==0
162
genvar i;
163
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
164 40 unneback
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
165 6 unneback
end
166
endgenerate
167
endmodule
168
`endif
169 32 unneback
///////////////////////////////////////////////////////////////////////////////
170 6 unneback
 //actel
171
//////////////////////////////////////////////////////////////////////
172
////                                                              ////
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////  Versatile library, registers                                ////
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////                                                              ////
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////  Description                                                 ////
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////  Different type of registers                                 ////
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////                                                              ////
178
////                                                              ////
179
////  To Do:                                                      ////
180
////   - add more different registers                             ////
181
////                                                              ////
182
////  Author(s):                                                  ////
183
////      - Michael Unneback, unneback@opencores.org              ////
184
////        ORSoC AB                                              ////
185
////                                                              ////
186
//////////////////////////////////////////////////////////////////////
187
////                                                              ////
188
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
189
////                                                              ////
190
//// This source file may be used and distributed without         ////
191
//// restriction provided that this copyright statement is not    ////
192
//// removed from the file and that any derivative work contains  ////
193
//// the original copyright notice and the associated disclaimer. ////
194
////                                                              ////
195
//// This source file is free software; you can redistribute it   ////
196
//// and/or modify it under the terms of the GNU Lesser General   ////
197
//// Public License as published by the Free Software Foundation; ////
198
//// either version 2.1 of the License, or (at your option) any   ////
199
//// later version.                                               ////
200
////                                                              ////
201
//// This source is distributed in the hope that it will be       ////
202
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
203
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
204
//// PURPOSE.  See the GNU Lesser General Public License for more ////
205
//// details.                                                     ////
206
////                                                              ////
207
//// You should have received a copy of the GNU Lesser General    ////
208
//// Public License along with this source; if not, download it   ////
209
//// from http://www.opencores.org/lgpl.shtml                     ////
210
////                                                              ////
211
//////////////////////////////////////////////////////////////////////
212 18 unneback
module vl_dff ( d, q, clk, rst);
213 6 unneback
        parameter width = 1;
214
        parameter reset_value = 0;
215
        input [width-1:0] d;
216
        input clk, rst;
217
        output reg [width-1:0] q;
218
        always @ (posedge clk or posedge rst)
219
        if (rst)
220
                q <= reset_value;
221
        else
222
                q <= d;
223
endmodule
224 18 unneback
module vl_dff_array ( d, q, clk, rst);
225 6 unneback
        parameter width = 1;
226
        parameter depth = 2;
227
        parameter reset_value = 1'b0;
228
        input [width-1:0] d;
229
        input clk, rst;
230
        output [width-1:0] q;
231
        reg  [0:depth-1] q_tmp [width-1:0];
232
        integer i;
233
        always @ (posedge clk or posedge rst)
234
        if (rst) begin
235
            for (i=0;i<depth;i=i+1)
236
                q_tmp[i] <= {width{reset_value}};
237
        end else begin
238
            q_tmp[0] <= d;
239
            for (i=1;i<depth;i=i+1)
240
                q_tmp[i] <= q_tmp[i-1];
241
        end
242
    assign q = q_tmp[depth-1];
243
endmodule
244 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
245 6 unneback
        parameter width = 1;
246
        parameter reset_value = 0;
247
        input [width-1:0] d;
248
        input ce, clk, rst;
249
        output reg [width-1:0] q;
250
        always @ (posedge clk or posedge rst)
251
        if (rst)
252
                q <= reset_value;
253
        else
254
                if (ce)
255
                        q <= d;
256
endmodule
257 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
258 8 unneback
        parameter width = 1;
259
        parameter reset_value = 0;
260
        input [width-1:0] d;
261 10 unneback
        input ce, clear, clk, rst;
262 8 unneback
        output reg [width-1:0] q;
263
        always @ (posedge clk or posedge rst)
264
        if (rst)
265
            q <= reset_value;
266
        else
267
            if (ce)
268
                if (clear)
269
                    q <= {width{1'b0}};
270
                else
271
                    q <= d;
272
endmodule
273 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
274
        parameter width = 1;
275
        parameter reset_value = 0;
276
        input [width-1:0] d;
277
        input ce, set, clk, rst;
278
        output reg [width-1:0] q;
279
        always @ (posedge clk or posedge rst)
280
        if (rst)
281
            q <= reset_value;
282
        else
283
            if (ce)
284
                if (set)
285
                    q <= {width{1'b1}};
286
                else
287
                    q <= d;
288
endmodule
289 29 unneback
module vl_spr ( sp, r, q, clk, rst);
290
        parameter width = 1;
291
        parameter reset_value = 0;
292
        input sp, r;
293
        output reg q;
294
        input clk, rst;
295
        always @ (posedge clk or posedge rst)
296
        if (rst)
297
            q <= reset_value;
298
        else
299
            if (sp)
300
                q <= 1'b1;
301
            else if (r)
302
                q <= 1'b0;
303
endmodule
304
module vl_srp ( s, rp, q, clk, rst);
305
        parameter width = 1;
306
        parameter reset_value = 0;
307
        input s, rp;
308
        output reg q;
309
        input clk, rst;
310
        always @ (posedge clk or posedge rst)
311
        if (rst)
312
            q <= reset_value;
313
        else
314
            if (rp)
315
                q <= 1'b0;
316
            else if (s)
317
                q <= 1'b1;
318
endmodule
319 18 unneback
module vl_dff_sr ( aclr, aset, clock, data, q);
320 6 unneback
    input         aclr;
321
    input         aset;
322
    input         clock;
323
    input         data;
324
    output reg    q;
325
   always @ (posedge clock or posedge aclr or posedge aset)
326
     if (aclr)
327
       q <= 1'b0;
328
     else if (aset)
329
       q <= 1'b1;
330
     else
331
       q <= data;
332
endmodule
333
// LATCH
334
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
335 40 unneback
module vl_latch ( d, le, q, clk);
336 6 unneback
input d, le;
337
output q;
338
input clk;/*
339
   always @ (posedge direction_set or posedge direction_clr)
340
     if (direction_clr)
341
       direction <= going_empty;
342
     else
343
       direction <= going_full;*/
344
endmodule
345 18 unneback
module vl_shreg ( d, q, clk, rst);
346 17 unneback
parameter depth = 10;
347
input d;
348
output q;
349
input clk, rst;
350
reg [1:depth] dffs;
351
always @ (posedge clk or posedge rst)
352
if (rst)
353
    dffs <= {depth{1'b0}};
354
else
355
    dffs <= {d,dffs[1:depth-1]};
356
assign q = dffs[depth];
357
endmodule
358 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
359 17 unneback
parameter depth = 10;
360
input d, ce;
361
output q;
362
input clk, rst;
363
reg [1:depth] dffs;
364
always @ (posedge clk or posedge rst)
365
if (rst)
366
    dffs <= {depth{1'b0}};
367
else
368
    if (ce)
369
        dffs <= {d,dffs[1:depth-1]};
370
assign q = dffs[depth];
371
endmodule
372 18 unneback
module vl_delay ( d, q, clk, rst);
373 15 unneback
parameter depth = 10;
374
input d;
375
output q;
376
input clk, rst;
377
reg [1:depth] dffs;
378
always @ (posedge clk or posedge rst)
379
if (rst)
380
    dffs <= {depth{1'b0}};
381
else
382
    dffs <= {d,dffs[1:depth-1]};
383
assign q = dffs[depth];
384
endmodule
385 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
386 17 unneback
parameter depth = 10;
387
input d;
388
output q, emptyflag;
389
input clk, rst;
390
reg [1:depth] dffs;
391
always @ (posedge clk or posedge rst)
392
if (rst)
393
    dffs <= {depth{1'b0}};
394
else
395
    dffs <= {d,dffs[1:depth-1]};
396
assign q = dffs[depth];
397
assign emptyflag = !(|dffs);
398
endmodule
399 6 unneback
//////////////////////////////////////////////////////////////////////
400
////                                                              ////
401 18 unneback
////  Logic functions                                             ////
402
////                                                              ////
403
////  Description                                                 ////
404
////  Logic functions such as multiplexers                        ////
405
////                                                              ////
406
////                                                              ////
407
////  To Do:                                                      ////
408
////   -                                                          ////
409
////                                                              ////
410
////  Author(s):                                                  ////
411
////      - Michael Unneback, unneback@opencores.org              ////
412
////        ORSoC AB                                              ////
413
////                                                              ////
414
//////////////////////////////////////////////////////////////////////
415
////                                                              ////
416
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
417
////                                                              ////
418
//// This source file may be used and distributed without         ////
419
//// restriction provided that this copyright statement is not    ////
420
//// removed from the file and that any derivative work contains  ////
421
//// the original copyright notice and the associated disclaimer. ////
422
////                                                              ////
423
//// This source file is free software; you can redistribute it   ////
424
//// and/or modify it under the terms of the GNU Lesser General   ////
425
//// Public License as published by the Free Software Foundation; ////
426
//// either version 2.1 of the License, or (at your option) any   ////
427
//// later version.                                               ////
428
////                                                              ////
429
//// This source is distributed in the hope that it will be       ////
430
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
431
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
432
//// PURPOSE.  See the GNU Lesser General Public License for more ////
433
//// details.                                                     ////
434
////                                                              ////
435
//// You should have received a copy of the GNU Lesser General    ////
436
//// Public License along with this source; if not, download it   ////
437
//// from http://www.opencores.org/lgpl.shtml                     ////
438
////                                                              ////
439
//////////////////////////////////////////////////////////////////////
440 36 unneback
module vl_mux_andor ( a, sel, dout);
441
parameter width = 32;
442
parameter nr_of_ports = 4;
443
input [nr_of_ports*width-1:0] a;
444
input [nr_of_ports-1:0] sel;
445
output reg [width-1:0] dout;
446 38 unneback
integer i,j;
447 36 unneback
always @ (a, sel)
448
begin
449
    dout = a[width-1:0] & {width{sel[0]}};
450 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
451
        for (j=0;j<width;j=j+1)
452
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
453 36 unneback
end
454
endmodule
455 34 unneback
module vl_mux2_andor ( a1, a0, sel, dout);
456
parameter width = 32;
457 35 unneback
localparam nr_of_ports = 2;
458 34 unneback
input [width-1:0] a1, a0;
459
input [nr_of_ports-1:0] sel;
460
output [width-1:0] dout;
461 36 unneback
vl_mux_andor
462 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
463 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
464 34 unneback
endmodule
465
module vl_mux3_andor ( a2, a1, a0, sel, dout);
466
parameter width = 32;
467 35 unneback
localparam nr_of_ports = 3;
468 34 unneback
input [width-1:0] a2, a1, a0;
469
input [nr_of_ports-1:0] sel;
470
output [width-1:0] dout;
471 36 unneback
vl_mux_andor
472 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
473 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
474 34 unneback
endmodule
475 18 unneback
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
476
parameter width = 32;
477 35 unneback
localparam nr_of_ports = 4;
478 18 unneback
input [width-1:0] a3, a2, a1, a0;
479
input [nr_of_ports-1:0] sel;
480 22 unneback
output [width-1:0] dout;
481 36 unneback
vl_mux_andor
482 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
483 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
484 18 unneback
endmodule
485
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
486
parameter width = 32;
487 35 unneback
localparam nr_of_ports = 5;
488 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
489
input [nr_of_ports-1:0] sel;
490 22 unneback
output [width-1:0] dout;
491 36 unneback
vl_mux_andor
492 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
493 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
494 18 unneback
endmodule
495
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
496
parameter width = 32;
497 35 unneback
localparam nr_of_ports = 6;
498 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
499
input [nr_of_ports-1:0] sel;
500 22 unneback
output [width-1:0] dout;
501 36 unneback
vl_mux_andor
502 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
503 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
504 18 unneback
endmodule
505
//////////////////////////////////////////////////////////////////////
506
////                                                              ////
507 6 unneback
////  Versatile counter                                           ////
508
////                                                              ////
509
////  Description                                                 ////
510
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
511
////  counter                                                     ////
512
////                                                              ////
513
////  To Do:                                                      ////
514
////   - add LFSR with more taps                                  ////
515
////                                                              ////
516
////  Author(s):                                                  ////
517
////      - Michael Unneback, unneback@opencores.org              ////
518
////        ORSoC AB                                              ////
519
////                                                              ////
520
//////////////////////////////////////////////////////////////////////
521
////                                                              ////
522
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
523
////                                                              ////
524
//// This source file may be used and distributed without         ////
525
//// restriction provided that this copyright statement is not    ////
526
//// removed from the file and that any derivative work contains  ////
527
//// the original copyright notice and the associated disclaimer. ////
528
////                                                              ////
529
//// This source file is free software; you can redistribute it   ////
530
//// and/or modify it under the terms of the GNU Lesser General   ////
531
//// Public License as published by the Free Software Foundation; ////
532
//// either version 2.1 of the License, or (at your option) any   ////
533
//// later version.                                               ////
534
////                                                              ////
535
//// This source is distributed in the hope that it will be       ////
536
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
537
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
538
//// PURPOSE.  See the GNU Lesser General Public License for more ////
539
//// details.                                                     ////
540
////                                                              ////
541
//// You should have received a copy of the GNU Lesser General    ////
542
//// Public License along with this source; if not, download it   ////
543
//// from http://www.opencores.org/lgpl.shtml                     ////
544
////                                                              ////
545
//////////////////////////////////////////////////////////////////////
546
// binary counter
547 40 unneback
module vl_cnt_bin_ce (
548
 cke, q, rst, clk);
549 22 unneback
   parameter length = 4;
550 6 unneback
   input cke;
551
   output [length:1] q;
552
   input rst;
553
   input clk;
554
   parameter clear_value = 0;
555
   parameter set_value = 1;
556
   parameter wrap_value = 0;
557
   parameter level1_value = 15;
558
   reg  [length:1] qi;
559
   wire [length:1] q_next;
560
   assign q_next = qi + {{length-1{1'b0}},1'b1};
561
   always @ (posedge clk or posedge rst)
562
     if (rst)
563
       qi <= {length{1'b0}};
564
     else
565
     if (cke)
566
       qi <= q_next;
567
   assign q = qi;
568
endmodule
569
//////////////////////////////////////////////////////////////////////
570
////                                                              ////
571
////  Versatile counter                                           ////
572
////                                                              ////
573
////  Description                                                 ////
574
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
575
////  counter                                                     ////
576
////                                                              ////
577
////  To Do:                                                      ////
578
////   - add LFSR with more taps                                  ////
579
////                                                              ////
580
////  Author(s):                                                  ////
581
////      - Michael Unneback, unneback@opencores.org              ////
582
////        ORSoC AB                                              ////
583
////                                                              ////
584
//////////////////////////////////////////////////////////////////////
585
////                                                              ////
586
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
587
////                                                              ////
588
//// This source file may be used and distributed without         ////
589
//// restriction provided that this copyright statement is not    ////
590
//// removed from the file and that any derivative work contains  ////
591
//// the original copyright notice and the associated disclaimer. ////
592
////                                                              ////
593
//// This source file is free software; you can redistribute it   ////
594
//// and/or modify it under the terms of the GNU Lesser General   ////
595
//// Public License as published by the Free Software Foundation; ////
596
//// either version 2.1 of the License, or (at your option) any   ////
597
//// later version.                                               ////
598
////                                                              ////
599
//// This source is distributed in the hope that it will be       ////
600
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
601
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
602
//// PURPOSE.  See the GNU Lesser General Public License for more ////
603
//// details.                                                     ////
604
////                                                              ////
605
//// You should have received a copy of the GNU Lesser General    ////
606
//// Public License along with this source; if not, download it   ////
607
//// from http://www.opencores.org/lgpl.shtml                     ////
608
////                                                              ////
609
//////////////////////////////////////////////////////////////////////
610
// binary counter
611 40 unneback
module vl_cnt_bin_ce_rew_zq_l1 (
612
 cke, rew, zq, level1, rst, clk);
613 6 unneback
   parameter length = 4;
614
   input cke;
615
   input rew;
616 25 unneback
   output reg zq;
617
   output reg level1;
618
   input rst;
619
   input clk;
620
   parameter clear_value = 0;
621
   parameter set_value = 1;
622
   parameter wrap_value = 1;
623
   parameter level1_value = 15;
624 29 unneback
   wire clear;
625 30 unneback
   assign clear = 1'b0;
626 25 unneback
   reg  [length:1] qi;
627
   wire  [length:1] q_next, q_next_fw, q_next_rew;
628
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
629
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
630
   assign q_next = rew ? q_next_rew : q_next_fw;
631
   always @ (posedge clk or posedge rst)
632
     if (rst)
633
       qi <= {length{1'b0}};
634
     else
635
     if (cke)
636
       qi <= q_next;
637
   always @ (posedge clk or posedge rst)
638
     if (rst)
639
       zq <= 1'b1;
640
     else
641
     if (cke)
642
       zq <= q_next == {length{1'b0}};
643
    always @ (posedge clk or posedge rst)
644
    if (rst)
645
        level1 <= 1'b0;
646
    else
647
    if (cke)
648 29 unneback
    if (clear)
649
        level1 <= 1'b0;
650
    else if (q_next == level1_value)
651 25 unneback
        level1 <= 1'b1;
652
    else if (qi == level1_value & rew)
653
        level1 <= 1'b0;
654
endmodule
655
//////////////////////////////////////////////////////////////////////
656
////                                                              ////
657
////  Versatile counter                                           ////
658
////                                                              ////
659
////  Description                                                 ////
660
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
661
////  counter                                                     ////
662
////                                                              ////
663
////  To Do:                                                      ////
664
////   - add LFSR with more taps                                  ////
665
////                                                              ////
666
////  Author(s):                                                  ////
667
////      - Michael Unneback, unneback@opencores.org              ////
668
////        ORSoC AB                                              ////
669
////                                                              ////
670
//////////////////////////////////////////////////////////////////////
671
////                                                              ////
672
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
673
////                                                              ////
674
//// This source file may be used and distributed without         ////
675
//// restriction provided that this copyright statement is not    ////
676
//// removed from the file and that any derivative work contains  ////
677
//// the original copyright notice and the associated disclaimer. ////
678
////                                                              ////
679
//// This source file is free software; you can redistribute it   ////
680
//// and/or modify it under the terms of the GNU Lesser General   ////
681
//// Public License as published by the Free Software Foundation; ////
682
//// either version 2.1 of the License, or (at your option) any   ////
683
//// later version.                                               ////
684
////                                                              ////
685
//// This source is distributed in the hope that it will be       ////
686
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
687
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
688
//// PURPOSE.  See the GNU Lesser General Public License for more ////
689
//// details.                                                     ////
690
////                                                              ////
691
//// You should have received a copy of the GNU Lesser General    ////
692
//// Public License along with this source; if not, download it   ////
693
//// from http://www.opencores.org/lgpl.shtml                     ////
694
////                                                              ////
695
//////////////////////////////////////////////////////////////////////
696
// binary counter
697 40 unneback
module vl_cnt_bin_ce_rew_q_zq_l1 (
698
 cke, rew, q, zq, level1, rst, clk);
699 25 unneback
   parameter length = 4;
700
   input cke;
701
   input rew;
702
   output [length:1] q;
703
   output reg zq;
704
   output reg level1;
705
   input rst;
706
   input clk;
707
   parameter clear_value = 0;
708
   parameter set_value = 1;
709
   parameter wrap_value = 1;
710
   parameter level1_value = 15;
711 29 unneback
   wire clear;
712 30 unneback
   assign clear = 1'b0;
713 25 unneback
   reg  [length:1] qi;
714
   wire  [length:1] q_next, q_next_fw, q_next_rew;
715
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
716
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
717
   assign q_next = rew ? q_next_rew : q_next_fw;
718
   always @ (posedge clk or posedge rst)
719
     if (rst)
720
       qi <= {length{1'b0}};
721
     else
722
     if (cke)
723
       qi <= q_next;
724
   assign q = qi;
725
   always @ (posedge clk or posedge rst)
726
     if (rst)
727
       zq <= 1'b1;
728
     else
729
     if (cke)
730
       zq <= q_next == {length{1'b0}};
731
    always @ (posedge clk or posedge rst)
732
    if (rst)
733
        level1 <= 1'b0;
734
    else
735
    if (cke)
736 29 unneback
    if (clear)
737
        level1 <= 1'b0;
738
    else if (q_next == level1_value)
739 25 unneback
        level1 <= 1'b1;
740
    else if (qi == level1_value & rew)
741
        level1 <= 1'b0;
742
endmodule
743
//////////////////////////////////////////////////////////////////////
744
////                                                              ////
745
////  Versatile counter                                           ////
746
////                                                              ////
747
////  Description                                                 ////
748
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
749
////  counter                                                     ////
750
////                                                              ////
751
////  To Do:                                                      ////
752
////   - add LFSR with more taps                                  ////
753
////                                                              ////
754
////  Author(s):                                                  ////
755
////      - Michael Unneback, unneback@opencores.org              ////
756
////        ORSoC AB                                              ////
757
////                                                              ////
758
//////////////////////////////////////////////////////////////////////
759
////                                                              ////
760
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
761
////                                                              ////
762
//// This source file may be used and distributed without         ////
763
//// restriction provided that this copyright statement is not    ////
764
//// removed from the file and that any derivative work contains  ////
765
//// the original copyright notice and the associated disclaimer. ////
766
////                                                              ////
767
//// This source file is free software; you can redistribute it   ////
768
//// and/or modify it under the terms of the GNU Lesser General   ////
769
//// Public License as published by the Free Software Foundation; ////
770
//// either version 2.1 of the License, or (at your option) any   ////
771
//// later version.                                               ////
772
////                                                              ////
773
//// This source is distributed in the hope that it will be       ////
774
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
775
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
776
//// PURPOSE.  See the GNU Lesser General Public License for more ////
777
//// details.                                                     ////
778
////                                                              ////
779
//// You should have received a copy of the GNU Lesser General    ////
780
//// Public License along with this source; if not, download it   ////
781
//// from http://www.opencores.org/lgpl.shtml                     ////
782
////                                                              ////
783
//////////////////////////////////////////////////////////////////////
784 6 unneback
// GRAY counter
785 40 unneback
module vl_cnt_gray_ce_bin (
786
 cke, q, q_bin, rst, clk);
787 6 unneback
   parameter length = 4;
788
   input cke;
789
   output reg [length:1] q;
790
   output [length:1] q_bin;
791
   input rst;
792
   input clk;
793
   parameter clear_value = 0;
794
   parameter set_value = 1;
795
   parameter wrap_value = 8;
796
   parameter level1_value = 15;
797
   reg  [length:1] qi;
798
   wire [length:1] q_next;
799
   assign q_next = qi + {{length-1{1'b0}},1'b1};
800
   always @ (posedge clk or posedge rst)
801
     if (rst)
802
       qi <= {length{1'b0}};
803
     else
804
     if (cke)
805
       qi <= q_next;
806
   always @ (posedge clk or posedge rst)
807
     if (rst)
808
       q <= {length{1'b0}};
809
     else
810
       if (cke)
811
         q <= (q_next>>1) ^ q_next;
812
   assign q_bin = qi;
813
endmodule
814
//////////////////////////////////////////////////////////////////////
815
////                                                              ////
816
////  Versatile library, counters                                 ////
817
////                                                              ////
818
////  Description                                                 ////
819
////  counters                                                    ////
820
////                                                              ////
821
////                                                              ////
822
////  To Do:                                                      ////
823
////   - add more counters                                        ////
824
////                                                              ////
825
////  Author(s):                                                  ////
826
////      - Michael Unneback, unneback@opencores.org              ////
827
////        ORSoC AB                                              ////
828
////                                                              ////
829
//////////////////////////////////////////////////////////////////////
830
////                                                              ////
831
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
832
////                                                              ////
833
//// This source file may be used and distributed without         ////
834
//// restriction provided that this copyright statement is not    ////
835
//// removed from the file and that any derivative work contains  ////
836
//// the original copyright notice and the associated disclaimer. ////
837
////                                                              ////
838
//// This source file is free software; you can redistribute it   ////
839
//// and/or modify it under the terms of the GNU Lesser General   ////
840
//// Public License as published by the Free Software Foundation; ////
841
//// either version 2.1 of the License, or (at your option) any   ////
842
//// later version.                                               ////
843
////                                                              ////
844
//// This source is distributed in the hope that it will be       ////
845
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
846
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
847
//// PURPOSE.  See the GNU Lesser General Public License for more ////
848
//// details.                                                     ////
849
////                                                              ////
850
//// You should have received a copy of the GNU Lesser General    ////
851
//// Public License along with this source; if not, download it   ////
852
//// from http://www.opencores.org/lgpl.shtml                     ////
853
////                                                              ////
854
//////////////////////////////////////////////////////////////////////
855 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
856 6 unneback
   parameter length = 4;
857
   output reg [0:length-1] q;
858
   input rst;
859
   input clk;
860
    always @ (posedge clk or posedge rst)
861
    if (rst)
862
        q <= {1'b1,{length-1{1'b0}}};
863
    else
864
        q <= {q[length-1],q[0:length-2]};
865
endmodule
866 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
867 6 unneback
   parameter length = 4;
868
   input cke;
869
   output reg [0:length-1] q;
870
   input rst;
871
   input clk;
872
    always @ (posedge clk or posedge rst)
873
    if (rst)
874
        q <= {1'b1,{length-1{1'b0}}};
875
    else
876
        if (cke)
877
            q <= {q[length-1],q[0:length-2]};
878
endmodule
879 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
880 6 unneback
   parameter length = 4;
881
   input cke, clear;
882
   output reg [0:length-1] q;
883
   input rst;
884
   input clk;
885
    always @ (posedge clk or posedge rst)
886
    if (rst)
887
        q <= {1'b1,{length-1{1'b0}}};
888
    else
889
        if (cke)
890
            if (clear)
891
                q <= {1'b1,{length-1{1'b0}}};
892
            else
893
                q <= q >> 1;
894
endmodule
895 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
896 6 unneback
   parameter length = 4;
897
   input cke, clear;
898
   output reg [0:length-1] q;
899
   input rst;
900
   input clk;
901
    always @ (posedge clk or posedge rst)
902
    if (rst)
903
        q <= {1'b1,{length-1{1'b0}}};
904
    else
905
        if (cke)
906
            if (clear)
907
                q <= {1'b1,{length-1{1'b0}}};
908
            else
909
            q <= {q[length-1],q[0:length-2]};
910
endmodule
911
//////////////////////////////////////////////////////////////////////
912
////                                                              ////
913
////  Versatile library, memories                                 ////
914
////                                                              ////
915
////  Description                                                 ////
916
////  memories                                                    ////
917
////                                                              ////
918
////                                                              ////
919
////  To Do:                                                      ////
920
////   - add more memory types                                    ////
921
////                                                              ////
922
////  Author(s):                                                  ////
923
////      - Michael Unneback, unneback@opencores.org              ////
924
////        ORSoC AB                                              ////
925
////                                                              ////
926
//////////////////////////////////////////////////////////////////////
927
////                                                              ////
928
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
929
////                                                              ////
930
//// This source file may be used and distributed without         ////
931
//// restriction provided that this copyright statement is not    ////
932
//// removed from the file and that any derivative work contains  ////
933
//// the original copyright notice and the associated disclaimer. ////
934
////                                                              ////
935
//// This source file is free software; you can redistribute it   ////
936
//// and/or modify it under the terms of the GNU Lesser General   ////
937
//// Public License as published by the Free Software Foundation; ////
938
//// either version 2.1 of the License, or (at your option) any   ////
939
//// later version.                                               ////
940
////                                                              ////
941
//// This source is distributed in the hope that it will be       ////
942
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
943
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
944
//// PURPOSE.  See the GNU Lesser General Public License for more ////
945
//// details.                                                     ////
946
////                                                              ////
947
//// You should have received a copy of the GNU Lesser General    ////
948
//// Public License along with this source; if not, download it   ////
949
//// from http://www.opencores.org/lgpl.shtml                     ////
950
////                                                              ////
951
//////////////////////////////////////////////////////////////////////
952
/// ROM
953 7 unneback
module vl_rom_init ( adr, q, clk);
954
   parameter data_width = 32;
955
   parameter addr_width = 8;
956
   input [(addr_width-1):0]       adr;
957
   output reg [(data_width-1):0] q;
958
   input                         clk;
959
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
960
   parameter memory_file = "vl_rom.vmem";
961
   initial
962
     begin
963
        $readmemh(memory_file, rom);
964
     end
965
   always @ (posedge clk)
966
     q <= rom[adr];
967
endmodule
968 14 unneback
/*
969 7 unneback
module vl_rom ( adr, q, clk);
970 6 unneback
parameter data_width = 32;
971
parameter addr_width = 4;
972
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
973
    {32'h18000000},
974
    {32'hA8200000},
975
    {32'hA8200000},
976
    {32'hA8200000},
977
    {32'h44003000},
978
    {32'h15000000},
979
    {32'h15000000},
980
    {32'h15000000},
981
    {32'h15000000},
982
    {32'h15000000},
983
    {32'h15000000},
984
    {32'h15000000},
985
    {32'h15000000},
986
    {32'h15000000},
987
    {32'h15000000},
988
    {32'h15000000}};
989 7 unneback
input [addr_width-1:0] adr;
990 6 unneback
output reg [data_width-1:0] q;
991
input clk;
992
always @ (posedge clk)
993 7 unneback
    q <= data[adr];
994 6 unneback
endmodule
995 14 unneback
*/
996 6 unneback
// Single port RAM
997
module vl_ram ( d, adr, we, q, clk);
998
   parameter data_width = 32;
999
   parameter addr_width = 8;
1000
   input [(data_width-1):0]      d;
1001
   input [(addr_width-1):0]       adr;
1002
   input                         we;
1003 7 unneback
   output reg [(data_width-1):0] q;
1004 6 unneback
   input                         clk;
1005
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1006 7 unneback
   parameter init = 0;
1007
   parameter memory_file = "vl_ram.vmem";
1008
   generate if (init) begin : init_mem
1009
   initial
1010
     begin
1011
        $readmemh(memory_file, ram);
1012
     end
1013
   end
1014
   endgenerate
1015 6 unneback
   always @ (posedge clk)
1016
   begin
1017
   if (we)
1018
     ram[adr] <= d;
1019
   q <= ram[adr];
1020
   end
1021
endmodule
1022 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
1023
   parameter data_width = 32;
1024
   parameter addr_width = 8;
1025
   input [(data_width-1):0]      d;
1026
   input [(addr_width-1):0]       adr;
1027
   input [(addr_width/4)-1:0]    be;
1028
   input                         we;
1029
   output reg [(data_width-1):0] q;
1030
   input                         clk;
1031
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1032
   parameter init = 0;
1033
   parameter memory_file = "vl_ram.vmem";
1034
   generate if (init) begin : init_mem
1035
   initial
1036
     begin
1037
        $readmemh(memory_file, ram);
1038
     end
1039
   end
1040
   endgenerate
1041
   genvar i;
1042
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
1043
      always @ (posedge clk)
1044
      if (we & be[i])
1045
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
1046
   end
1047
   endgenerate
1048
   always @ (posedge clk)
1049
      q <= ram[adr];
1050
endmodule
1051 6 unneback
// Dual port RAM
1052
// ACTEL FPGA should not use logic to handle rw collision
1053 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1054 6 unneback
   parameter data_width = 32;
1055
   parameter addr_width = 8;
1056
   input [(data_width-1):0]      d_a;
1057
   input [(addr_width-1):0]       adr_a;
1058
   input [(addr_width-1):0]       adr_b;
1059
   input                         we_a;
1060
   output [(data_width-1):0]      q_b;
1061
   input                         clk_a, clk_b;
1062
   reg [(addr_width-1):0]         adr_b_reg;
1063
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1064 7 unneback
   parameter init = 0;
1065
   parameter memory_file = "vl_ram.vmem";
1066
   generate if (init) begin : init_mem
1067
   initial
1068
     begin
1069
        $readmemh(memory_file, ram);
1070
     end
1071
   end
1072
   endgenerate
1073 6 unneback
   always @ (posedge clk_a)
1074
   if (we_a)
1075
     ram[adr_a] <= d_a;
1076
   always @ (posedge clk_b)
1077
   adr_b_reg <= adr_b;
1078
   assign q_b = ram[adr_b_reg];
1079
endmodule
1080 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1081 6 unneback
   parameter data_width = 32;
1082
   parameter addr_width = 8;
1083
   input [(data_width-1):0]      d_a;
1084
   input [(addr_width-1):0]       adr_a;
1085
   input [(addr_width-1):0]       adr_b;
1086
   input                         we_a;
1087
   output [(data_width-1):0]      q_b;
1088
   output reg [(data_width-1):0] q_a;
1089
   input                         clk_a, clk_b;
1090
   reg [(data_width-1):0]         q_b;
1091
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1092 7 unneback
   parameter init = 0;
1093
   parameter memory_file = "vl_ram.vmem";
1094
   generate if (init) begin : init_mem
1095
   initial
1096
     begin
1097
        $readmemh(memory_file, ram);
1098
     end
1099
   end
1100
   endgenerate
1101 6 unneback
   always @ (posedge clk_a)
1102
     begin
1103
        q_a <= ram[adr_a];
1104
        if (we_a)
1105
             ram[adr_a] <= d_a;
1106
     end
1107
   always @ (posedge clk_b)
1108
          q_b <= ram[adr_b];
1109
endmodule
1110 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
1111 6 unneback
   parameter data_width = 32;
1112
   parameter addr_width = 8;
1113
   input [(data_width-1):0]      d_a;
1114
   input [(addr_width-1):0]       adr_a;
1115
   input [(addr_width-1):0]       adr_b;
1116
   input                         we_a;
1117
   output [(data_width-1):0]      q_b;
1118
   input [(data_width-1):0]       d_b;
1119
   output reg [(data_width-1):0] q_a;
1120
   input                         we_b;
1121
   input                         clk_a, clk_b;
1122
   reg [(data_width-1):0]         q_b;
1123
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1124 7 unneback
   parameter init = 0;
1125
   parameter memory_file = "vl_ram.vmem";
1126
   generate if (init) begin : init_mem
1127
   initial
1128
     begin
1129
        $readmemh(memory_file, ram);
1130
     end
1131
   end
1132
   endgenerate
1133 6 unneback
   always @ (posedge clk_a)
1134
     begin
1135
        q_a <= ram[adr_a];
1136
        if (we_a)
1137
             ram[adr_a] <= d_a;
1138
     end
1139
   always @ (posedge clk_b)
1140
     begin
1141
        q_b <= ram[adr_b];
1142
        if (we_b)
1143
          ram[adr_b] <= d_b;
1144
     end
1145
endmodule
1146
// Content addresable memory, CAM
1147
// FIFO
1148 25 unneback
module vl_fifo_1r1w_fill_level_sync (
1149
    d, wr, fifo_full,
1150
    q, rd, fifo_empty,
1151
    fill_level,
1152
    clk, rst
1153
    );
1154
parameter data_width = 18;
1155
parameter addr_width = 4;
1156
// write side
1157
input  [data_width-1:0] d;
1158
input                   wr;
1159
output                  fifo_full;
1160
// read side
1161
output [data_width-1:0] q;
1162
input                   rd;
1163
output                  fifo_empty;
1164
// common
1165
output [addr_width:0]   fill_level;
1166
input rst, clk;
1167
wire [addr_width:1] wadr, radr;
1168
vl_cnt_bin_ce
1169
    # ( .length(addr_width))
1170
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
1171
vl_cnt_bin_ce
1172
    # (.length(addr_width))
1173
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
1174
vl_dpram_1r1w
1175
    # (.data_width(data_width), .addr_width(addr_width))
1176
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
1177 31 unneback
vl_cnt_bin_ce_rew_q_zq_l1
1178 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
1179 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
1180
endmodule
1181 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
1182
// RAM is supposed to be larger than the two FIFOs
1183
// LFSR counters used adr pointers
1184
module vl_fifo_2r2w_sync_simplex (
1185
    // a side
1186
    a_d, a_wr, a_fifo_full,
1187
    a_q, a_rd, a_fifo_empty,
1188
    a_fill_level,
1189
    // b side
1190
    b_d, b_wr, b_fifo_full,
1191
    b_q, b_rd, b_fifo_empty,
1192
    b_fill_level,
1193
    // common
1194
    clk, rst
1195
    );
1196
parameter data_width = 8;
1197
parameter addr_width = 5;
1198
parameter fifo_full_level = (1<<addr_width)-1;
1199
// a side
1200
input  [data_width-1:0] a_d;
1201
input                   a_wr;
1202
output                  a_fifo_full;
1203
output [data_width-1:0] a_q;
1204
input                   a_rd;
1205
output                  a_fifo_empty;
1206
output [addr_width-1:0] a_fill_level;
1207
// b side
1208
input  [data_width-1:0] b_d;
1209
input                   b_wr;
1210
output                  b_fifo_full;
1211
output [data_width-1:0] b_q;
1212
input                   b_rd;
1213
output                  b_fifo_empty;
1214
output [addr_width-1:0] b_fill_level;
1215
input                   clk;
1216
input                   rst;
1217
// adr_gen
1218
wire [addr_width:1] a_wadr, a_radr;
1219
wire [addr_width:1] b_wadr, b_radr;
1220
// dpram
1221
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1222
vl_cnt_lfsr_ce
1223
    # ( .length(addr_width))
1224
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
1225
vl_cnt_lfsr_ce
1226
    # (.length(addr_width))
1227
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
1228
vl_cnt_lfsr_ce
1229
    # ( .length(addr_width))
1230
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
1231
vl_cnt_lfsr_ce
1232
    # (.length(addr_width))
1233
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
1234
// mux read or write adr to DPRAM
1235
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
1236
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
1237
vl_dpram_2r2w
1238
    # (.data_width(data_width), .addr_width(addr_width+1))
1239
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1240
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1241
vl_cnt_bin_ce_rew_zq_l1
1242 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
1243 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
1244
vl_cnt_bin_ce_rew_zq_l1
1245 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
1246 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
1247
endmodule
1248 6 unneback
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
1249 11 unneback
   parameter addr_width = 4;
1250
   parameter N = addr_width-1;
1251 6 unneback
   parameter Q1 = 2'b00;
1252
   parameter Q2 = 2'b01;
1253
   parameter Q3 = 2'b11;
1254
   parameter Q4 = 2'b10;
1255
   parameter going_empty = 1'b0;
1256
   parameter going_full  = 1'b1;
1257
   input [N:0]  wptr, rptr;
1258 14 unneback
   output       fifo_empty;
1259 6 unneback
   output       fifo_full;
1260
   input        wclk, rclk, rst;
1261
   wire direction;
1262
   reg  direction_set, direction_clr;
1263
   wire async_empty, async_full;
1264
   wire fifo_full2;
1265 14 unneback
   wire fifo_empty2;
1266 6 unneback
   // direction_set
1267
   always @ (wptr[N:N-1] or rptr[N:N-1])
1268
     case ({wptr[N:N-1],rptr[N:N-1]})
1269
       {Q1,Q2} : direction_set <= 1'b1;
1270
       {Q2,Q3} : direction_set <= 1'b1;
1271
       {Q3,Q4} : direction_set <= 1'b1;
1272
       {Q4,Q1} : direction_set <= 1'b1;
1273
       default : direction_set <= 1'b0;
1274
     endcase
1275
   // direction_clear
1276
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
1277
     if (rst)
1278
       direction_clr <= 1'b1;
1279
     else
1280
       case ({wptr[N:N-1],rptr[N:N-1]})
1281
         {Q2,Q1} : direction_clr <= 1'b1;
1282
         {Q3,Q2} : direction_clr <= 1'b1;
1283
         {Q4,Q3} : direction_clr <= 1'b1;
1284
         {Q1,Q4} : direction_clr <= 1'b1;
1285
         default : direction_clr <= 1'b0;
1286
       endcase
1287 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
1288 6 unneback
   assign async_empty = (wptr == rptr) && (direction==going_empty);
1289
   assign async_full  = (wptr == rptr) && (direction==going_full);
1290 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
1291
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
1292 6 unneback
/*
1293
   always @ (posedge wclk or posedge rst or posedge async_full)
1294
     if (rst)
1295
       {fifo_full, fifo_full2} <= 2'b00;
1296
     else if (async_full)
1297
       {fifo_full, fifo_full2} <= 2'b11;
1298
     else
1299
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
1300
*/
1301 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
1302 6 unneback
     if (async_empty)
1303
       {fifo_empty, fifo_empty2} <= 2'b11;
1304
     else
1305 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
1306 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
1307
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
1308 27 unneback
endmodule // async_compb
1309 6 unneback
module vl_fifo_1r1w_async (
1310
    d, wr, fifo_full, wr_clk, wr_rst,
1311
    q, rd, fifo_empty, rd_clk, rd_rst
1312
    );
1313
parameter data_width = 18;
1314
parameter addr_width = 4;
1315
// write side
1316
input  [data_width-1:0] d;
1317
input                   wr;
1318
output                  fifo_full;
1319
input                   wr_clk;
1320
input                   wr_rst;
1321
// read side
1322
output [data_width-1:0] q;
1323
input                   rd;
1324
output                  fifo_empty;
1325
input                   rd_clk;
1326
input                   rd_rst;
1327
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
1328 18 unneback
vl_cnt_gray_ce_bin
1329 6 unneback
    # ( .length(addr_width))
1330
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
1331 18 unneback
vl_cnt_gray_ce_bin
1332 6 unneback
    # (.length(addr_width))
1333 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
1334 7 unneback
vl_dpram_1r1w
1335 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
1336
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
1337
vl_fifo_cmp_async
1338
    # (.addr_width(addr_width))
1339
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
1340
endmodule
1341 8 unneback
module vl_fifo_2r2w_async (
1342 6 unneback
    // a side
1343
    a_d, a_wr, a_fifo_full,
1344
    a_q, a_rd, a_fifo_empty,
1345
    a_clk, a_rst,
1346
    // b side
1347
    b_d, b_wr, b_fifo_full,
1348
    b_q, b_rd, b_fifo_empty,
1349
    b_clk, b_rst
1350
    );
1351
parameter data_width = 18;
1352
parameter addr_width = 4;
1353
// a side
1354
input  [data_width-1:0] a_d;
1355
input                   a_wr;
1356
output                  a_fifo_full;
1357
output [data_width-1:0] a_q;
1358
input                   a_rd;
1359
output                  a_fifo_empty;
1360
input                   a_clk;
1361
input                   a_rst;
1362
// b side
1363
input  [data_width-1:0] b_d;
1364
input                   b_wr;
1365
output                  b_fifo_full;
1366
output [data_width-1:0] b_q;
1367
input                   b_rd;
1368
output                  b_fifo_empty;
1369
input                   b_clk;
1370
input                   b_rst;
1371
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1372
vl_fifo_1r1w_async_a (
1373
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
1374
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
1375
    );
1376
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1377
vl_fifo_1r1w_async_b (
1378
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
1379
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
1380
    );
1381
endmodule
1382 8 unneback
module vl_fifo_2r2w_async_simplex (
1383 6 unneback
    // a side
1384
    a_d, a_wr, a_fifo_full,
1385
    a_q, a_rd, a_fifo_empty,
1386
    a_clk, a_rst,
1387
    // b side
1388
    b_d, b_wr, b_fifo_full,
1389
    b_q, b_rd, b_fifo_empty,
1390
    b_clk, b_rst
1391
    );
1392
parameter data_width = 18;
1393
parameter addr_width = 4;
1394
// a side
1395
input  [data_width-1:0] a_d;
1396
input                   a_wr;
1397
output                  a_fifo_full;
1398
output [data_width-1:0] a_q;
1399
input                   a_rd;
1400
output                  a_fifo_empty;
1401
input                   a_clk;
1402
input                   a_rst;
1403
// b side
1404
input  [data_width-1:0] b_d;
1405
input                   b_wr;
1406
output                  b_fifo_full;
1407
output [data_width-1:0] b_q;
1408
input                   b_rd;
1409
output                  b_fifo_empty;
1410
input                   b_clk;
1411
input                   b_rst;
1412
// adr_gen
1413
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
1414
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
1415
// dpram
1416
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1417 18 unneback
vl_cnt_gray_ce_bin
1418 6 unneback
    # ( .length(addr_width))
1419
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
1420 18 unneback
vl_cnt_gray_ce_bin
1421 6 unneback
    # (.length(addr_width))
1422
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
1423 18 unneback
vl_cnt_gray_ce_bin
1424 6 unneback
    # ( .length(addr_width))
1425
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
1426 18 unneback
vl_cnt_gray_ce_bin
1427 6 unneback
    # (.length(addr_width))
1428
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
1429
// mux read or write adr to DPRAM
1430
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
1431
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
1432 11 unneback
vl_dpram_2r2w
1433 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
1434
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1435
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1436 11 unneback
vl_fifo_cmp_async
1437 6 unneback
    # (.addr_width(addr_width))
1438
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
1439 11 unneback
vl_fifo_cmp_async
1440 6 unneback
    # (.addr_width(addr_width))
1441
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
1442
endmodule
1443 12 unneback
//////////////////////////////////////////////////////////////////////
1444
////                                                              ////
1445
////  Versatile library, wishbone stuff                           ////
1446
////                                                              ////
1447
////  Description                                                 ////
1448
////  Wishbone compliant modules                                  ////
1449
////                                                              ////
1450
////                                                              ////
1451
////  To Do:                                                      ////
1452
////   -                                                          ////
1453
////                                                              ////
1454
////  Author(s):                                                  ////
1455
////      - Michael Unneback, unneback@opencores.org              ////
1456
////        ORSoC AB                                              ////
1457
////                                                              ////
1458
//////////////////////////////////////////////////////////////////////
1459
////                                                              ////
1460
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1461
////                                                              ////
1462
//// This source file may be used and distributed without         ////
1463
//// restriction provided that this copyright statement is not    ////
1464
//// removed from the file and that any derivative work contains  ////
1465
//// the original copyright notice and the associated disclaimer. ////
1466
////                                                              ////
1467
//// This source file is free software; you can redistribute it   ////
1468
//// and/or modify it under the terms of the GNU Lesser General   ////
1469
//// Public License as published by the Free Software Foundation; ////
1470
//// either version 2.1 of the License, or (at your option) any   ////
1471
//// later version.                                               ////
1472
////                                                              ////
1473
//// This source is distributed in the hope that it will be       ////
1474
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1475
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1476
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1477
//// details.                                                     ////
1478
////                                                              ////
1479
//// You should have received a copy of the GNU Lesser General    ////
1480
//// Public License along with this source; if not, download it   ////
1481
//// from http://www.opencores.org/lgpl.shtml                     ////
1482
////                                                              ////
1483
//////////////////////////////////////////////////////////////////////
1484
// async wb3 - wb3 bridge
1485
`timescale 1ns/1ns
1486 18 unneback
module vl_wb3wb3_bridge (
1487 12 unneback
        // wishbone slave side
1488
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
1489
        // wishbone master side
1490
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
1491
input [31:0] wbs_dat_i;
1492
input [31:2] wbs_adr_i;
1493
input [3:0]  wbs_sel_i;
1494
input [1:0]  wbs_bte_i;
1495
input [2:0]  wbs_cti_i;
1496
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
1497
output [31:0] wbs_dat_o;
1498 14 unneback
output wbs_ack_o;
1499 12 unneback
input wbs_clk, wbs_rst;
1500
output [31:0] wbm_dat_o;
1501
output reg [31:2] wbm_adr_o;
1502
output [3:0]  wbm_sel_o;
1503
output reg [1:0]  wbm_bte_o;
1504
output reg [2:0]  wbm_cti_o;
1505 14 unneback
output reg wbm_we_o;
1506
output wbm_cyc_o;
1507 12 unneback
output wbm_stb_o;
1508
input [31:0]  wbm_dat_i;
1509
input wbm_ack_i;
1510
input wbm_clk, wbm_rst;
1511
parameter addr_width = 4;
1512
// bte
1513
parameter linear       = 2'b00;
1514
parameter wrap4        = 2'b01;
1515
parameter wrap8        = 2'b10;
1516
parameter wrap16       = 2'b11;
1517
// cti
1518
parameter classic      = 3'b000;
1519
parameter incburst     = 3'b010;
1520
parameter endofburst   = 3'b111;
1521
parameter wbs_adr  = 1'b0;
1522
parameter wbs_data = 1'b1;
1523 33 unneback
parameter wbm_adr0      = 2'b00;
1524
parameter wbm_adr1      = 2'b01;
1525
parameter wbm_data      = 2'b10;
1526
parameter wbm_data_wait = 2'b11;
1527 12 unneback
reg [1:0] wbs_bte_reg;
1528
reg wbs;
1529
wire wbs_eoc_alert, wbm_eoc_alert;
1530
reg wbs_eoc, wbm_eoc;
1531
reg [1:0] wbm;
1532 14 unneback
wire [1:16] wbs_count, wbm_count;
1533 12 unneback
wire [35:0] a_d, a_q, b_d, b_q;
1534
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
1535
reg a_rd_reg;
1536
wire b_rd_adr, b_rd_data;
1537 14 unneback
wire b_rd_data_reg;
1538
wire [35:0] temp;
1539 12 unneback
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
1540
always @ (posedge wbs_clk or posedge wbs_rst)
1541
if (wbs_rst)
1542
        wbs_eoc <= 1'b0;
1543
else
1544
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
1545
                wbs_eoc <= wbs_bte_i==linear;
1546
        else if (wbs_eoc_alert & (a_rd | a_wr))
1547
                wbs_eoc <= 1'b1;
1548 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
1549 12 unneback
    cnt0 (
1550
        .cke(wbs_ack_o),
1551
        .clear(wbs_eoc),
1552
        .q(wbs_count),
1553
        .rst(wbs_rst),
1554
        .clk(wbs_clk));
1555
always @ (posedge wbs_clk or posedge wbs_rst)
1556
if (wbs_rst)
1557
        wbs <= wbs_adr;
1558
else
1559
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
1560
                wbs <= wbs_data;
1561
        else if (wbs_eoc & wbs_ack_o)
1562
                wbs <= wbs_adr;
1563
// wbs FIFO
1564
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
1565
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
1566
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
1567
              1'b0;
1568
assign a_rd = !a_fifo_empty;
1569
always @ (posedge wbs_clk or posedge wbs_rst)
1570
if (wbs_rst)
1571
        a_rd_reg <= 1'b0;
1572
else
1573
        a_rd_reg <= a_rd;
1574
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
1575
assign wbs_dat_o = a_q[35:4];
1576
always @ (posedge wbs_clk or posedge wbs_rst)
1577
if (wbs_rst)
1578 13 unneback
        wbs_bte_reg <= 2'b00;
1579 12 unneback
else
1580 13 unneback
        wbs_bte_reg <= wbs_bte_i;
1581 12 unneback
// wbm FIFO
1582
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
1583
always @ (posedge wbm_clk or posedge wbm_rst)
1584
if (wbm_rst)
1585
        wbm_eoc <= 1'b0;
1586
else
1587
        if (wbm==wbm_adr0 & !b_fifo_empty)
1588
                wbm_eoc <= b_q[4:3] == linear;
1589
        else if (wbm_eoc_alert & wbm_ack_i)
1590
                wbm_eoc <= 1'b1;
1591
always @ (posedge wbm_clk or posedge wbm_rst)
1592
if (wbm_rst)
1593
        wbm <= wbm_adr0;
1594
else
1595 33 unneback
/*
1596 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
1597
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
1598
        (wbm==wbm_adr1 & !wbm_we_o) |
1599
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
1600
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
1601 33 unneback
*/
1602
    case (wbm)
1603
    wbm_adr0:
1604
        if (!b_fifo_empty)
1605
            wbm <= wbm_adr1;
1606
    wbm_adr1:
1607
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
1608
            wbm <= wbm_data;
1609
    wbm_data:
1610
        if (wbm_ack_i & wbm_eoc)
1611
            wbm <= wbm_adr0;
1612
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
1613
            wbm <= wbm_data_wait;
1614
    wbm_data_wait:
1615
        if (!b_fifo_empty)
1616
            wbm <= wbm_data;
1617
    endcase
1618 12 unneback
assign b_d = {wbm_dat_i,4'b1111};
1619
assign b_wr = !wbm_we_o & wbm_ack_i;
1620
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
1621
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
1622
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
1623 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
1624 12 unneback
                   1'b0;
1625
assign b_rd = b_rd_adr | b_rd_data;
1626 18 unneback
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
1627
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
1628 12 unneback
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
1629 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
1630 12 unneback
    cnt1 (
1631
        .cke(wbm_ack_i),
1632
        .clear(wbm_eoc),
1633
        .q(wbm_count),
1634
        .rst(wbm_rst),
1635
        .clk(wbm_clk));
1636 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
1637
assign wbm_stb_o = (wbm==wbm_data);
1638 12 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
1639
if (wbm_rst)
1640
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
1641
else begin
1642
        if (wbm==wbm_adr0 & !b_fifo_empty)
1643
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
1644
        else if (wbm_eoc_alert & wbm_ack_i)
1645
                wbm_cti_o <= endofburst;
1646
end
1647
//async_fifo_dw_simplex_top
1648
vl_fifo_2r2w_async_simplex
1649
# ( .data_width(36), .addr_width(addr_width))
1650
fifo (
1651
    // a side
1652
    .a_d(a_d),
1653
    .a_wr(a_wr),
1654
    .a_fifo_full(a_fifo_full),
1655
    .a_q(a_q),
1656
    .a_rd(a_rd),
1657
    .a_fifo_empty(a_fifo_empty),
1658
    .a_clk(wbs_clk),
1659
    .a_rst(wbs_rst),
1660
    // b side
1661
    .b_d(b_d),
1662
    .b_wr(b_wr),
1663
    .b_fifo_full(b_fifo_full),
1664
    .b_q(b_q),
1665
    .b_rd(b_rd),
1666
    .b_fifo_empty(b_fifo_empty),
1667
    .b_clk(wbm_clk),
1668
    .b_rst(wbm_rst)
1669
    );
1670
endmodule
1671 39 unneback
module vl_wb3_arbiter_type1 (
1672
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
1673
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
1674
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
1675
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
1676
    wb_clk, wb_rst
1677
);
1678
parameter nr_of_ports = 3;
1679
parameter adr_size = 26;
1680
parameter adr_lo   = 2;
1681
parameter dat_size = 32;
1682
parameter sel_size = dat_size/8;
1683
localparam aw = (adr_size - adr_lo) * nr_of_ports;
1684
localparam dw = dat_size * nr_of_ports;
1685
localparam sw = sel_size * nr_of_ports;
1686
localparam cw = 3 * nr_of_ports;
1687
localparam bw = 2 * nr_of_ports;
1688
input  [dw-1:0] wbm_dat_o;
1689
input  [aw-1:0] wbm_adr_o;
1690
input  [sw-1:0] wbm_sel_o;
1691
input  [cw-1:0] wbm_cti_o;
1692
input  [bw-1:0] wbm_bte_o;
1693
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
1694
output [dw-1:0] wbm_dat_i;
1695
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
1696
output [dat_size-1:0] wbs_dat_i;
1697
output [adr_size-1:adr_lo] wbs_adr_i;
1698
output [sel_size-1:0] wbs_sel_i;
1699
output [2:0] wbs_cti_i;
1700
output [1:0] wbs_bte_i;
1701
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
1702
input  [dat_size-1:0] wbs_dat_o;
1703
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
1704
input wb_clk, wb_rst;
1705
wire [nr_of_ports-1:0] select;
1706
wire [nr_of_ports-1:0] state;
1707
wire [nr_of_ports-1:0] eoc; // end-of-cycle
1708
wire [nr_of_ports-1:0] sel;
1709
wire idle;
1710
genvar i;
1711
assign idle = !(|state);
1712
generate
1713
if (nr_of_ports == 2) begin
1714
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
1715
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
1716
    assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : 2'b00;
1717
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
1718
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
1719
end
1720
endgenerate
1721
generate
1722
if (nr_of_ports == 3) begin
1723
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
1724
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
1725
    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : 3'b000;
1726
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
1727
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
1728
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
1729
end
1730
endgenerate
1731
generate
1732
for (i=0;i<nr_of_ports;i=i+1) begin
1733
    vl_spr sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
1734
end
1735
endgenerate
1736
    assign sel = select | state;
1737
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
1738
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
1739
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
1740
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
1741
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
1742
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
1743
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
1744
    assign wbs_cyc_i = |sel;
1745
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
1746
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
1747
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
1748
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
1749
endmodule
1750 17 unneback
// WB ROM
1751 18 unneback
module vl_wb_boot_rom (
1752 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
1753 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
1754
    parameter adr_hi = 31;
1755
    parameter adr_lo = 28;
1756
    parameter adr_sel = 4'hf;
1757
    parameter addr_width = 5;
1758 33 unneback
/*
1759 17 unneback
`ifndef BOOT_ROM
1760
`define BOOT_ROM "boot_rom.v"
1761
`endif
1762 33 unneback
*/
1763 18 unneback
    input [adr_hi:2]    wb_adr_i;
1764
    input               wb_stb_i;
1765
    input               wb_cyc_i;
1766
    output [31:0]        wb_dat_o;
1767
    output              wb_ack_o;
1768
    output              hit_o;
1769
    input               wb_clk;
1770
    input               wb_rst;
1771
    wire hit;
1772
    reg [31:0] wb_dat;
1773
    reg wb_ack;
1774
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
1775 17 unneback
always @ (posedge wb_clk or posedge wb_rst)
1776
    if (wb_rst)
1777 18 unneback
        wb_dat <= 32'h15000000;
1778 17 unneback
    else
1779 18 unneback
         case (wb_adr_i[addr_width-1:2])
1780 33 unneback
`ifdef BOOT_ROM
1781 17 unneback
`include `BOOT_ROM
1782 33 unneback
`endif
1783 17 unneback
           /*
1784
            // Zero r0 and jump to 0x00000100
1785 18 unneback
 
1786
            1 : wb_dat <= 32'hA8200000;
1787
            2 : wb_dat <= 32'hA8C00100;
1788
            3 : wb_dat <= 32'h44003000;
1789
            4 : wb_dat <= 32'h15000000;
1790 17 unneback
            */
1791
           default:
1792 18 unneback
             wb_dat <= 32'h00000000;
1793 17 unneback
         endcase // case (wb_adr_i)
1794
always @ (posedge wb_clk or posedge wb_rst)
1795
    if (wb_rst)
1796 18 unneback
        wb_ack <= 1'b0;
1797 17 unneback
    else
1798 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
1799
assign hit_o = hit;
1800
assign wb_dat_o = wb_dat & {32{wb_ack}};
1801
assign wb_ack_o = wb_ack;
1802 17 unneback
endmodule
1803 32 unneback
module vl_wb_dpram (
1804
        // wishbone slave side a
1805
        wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
1806
        wbsa_clk, wbsa_rst,
1807
        // wishbone slave side a
1808
        wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
1809
        wbsb_clk, wbsb_rst);
1810
parameter data_width = 32;
1811
parameter addr_width = 8;
1812
parameter dat_o_mask_a = 1;
1813
parameter dat_o_mask_b = 1;
1814
input [31:0] wbsa_dat_i;
1815
input [addr_width-1:2] wbsa_adr_i;
1816
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
1817
output [31:0] wbsa_dat_o;
1818
output wbsa_ack_o;
1819
input wbsa_clk, wbsa_rst;
1820
input [31:0] wbsb_dat_i;
1821
input [addr_width-1:2] wbsb_adr_i;
1822
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
1823
output [31:0] wbsb_dat_o;
1824
output wbsb_ack_o;
1825
input wbsb_clk, wbsb_rst;
1826
wire wbsa_dat_tmp, wbsb_dat_tmp;
1827
vl_dpram_2r2w # (
1828 33 unneback
    .data_width(data_width), .addr_width(addr_width) )
1829 32 unneback
dpram0(
1830
    .d_a(wbsa_dat_i),
1831
    .q_a(wbsa_dat_tmp),
1832
    .adr_a(wbsa_adr_i),
1833
    .we_a(wbsa_we_i),
1834
    .clk_a(wbsa_clk),
1835
    .d_b(wbsb_dat_i),
1836
    .q_b(wbsb_dat_tmp),
1837
    .adr_b(wbsb_adr_i),
1838
    .we_b(wbsb_we_i),
1839
    .clk_b(wbsb_clk) );
1840 33 unneback
generate if (dat_o_mask_a==1)
1841 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
1842
endgenerate
1843 33 unneback
generate if (dat_o_mask_a==0)
1844 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp;
1845
endgenerate
1846 33 unneback
generate if (dat_o_mask_b==1)
1847 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
1848
endgenerate
1849 33 unneback
generate if (dat_o_mask_b==0)
1850 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp;
1851
endgenerate
1852
vl_spr ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
1853
vl_spr ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
1854
endmodule
1855 18 unneback
//////////////////////////////////////////////////////////////////////
1856
////                                                              ////
1857
////  Arithmetic functions                                        ////
1858
////                                                              ////
1859
////  Description                                                 ////
1860
////  Arithmetic functions for ALU and DSP                        ////
1861
////                                                              ////
1862
////                                                              ////
1863
////  To Do:                                                      ////
1864
////   -                                                          ////
1865
////                                                              ////
1866
////  Author(s):                                                  ////
1867
////      - Michael Unneback, unneback@opencores.org              ////
1868
////        ORSoC AB                                              ////
1869
////                                                              ////
1870
//////////////////////////////////////////////////////////////////////
1871
////                                                              ////
1872
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1873
////                                                              ////
1874
//// This source file may be used and distributed without         ////
1875
//// restriction provided that this copyright statement is not    ////
1876
//// removed from the file and that any derivative work contains  ////
1877
//// the original copyright notice and the associated disclaimer. ////
1878
////                                                              ////
1879
//// This source file is free software; you can redistribute it   ////
1880
//// and/or modify it under the terms of the GNU Lesser General   ////
1881
//// Public License as published by the Free Software Foundation; ////
1882
//// either version 2.1 of the License, or (at your option) any   ////
1883
//// later version.                                               ////
1884
////                                                              ////
1885
//// This source is distributed in the hope that it will be       ////
1886
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1887
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1888
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1889
//// details.                                                     ////
1890
////                                                              ////
1891
//// You should have received a copy of the GNU Lesser General    ////
1892
//// Public License along with this source; if not, download it   ////
1893
//// from http://www.opencores.org/lgpl.shtml                     ////
1894
////                                                              ////
1895
//////////////////////////////////////////////////////////////////////
1896
// signed multiplication
1897
module vl_mults (a,b,p);
1898
parameter operand_a_width = 18;
1899
parameter operand_b_width = 18;
1900
parameter result_hi = 35;
1901
parameter result_lo = 0;
1902
input [operand_a_width-1:0] a;
1903
input [operand_b_width-1:0] b;
1904
output [result_hi:result_lo] p;
1905
wire signed [operand_a_width-1:0] ai;
1906
wire signed [operand_b_width-1:0] bi;
1907
wire signed [operand_a_width+operand_b_width-1:0] result;
1908
    assign ai = a;
1909
    assign bi = b;
1910
    assign result = ai * bi;
1911
    assign p = result[result_hi:result_lo];
1912
endmodule
1913
module vl_mults18x18 (a,b,p);
1914
input [17:0] a,b;
1915
output [35:0] p;
1916
vl_mult
1917
    # (.operand_a_width(18), .operand_b_width(18))
1918
    mult0 (.a(a), .b(b), .p(p));
1919
endmodule
1920
// unsigned multiplication
1921
module vl_mult (a,b,p);
1922
parameter operand_a_width = 18;
1923
parameter operand_b_width = 18;
1924
parameter result_hi = 35;
1925
parameter result_lo = 0;
1926
input [operand_a_width-1:0] a;
1927
input [operand_b_width-1:0] b;
1928
output [result_hi:result_hi] p;
1929
wire [operand_a_width+operand_b_width-1:0] result;
1930
    assign result = a * b;
1931
    assign p = result[result_hi:result_lo];
1932
endmodule
1933
// shift unit
1934
// supporting the following shift functions
1935
//   SLL
1936
//   SRL
1937
//   SRA
1938
module vl_shift_unit_32( din, s, dout, opcode);
1939
input [31:0] din; // data in operand
1940
input [4:0] s; // shift operand
1941
input [1:0] opcode;
1942
output [31:0] dout;
1943
parameter opcode_sll = 2'b00;
1944
//parameter opcode_srl = 2'b01;
1945
parameter opcode_sra = 2'b10;
1946
//parameter opcode_ror = 2'b11;
1947
wire sll, sra;
1948
assign sll = opcode == opcode_sll;
1949
assign sra = opcode == opcode_sra;
1950
wire [15:1] s1;
1951
wire [3:0] sign;
1952
wire [7:0] tmp [0:3];
1953
// first stage is multiplier based
1954
// shift operand as fractional 8.7
1955
assign s1[15] = sll & s[2:0]==3'd7;
1956
assign s1[14] = sll & s[2:0]==3'd6;
1957
assign s1[13] = sll & s[2:0]==3'd5;
1958
assign s1[12] = sll & s[2:0]==3'd4;
1959
assign s1[11] = sll & s[2:0]==3'd3;
1960
assign s1[10] = sll & s[2:0]==3'd2;
1961
assign s1[ 9] = sll & s[2:0]==3'd1;
1962
assign s1[ 8] = s[2:0]==3'd0;
1963
assign s1[ 7] = !sll & s[2:0]==3'd1;
1964
assign s1[ 6] = !sll & s[2:0]==3'd2;
1965
assign s1[ 5] = !sll & s[2:0]==3'd3;
1966
assign s1[ 4] = !sll & s[2:0]==3'd4;
1967
assign s1[ 3] = !sll & s[2:0]==3'd5;
1968
assign s1[ 2] = !sll & s[2:0]==3'd6;
1969
assign s1[ 1] = !sll & s[2:0]==3'd7;
1970
assign sign[3] = din[31] & sra;
1971
assign sign[2] = sign[3] & (&din[31:24]);
1972
assign sign[1] = sign[2] & (&din[23:16]);
1973
assign sign[0] = sign[1] & (&din[15:8]);
1974
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
1975
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
1976
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
1977
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
1978
// second stage is multiplexer based
1979
// shift on byte level
1980
// mux byte 3
1981
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
1982
                     (sll & s[4:3]==2'b01) ? tmp[2] :
1983
                     (sll & s[4:3]==2'b10) ? tmp[1] :
1984
                     (sll & s[4:3]==2'b11) ? tmp[0] :
1985
                     {8{sign[3]}};
1986
// mux byte 2
1987
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
1988
                     (sll & s[4:3]==2'b01) ? tmp[1] :
1989
                     (sll & s[4:3]==2'b10) ? tmp[0] :
1990
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
1991
                     (s[4:3]==2'b01) ? tmp[3] :
1992
                     {8{sign[3]}};
1993
// mux byte 1
1994
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
1995
                     (sll & s[4:3]==2'b01) ? tmp[0] :
1996
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
1997
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
1998
                     (s[4:3]==2'b01) ? tmp[2] :
1999
                     (s[4:3]==2'b10) ? tmp[3] :
2000
                     {8{sign[3]}};
2001
// mux byte 0
2002
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
2003
                     (sll) ?  {8{1'b0}}:
2004
                     (s[4:3]==2'b01) ? tmp[1] :
2005
                     (s[4:3]==2'b10) ? tmp[2] :
2006
                     tmp[3];
2007
endmodule
2008
// logic unit
2009
// supporting the following logic functions
2010
//    a and b
2011
//    a or  b
2012
//    a xor b
2013
//    not b
2014
module vl_logic_unit( a, b, result, opcode);
2015
parameter width = 32;
2016
parameter opcode_and = 2'b00;
2017
parameter opcode_or  = 2'b01;
2018
parameter opcode_xor = 2'b10;
2019
input [width-1:0] a,b;
2020
output [width-1:0] result;
2021
input [1:0] opcode;
2022
assign result = (opcode==opcode_and) ? a & b :
2023
                (opcode==opcode_or)  ? a | b :
2024
                (opcode==opcode_xor) ? a ^ b :
2025
                b;
2026
endmodule
2027
module vl_arith_unit ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
2028
parameter width = 32;
2029
parameter opcode_add = 1'b0;
2030
parameter opcode_sub = 1'b1;
2031
input [width-1:0] a,b;
2032
input c_in, add_sub, sign;
2033
output [width-1:0] result;
2034
output c_out, z, ovfl;
2035
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
2036
assign z = (result=={width{1'b0}});
2037
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
2038
               (~a[width-1] & ~b[width-1] &  result[width-1]);
2039
endmodule

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