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1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  Versatile library, clock and reset                          ////
4
////                                                              ////
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////  Description                                                 ////
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////  Logic related to clock and reset                            ////
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////                                                              ////
8
////                                                              ////
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////  To Do:                                                      ////
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////   - add more different registers                             ////
11
////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
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////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
// Global buffer
43
// usage:
44
// use to enable global buffers for high fan out signals such as clock and reset
45
`timescale 1 ns/100 ps
46
// Version: 8.4 8.4.0.33
47
module gbuf(GL,CLK);
48
output GL;
49
input  CLK;
50
    wire GND;
51
    GND GND_1_net(.Y(GND));
52
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
53
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
54
endmodule
55
`timescale 1 ns/1 ns
56
module vl_gbuf ( i, o);
57
input i;
58
output o;
59
`ifdef SIM_GBUF
60
assign o=i;
61
`else
62
gbuf gbuf_i0 ( .CLK(i), .GL(o));
63
`endif
64
endmodule
65
 //ACTEL
66
// sync reset
67 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
68 6 unneback
// output active high global reset sync with two DFFs 
69
`timescale 1 ns/100 ps
70
module vl_sync_rst ( rst_n_i, rst_o, clk);
71
input rst_n_i, clk;
72
output rst_o;
73 18 unneback
reg [1:0] tmp;
74 6 unneback
always @ (posedge clk or negedge rst_n_i)
75
if (!rst_n_i)
76 17 unneback
        tmp <= 2'b11;
77 6 unneback
else
78 33 unneback
        tmp <= {1'b0,tmp[1]};
79 17 unneback
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
80 6 unneback
endmodule
81
// vl_pll
82 32 unneback
///////////////////////////////////////////////////////////////////////////////
83 17 unneback
`timescale 1 ps/1 ps
84 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
85
parameter index = 0;
86
parameter number_of_clk = 1;
87 17 unneback
parameter period_time_0 = 20000;
88
parameter period_time_1 = 20000;
89
parameter period_time_2 = 20000;
90
parameter lock_delay = 2000000;
91 6 unneback
input clk_i, rst_n_i;
92
output lock;
93
output reg [0:number_of_clk-1] clk_o;
94
output [0:number_of_clk-1] rst_o;
95
`ifdef SIM_PLL
96
always
97
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
98
generate if (number_of_clk > 1)
99
always
100
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
101
endgenerate
102
generate if (number_of_clk > 2)
103
always
104
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
105
endgenerate
106
genvar i;
107
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
108
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
109
end
110
endgenerate
111
assign #lock_delay lock = rst_n_i;
112
endmodule
113
`else
114
generate if (number_of_clk==1 & index==0) begin
115
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
116
end
117
endgenerate // index==0
118
generate if (number_of_clk==1 & index==1) begin
119
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
120
end
121
endgenerate // index==1
122
generate if (number_of_clk==1 & index==2) begin
123
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
124
end
125
endgenerate // index==2
126
generate if (number_of_clk==1 & index==3) begin
127
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
128
end
129
endgenerate // index==0
130
generate if (number_of_clk==2 & index==0) begin
131
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
132
end
133
endgenerate // index==0
134
generate if (number_of_clk==2 & index==1) begin
135
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
136
end
137
endgenerate // index==1
138
generate if (number_of_clk==2 & index==2) begin
139
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
140
end
141
endgenerate // index==2
142
generate if (number_of_clk==2 & index==3) begin
143
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
144
end
145
endgenerate // index==0
146
generate if (number_of_clk==3 & index==0) begin
147
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
148
end
149
endgenerate // index==0
150
generate if (number_of_clk==3 & index==1) begin
151
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
152
end
153
endgenerate // index==1
154
generate if (number_of_clk==3 & index==2) begin
155
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
156
end
157
endgenerate // index==2
158
generate if (number_of_clk==3 & index==3) begin
159
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
160
end
161
endgenerate // index==0
162
genvar i;
163
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
164 40 unneback
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
165 6 unneback
end
166
endgenerate
167
endmodule
168
`endif
169 32 unneback
///////////////////////////////////////////////////////////////////////////////
170 6 unneback
 //actel
171
//////////////////////////////////////////////////////////////////////
172
////                                                              ////
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////  Versatile library, registers                                ////
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////                                                              ////
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////  Description                                                 ////
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////  Different type of registers                                 ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
180
////   - add more different registers                             ////
181
////                                                              ////
182
////  Author(s):                                                  ////
183
////      - Michael Unneback, unneback@opencores.org              ////
184
////        ORSoC AB                                              ////
185
////                                                              ////
186
//////////////////////////////////////////////////////////////////////
187
////                                                              ////
188
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
189
////                                                              ////
190
//// This source file may be used and distributed without         ////
191
//// restriction provided that this copyright statement is not    ////
192
//// removed from the file and that any derivative work contains  ////
193
//// the original copyright notice and the associated disclaimer. ////
194
////                                                              ////
195
//// This source file is free software; you can redistribute it   ////
196
//// and/or modify it under the terms of the GNU Lesser General   ////
197
//// Public License as published by the Free Software Foundation; ////
198
//// either version 2.1 of the License, or (at your option) any   ////
199
//// later version.                                               ////
200
////                                                              ////
201
//// This source is distributed in the hope that it will be       ////
202
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
203
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
204
//// PURPOSE.  See the GNU Lesser General Public License for more ////
205
//// details.                                                     ////
206
////                                                              ////
207
//// You should have received a copy of the GNU Lesser General    ////
208
//// Public License along with this source; if not, download it   ////
209
//// from http://www.opencores.org/lgpl.shtml                     ////
210
////                                                              ////
211
//////////////////////////////////////////////////////////////////////
212 18 unneback
module vl_dff ( d, q, clk, rst);
213 6 unneback
        parameter width = 1;
214
        parameter reset_value = 0;
215
        input [width-1:0] d;
216
        input clk, rst;
217
        output reg [width-1:0] q;
218
        always @ (posedge clk or posedge rst)
219
        if (rst)
220
                q <= reset_value;
221
        else
222
                q <= d;
223
endmodule
224 18 unneback
module vl_dff_array ( d, q, clk, rst);
225 6 unneback
        parameter width = 1;
226
        parameter depth = 2;
227
        parameter reset_value = 1'b0;
228
        input [width-1:0] d;
229
        input clk, rst;
230
        output [width-1:0] q;
231
        reg  [0:depth-1] q_tmp [width-1:0];
232
        integer i;
233
        always @ (posedge clk or posedge rst)
234
        if (rst) begin
235
            for (i=0;i<depth;i=i+1)
236
                q_tmp[i] <= {width{reset_value}};
237
        end else begin
238
            q_tmp[0] <= d;
239
            for (i=1;i<depth;i=i+1)
240
                q_tmp[i] <= q_tmp[i-1];
241
        end
242
    assign q = q_tmp[depth-1];
243
endmodule
244 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
245 6 unneback
        parameter width = 1;
246
        parameter reset_value = 0;
247
        input [width-1:0] d;
248
        input ce, clk, rst;
249
        output reg [width-1:0] q;
250
        always @ (posedge clk or posedge rst)
251
        if (rst)
252
                q <= reset_value;
253
        else
254
                if (ce)
255
                        q <= d;
256
endmodule
257 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
258 8 unneback
        parameter width = 1;
259
        parameter reset_value = 0;
260
        input [width-1:0] d;
261 10 unneback
        input ce, clear, clk, rst;
262 8 unneback
        output reg [width-1:0] q;
263
        always @ (posedge clk or posedge rst)
264
        if (rst)
265
            q <= reset_value;
266
        else
267
            if (ce)
268
                if (clear)
269
                    q <= {width{1'b0}};
270
                else
271
                    q <= d;
272
endmodule
273 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
274
        parameter width = 1;
275
        parameter reset_value = 0;
276
        input [width-1:0] d;
277
        input ce, set, clk, rst;
278
        output reg [width-1:0] q;
279
        always @ (posedge clk or posedge rst)
280
        if (rst)
281
            q <= reset_value;
282
        else
283
            if (ce)
284
                if (set)
285
                    q <= {width{1'b1}};
286
                else
287
                    q <= d;
288
endmodule
289 29 unneback
module vl_spr ( sp, r, q, clk, rst);
290
        parameter width = 1;
291
        parameter reset_value = 0;
292
        input sp, r;
293
        output reg q;
294
        input clk, rst;
295
        always @ (posedge clk or posedge rst)
296
        if (rst)
297
            q <= reset_value;
298
        else
299
            if (sp)
300
                q <= 1'b1;
301
            else if (r)
302
                q <= 1'b0;
303
endmodule
304
module vl_srp ( s, rp, q, clk, rst);
305
        parameter width = 1;
306
        parameter reset_value = 0;
307
        input s, rp;
308
        output reg q;
309
        input clk, rst;
310
        always @ (posedge clk or posedge rst)
311
        if (rst)
312
            q <= reset_value;
313
        else
314
            if (rp)
315
                q <= 1'b0;
316
            else if (s)
317
                q <= 1'b1;
318
endmodule
319 18 unneback
module vl_dff_sr ( aclr, aset, clock, data, q);
320 6 unneback
    input         aclr;
321
    input         aset;
322
    input         clock;
323
    input         data;
324
    output reg    q;
325
   always @ (posedge clock or posedge aclr or posedge aset)
326
     if (aclr)
327
       q <= 1'b0;
328
     else if (aset)
329
       q <= 1'b1;
330
     else
331
       q <= data;
332
endmodule
333
// LATCH
334
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
335 40 unneback
module vl_latch ( d, le, q, clk);
336 6 unneback
input d, le;
337
output q;
338
input clk;/*
339
   always @ (posedge direction_set or posedge direction_clr)
340
     if (direction_clr)
341
       direction <= going_empty;
342
     else
343
       direction <= going_full;*/
344
endmodule
345 18 unneback
module vl_shreg ( d, q, clk, rst);
346 17 unneback
parameter depth = 10;
347
input d;
348
output q;
349
input clk, rst;
350
reg [1:depth] dffs;
351
always @ (posedge clk or posedge rst)
352
if (rst)
353
    dffs <= {depth{1'b0}};
354
else
355
    dffs <= {d,dffs[1:depth-1]};
356
assign q = dffs[depth];
357
endmodule
358 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
359 17 unneback
parameter depth = 10;
360
input d, ce;
361
output q;
362
input clk, rst;
363
reg [1:depth] dffs;
364
always @ (posedge clk or posedge rst)
365
if (rst)
366
    dffs <= {depth{1'b0}};
367
else
368
    if (ce)
369
        dffs <= {d,dffs[1:depth-1]};
370
assign q = dffs[depth];
371
endmodule
372 18 unneback
module vl_delay ( d, q, clk, rst);
373 15 unneback
parameter depth = 10;
374
input d;
375
output q;
376
input clk, rst;
377
reg [1:depth] dffs;
378
always @ (posedge clk or posedge rst)
379
if (rst)
380
    dffs <= {depth{1'b0}};
381
else
382
    dffs <= {d,dffs[1:depth-1]};
383
assign q = dffs[depth];
384
endmodule
385 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
386 17 unneback
parameter depth = 10;
387
input d;
388
output q, emptyflag;
389
input clk, rst;
390
reg [1:depth] dffs;
391
always @ (posedge clk or posedge rst)
392
if (rst)
393
    dffs <= {depth{1'b0}};
394
else
395
    dffs <= {d,dffs[1:depth-1]};
396
assign q = dffs[depth];
397
assign emptyflag = !(|dffs);
398
endmodule
399 6 unneback
//////////////////////////////////////////////////////////////////////
400
////                                                              ////
401 18 unneback
////  Logic functions                                             ////
402
////                                                              ////
403
////  Description                                                 ////
404
////  Logic functions such as multiplexers                        ////
405
////                                                              ////
406
////                                                              ////
407
////  To Do:                                                      ////
408
////   -                                                          ////
409
////                                                              ////
410
////  Author(s):                                                  ////
411
////      - Michael Unneback, unneback@opencores.org              ////
412
////        ORSoC AB                                              ////
413
////                                                              ////
414
//////////////////////////////////////////////////////////////////////
415
////                                                              ////
416
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
417
////                                                              ////
418
//// This source file may be used and distributed without         ////
419
//// restriction provided that this copyright statement is not    ////
420
//// removed from the file and that any derivative work contains  ////
421
//// the original copyright notice and the associated disclaimer. ////
422
////                                                              ////
423
//// This source file is free software; you can redistribute it   ////
424
//// and/or modify it under the terms of the GNU Lesser General   ////
425
//// Public License as published by the Free Software Foundation; ////
426
//// either version 2.1 of the License, or (at your option) any   ////
427
//// later version.                                               ////
428
////                                                              ////
429
//// This source is distributed in the hope that it will be       ////
430
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
431
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
432
//// PURPOSE.  See the GNU Lesser General Public License for more ////
433
//// details.                                                     ////
434
////                                                              ////
435
//// You should have received a copy of the GNU Lesser General    ////
436
//// Public License along with this source; if not, download it   ////
437
//// from http://www.opencores.org/lgpl.shtml                     ////
438
////                                                              ////
439
//////////////////////////////////////////////////////////////////////
440 36 unneback
module vl_mux_andor ( a, sel, dout);
441
parameter width = 32;
442
parameter nr_of_ports = 4;
443
input [nr_of_ports*width-1:0] a;
444
input [nr_of_ports-1:0] sel;
445
output reg [width-1:0] dout;
446 38 unneback
integer i,j;
447 36 unneback
always @ (a, sel)
448
begin
449
    dout = a[width-1:0] & {width{sel[0]}};
450 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
451
        for (j=0;j<width;j=j+1)
452
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
453 36 unneback
end
454
endmodule
455 34 unneback
module vl_mux2_andor ( a1, a0, sel, dout);
456
parameter width = 32;
457 35 unneback
localparam nr_of_ports = 2;
458 34 unneback
input [width-1:0] a1, a0;
459
input [nr_of_ports-1:0] sel;
460
output [width-1:0] dout;
461 36 unneback
vl_mux_andor
462 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
463 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
464 34 unneback
endmodule
465
module vl_mux3_andor ( a2, a1, a0, sel, dout);
466
parameter width = 32;
467 35 unneback
localparam nr_of_ports = 3;
468 34 unneback
input [width-1:0] a2, a1, a0;
469
input [nr_of_ports-1:0] sel;
470
output [width-1:0] dout;
471 36 unneback
vl_mux_andor
472 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
473 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
474 34 unneback
endmodule
475 18 unneback
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
476
parameter width = 32;
477 35 unneback
localparam nr_of_ports = 4;
478 18 unneback
input [width-1:0] a3, a2, a1, a0;
479
input [nr_of_ports-1:0] sel;
480 22 unneback
output [width-1:0] dout;
481 36 unneback
vl_mux_andor
482 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
483 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
484 18 unneback
endmodule
485
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
486
parameter width = 32;
487 35 unneback
localparam nr_of_ports = 5;
488 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
489
input [nr_of_ports-1:0] sel;
490 22 unneback
output [width-1:0] dout;
491 36 unneback
vl_mux_andor
492 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
493 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
494 18 unneback
endmodule
495
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
496
parameter width = 32;
497 35 unneback
localparam nr_of_ports = 6;
498 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
499
input [nr_of_ports-1:0] sel;
500 22 unneback
output [width-1:0] dout;
501 36 unneback
vl_mux_andor
502 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
503 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
504 18 unneback
endmodule
505 43 unneback
module vl_parity_generate (data, parity);
506
parameter word_size = 32;
507
parameter chunk_size = 8;
508
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
509
input [word_size-1:0] data;
510
output reg [word_size/chunk_size-1:0] parity;
511
integer i,j;
512
always @ (data)
513
for (i=0;i<word_size/chunk_size;i=i+1) begin
514
    parity[i] = parity_type;
515
    for (j=0;j<chunk_size;j=j+1) begin
516
        parity[i] = data[i+j] ^ parity[i];
517
    end
518
end
519
endmodule
520
module vl_parity_check( data, parity, parity_error);
521
parameter word_size = 32;
522
parameter chunk_size = 8;
523
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
524
input [word_size-1:0] data;
525
input [word_size/chunk_size-1:0] parity;
526
output parity_error;
527
reg [chunk_size-1:0] error_flag;
528
integer i,j;
529
always @ (data or parity)
530
for (i=0;i<word_size/chunk_size;i=i+1) begin
531
    error_flag[i] = parity[i] ^ parity_type;
532
    for (j=0;j<chunk_size;j=j+1) begin
533
        error_flag[i] = data[i+j] ^ error_flag[i];
534
    end
535
end
536
assign parity_error = |error_flag;
537
endmodule
538 18 unneback
//////////////////////////////////////////////////////////////////////
539
////                                                              ////
540 6 unneback
////  Versatile counter                                           ////
541
////                                                              ////
542
////  Description                                                 ////
543
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
544
////  counter                                                     ////
545
////                                                              ////
546
////  To Do:                                                      ////
547
////   - add LFSR with more taps                                  ////
548
////                                                              ////
549
////  Author(s):                                                  ////
550
////      - Michael Unneback, unneback@opencores.org              ////
551
////        ORSoC AB                                              ////
552
////                                                              ////
553
//////////////////////////////////////////////////////////////////////
554
////                                                              ////
555
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
556
////                                                              ////
557
//// This source file may be used and distributed without         ////
558
//// restriction provided that this copyright statement is not    ////
559
//// removed from the file and that any derivative work contains  ////
560
//// the original copyright notice and the associated disclaimer. ////
561
////                                                              ////
562
//// This source file is free software; you can redistribute it   ////
563
//// and/or modify it under the terms of the GNU Lesser General   ////
564
//// Public License as published by the Free Software Foundation; ////
565
//// either version 2.1 of the License, or (at your option) any   ////
566
//// later version.                                               ////
567
////                                                              ////
568
//// This source is distributed in the hope that it will be       ////
569
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
570
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
571
//// PURPOSE.  See the GNU Lesser General Public License for more ////
572
//// details.                                                     ////
573
////                                                              ////
574
//// You should have received a copy of the GNU Lesser General    ////
575
//// Public License along with this source; if not, download it   ////
576
//// from http://www.opencores.org/lgpl.shtml                     ////
577
////                                                              ////
578
//////////////////////////////////////////////////////////////////////
579
// binary counter
580 40 unneback
module vl_cnt_bin_ce (
581
 cke, q, rst, clk);
582 22 unneback
   parameter length = 4;
583 6 unneback
   input cke;
584
   output [length:1] q;
585
   input rst;
586
   input clk;
587
   parameter clear_value = 0;
588
   parameter set_value = 1;
589
   parameter wrap_value = 0;
590
   parameter level1_value = 15;
591
   reg  [length:1] qi;
592
   wire [length:1] q_next;
593
   assign q_next = qi + {{length-1{1'b0}},1'b1};
594
   always @ (posedge clk or posedge rst)
595
     if (rst)
596
       qi <= {length{1'b0}};
597
     else
598
     if (cke)
599
       qi <= q_next;
600
   assign q = qi;
601
endmodule
602
//////////////////////////////////////////////////////////////////////
603
////                                                              ////
604
////  Versatile counter                                           ////
605
////                                                              ////
606
////  Description                                                 ////
607
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
608
////  counter                                                     ////
609
////                                                              ////
610
////  To Do:                                                      ////
611
////   - add LFSR with more taps                                  ////
612
////                                                              ////
613
////  Author(s):                                                  ////
614
////      - Michael Unneback, unneback@opencores.org              ////
615
////        ORSoC AB                                              ////
616
////                                                              ////
617
//////////////////////////////////////////////////////////////////////
618
////                                                              ////
619
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
620
////                                                              ////
621
//// This source file may be used and distributed without         ////
622
//// restriction provided that this copyright statement is not    ////
623
//// removed from the file and that any derivative work contains  ////
624
//// the original copyright notice and the associated disclaimer. ////
625
////                                                              ////
626
//// This source file is free software; you can redistribute it   ////
627
//// and/or modify it under the terms of the GNU Lesser General   ////
628
//// Public License as published by the Free Software Foundation; ////
629
//// either version 2.1 of the License, or (at your option) any   ////
630
//// later version.                                               ////
631
////                                                              ////
632
//// This source is distributed in the hope that it will be       ////
633
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
634
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
635
//// PURPOSE.  See the GNU Lesser General Public License for more ////
636
//// details.                                                     ////
637
////                                                              ////
638
//// You should have received a copy of the GNU Lesser General    ////
639
//// Public License along with this source; if not, download it   ////
640
//// from http://www.opencores.org/lgpl.shtml                     ////
641
////                                                              ////
642
//////////////////////////////////////////////////////////////////////
643
// binary counter
644 40 unneback
module vl_cnt_bin_ce_rew_zq_l1 (
645
 cke, rew, zq, level1, rst, clk);
646 6 unneback
   parameter length = 4;
647
   input cke;
648
   input rew;
649 25 unneback
   output reg zq;
650
   output reg level1;
651
   input rst;
652
   input clk;
653
   parameter clear_value = 0;
654
   parameter set_value = 1;
655
   parameter wrap_value = 1;
656
   parameter level1_value = 15;
657 29 unneback
   wire clear;
658 30 unneback
   assign clear = 1'b0;
659 25 unneback
   reg  [length:1] qi;
660
   wire  [length:1] q_next, q_next_fw, q_next_rew;
661
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
662
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
663
   assign q_next = rew ? q_next_rew : q_next_fw;
664
   always @ (posedge clk or posedge rst)
665
     if (rst)
666
       qi <= {length{1'b0}};
667
     else
668
     if (cke)
669
       qi <= q_next;
670
   always @ (posedge clk or posedge rst)
671
     if (rst)
672
       zq <= 1'b1;
673
     else
674
     if (cke)
675
       zq <= q_next == {length{1'b0}};
676
    always @ (posedge clk or posedge rst)
677
    if (rst)
678
        level1 <= 1'b0;
679
    else
680
    if (cke)
681 29 unneback
    if (clear)
682
        level1 <= 1'b0;
683
    else if (q_next == level1_value)
684 25 unneback
        level1 <= 1'b1;
685
    else if (qi == level1_value & rew)
686
        level1 <= 1'b0;
687
endmodule
688
//////////////////////////////////////////////////////////////////////
689
////                                                              ////
690
////  Versatile counter                                           ////
691
////                                                              ////
692
////  Description                                                 ////
693
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
694
////  counter                                                     ////
695
////                                                              ////
696
////  To Do:                                                      ////
697
////   - add LFSR with more taps                                  ////
698
////                                                              ////
699
////  Author(s):                                                  ////
700
////      - Michael Unneback, unneback@opencores.org              ////
701
////        ORSoC AB                                              ////
702
////                                                              ////
703
//////////////////////////////////////////////////////////////////////
704
////                                                              ////
705
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
706
////                                                              ////
707
//// This source file may be used and distributed without         ////
708
//// restriction provided that this copyright statement is not    ////
709
//// removed from the file and that any derivative work contains  ////
710
//// the original copyright notice and the associated disclaimer. ////
711
////                                                              ////
712
//// This source file is free software; you can redistribute it   ////
713
//// and/or modify it under the terms of the GNU Lesser General   ////
714
//// Public License as published by the Free Software Foundation; ////
715
//// either version 2.1 of the License, or (at your option) any   ////
716
//// later version.                                               ////
717
////                                                              ////
718
//// This source is distributed in the hope that it will be       ////
719
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
720
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
721
//// PURPOSE.  See the GNU Lesser General Public License for more ////
722
//// details.                                                     ////
723
////                                                              ////
724
//// You should have received a copy of the GNU Lesser General    ////
725
//// Public License along with this source; if not, download it   ////
726
//// from http://www.opencores.org/lgpl.shtml                     ////
727
////                                                              ////
728
//////////////////////////////////////////////////////////////////////
729
// binary counter
730 40 unneback
module vl_cnt_bin_ce_rew_q_zq_l1 (
731
 cke, rew, q, zq, level1, rst, clk);
732 25 unneback
   parameter length = 4;
733
   input cke;
734
   input rew;
735
   output [length:1] q;
736
   output reg zq;
737
   output reg level1;
738
   input rst;
739
   input clk;
740
   parameter clear_value = 0;
741
   parameter set_value = 1;
742
   parameter wrap_value = 1;
743
   parameter level1_value = 15;
744 29 unneback
   wire clear;
745 30 unneback
   assign clear = 1'b0;
746 25 unneback
   reg  [length:1] qi;
747
   wire  [length:1] q_next, q_next_fw, q_next_rew;
748
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
749
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
750
   assign q_next = rew ? q_next_rew : q_next_fw;
751
   always @ (posedge clk or posedge rst)
752
     if (rst)
753
       qi <= {length{1'b0}};
754
     else
755
     if (cke)
756
       qi <= q_next;
757
   assign q = qi;
758
   always @ (posedge clk or posedge rst)
759
     if (rst)
760
       zq <= 1'b1;
761
     else
762
     if (cke)
763
       zq <= q_next == {length{1'b0}};
764
    always @ (posedge clk or posedge rst)
765
    if (rst)
766
        level1 <= 1'b0;
767
    else
768
    if (cke)
769 29 unneback
    if (clear)
770
        level1 <= 1'b0;
771
    else if (q_next == level1_value)
772 25 unneback
        level1 <= 1'b1;
773
    else if (qi == level1_value & rew)
774
        level1 <= 1'b0;
775
endmodule
776
//////////////////////////////////////////////////////////////////////
777
////                                                              ////
778
////  Versatile counter                                           ////
779
////                                                              ////
780
////  Description                                                 ////
781
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
782
////  counter                                                     ////
783
////                                                              ////
784
////  To Do:                                                      ////
785
////   - add LFSR with more taps                                  ////
786
////                                                              ////
787
////  Author(s):                                                  ////
788
////      - Michael Unneback, unneback@opencores.org              ////
789
////        ORSoC AB                                              ////
790
////                                                              ////
791
//////////////////////////////////////////////////////////////////////
792
////                                                              ////
793
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
794
////                                                              ////
795
//// This source file may be used and distributed without         ////
796
//// restriction provided that this copyright statement is not    ////
797
//// removed from the file and that any derivative work contains  ////
798
//// the original copyright notice and the associated disclaimer. ////
799
////                                                              ////
800
//// This source file is free software; you can redistribute it   ////
801
//// and/or modify it under the terms of the GNU Lesser General   ////
802
//// Public License as published by the Free Software Foundation; ////
803
//// either version 2.1 of the License, or (at your option) any   ////
804
//// later version.                                               ////
805
////                                                              ////
806
//// This source is distributed in the hope that it will be       ////
807
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
808
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
809
//// PURPOSE.  See the GNU Lesser General Public License for more ////
810
//// details.                                                     ////
811
////                                                              ////
812
//// You should have received a copy of the GNU Lesser General    ////
813
//// Public License along with this source; if not, download it   ////
814
//// from http://www.opencores.org/lgpl.shtml                     ////
815
////                                                              ////
816
//////////////////////////////////////////////////////////////////////
817 6 unneback
// GRAY counter
818 40 unneback
module vl_cnt_gray_ce_bin (
819
 cke, q, q_bin, rst, clk);
820 6 unneback
   parameter length = 4;
821
   input cke;
822
   output reg [length:1] q;
823
   output [length:1] q_bin;
824
   input rst;
825
   input clk;
826
   parameter clear_value = 0;
827
   parameter set_value = 1;
828
   parameter wrap_value = 8;
829
   parameter level1_value = 15;
830
   reg  [length:1] qi;
831
   wire [length:1] q_next;
832
   assign q_next = qi + {{length-1{1'b0}},1'b1};
833
   always @ (posedge clk or posedge rst)
834
     if (rst)
835
       qi <= {length{1'b0}};
836
     else
837
     if (cke)
838
       qi <= q_next;
839
   always @ (posedge clk or posedge rst)
840
     if (rst)
841
       q <= {length{1'b0}};
842
     else
843
       if (cke)
844
         q <= (q_next>>1) ^ q_next;
845
   assign q_bin = qi;
846
endmodule
847
//////////////////////////////////////////////////////////////////////
848
////                                                              ////
849
////  Versatile library, counters                                 ////
850
////                                                              ////
851
////  Description                                                 ////
852
////  counters                                                    ////
853
////                                                              ////
854
////                                                              ////
855
////  To Do:                                                      ////
856
////   - add more counters                                        ////
857
////                                                              ////
858
////  Author(s):                                                  ////
859
////      - Michael Unneback, unneback@opencores.org              ////
860
////        ORSoC AB                                              ////
861
////                                                              ////
862
//////////////////////////////////////////////////////////////////////
863
////                                                              ////
864
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
865
////                                                              ////
866
//// This source file may be used and distributed without         ////
867
//// restriction provided that this copyright statement is not    ////
868
//// removed from the file and that any derivative work contains  ////
869
//// the original copyright notice and the associated disclaimer. ////
870
////                                                              ////
871
//// This source file is free software; you can redistribute it   ////
872
//// and/or modify it under the terms of the GNU Lesser General   ////
873
//// Public License as published by the Free Software Foundation; ////
874
//// either version 2.1 of the License, or (at your option) any   ////
875
//// later version.                                               ////
876
////                                                              ////
877
//// This source is distributed in the hope that it will be       ////
878
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
879
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
880
//// PURPOSE.  See the GNU Lesser General Public License for more ////
881
//// details.                                                     ////
882
////                                                              ////
883
//// You should have received a copy of the GNU Lesser General    ////
884
//// Public License along with this source; if not, download it   ////
885
//// from http://www.opencores.org/lgpl.shtml                     ////
886
////                                                              ////
887
//////////////////////////////////////////////////////////////////////
888 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
889 6 unneback
   parameter length = 4;
890
   output reg [0:length-1] q;
891
   input rst;
892
   input clk;
893
    always @ (posedge clk or posedge rst)
894
    if (rst)
895
        q <= {1'b1,{length-1{1'b0}}};
896
    else
897
        q <= {q[length-1],q[0:length-2]};
898
endmodule
899 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
900 6 unneback
   parameter length = 4;
901
   input cke;
902
   output reg [0:length-1] q;
903
   input rst;
904
   input clk;
905
    always @ (posedge clk or posedge rst)
906
    if (rst)
907
        q <= {1'b1,{length-1{1'b0}}};
908
    else
909
        if (cke)
910
            q <= {q[length-1],q[0:length-2]};
911
endmodule
912 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
913 6 unneback
   parameter length = 4;
914
   input cke, clear;
915
   output reg [0:length-1] q;
916
   input rst;
917
   input clk;
918
    always @ (posedge clk or posedge rst)
919
    if (rst)
920
        q <= {1'b1,{length-1{1'b0}}};
921
    else
922
        if (cke)
923
            if (clear)
924
                q <= {1'b1,{length-1{1'b0}}};
925
            else
926
                q <= q >> 1;
927
endmodule
928 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
929 6 unneback
   parameter length = 4;
930
   input cke, clear;
931
   output reg [0:length-1] q;
932
   input rst;
933
   input clk;
934
    always @ (posedge clk or posedge rst)
935
    if (rst)
936
        q <= {1'b1,{length-1{1'b0}}};
937
    else
938
        if (cke)
939
            if (clear)
940
                q <= {1'b1,{length-1{1'b0}}};
941
            else
942
            q <= {q[length-1],q[0:length-2]};
943
endmodule
944
//////////////////////////////////////////////////////////////////////
945
////                                                              ////
946
////  Versatile library, memories                                 ////
947
////                                                              ////
948
////  Description                                                 ////
949
////  memories                                                    ////
950
////                                                              ////
951
////                                                              ////
952
////  To Do:                                                      ////
953
////   - add more memory types                                    ////
954
////                                                              ////
955
////  Author(s):                                                  ////
956
////      - Michael Unneback, unneback@opencores.org              ////
957
////        ORSoC AB                                              ////
958
////                                                              ////
959
//////////////////////////////////////////////////////////////////////
960
////                                                              ////
961
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
962
////                                                              ////
963
//// This source file may be used and distributed without         ////
964
//// restriction provided that this copyright statement is not    ////
965
//// removed from the file and that any derivative work contains  ////
966
//// the original copyright notice and the associated disclaimer. ////
967
////                                                              ////
968
//// This source file is free software; you can redistribute it   ////
969
//// and/or modify it under the terms of the GNU Lesser General   ////
970
//// Public License as published by the Free Software Foundation; ////
971
//// either version 2.1 of the License, or (at your option) any   ////
972
//// later version.                                               ////
973
////                                                              ////
974
//// This source is distributed in the hope that it will be       ////
975
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
976
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
977
//// PURPOSE.  See the GNU Lesser General Public License for more ////
978
//// details.                                                     ////
979
////                                                              ////
980
//// You should have received a copy of the GNU Lesser General    ////
981
//// Public License along with this source; if not, download it   ////
982
//// from http://www.opencores.org/lgpl.shtml                     ////
983
////                                                              ////
984
//////////////////////////////////////////////////////////////////////
985
/// ROM
986 7 unneback
module vl_rom_init ( adr, q, clk);
987
   parameter data_width = 32;
988
   parameter addr_width = 8;
989
   input [(addr_width-1):0]       adr;
990
   output reg [(data_width-1):0] q;
991
   input                         clk;
992
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
993
   parameter memory_file = "vl_rom.vmem";
994
   initial
995
     begin
996
        $readmemh(memory_file, rom);
997
     end
998
   always @ (posedge clk)
999
     q <= rom[adr];
1000
endmodule
1001 14 unneback
/*
1002 7 unneback
module vl_rom ( adr, q, clk);
1003 6 unneback
parameter data_width = 32;
1004
parameter addr_width = 4;
1005
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
1006
    {32'h18000000},
1007
    {32'hA8200000},
1008
    {32'hA8200000},
1009
    {32'hA8200000},
1010
    {32'h44003000},
1011
    {32'h15000000},
1012
    {32'h15000000},
1013
    {32'h15000000},
1014
    {32'h15000000},
1015
    {32'h15000000},
1016
    {32'h15000000},
1017
    {32'h15000000},
1018
    {32'h15000000},
1019
    {32'h15000000},
1020
    {32'h15000000},
1021
    {32'h15000000}};
1022 7 unneback
input [addr_width-1:0] adr;
1023 6 unneback
output reg [data_width-1:0] q;
1024
input clk;
1025
always @ (posedge clk)
1026 7 unneback
    q <= data[adr];
1027 6 unneback
endmodule
1028 14 unneback
*/
1029 6 unneback
// Single port RAM
1030
module vl_ram ( d, adr, we, q, clk);
1031
   parameter data_width = 32;
1032
   parameter addr_width = 8;
1033
   input [(data_width-1):0]      d;
1034
   input [(addr_width-1):0]       adr;
1035
   input                         we;
1036 7 unneback
   output reg [(data_width-1):0] q;
1037 6 unneback
   input                         clk;
1038
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1039 7 unneback
   parameter init = 0;
1040
   parameter memory_file = "vl_ram.vmem";
1041
   generate if (init) begin : init_mem
1042
   initial
1043
     begin
1044
        $readmemh(memory_file, ram);
1045
     end
1046
   end
1047
   endgenerate
1048 6 unneback
   always @ (posedge clk)
1049
   begin
1050
   if (we)
1051
     ram[adr] <= d;
1052
   q <= ram[adr];
1053
   end
1054
endmodule
1055 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
1056
   parameter data_width = 32;
1057
   parameter addr_width = 8;
1058
   input [(data_width-1):0]      d;
1059
   input [(addr_width-1):0]       adr;
1060
   input [(addr_width/4)-1:0]    be;
1061
   input                         we;
1062
   output reg [(data_width-1):0] q;
1063
   input                         clk;
1064
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1065
   parameter init = 0;
1066
   parameter memory_file = "vl_ram.vmem";
1067
   generate if (init) begin : init_mem
1068
   initial
1069
     begin
1070
        $readmemh(memory_file, ram);
1071
     end
1072
   end
1073
   endgenerate
1074
   genvar i;
1075
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
1076
      always @ (posedge clk)
1077
      if (we & be[i])
1078
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
1079
   end
1080
   endgenerate
1081
   always @ (posedge clk)
1082
      q <= ram[adr];
1083
endmodule
1084 6 unneback
// Dual port RAM
1085
// ACTEL FPGA should not use logic to handle rw collision
1086 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1087 6 unneback
   parameter data_width = 32;
1088
   parameter addr_width = 8;
1089
   input [(data_width-1):0]      d_a;
1090
   input [(addr_width-1):0]       adr_a;
1091
   input [(addr_width-1):0]       adr_b;
1092
   input                         we_a;
1093
   output [(data_width-1):0]      q_b;
1094
   input                         clk_a, clk_b;
1095
   reg [(addr_width-1):0]         adr_b_reg;
1096
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1097 7 unneback
   parameter init = 0;
1098
   parameter memory_file = "vl_ram.vmem";
1099
   generate if (init) begin : init_mem
1100
   initial
1101
     begin
1102
        $readmemh(memory_file, ram);
1103
     end
1104
   end
1105
   endgenerate
1106 6 unneback
   always @ (posedge clk_a)
1107
   if (we_a)
1108
     ram[adr_a] <= d_a;
1109
   always @ (posedge clk_b)
1110
   adr_b_reg <= adr_b;
1111
   assign q_b = ram[adr_b_reg];
1112
endmodule
1113 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1114 6 unneback
   parameter data_width = 32;
1115
   parameter addr_width = 8;
1116
   input [(data_width-1):0]      d_a;
1117
   input [(addr_width-1):0]       adr_a;
1118
   input [(addr_width-1):0]       adr_b;
1119
   input                         we_a;
1120
   output [(data_width-1):0]      q_b;
1121
   output reg [(data_width-1):0] q_a;
1122
   input                         clk_a, clk_b;
1123
   reg [(data_width-1):0]         q_b;
1124
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1125 7 unneback
   parameter init = 0;
1126
   parameter memory_file = "vl_ram.vmem";
1127
   generate if (init) begin : init_mem
1128
   initial
1129
     begin
1130
        $readmemh(memory_file, ram);
1131
     end
1132
   end
1133
   endgenerate
1134 6 unneback
   always @ (posedge clk_a)
1135
     begin
1136
        q_a <= ram[adr_a];
1137
        if (we_a)
1138
             ram[adr_a] <= d_a;
1139
     end
1140
   always @ (posedge clk_b)
1141
          q_b <= ram[adr_b];
1142
endmodule
1143 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
1144 6 unneback
   parameter data_width = 32;
1145
   parameter addr_width = 8;
1146
   input [(data_width-1):0]      d_a;
1147
   input [(addr_width-1):0]       adr_a;
1148
   input [(addr_width-1):0]       adr_b;
1149
   input                         we_a;
1150
   output [(data_width-1):0]      q_b;
1151
   input [(data_width-1):0]       d_b;
1152
   output reg [(data_width-1):0] q_a;
1153
   input                         we_b;
1154
   input                         clk_a, clk_b;
1155
   reg [(data_width-1):0]         q_b;
1156
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1157 7 unneback
   parameter init = 0;
1158
   parameter memory_file = "vl_ram.vmem";
1159
   generate if (init) begin : init_mem
1160
   initial
1161
     begin
1162
        $readmemh(memory_file, ram);
1163
     end
1164
   end
1165
   endgenerate
1166 6 unneback
   always @ (posedge clk_a)
1167
     begin
1168
        q_a <= ram[adr_a];
1169
        if (we_a)
1170
             ram[adr_a] <= d_a;
1171
     end
1172
   always @ (posedge clk_b)
1173
     begin
1174
        q_b <= ram[adr_b];
1175
        if (we_b)
1176
          ram[adr_b] <= d_b;
1177
     end
1178
endmodule
1179
// Content addresable memory, CAM
1180
// FIFO
1181 25 unneback
module vl_fifo_1r1w_fill_level_sync (
1182
    d, wr, fifo_full,
1183
    q, rd, fifo_empty,
1184
    fill_level,
1185
    clk, rst
1186
    );
1187
parameter data_width = 18;
1188
parameter addr_width = 4;
1189
// write side
1190
input  [data_width-1:0] d;
1191
input                   wr;
1192
output                  fifo_full;
1193
// read side
1194
output [data_width-1:0] q;
1195
input                   rd;
1196
output                  fifo_empty;
1197
// common
1198
output [addr_width:0]   fill_level;
1199
input rst, clk;
1200
wire [addr_width:1] wadr, radr;
1201
vl_cnt_bin_ce
1202
    # ( .length(addr_width))
1203
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
1204
vl_cnt_bin_ce
1205
    # (.length(addr_width))
1206
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
1207
vl_dpram_1r1w
1208
    # (.data_width(data_width), .addr_width(addr_width))
1209
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
1210 31 unneback
vl_cnt_bin_ce_rew_q_zq_l1
1211 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
1212 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
1213
endmodule
1214 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
1215
// RAM is supposed to be larger than the two FIFOs
1216
// LFSR counters used adr pointers
1217
module vl_fifo_2r2w_sync_simplex (
1218
    // a side
1219
    a_d, a_wr, a_fifo_full,
1220
    a_q, a_rd, a_fifo_empty,
1221
    a_fill_level,
1222
    // b side
1223
    b_d, b_wr, b_fifo_full,
1224
    b_q, b_rd, b_fifo_empty,
1225
    b_fill_level,
1226
    // common
1227
    clk, rst
1228
    );
1229
parameter data_width = 8;
1230
parameter addr_width = 5;
1231
parameter fifo_full_level = (1<<addr_width)-1;
1232
// a side
1233
input  [data_width-1:0] a_d;
1234
input                   a_wr;
1235
output                  a_fifo_full;
1236
output [data_width-1:0] a_q;
1237
input                   a_rd;
1238
output                  a_fifo_empty;
1239
output [addr_width-1:0] a_fill_level;
1240
// b side
1241
input  [data_width-1:0] b_d;
1242
input                   b_wr;
1243
output                  b_fifo_full;
1244
output [data_width-1:0] b_q;
1245
input                   b_rd;
1246
output                  b_fifo_empty;
1247
output [addr_width-1:0] b_fill_level;
1248
input                   clk;
1249
input                   rst;
1250
// adr_gen
1251
wire [addr_width:1] a_wadr, a_radr;
1252
wire [addr_width:1] b_wadr, b_radr;
1253
// dpram
1254
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1255
vl_cnt_lfsr_ce
1256
    # ( .length(addr_width))
1257
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
1258
vl_cnt_lfsr_ce
1259
    # (.length(addr_width))
1260
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
1261
vl_cnt_lfsr_ce
1262
    # ( .length(addr_width))
1263
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
1264
vl_cnt_lfsr_ce
1265
    # (.length(addr_width))
1266
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
1267
// mux read or write adr to DPRAM
1268
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
1269
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
1270
vl_dpram_2r2w
1271
    # (.data_width(data_width), .addr_width(addr_width+1))
1272
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1273
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1274
vl_cnt_bin_ce_rew_zq_l1
1275 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
1276 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
1277
vl_cnt_bin_ce_rew_zq_l1
1278 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
1279 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
1280
endmodule
1281 6 unneback
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
1282 11 unneback
   parameter addr_width = 4;
1283
   parameter N = addr_width-1;
1284 6 unneback
   parameter Q1 = 2'b00;
1285
   parameter Q2 = 2'b01;
1286
   parameter Q3 = 2'b11;
1287
   parameter Q4 = 2'b10;
1288
   parameter going_empty = 1'b0;
1289
   parameter going_full  = 1'b1;
1290
   input [N:0]  wptr, rptr;
1291 14 unneback
   output       fifo_empty;
1292 6 unneback
   output       fifo_full;
1293
   input        wclk, rclk, rst;
1294
   wire direction;
1295
   reg  direction_set, direction_clr;
1296
   wire async_empty, async_full;
1297
   wire fifo_full2;
1298 14 unneback
   wire fifo_empty2;
1299 6 unneback
   // direction_set
1300
   always @ (wptr[N:N-1] or rptr[N:N-1])
1301
     case ({wptr[N:N-1],rptr[N:N-1]})
1302
       {Q1,Q2} : direction_set <= 1'b1;
1303
       {Q2,Q3} : direction_set <= 1'b1;
1304
       {Q3,Q4} : direction_set <= 1'b1;
1305
       {Q4,Q1} : direction_set <= 1'b1;
1306
       default : direction_set <= 1'b0;
1307
     endcase
1308
   // direction_clear
1309
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
1310
     if (rst)
1311
       direction_clr <= 1'b1;
1312
     else
1313
       case ({wptr[N:N-1],rptr[N:N-1]})
1314
         {Q2,Q1} : direction_clr <= 1'b1;
1315
         {Q3,Q2} : direction_clr <= 1'b1;
1316
         {Q4,Q3} : direction_clr <= 1'b1;
1317
         {Q1,Q4} : direction_clr <= 1'b1;
1318
         default : direction_clr <= 1'b0;
1319
       endcase
1320 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
1321 6 unneback
   assign async_empty = (wptr == rptr) && (direction==going_empty);
1322
   assign async_full  = (wptr == rptr) && (direction==going_full);
1323 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
1324
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
1325 6 unneback
/*
1326
   always @ (posedge wclk or posedge rst or posedge async_full)
1327
     if (rst)
1328
       {fifo_full, fifo_full2} <= 2'b00;
1329
     else if (async_full)
1330
       {fifo_full, fifo_full2} <= 2'b11;
1331
     else
1332
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
1333
*/
1334 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
1335 6 unneback
     if (async_empty)
1336
       {fifo_empty, fifo_empty2} <= 2'b11;
1337
     else
1338 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
1339 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
1340
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
1341 27 unneback
endmodule // async_compb
1342 6 unneback
module vl_fifo_1r1w_async (
1343
    d, wr, fifo_full, wr_clk, wr_rst,
1344
    q, rd, fifo_empty, rd_clk, rd_rst
1345
    );
1346
parameter data_width = 18;
1347
parameter addr_width = 4;
1348
// write side
1349
input  [data_width-1:0] d;
1350
input                   wr;
1351
output                  fifo_full;
1352
input                   wr_clk;
1353
input                   wr_rst;
1354
// read side
1355
output [data_width-1:0] q;
1356
input                   rd;
1357
output                  fifo_empty;
1358
input                   rd_clk;
1359
input                   rd_rst;
1360
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
1361 18 unneback
vl_cnt_gray_ce_bin
1362 6 unneback
    # ( .length(addr_width))
1363
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
1364 18 unneback
vl_cnt_gray_ce_bin
1365 6 unneback
    # (.length(addr_width))
1366 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
1367 7 unneback
vl_dpram_1r1w
1368 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
1369
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
1370
vl_fifo_cmp_async
1371
    # (.addr_width(addr_width))
1372
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
1373
endmodule
1374 8 unneback
module vl_fifo_2r2w_async (
1375 6 unneback
    // a side
1376
    a_d, a_wr, a_fifo_full,
1377
    a_q, a_rd, a_fifo_empty,
1378
    a_clk, a_rst,
1379
    // b side
1380
    b_d, b_wr, b_fifo_full,
1381
    b_q, b_rd, b_fifo_empty,
1382
    b_clk, b_rst
1383
    );
1384
parameter data_width = 18;
1385
parameter addr_width = 4;
1386
// a side
1387
input  [data_width-1:0] a_d;
1388
input                   a_wr;
1389
output                  a_fifo_full;
1390
output [data_width-1:0] a_q;
1391
input                   a_rd;
1392
output                  a_fifo_empty;
1393
input                   a_clk;
1394
input                   a_rst;
1395
// b side
1396
input  [data_width-1:0] b_d;
1397
input                   b_wr;
1398
output                  b_fifo_full;
1399
output [data_width-1:0] b_q;
1400
input                   b_rd;
1401
output                  b_fifo_empty;
1402
input                   b_clk;
1403
input                   b_rst;
1404
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1405
vl_fifo_1r1w_async_a (
1406
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
1407
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
1408
    );
1409
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1410
vl_fifo_1r1w_async_b (
1411
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
1412
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
1413
    );
1414
endmodule
1415 8 unneback
module vl_fifo_2r2w_async_simplex (
1416 6 unneback
    // a side
1417
    a_d, a_wr, a_fifo_full,
1418
    a_q, a_rd, a_fifo_empty,
1419
    a_clk, a_rst,
1420
    // b side
1421
    b_d, b_wr, b_fifo_full,
1422
    b_q, b_rd, b_fifo_empty,
1423
    b_clk, b_rst
1424
    );
1425
parameter data_width = 18;
1426
parameter addr_width = 4;
1427
// a side
1428
input  [data_width-1:0] a_d;
1429
input                   a_wr;
1430
output                  a_fifo_full;
1431
output [data_width-1:0] a_q;
1432
input                   a_rd;
1433
output                  a_fifo_empty;
1434
input                   a_clk;
1435
input                   a_rst;
1436
// b side
1437
input  [data_width-1:0] b_d;
1438
input                   b_wr;
1439
output                  b_fifo_full;
1440
output [data_width-1:0] b_q;
1441
input                   b_rd;
1442
output                  b_fifo_empty;
1443
input                   b_clk;
1444
input                   b_rst;
1445
// adr_gen
1446
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
1447
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
1448
// dpram
1449
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1450 18 unneback
vl_cnt_gray_ce_bin
1451 6 unneback
    # ( .length(addr_width))
1452
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
1453 18 unneback
vl_cnt_gray_ce_bin
1454 6 unneback
    # (.length(addr_width))
1455
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
1456 18 unneback
vl_cnt_gray_ce_bin
1457 6 unneback
    # ( .length(addr_width))
1458
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
1459 18 unneback
vl_cnt_gray_ce_bin
1460 6 unneback
    # (.length(addr_width))
1461
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
1462
// mux read or write adr to DPRAM
1463
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
1464
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
1465 11 unneback
vl_dpram_2r2w
1466 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
1467
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1468
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1469 11 unneback
vl_fifo_cmp_async
1470 6 unneback
    # (.addr_width(addr_width))
1471
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
1472 11 unneback
vl_fifo_cmp_async
1473 6 unneback
    # (.addr_width(addr_width))
1474
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
1475
endmodule
1476 12 unneback
//////////////////////////////////////////////////////////////////////
1477
////                                                              ////
1478
////  Versatile library, wishbone stuff                           ////
1479
////                                                              ////
1480
////  Description                                                 ////
1481
////  Wishbone compliant modules                                  ////
1482
////                                                              ////
1483
////                                                              ////
1484
////  To Do:                                                      ////
1485
////   -                                                          ////
1486
////                                                              ////
1487
////  Author(s):                                                  ////
1488
////      - Michael Unneback, unneback@opencores.org              ////
1489
////        ORSoC AB                                              ////
1490
////                                                              ////
1491
//////////////////////////////////////////////////////////////////////
1492
////                                                              ////
1493
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1494
////                                                              ////
1495
//// This source file may be used and distributed without         ////
1496
//// restriction provided that this copyright statement is not    ////
1497
//// removed from the file and that any derivative work contains  ////
1498
//// the original copyright notice and the associated disclaimer. ////
1499
////                                                              ////
1500
//// This source file is free software; you can redistribute it   ////
1501
//// and/or modify it under the terms of the GNU Lesser General   ////
1502
//// Public License as published by the Free Software Foundation; ////
1503
//// either version 2.1 of the License, or (at your option) any   ////
1504
//// later version.                                               ////
1505
////                                                              ////
1506
//// This source is distributed in the hope that it will be       ////
1507
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1508
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1509
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1510
//// details.                                                     ////
1511
////                                                              ////
1512
//// You should have received a copy of the GNU Lesser General    ////
1513
//// Public License along with this source; if not, download it   ////
1514
//// from http://www.opencores.org/lgpl.shtml                     ////
1515
////                                                              ////
1516
//////////////////////////////////////////////////////////////////////
1517
// async wb3 - wb3 bridge
1518
`timescale 1ns/1ns
1519 18 unneback
module vl_wb3wb3_bridge (
1520 12 unneback
        // wishbone slave side
1521
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
1522
        // wishbone master side
1523
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
1524
input [31:0] wbs_dat_i;
1525
input [31:2] wbs_adr_i;
1526
input [3:0]  wbs_sel_i;
1527
input [1:0]  wbs_bte_i;
1528
input [2:0]  wbs_cti_i;
1529
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
1530
output [31:0] wbs_dat_o;
1531 14 unneback
output wbs_ack_o;
1532 12 unneback
input wbs_clk, wbs_rst;
1533
output [31:0] wbm_dat_o;
1534
output reg [31:2] wbm_adr_o;
1535
output [3:0]  wbm_sel_o;
1536
output reg [1:0]  wbm_bte_o;
1537
output reg [2:0]  wbm_cti_o;
1538 14 unneback
output reg wbm_we_o;
1539
output wbm_cyc_o;
1540 12 unneback
output wbm_stb_o;
1541
input [31:0]  wbm_dat_i;
1542
input wbm_ack_i;
1543
input wbm_clk, wbm_rst;
1544
parameter addr_width = 4;
1545
// bte
1546
parameter linear       = 2'b00;
1547
parameter wrap4        = 2'b01;
1548
parameter wrap8        = 2'b10;
1549
parameter wrap16       = 2'b11;
1550
// cti
1551
parameter classic      = 3'b000;
1552
parameter incburst     = 3'b010;
1553
parameter endofburst   = 3'b111;
1554
parameter wbs_adr  = 1'b0;
1555
parameter wbs_data = 1'b1;
1556 33 unneback
parameter wbm_adr0      = 2'b00;
1557
parameter wbm_adr1      = 2'b01;
1558
parameter wbm_data      = 2'b10;
1559
parameter wbm_data_wait = 2'b11;
1560 12 unneback
reg [1:0] wbs_bte_reg;
1561
reg wbs;
1562
wire wbs_eoc_alert, wbm_eoc_alert;
1563
reg wbs_eoc, wbm_eoc;
1564
reg [1:0] wbm;
1565 14 unneback
wire [1:16] wbs_count, wbm_count;
1566 12 unneback
wire [35:0] a_d, a_q, b_d, b_q;
1567
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
1568
reg a_rd_reg;
1569
wire b_rd_adr, b_rd_data;
1570 14 unneback
wire b_rd_data_reg;
1571
wire [35:0] temp;
1572 12 unneback
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
1573
always @ (posedge wbs_clk or posedge wbs_rst)
1574
if (wbs_rst)
1575
        wbs_eoc <= 1'b0;
1576
else
1577
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
1578
                wbs_eoc <= wbs_bte_i==linear;
1579
        else if (wbs_eoc_alert & (a_rd | a_wr))
1580
                wbs_eoc <= 1'b1;
1581 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
1582 12 unneback
    cnt0 (
1583
        .cke(wbs_ack_o),
1584
        .clear(wbs_eoc),
1585
        .q(wbs_count),
1586
        .rst(wbs_rst),
1587
        .clk(wbs_clk));
1588
always @ (posedge wbs_clk or posedge wbs_rst)
1589
if (wbs_rst)
1590
        wbs <= wbs_adr;
1591
else
1592
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
1593
                wbs <= wbs_data;
1594
        else if (wbs_eoc & wbs_ack_o)
1595
                wbs <= wbs_adr;
1596
// wbs FIFO
1597
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
1598
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
1599
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
1600
              1'b0;
1601
assign a_rd = !a_fifo_empty;
1602
always @ (posedge wbs_clk or posedge wbs_rst)
1603
if (wbs_rst)
1604
        a_rd_reg <= 1'b0;
1605
else
1606
        a_rd_reg <= a_rd;
1607
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
1608
assign wbs_dat_o = a_q[35:4];
1609
always @ (posedge wbs_clk or posedge wbs_rst)
1610
if (wbs_rst)
1611 13 unneback
        wbs_bte_reg <= 2'b00;
1612 12 unneback
else
1613 13 unneback
        wbs_bte_reg <= wbs_bte_i;
1614 12 unneback
// wbm FIFO
1615
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
1616
always @ (posedge wbm_clk or posedge wbm_rst)
1617
if (wbm_rst)
1618
        wbm_eoc <= 1'b0;
1619
else
1620
        if (wbm==wbm_adr0 & !b_fifo_empty)
1621
                wbm_eoc <= b_q[4:3] == linear;
1622
        else if (wbm_eoc_alert & wbm_ack_i)
1623
                wbm_eoc <= 1'b1;
1624
always @ (posedge wbm_clk or posedge wbm_rst)
1625
if (wbm_rst)
1626
        wbm <= wbm_adr0;
1627
else
1628 33 unneback
/*
1629 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
1630
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
1631
        (wbm==wbm_adr1 & !wbm_we_o) |
1632
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
1633
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
1634 33 unneback
*/
1635
    case (wbm)
1636
    wbm_adr0:
1637
        if (!b_fifo_empty)
1638
            wbm <= wbm_adr1;
1639
    wbm_adr1:
1640
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
1641
            wbm <= wbm_data;
1642
    wbm_data:
1643
        if (wbm_ack_i & wbm_eoc)
1644
            wbm <= wbm_adr0;
1645
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
1646
            wbm <= wbm_data_wait;
1647
    wbm_data_wait:
1648
        if (!b_fifo_empty)
1649
            wbm <= wbm_data;
1650
    endcase
1651 12 unneback
assign b_d = {wbm_dat_i,4'b1111};
1652
assign b_wr = !wbm_we_o & wbm_ack_i;
1653
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
1654
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
1655
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
1656 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
1657 12 unneback
                   1'b0;
1658
assign b_rd = b_rd_adr | b_rd_data;
1659 18 unneback
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
1660
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
1661 12 unneback
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
1662 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
1663 12 unneback
    cnt1 (
1664
        .cke(wbm_ack_i),
1665
        .clear(wbm_eoc),
1666
        .q(wbm_count),
1667
        .rst(wbm_rst),
1668
        .clk(wbm_clk));
1669 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
1670
assign wbm_stb_o = (wbm==wbm_data);
1671 12 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
1672
if (wbm_rst)
1673
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
1674
else begin
1675
        if (wbm==wbm_adr0 & !b_fifo_empty)
1676
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
1677
        else if (wbm_eoc_alert & wbm_ack_i)
1678
                wbm_cti_o <= endofburst;
1679
end
1680
//async_fifo_dw_simplex_top
1681
vl_fifo_2r2w_async_simplex
1682
# ( .data_width(36), .addr_width(addr_width))
1683
fifo (
1684
    // a side
1685
    .a_d(a_d),
1686
    .a_wr(a_wr),
1687
    .a_fifo_full(a_fifo_full),
1688
    .a_q(a_q),
1689
    .a_rd(a_rd),
1690
    .a_fifo_empty(a_fifo_empty),
1691
    .a_clk(wbs_clk),
1692
    .a_rst(wbs_rst),
1693
    // b side
1694
    .b_d(b_d),
1695
    .b_wr(b_wr),
1696
    .b_fifo_full(b_fifo_full),
1697
    .b_q(b_q),
1698
    .b_rd(b_rd),
1699
    .b_fifo_empty(b_fifo_empty),
1700
    .b_clk(wbm_clk),
1701
    .b_rst(wbm_rst)
1702
    );
1703
endmodule
1704 39 unneback
module vl_wb3_arbiter_type1 (
1705
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
1706
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
1707
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
1708
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
1709
    wb_clk, wb_rst
1710
);
1711
parameter nr_of_ports = 3;
1712
parameter adr_size = 26;
1713
parameter adr_lo   = 2;
1714
parameter dat_size = 32;
1715
parameter sel_size = dat_size/8;
1716
localparam aw = (adr_size - adr_lo) * nr_of_ports;
1717
localparam dw = dat_size * nr_of_ports;
1718
localparam sw = sel_size * nr_of_ports;
1719
localparam cw = 3 * nr_of_ports;
1720
localparam bw = 2 * nr_of_ports;
1721
input  [dw-1:0] wbm_dat_o;
1722
input  [aw-1:0] wbm_adr_o;
1723
input  [sw-1:0] wbm_sel_o;
1724
input  [cw-1:0] wbm_cti_o;
1725
input  [bw-1:0] wbm_bte_o;
1726
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
1727
output [dw-1:0] wbm_dat_i;
1728
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
1729
output [dat_size-1:0] wbs_dat_i;
1730
output [adr_size-1:adr_lo] wbs_adr_i;
1731
output [sel_size-1:0] wbs_sel_i;
1732
output [2:0] wbs_cti_i;
1733
output [1:0] wbs_bte_i;
1734
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
1735
input  [dat_size-1:0] wbs_dat_o;
1736
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
1737
input wb_clk, wb_rst;
1738
wire [nr_of_ports-1:0] select;
1739
wire [nr_of_ports-1:0] state;
1740
wire [nr_of_ports-1:0] eoc; // end-of-cycle
1741
wire [nr_of_ports-1:0] sel;
1742
wire idle;
1743
genvar i;
1744
assign idle = !(|state);
1745
generate
1746
if (nr_of_ports == 2) begin
1747
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
1748
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
1749
    assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : 2'b00;
1750
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
1751
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
1752
end
1753
endgenerate
1754
generate
1755
if (nr_of_ports == 3) begin
1756
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
1757
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
1758
    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : 3'b000;
1759
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
1760
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
1761
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
1762
end
1763
endgenerate
1764
generate
1765
for (i=0;i<nr_of_ports;i=i+1) begin
1766
    vl_spr sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
1767
end
1768
endgenerate
1769
    assign sel = select | state;
1770
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
1771
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
1772
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
1773
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
1774
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
1775
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
1776
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
1777
    assign wbs_cyc_i = |sel;
1778
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
1779
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
1780
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
1781
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
1782
endmodule
1783 17 unneback
// WB ROM
1784 18 unneback
module vl_wb_boot_rom (
1785 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
1786 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
1787
    parameter adr_hi = 31;
1788
    parameter adr_lo = 28;
1789
    parameter adr_sel = 4'hf;
1790
    parameter addr_width = 5;
1791 33 unneback
/*
1792 17 unneback
`ifndef BOOT_ROM
1793
`define BOOT_ROM "boot_rom.v"
1794
`endif
1795 33 unneback
*/
1796 18 unneback
    input [adr_hi:2]    wb_adr_i;
1797
    input               wb_stb_i;
1798
    input               wb_cyc_i;
1799
    output [31:0]        wb_dat_o;
1800
    output              wb_ack_o;
1801
    output              hit_o;
1802
    input               wb_clk;
1803
    input               wb_rst;
1804
    wire hit;
1805
    reg [31:0] wb_dat;
1806
    reg wb_ack;
1807
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
1808 17 unneback
always @ (posedge wb_clk or posedge wb_rst)
1809
    if (wb_rst)
1810 18 unneback
        wb_dat <= 32'h15000000;
1811 17 unneback
    else
1812 18 unneback
         case (wb_adr_i[addr_width-1:2])
1813 33 unneback
`ifdef BOOT_ROM
1814 17 unneback
`include `BOOT_ROM
1815 33 unneback
`endif
1816 17 unneback
           /*
1817
            // Zero r0 and jump to 0x00000100
1818 18 unneback
 
1819
            1 : wb_dat <= 32'hA8200000;
1820
            2 : wb_dat <= 32'hA8C00100;
1821
            3 : wb_dat <= 32'h44003000;
1822
            4 : wb_dat <= 32'h15000000;
1823 17 unneback
            */
1824
           default:
1825 18 unneback
             wb_dat <= 32'h00000000;
1826 17 unneback
         endcase // case (wb_adr_i)
1827
always @ (posedge wb_clk or posedge wb_rst)
1828
    if (wb_rst)
1829 18 unneback
        wb_ack <= 1'b0;
1830 17 unneback
    else
1831 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
1832
assign hit_o = hit;
1833
assign wb_dat_o = wb_dat & {32{wb_ack}};
1834
assign wb_ack_o = wb_ack;
1835 17 unneback
endmodule
1836 32 unneback
module vl_wb_dpram (
1837
        // wishbone slave side a
1838
        wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
1839
        wbsa_clk, wbsa_rst,
1840
        // wishbone slave side a
1841
        wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
1842
        wbsb_clk, wbsb_rst);
1843
parameter data_width = 32;
1844
parameter addr_width = 8;
1845
parameter dat_o_mask_a = 1;
1846
parameter dat_o_mask_b = 1;
1847
input [31:0] wbsa_dat_i;
1848
input [addr_width-1:2] wbsa_adr_i;
1849
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
1850
output [31:0] wbsa_dat_o;
1851
output wbsa_ack_o;
1852
input wbsa_clk, wbsa_rst;
1853
input [31:0] wbsb_dat_i;
1854
input [addr_width-1:2] wbsb_adr_i;
1855
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
1856
output [31:0] wbsb_dat_o;
1857
output wbsb_ack_o;
1858
input wbsb_clk, wbsb_rst;
1859
wire wbsa_dat_tmp, wbsb_dat_tmp;
1860
vl_dpram_2r2w # (
1861 33 unneback
    .data_width(data_width), .addr_width(addr_width) )
1862 32 unneback
dpram0(
1863
    .d_a(wbsa_dat_i),
1864
    .q_a(wbsa_dat_tmp),
1865
    .adr_a(wbsa_adr_i),
1866
    .we_a(wbsa_we_i),
1867
    .clk_a(wbsa_clk),
1868
    .d_b(wbsb_dat_i),
1869
    .q_b(wbsb_dat_tmp),
1870
    .adr_b(wbsb_adr_i),
1871
    .we_b(wbsb_we_i),
1872
    .clk_b(wbsb_clk) );
1873 33 unneback
generate if (dat_o_mask_a==1)
1874 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
1875
endgenerate
1876 33 unneback
generate if (dat_o_mask_a==0)
1877 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp;
1878
endgenerate
1879 33 unneback
generate if (dat_o_mask_b==1)
1880 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
1881
endgenerate
1882 33 unneback
generate if (dat_o_mask_b==0)
1883 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp;
1884
endgenerate
1885
vl_spr ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
1886
vl_spr ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
1887
endmodule
1888 18 unneback
//////////////////////////////////////////////////////////////////////
1889
////                                                              ////
1890
////  Arithmetic functions                                        ////
1891
////                                                              ////
1892
////  Description                                                 ////
1893
////  Arithmetic functions for ALU and DSP                        ////
1894
////                                                              ////
1895
////                                                              ////
1896
////  To Do:                                                      ////
1897
////   -                                                          ////
1898
////                                                              ////
1899
////  Author(s):                                                  ////
1900
////      - Michael Unneback, unneback@opencores.org              ////
1901
////        ORSoC AB                                              ////
1902
////                                                              ////
1903
//////////////////////////////////////////////////////////////////////
1904
////                                                              ////
1905
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1906
////                                                              ////
1907
//// This source file may be used and distributed without         ////
1908
//// restriction provided that this copyright statement is not    ////
1909
//// removed from the file and that any derivative work contains  ////
1910
//// the original copyright notice and the associated disclaimer. ////
1911
////                                                              ////
1912
//// This source file is free software; you can redistribute it   ////
1913
//// and/or modify it under the terms of the GNU Lesser General   ////
1914
//// Public License as published by the Free Software Foundation; ////
1915
//// either version 2.1 of the License, or (at your option) any   ////
1916
//// later version.                                               ////
1917
////                                                              ////
1918
//// This source is distributed in the hope that it will be       ////
1919
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1920
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1921
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1922
//// details.                                                     ////
1923
////                                                              ////
1924
//// You should have received a copy of the GNU Lesser General    ////
1925
//// Public License along with this source; if not, download it   ////
1926
//// from http://www.opencores.org/lgpl.shtml                     ////
1927
////                                                              ////
1928
//////////////////////////////////////////////////////////////////////
1929
// signed multiplication
1930
module vl_mults (a,b,p);
1931
parameter operand_a_width = 18;
1932
parameter operand_b_width = 18;
1933
parameter result_hi = 35;
1934
parameter result_lo = 0;
1935
input [operand_a_width-1:0] a;
1936
input [operand_b_width-1:0] b;
1937
output [result_hi:result_lo] p;
1938
wire signed [operand_a_width-1:0] ai;
1939
wire signed [operand_b_width-1:0] bi;
1940
wire signed [operand_a_width+operand_b_width-1:0] result;
1941
    assign ai = a;
1942
    assign bi = b;
1943
    assign result = ai * bi;
1944
    assign p = result[result_hi:result_lo];
1945
endmodule
1946
module vl_mults18x18 (a,b,p);
1947
input [17:0] a,b;
1948
output [35:0] p;
1949
vl_mult
1950
    # (.operand_a_width(18), .operand_b_width(18))
1951
    mult0 (.a(a), .b(b), .p(p));
1952
endmodule
1953
// unsigned multiplication
1954
module vl_mult (a,b,p);
1955
parameter operand_a_width = 18;
1956
parameter operand_b_width = 18;
1957
parameter result_hi = 35;
1958
parameter result_lo = 0;
1959
input [operand_a_width-1:0] a;
1960
input [operand_b_width-1:0] b;
1961
output [result_hi:result_hi] p;
1962
wire [operand_a_width+operand_b_width-1:0] result;
1963
    assign result = a * b;
1964
    assign p = result[result_hi:result_lo];
1965
endmodule
1966
// shift unit
1967
// supporting the following shift functions
1968
//   SLL
1969
//   SRL
1970
//   SRA
1971
module vl_shift_unit_32( din, s, dout, opcode);
1972
input [31:0] din; // data in operand
1973
input [4:0] s; // shift operand
1974
input [1:0] opcode;
1975
output [31:0] dout;
1976
parameter opcode_sll = 2'b00;
1977
//parameter opcode_srl = 2'b01;
1978
parameter opcode_sra = 2'b10;
1979
//parameter opcode_ror = 2'b11;
1980
wire sll, sra;
1981
assign sll = opcode == opcode_sll;
1982
assign sra = opcode == opcode_sra;
1983
wire [15:1] s1;
1984
wire [3:0] sign;
1985
wire [7:0] tmp [0:3];
1986
// first stage is multiplier based
1987
// shift operand as fractional 8.7
1988
assign s1[15] = sll & s[2:0]==3'd7;
1989
assign s1[14] = sll & s[2:0]==3'd6;
1990
assign s1[13] = sll & s[2:0]==3'd5;
1991
assign s1[12] = sll & s[2:0]==3'd4;
1992
assign s1[11] = sll & s[2:0]==3'd3;
1993
assign s1[10] = sll & s[2:0]==3'd2;
1994
assign s1[ 9] = sll & s[2:0]==3'd1;
1995
assign s1[ 8] = s[2:0]==3'd0;
1996
assign s1[ 7] = !sll & s[2:0]==3'd1;
1997
assign s1[ 6] = !sll & s[2:0]==3'd2;
1998
assign s1[ 5] = !sll & s[2:0]==3'd3;
1999
assign s1[ 4] = !sll & s[2:0]==3'd4;
2000
assign s1[ 3] = !sll & s[2:0]==3'd5;
2001
assign s1[ 2] = !sll & s[2:0]==3'd6;
2002
assign s1[ 1] = !sll & s[2:0]==3'd7;
2003
assign sign[3] = din[31] & sra;
2004
assign sign[2] = sign[3] & (&din[31:24]);
2005
assign sign[1] = sign[2] & (&din[23:16]);
2006
assign sign[0] = sign[1] & (&din[15:8]);
2007
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
2008
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
2009
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
2010
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
2011
// second stage is multiplexer based
2012
// shift on byte level
2013
// mux byte 3
2014
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
2015
                     (sll & s[4:3]==2'b01) ? tmp[2] :
2016
                     (sll & s[4:3]==2'b10) ? tmp[1] :
2017
                     (sll & s[4:3]==2'b11) ? tmp[0] :
2018
                     {8{sign[3]}};
2019
// mux byte 2
2020
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
2021
                     (sll & s[4:3]==2'b01) ? tmp[1] :
2022
                     (sll & s[4:3]==2'b10) ? tmp[0] :
2023
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
2024
                     (s[4:3]==2'b01) ? tmp[3] :
2025
                     {8{sign[3]}};
2026
// mux byte 1
2027
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
2028
                     (sll & s[4:3]==2'b01) ? tmp[0] :
2029
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
2030
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
2031
                     (s[4:3]==2'b01) ? tmp[2] :
2032
                     (s[4:3]==2'b10) ? tmp[3] :
2033
                     {8{sign[3]}};
2034
// mux byte 0
2035
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
2036
                     (sll) ?  {8{1'b0}}:
2037
                     (s[4:3]==2'b01) ? tmp[1] :
2038
                     (s[4:3]==2'b10) ? tmp[2] :
2039
                     tmp[3];
2040
endmodule
2041
// logic unit
2042
// supporting the following logic functions
2043
//    a and b
2044
//    a or  b
2045
//    a xor b
2046
//    not b
2047
module vl_logic_unit( a, b, result, opcode);
2048
parameter width = 32;
2049
parameter opcode_and = 2'b00;
2050
parameter opcode_or  = 2'b01;
2051
parameter opcode_xor = 2'b10;
2052
input [width-1:0] a,b;
2053
output [width-1:0] result;
2054
input [1:0] opcode;
2055
assign result = (opcode==opcode_and) ? a & b :
2056
                (opcode==opcode_or)  ? a | b :
2057
                (opcode==opcode_xor) ? a ^ b :
2058
                b;
2059
endmodule
2060
module vl_arith_unit ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
2061
parameter width = 32;
2062
parameter opcode_add = 1'b0;
2063
parameter opcode_sub = 1'b1;
2064
input [width-1:0] a,b;
2065
input c_in, add_sub, sign;
2066
output [width-1:0] result;
2067
output c_out, z, ovfl;
2068
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
2069
assign z = (result=={width{1'b0}});
2070
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
2071
               (~a[width-1] & ~b[width-1] &  result[width-1]);
2072
endmodule

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