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1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  Versatile library, clock and reset                          ////
4
////                                                              ////
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////  Description                                                 ////
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////  Logic related to clock and reset                            ////
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////                                                              ////
8
////                                                              ////
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////  To Do:                                                      ////
10
////   - add more different registers                             ////
11
////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
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////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
// Global buffer
43
// usage:
44
// use to enable global buffers for high fan out signals such as clock and reset
45
`timescale 1 ns/100 ps
46
// Version: 8.4 8.4.0.33
47
module gbuf(GL,CLK);
48
output GL;
49
input  CLK;
50
    wire GND;
51
    GND GND_1_net(.Y(GND));
52
    CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
53
        .DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
54
endmodule
55
`timescale 1 ns/1 ns
56
module vl_gbuf ( i, o);
57
input i;
58
output o;
59
`ifdef SIM_GBUF
60
assign o=i;
61
`else
62
gbuf gbuf_i0 ( .CLK(i), .GL(o));
63
`endif
64
endmodule
65
 //ACTEL
66
// sync reset
67 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
68 6 unneback
// output active high global reset sync with two DFFs 
69
`timescale 1 ns/100 ps
70
module vl_sync_rst ( rst_n_i, rst_o, clk);
71
input rst_n_i, clk;
72
output rst_o;
73 18 unneback
reg [1:0] tmp;
74 6 unneback
always @ (posedge clk or negedge rst_n_i)
75
if (!rst_n_i)
76 17 unneback
        tmp <= 2'b11;
77 6 unneback
else
78 33 unneback
        tmp <= {1'b0,tmp[1]};
79 17 unneback
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
80 6 unneback
endmodule
81
// vl_pll
82 32 unneback
///////////////////////////////////////////////////////////////////////////////
83 17 unneback
`timescale 1 ps/1 ps
84 6 unneback
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
85
parameter index = 0;
86
parameter number_of_clk = 1;
87 17 unneback
parameter period_time_0 = 20000;
88
parameter period_time_1 = 20000;
89
parameter period_time_2 = 20000;
90
parameter lock_delay = 2000000;
91 6 unneback
input clk_i, rst_n_i;
92
output lock;
93
output reg [0:number_of_clk-1] clk_o;
94
output [0:number_of_clk-1] rst_o;
95
`ifdef SIM_PLL
96
always
97
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
98
generate if (number_of_clk > 1)
99
always
100
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
101
endgenerate
102
generate if (number_of_clk > 2)
103
always
104
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
105
endgenerate
106
genvar i;
107
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
108
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
109
end
110
endgenerate
111
assign #lock_delay lock = rst_n_i;
112
endmodule
113
`else
114
generate if (number_of_clk==1 & index==0) begin
115
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
116
end
117
endgenerate // index==0
118
generate if (number_of_clk==1 & index==1) begin
119
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
120
end
121
endgenerate // index==1
122
generate if (number_of_clk==1 & index==2) begin
123
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
124
end
125
endgenerate // index==2
126
generate if (number_of_clk==1 & index==3) begin
127
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
128
end
129
endgenerate // index==0
130
generate if (number_of_clk==2 & index==0) begin
131
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
132
end
133
endgenerate // index==0
134
generate if (number_of_clk==2 & index==1) begin
135
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
136
end
137
endgenerate // index==1
138
generate if (number_of_clk==2 & index==2) begin
139
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
140
end
141
endgenerate // index==2
142
generate if (number_of_clk==2 & index==3) begin
143
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
144
end
145
endgenerate // index==0
146
generate if (number_of_clk==3 & index==0) begin
147
        pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
148
end
149
endgenerate // index==0
150
generate if (number_of_clk==3 & index==1) begin
151
        pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
152
end
153
endgenerate // index==1
154
generate if (number_of_clk==3 & index==2) begin
155
        pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
156
end
157
endgenerate // index==2
158
generate if (number_of_clk==3 & index==3) begin
159
        pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
160
end
161
endgenerate // index==0
162
genvar i;
163
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
164 40 unneback
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
165 6 unneback
end
166
endgenerate
167
endmodule
168
`endif
169 32 unneback
///////////////////////////////////////////////////////////////////////////////
170 6 unneback
 //actel
171
//////////////////////////////////////////////////////////////////////
172
////                                                              ////
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////  Versatile library, registers                                ////
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////                                                              ////
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////  Description                                                 ////
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////  Different type of registers                                 ////
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////                                                              ////
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////                                                              ////
179
////  To Do:                                                      ////
180
////   - add more different registers                             ////
181
////                                                              ////
182
////  Author(s):                                                  ////
183
////      - Michael Unneback, unneback@opencores.org              ////
184
////        ORSoC AB                                              ////
185
////                                                              ////
186
//////////////////////////////////////////////////////////////////////
187
////                                                              ////
188
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
189
////                                                              ////
190
//// This source file may be used and distributed without         ////
191
//// restriction provided that this copyright statement is not    ////
192
//// removed from the file and that any derivative work contains  ////
193
//// the original copyright notice and the associated disclaimer. ////
194
////                                                              ////
195
//// This source file is free software; you can redistribute it   ////
196
//// and/or modify it under the terms of the GNU Lesser General   ////
197
//// Public License as published by the Free Software Foundation; ////
198
//// either version 2.1 of the License, or (at your option) any   ////
199
//// later version.                                               ////
200
////                                                              ////
201
//// This source is distributed in the hope that it will be       ////
202
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
203
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
204
//// PURPOSE.  See the GNU Lesser General Public License for more ////
205
//// details.                                                     ////
206
////                                                              ////
207
//// You should have received a copy of the GNU Lesser General    ////
208
//// Public License along with this source; if not, download it   ////
209
//// from http://www.opencores.org/lgpl.shtml                     ////
210
////                                                              ////
211
//////////////////////////////////////////////////////////////////////
212 18 unneback
module vl_dff ( d, q, clk, rst);
213 6 unneback
        parameter width = 1;
214
        parameter reset_value = 0;
215
        input [width-1:0] d;
216
        input clk, rst;
217
        output reg [width-1:0] q;
218
        always @ (posedge clk or posedge rst)
219
        if (rst)
220
                q <= reset_value;
221
        else
222
                q <= d;
223
endmodule
224 18 unneback
module vl_dff_array ( d, q, clk, rst);
225 6 unneback
        parameter width = 1;
226
        parameter depth = 2;
227
        parameter reset_value = 1'b0;
228
        input [width-1:0] d;
229
        input clk, rst;
230
        output [width-1:0] q;
231
        reg  [0:depth-1] q_tmp [width-1:0];
232
        integer i;
233
        always @ (posedge clk or posedge rst)
234
        if (rst) begin
235
            for (i=0;i<depth;i=i+1)
236
                q_tmp[i] <= {width{reset_value}};
237
        end else begin
238
            q_tmp[0] <= d;
239
            for (i=1;i<depth;i=i+1)
240
                q_tmp[i] <= q_tmp[i-1];
241
        end
242
    assign q = q_tmp[depth-1];
243
endmodule
244 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
245 6 unneback
        parameter width = 1;
246
        parameter reset_value = 0;
247
        input [width-1:0] d;
248
        input ce, clk, rst;
249
        output reg [width-1:0] q;
250
        always @ (posedge clk or posedge rst)
251
        if (rst)
252
                q <= reset_value;
253
        else
254
                if (ce)
255
                        q <= d;
256
endmodule
257 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
258 8 unneback
        parameter width = 1;
259
        parameter reset_value = 0;
260
        input [width-1:0] d;
261 10 unneback
        input ce, clear, clk, rst;
262 8 unneback
        output reg [width-1:0] q;
263
        always @ (posedge clk or posedge rst)
264
        if (rst)
265
            q <= reset_value;
266
        else
267
            if (ce)
268
                if (clear)
269
                    q <= {width{1'b0}};
270
                else
271
                    q <= d;
272
endmodule
273 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
274
        parameter width = 1;
275
        parameter reset_value = 0;
276
        input [width-1:0] d;
277
        input ce, set, clk, rst;
278
        output reg [width-1:0] q;
279
        always @ (posedge clk or posedge rst)
280
        if (rst)
281
            q <= reset_value;
282
        else
283
            if (ce)
284
                if (set)
285
                    q <= {width{1'b1}};
286
                else
287
                    q <= d;
288
endmodule
289 29 unneback
module vl_spr ( sp, r, q, clk, rst);
290
        parameter width = 1;
291
        parameter reset_value = 0;
292
        input sp, r;
293
        output reg q;
294
        input clk, rst;
295
        always @ (posedge clk or posedge rst)
296
        if (rst)
297
            q <= reset_value;
298
        else
299
            if (sp)
300
                q <= 1'b1;
301
            else if (r)
302
                q <= 1'b0;
303
endmodule
304
module vl_srp ( s, rp, q, clk, rst);
305
        parameter width = 1;
306
        parameter reset_value = 0;
307
        input s, rp;
308
        output reg q;
309
        input clk, rst;
310
        always @ (posedge clk or posedge rst)
311
        if (rst)
312
            q <= reset_value;
313
        else
314
            if (rp)
315
                q <= 1'b0;
316
            else if (s)
317
                q <= 1'b1;
318
endmodule
319 18 unneback
module vl_dff_sr ( aclr, aset, clock, data, q);
320 6 unneback
    input         aclr;
321
    input         aset;
322
    input         clock;
323
    input         data;
324
    output reg    q;
325
   always @ (posedge clock or posedge aclr or posedge aset)
326
     if (aclr)
327
       q <= 1'b0;
328
     else if (aset)
329
       q <= 1'b1;
330
     else
331
       q <= data;
332
endmodule
333
// LATCH
334
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
335 40 unneback
module vl_latch ( d, le, q, clk);
336 6 unneback
input d, le;
337
output q;
338
input clk;/*
339
   always @ (posedge direction_set or posedge direction_clr)
340
     if (direction_clr)
341
       direction <= going_empty;
342
     else
343
       direction <= going_full;*/
344
endmodule
345 18 unneback
module vl_shreg ( d, q, clk, rst);
346 17 unneback
parameter depth = 10;
347
input d;
348
output q;
349
input clk, rst;
350
reg [1:depth] dffs;
351
always @ (posedge clk or posedge rst)
352
if (rst)
353
    dffs <= {depth{1'b0}};
354
else
355
    dffs <= {d,dffs[1:depth-1]};
356
assign q = dffs[depth];
357
endmodule
358 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
359 17 unneback
parameter depth = 10;
360
input d, ce;
361
output q;
362
input clk, rst;
363
reg [1:depth] dffs;
364
always @ (posedge clk or posedge rst)
365
if (rst)
366
    dffs <= {depth{1'b0}};
367
else
368
    if (ce)
369
        dffs <= {d,dffs[1:depth-1]};
370
assign q = dffs[depth];
371
endmodule
372 18 unneback
module vl_delay ( d, q, clk, rst);
373 15 unneback
parameter depth = 10;
374
input d;
375
output q;
376
input clk, rst;
377
reg [1:depth] dffs;
378
always @ (posedge clk or posedge rst)
379
if (rst)
380
    dffs <= {depth{1'b0}};
381
else
382
    dffs <= {d,dffs[1:depth-1]};
383
assign q = dffs[depth];
384
endmodule
385 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
386 17 unneback
parameter depth = 10;
387
input d;
388
output q, emptyflag;
389
input clk, rst;
390
reg [1:depth] dffs;
391
always @ (posedge clk or posedge rst)
392
if (rst)
393
    dffs <= {depth{1'b0}};
394
else
395
    dffs <= {d,dffs[1:depth-1]};
396
assign q = dffs[depth];
397
assign emptyflag = !(|dffs);
398
endmodule
399 6 unneback
//////////////////////////////////////////////////////////////////////
400
////                                                              ////
401 18 unneback
////  Logic functions                                             ////
402
////                                                              ////
403
////  Description                                                 ////
404
////  Logic functions such as multiplexers                        ////
405
////                                                              ////
406
////                                                              ////
407
////  To Do:                                                      ////
408
////   -                                                          ////
409
////                                                              ////
410
////  Author(s):                                                  ////
411
////      - Michael Unneback, unneback@opencores.org              ////
412
////        ORSoC AB                                              ////
413
////                                                              ////
414
//////////////////////////////////////////////////////////////////////
415
////                                                              ////
416
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
417
////                                                              ////
418
//// This source file may be used and distributed without         ////
419
//// restriction provided that this copyright statement is not    ////
420
//// removed from the file and that any derivative work contains  ////
421
//// the original copyright notice and the associated disclaimer. ////
422
////                                                              ////
423
//// This source file is free software; you can redistribute it   ////
424
//// and/or modify it under the terms of the GNU Lesser General   ////
425
//// Public License as published by the Free Software Foundation; ////
426
//// either version 2.1 of the License, or (at your option) any   ////
427
//// later version.                                               ////
428
////                                                              ////
429
//// This source is distributed in the hope that it will be       ////
430
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
431
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
432
//// PURPOSE.  See the GNU Lesser General Public License for more ////
433
//// details.                                                     ////
434
////                                                              ////
435
//// You should have received a copy of the GNU Lesser General    ////
436
//// Public License along with this source; if not, download it   ////
437
//// from http://www.opencores.org/lgpl.shtml                     ////
438
////                                                              ////
439
//////////////////////////////////////////////////////////////////////
440 36 unneback
module vl_mux_andor ( a, sel, dout);
441
parameter width = 32;
442
parameter nr_of_ports = 4;
443
input [nr_of_ports*width-1:0] a;
444
input [nr_of_ports-1:0] sel;
445
output reg [width-1:0] dout;
446 38 unneback
integer i,j;
447 36 unneback
always @ (a, sel)
448
begin
449
    dout = a[width-1:0] & {width{sel[0]}};
450 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
451
        for (j=0;j<width;j=j+1)
452
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
453 36 unneback
end
454
endmodule
455 34 unneback
module vl_mux2_andor ( a1, a0, sel, dout);
456
parameter width = 32;
457 35 unneback
localparam nr_of_ports = 2;
458 34 unneback
input [width-1:0] a1, a0;
459
input [nr_of_ports-1:0] sel;
460
output [width-1:0] dout;
461 36 unneback
vl_mux_andor
462 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
463 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
464 34 unneback
endmodule
465
module vl_mux3_andor ( a2, a1, a0, sel, dout);
466
parameter width = 32;
467 35 unneback
localparam nr_of_ports = 3;
468 34 unneback
input [width-1:0] a2, a1, a0;
469
input [nr_of_ports-1:0] sel;
470
output [width-1:0] dout;
471 36 unneback
vl_mux_andor
472 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
473 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
474 34 unneback
endmodule
475 18 unneback
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
476
parameter width = 32;
477 35 unneback
localparam nr_of_ports = 4;
478 18 unneback
input [width-1:0] a3, a2, a1, a0;
479
input [nr_of_ports-1:0] sel;
480 22 unneback
output [width-1:0] dout;
481 36 unneback
vl_mux_andor
482 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
483 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
484 18 unneback
endmodule
485
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
486
parameter width = 32;
487 35 unneback
localparam nr_of_ports = 5;
488 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
489
input [nr_of_ports-1:0] sel;
490 22 unneback
output [width-1:0] dout;
491 36 unneback
vl_mux_andor
492 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
493 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
494 18 unneback
endmodule
495
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
496
parameter width = 32;
497 35 unneback
localparam nr_of_ports = 6;
498 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
499
input [nr_of_ports-1:0] sel;
500 22 unneback
output [width-1:0] dout;
501 36 unneback
vl_mux_andor
502 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
503 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
504 18 unneback
endmodule
505 43 unneback
module vl_parity_generate (data, parity);
506
parameter word_size = 32;
507
parameter chunk_size = 8;
508
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
509
input [word_size-1:0] data;
510
output reg [word_size/chunk_size-1:0] parity;
511
integer i,j;
512
always @ (data)
513
for (i=0;i<word_size/chunk_size;i=i+1) begin
514
    parity[i] = parity_type;
515
    for (j=0;j<chunk_size;j=j+1) begin
516 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
517 43 unneback
    end
518
end
519
endmodule
520
module vl_parity_check( data, parity, parity_error);
521
parameter word_size = 32;
522
parameter chunk_size = 8;
523
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
524
input [word_size-1:0] data;
525
input [word_size/chunk_size-1:0] parity;
526
output parity_error;
527 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
528 43 unneback
integer i,j;
529
always @ (data or parity)
530
for (i=0;i<word_size/chunk_size;i=i+1) begin
531
    error_flag[i] = parity[i] ^ parity_type;
532
    for (j=0;j<chunk_size;j=j+1) begin
533 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
534 43 unneback
    end
535
end
536
assign parity_error = |error_flag;
537
endmodule
538 18 unneback
//////////////////////////////////////////////////////////////////////
539
////                                                              ////
540 44 unneback
////  IO functions                                                ////
541
////                                                              ////
542
////  Description                                                 ////
543
////  IO functions such as IOB flip-flops                         ////
544
////                                                              ////
545
////                                                              ////
546
////  To Do:                                                      ////
547
////   -                                                          ////
548
////                                                              ////
549
////  Author(s):                                                  ////
550
////      - Michael Unneback, unneback@opencores.org              ////
551
////        ORSoC AB                                              ////
552
////                                                              ////
553
//////////////////////////////////////////////////////////////////////
554
////                                                              ////
555
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
556
////                                                              ////
557
//// This source file may be used and distributed without         ////
558
//// restriction provided that this copyright statement is not    ////
559
//// removed from the file and that any derivative work contains  ////
560
//// the original copyright notice and the associated disclaimer. ////
561
////                                                              ////
562
//// This source file is free software; you can redistribute it   ////
563
//// and/or modify it under the terms of the GNU Lesser General   ////
564
//// Public License as published by the Free Software Foundation; ////
565
//// either version 2.1 of the License, or (at your option) any   ////
566
//// later version.                                               ////
567
////                                                              ////
568
//// This source is distributed in the hope that it will be       ////
569
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
570
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
571
//// PURPOSE.  See the GNU Lesser General Public License for more ////
572
//// details.                                                     ////
573
////                                                              ////
574
//// You should have received a copy of the GNU Lesser General    ////
575
//// Public License along with this source; if not, download it   ////
576
//// from http://www.opencores.org/lgpl.shtml                     ////
577
////                                                              ////
578
//////////////////////////////////////////////////////////////////////
579 45 unneback
`timescale 1ns/1ns
580 44 unneback
module vl_o_dff (d_i, o_pad, clk, rst);
581
parameter width = 1;
582 45 unneback
parameter reset_value = {width{1'b0}};
583
input  [width-1:0]  d_i;
584 44 unneback
output [width-1:0] o_pad;
585
input clk, rst;
586
wire [width-1:0] d_i_int /*synthesis syn_keep = 1*/;
587 45 unneback
reg  [width-1:0] o_pad_int;
588 44 unneback
assign d_i_int = d_i;
589
genvar i;
590 45 unneback
generate
591 44 unneback
for (i=0;i<width;i=i+1) begin
592
    always @ (posedge clk or posedge rst)
593
    if (rst)
594 45 unneback
        o_pad_int[i] <= reset_value[i];
595 44 unneback
    else
596 45 unneback
        o_pad_int[i] <= d_i_int[i];
597
    assign #1 o_pad[i] = o_pad_int[i];
598 44 unneback
end
599
endgenerate
600
endmodule
601 45 unneback
`timescale 1ns/1ns
602 44 unneback
module vl_io_dff_oe ( d_i, d_o, oe, io_pad, clk, rst);
603
parameter width = 1;
604
input  [width-1:0] d_o;
605
output reg [width-1:0] d_i;
606
input oe;
607
inout [width-1:0] io_pad;
608
input clk, rst;
609
wire [width-1:0] oe_d /*synthesis syn_keep = 1*/;
610
reg [width-1:0] oe_q;
611
reg [width-1:0] d_o_q;
612
assign oe_d = {width{oe}};
613
genvar i;
614
generate
615
for (i=0;i<width;i=i+1) begin
616
    always @ (posedge clk or posedge rst)
617
    if (rst)
618
        oe_q[i] <= 1'b0;
619
    else
620
        oe_q[i] <= oe_d[i];
621
    always @ (posedge clk or posedge rst)
622
    if (rst)
623
        d_o_q[i] <= 1'b0;
624
    else
625
        d_o_q[i] <= d_o[i];
626
    always @ (posedge clk or posedge rst)
627
    if (rst)
628
        d_i[i] <= 1'b0;
629
    else
630
        d_i[i] <= io_pad[i];
631 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
632 44 unneback
end
633
endgenerate
634
endmodule
635
//////////////////////////////////////////////////////////////////////
636
////                                                              ////
637 6 unneback
////  Versatile counter                                           ////
638
////                                                              ////
639
////  Description                                                 ////
640
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
641
////  counter                                                     ////
642
////                                                              ////
643
////  To Do:                                                      ////
644
////   - add LFSR with more taps                                  ////
645
////                                                              ////
646
////  Author(s):                                                  ////
647
////      - Michael Unneback, unneback@opencores.org              ////
648
////        ORSoC AB                                              ////
649
////                                                              ////
650
//////////////////////////////////////////////////////////////////////
651
////                                                              ////
652
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
653
////                                                              ////
654
//// This source file may be used and distributed without         ////
655
//// restriction provided that this copyright statement is not    ////
656
//// removed from the file and that any derivative work contains  ////
657
//// the original copyright notice and the associated disclaimer. ////
658
////                                                              ////
659
//// This source file is free software; you can redistribute it   ////
660
//// and/or modify it under the terms of the GNU Lesser General   ////
661
//// Public License as published by the Free Software Foundation; ////
662
//// either version 2.1 of the License, or (at your option) any   ////
663
//// later version.                                               ////
664
////                                                              ////
665
//// This source is distributed in the hope that it will be       ////
666
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
667
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
668
//// PURPOSE.  See the GNU Lesser General Public License for more ////
669
//// details.                                                     ////
670
////                                                              ////
671
//// You should have received a copy of the GNU Lesser General    ////
672
//// Public License along with this source; if not, download it   ////
673
//// from http://www.opencores.org/lgpl.shtml                     ////
674
////                                                              ////
675
//////////////////////////////////////////////////////////////////////
676
// binary counter
677 40 unneback
module vl_cnt_bin_ce (
678
 cke, q, rst, clk);
679 22 unneback
   parameter length = 4;
680 6 unneback
   input cke;
681
   output [length:1] q;
682
   input rst;
683
   input clk;
684
   parameter clear_value = 0;
685
   parameter set_value = 1;
686
   parameter wrap_value = 0;
687
   parameter level1_value = 15;
688
   reg  [length:1] qi;
689
   wire [length:1] q_next;
690
   assign q_next = qi + {{length-1{1'b0}},1'b1};
691
   always @ (posedge clk or posedge rst)
692
     if (rst)
693
       qi <= {length{1'b0}};
694
     else
695
     if (cke)
696
       qi <= q_next;
697
   assign q = qi;
698
endmodule
699
//////////////////////////////////////////////////////////////////////
700
////                                                              ////
701
////  Versatile counter                                           ////
702
////                                                              ////
703
////  Description                                                 ////
704
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
705
////  counter                                                     ////
706
////                                                              ////
707
////  To Do:                                                      ////
708
////   - add LFSR with more taps                                  ////
709
////                                                              ////
710
////  Author(s):                                                  ////
711
////      - Michael Unneback, unneback@opencores.org              ////
712
////        ORSoC AB                                              ////
713
////                                                              ////
714
//////////////////////////////////////////////////////////////////////
715
////                                                              ////
716
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
717
////                                                              ////
718
//// This source file may be used and distributed without         ////
719
//// restriction provided that this copyright statement is not    ////
720
//// removed from the file and that any derivative work contains  ////
721
//// the original copyright notice and the associated disclaimer. ////
722
////                                                              ////
723
//// This source file is free software; you can redistribute it   ////
724
//// and/or modify it under the terms of the GNU Lesser General   ////
725
//// Public License as published by the Free Software Foundation; ////
726
//// either version 2.1 of the License, or (at your option) any   ////
727
//// later version.                                               ////
728
////                                                              ////
729
//// This source is distributed in the hope that it will be       ////
730
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
731
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
732
//// PURPOSE.  See the GNU Lesser General Public License for more ////
733
//// details.                                                     ////
734
////                                                              ////
735
//// You should have received a copy of the GNU Lesser General    ////
736
//// Public License along with this source; if not, download it   ////
737
//// from http://www.opencores.org/lgpl.shtml                     ////
738
////                                                              ////
739
//////////////////////////////////////////////////////////////////////
740
// binary counter
741 40 unneback
module vl_cnt_bin_ce_rew_zq_l1 (
742
 cke, rew, zq, level1, rst, clk);
743 6 unneback
   parameter length = 4;
744
   input cke;
745
   input rew;
746 25 unneback
   output reg zq;
747
   output reg level1;
748
   input rst;
749
   input clk;
750
   parameter clear_value = 0;
751
   parameter set_value = 1;
752
   parameter wrap_value = 1;
753
   parameter level1_value = 15;
754 29 unneback
   wire clear;
755 30 unneback
   assign clear = 1'b0;
756 25 unneback
   reg  [length:1] qi;
757
   wire  [length:1] q_next, q_next_fw, q_next_rew;
758
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
759
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
760
   assign q_next = rew ? q_next_rew : q_next_fw;
761
   always @ (posedge clk or posedge rst)
762
     if (rst)
763
       qi <= {length{1'b0}};
764
     else
765
     if (cke)
766
       qi <= q_next;
767
   always @ (posedge clk or posedge rst)
768
     if (rst)
769
       zq <= 1'b1;
770
     else
771
     if (cke)
772
       zq <= q_next == {length{1'b0}};
773
    always @ (posedge clk or posedge rst)
774
    if (rst)
775
        level1 <= 1'b0;
776
    else
777
    if (cke)
778 29 unneback
    if (clear)
779
        level1 <= 1'b0;
780
    else if (q_next == level1_value)
781 25 unneback
        level1 <= 1'b1;
782
    else if (qi == level1_value & rew)
783
        level1 <= 1'b0;
784
endmodule
785
//////////////////////////////////////////////////////////////////////
786
////                                                              ////
787
////  Versatile counter                                           ////
788
////                                                              ////
789
////  Description                                                 ////
790
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
791
////  counter                                                     ////
792
////                                                              ////
793
////  To Do:                                                      ////
794
////   - add LFSR with more taps                                  ////
795
////                                                              ////
796
////  Author(s):                                                  ////
797
////      - Michael Unneback, unneback@opencores.org              ////
798
////        ORSoC AB                                              ////
799
////                                                              ////
800
//////////////////////////////////////////////////////////////////////
801
////                                                              ////
802
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
803
////                                                              ////
804
//// This source file may be used and distributed without         ////
805
//// restriction provided that this copyright statement is not    ////
806
//// removed from the file and that any derivative work contains  ////
807
//// the original copyright notice and the associated disclaimer. ////
808
////                                                              ////
809
//// This source file is free software; you can redistribute it   ////
810
//// and/or modify it under the terms of the GNU Lesser General   ////
811
//// Public License as published by the Free Software Foundation; ////
812
//// either version 2.1 of the License, or (at your option) any   ////
813
//// later version.                                               ////
814
////                                                              ////
815
//// This source is distributed in the hope that it will be       ////
816
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
817
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
818
//// PURPOSE.  See the GNU Lesser General Public License for more ////
819
//// details.                                                     ////
820
////                                                              ////
821
//// You should have received a copy of the GNU Lesser General    ////
822
//// Public License along with this source; if not, download it   ////
823
//// from http://www.opencores.org/lgpl.shtml                     ////
824
////                                                              ////
825
//////////////////////////////////////////////////////////////////////
826
// binary counter
827 40 unneback
module vl_cnt_bin_ce_rew_q_zq_l1 (
828
 cke, rew, q, zq, level1, rst, clk);
829 25 unneback
   parameter length = 4;
830
   input cke;
831
   input rew;
832
   output [length:1] q;
833
   output reg zq;
834
   output reg level1;
835
   input rst;
836
   input clk;
837
   parameter clear_value = 0;
838
   parameter set_value = 1;
839
   parameter wrap_value = 1;
840
   parameter level1_value = 15;
841 29 unneback
   wire clear;
842 30 unneback
   assign clear = 1'b0;
843 25 unneback
   reg  [length:1] qi;
844
   wire  [length:1] q_next, q_next_fw, q_next_rew;
845
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
846
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
847
   assign q_next = rew ? q_next_rew : q_next_fw;
848
   always @ (posedge clk or posedge rst)
849
     if (rst)
850
       qi <= {length{1'b0}};
851
     else
852
     if (cke)
853
       qi <= q_next;
854
   assign q = qi;
855
   always @ (posedge clk or posedge rst)
856
     if (rst)
857
       zq <= 1'b1;
858
     else
859
     if (cke)
860
       zq <= q_next == {length{1'b0}};
861
    always @ (posedge clk or posedge rst)
862
    if (rst)
863
        level1 <= 1'b0;
864
    else
865
    if (cke)
866 29 unneback
    if (clear)
867
        level1 <= 1'b0;
868
    else if (q_next == level1_value)
869 25 unneback
        level1 <= 1'b1;
870
    else if (qi == level1_value & rew)
871
        level1 <= 1'b0;
872
endmodule
873
//////////////////////////////////////////////////////////////////////
874
////                                                              ////
875
////  Versatile counter                                           ////
876
////                                                              ////
877
////  Description                                                 ////
878
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
879
////  counter                                                     ////
880
////                                                              ////
881
////  To Do:                                                      ////
882
////   - add LFSR with more taps                                  ////
883
////                                                              ////
884
////  Author(s):                                                  ////
885
////      - Michael Unneback, unneback@opencores.org              ////
886
////        ORSoC AB                                              ////
887
////                                                              ////
888
//////////////////////////////////////////////////////////////////////
889
////                                                              ////
890
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
891
////                                                              ////
892
//// This source file may be used and distributed without         ////
893
//// restriction provided that this copyright statement is not    ////
894
//// removed from the file and that any derivative work contains  ////
895
//// the original copyright notice and the associated disclaimer. ////
896
////                                                              ////
897
//// This source file is free software; you can redistribute it   ////
898
//// and/or modify it under the terms of the GNU Lesser General   ////
899
//// Public License as published by the Free Software Foundation; ////
900
//// either version 2.1 of the License, or (at your option) any   ////
901
//// later version.                                               ////
902
////                                                              ////
903
//// This source is distributed in the hope that it will be       ////
904
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
905
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
906
//// PURPOSE.  See the GNU Lesser General Public License for more ////
907
//// details.                                                     ////
908
////                                                              ////
909
//// You should have received a copy of the GNU Lesser General    ////
910
//// Public License along with this source; if not, download it   ////
911
//// from http://www.opencores.org/lgpl.shtml                     ////
912
////                                                              ////
913
//////////////////////////////////////////////////////////////////////
914 6 unneback
// GRAY counter
915 40 unneback
module vl_cnt_gray_ce_bin (
916
 cke, q, q_bin, rst, clk);
917 6 unneback
   parameter length = 4;
918
   input cke;
919
   output reg [length:1] q;
920
   output [length:1] q_bin;
921
   input rst;
922
   input clk;
923
   parameter clear_value = 0;
924
   parameter set_value = 1;
925
   parameter wrap_value = 8;
926
   parameter level1_value = 15;
927
   reg  [length:1] qi;
928
   wire [length:1] q_next;
929
   assign q_next = qi + {{length-1{1'b0}},1'b1};
930
   always @ (posedge clk or posedge rst)
931
     if (rst)
932
       qi <= {length{1'b0}};
933
     else
934
     if (cke)
935
       qi <= q_next;
936
   always @ (posedge clk or posedge rst)
937
     if (rst)
938
       q <= {length{1'b0}};
939
     else
940
       if (cke)
941
         q <= (q_next>>1) ^ q_next;
942
   assign q_bin = qi;
943
endmodule
944
//////////////////////////////////////////////////////////////////////
945
////                                                              ////
946
////  Versatile library, counters                                 ////
947
////                                                              ////
948
////  Description                                                 ////
949
////  counters                                                    ////
950
////                                                              ////
951
////                                                              ////
952
////  To Do:                                                      ////
953
////   - add more counters                                        ////
954
////                                                              ////
955
////  Author(s):                                                  ////
956
////      - Michael Unneback, unneback@opencores.org              ////
957
////        ORSoC AB                                              ////
958
////                                                              ////
959
//////////////////////////////////////////////////////////////////////
960
////                                                              ////
961
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
962
////                                                              ////
963
//// This source file may be used and distributed without         ////
964
//// restriction provided that this copyright statement is not    ////
965
//// removed from the file and that any derivative work contains  ////
966
//// the original copyright notice and the associated disclaimer. ////
967
////                                                              ////
968
//// This source file is free software; you can redistribute it   ////
969
//// and/or modify it under the terms of the GNU Lesser General   ////
970
//// Public License as published by the Free Software Foundation; ////
971
//// either version 2.1 of the License, or (at your option) any   ////
972
//// later version.                                               ////
973
////                                                              ////
974
//// This source is distributed in the hope that it will be       ////
975
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
976
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
977
//// PURPOSE.  See the GNU Lesser General Public License for more ////
978
//// details.                                                     ////
979
////                                                              ////
980
//// You should have received a copy of the GNU Lesser General    ////
981
//// Public License along with this source; if not, download it   ////
982
//// from http://www.opencores.org/lgpl.shtml                     ////
983
////                                                              ////
984
//////////////////////////////////////////////////////////////////////
985 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
986 6 unneback
   parameter length = 4;
987
   output reg [0:length-1] q;
988
   input rst;
989
   input clk;
990
    always @ (posedge clk or posedge rst)
991
    if (rst)
992
        q <= {1'b1,{length-1{1'b0}}};
993
    else
994
        q <= {q[length-1],q[0:length-2]};
995
endmodule
996 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
997 6 unneback
   parameter length = 4;
998
   input cke;
999
   output reg [0:length-1] q;
1000
   input rst;
1001
   input clk;
1002
    always @ (posedge clk or posedge rst)
1003
    if (rst)
1004
        q <= {1'b1,{length-1{1'b0}}};
1005
    else
1006
        if (cke)
1007
            q <= {q[length-1],q[0:length-2]};
1008
endmodule
1009 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1010 6 unneback
   parameter length = 4;
1011
   input cke, clear;
1012
   output reg [0:length-1] q;
1013
   input rst;
1014
   input clk;
1015
    always @ (posedge clk or posedge rst)
1016
    if (rst)
1017
        q <= {1'b1,{length-1{1'b0}}};
1018
    else
1019
        if (cke)
1020
            if (clear)
1021
                q <= {1'b1,{length-1{1'b0}}};
1022
            else
1023
                q <= q >> 1;
1024
endmodule
1025 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
1026 6 unneback
   parameter length = 4;
1027
   input cke, clear;
1028
   output reg [0:length-1] q;
1029
   input rst;
1030
   input clk;
1031
    always @ (posedge clk or posedge rst)
1032
    if (rst)
1033
        q <= {1'b1,{length-1{1'b0}}};
1034
    else
1035
        if (cke)
1036
            if (clear)
1037
                q <= {1'b1,{length-1{1'b0}}};
1038
            else
1039
            q <= {q[length-1],q[0:length-2]};
1040
endmodule
1041
//////////////////////////////////////////////////////////////////////
1042
////                                                              ////
1043
////  Versatile library, memories                                 ////
1044
////                                                              ////
1045
////  Description                                                 ////
1046
////  memories                                                    ////
1047
////                                                              ////
1048
////                                                              ////
1049
////  To Do:                                                      ////
1050
////   - add more memory types                                    ////
1051
////                                                              ////
1052
////  Author(s):                                                  ////
1053
////      - Michael Unneback, unneback@opencores.org              ////
1054
////        ORSoC AB                                              ////
1055
////                                                              ////
1056
//////////////////////////////////////////////////////////////////////
1057
////                                                              ////
1058
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1059
////                                                              ////
1060
//// This source file may be used and distributed without         ////
1061
//// restriction provided that this copyright statement is not    ////
1062
//// removed from the file and that any derivative work contains  ////
1063
//// the original copyright notice and the associated disclaimer. ////
1064
////                                                              ////
1065
//// This source file is free software; you can redistribute it   ////
1066
//// and/or modify it under the terms of the GNU Lesser General   ////
1067
//// Public License as published by the Free Software Foundation; ////
1068
//// either version 2.1 of the License, or (at your option) any   ////
1069
//// later version.                                               ////
1070
////                                                              ////
1071
//// This source is distributed in the hope that it will be       ////
1072
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1073
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1074
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1075
//// details.                                                     ////
1076
////                                                              ////
1077
//// You should have received a copy of the GNU Lesser General    ////
1078
//// Public License along with this source; if not, download it   ////
1079
//// from http://www.opencores.org/lgpl.shtml                     ////
1080
////                                                              ////
1081
//////////////////////////////////////////////////////////////////////
1082
/// ROM
1083 7 unneback
module vl_rom_init ( adr, q, clk);
1084
   parameter data_width = 32;
1085
   parameter addr_width = 8;
1086
   input [(addr_width-1):0]       adr;
1087
   output reg [(data_width-1):0] q;
1088
   input                         clk;
1089
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
1090
   parameter memory_file = "vl_rom.vmem";
1091
   initial
1092
     begin
1093
        $readmemh(memory_file, rom);
1094
     end
1095
   always @ (posedge clk)
1096
     q <= rom[adr];
1097
endmodule
1098 14 unneback
/*
1099 7 unneback
module vl_rom ( adr, q, clk);
1100 6 unneback
parameter data_width = 32;
1101
parameter addr_width = 4;
1102
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
1103
    {32'h18000000},
1104
    {32'hA8200000},
1105
    {32'hA8200000},
1106
    {32'hA8200000},
1107
    {32'h44003000},
1108
    {32'h15000000},
1109
    {32'h15000000},
1110
    {32'h15000000},
1111
    {32'h15000000},
1112
    {32'h15000000},
1113
    {32'h15000000},
1114
    {32'h15000000},
1115
    {32'h15000000},
1116
    {32'h15000000},
1117
    {32'h15000000},
1118
    {32'h15000000}};
1119 7 unneback
input [addr_width-1:0] adr;
1120 6 unneback
output reg [data_width-1:0] q;
1121
input clk;
1122
always @ (posedge clk)
1123 7 unneback
    q <= data[adr];
1124 6 unneback
endmodule
1125 14 unneback
*/
1126 6 unneback
// Single port RAM
1127
module vl_ram ( d, adr, we, q, clk);
1128
   parameter data_width = 32;
1129
   parameter addr_width = 8;
1130
   input [(data_width-1):0]      d;
1131
   input [(addr_width-1):0]       adr;
1132
   input                         we;
1133 7 unneback
   output reg [(data_width-1):0] q;
1134 6 unneback
   input                         clk;
1135
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1136 7 unneback
   parameter init = 0;
1137
   parameter memory_file = "vl_ram.vmem";
1138
   generate if (init) begin : init_mem
1139
   initial
1140
     begin
1141
        $readmemh(memory_file, ram);
1142
     end
1143
   end
1144
   endgenerate
1145 6 unneback
   always @ (posedge clk)
1146
   begin
1147
   if (we)
1148
     ram[adr] <= d;
1149
   q <= ram[adr];
1150
   end
1151
endmodule
1152 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
1153
   parameter data_width = 32;
1154
   parameter addr_width = 8;
1155
   input [(data_width-1):0]      d;
1156
   input [(addr_width-1):0]       adr;
1157
   input [(addr_width/4)-1:0]    be;
1158
   input                         we;
1159
   output reg [(data_width-1):0] q;
1160
   input                         clk;
1161
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1162
   parameter init = 0;
1163
   parameter memory_file = "vl_ram.vmem";
1164
   generate if (init) begin : init_mem
1165
   initial
1166
     begin
1167
        $readmemh(memory_file, ram);
1168
     end
1169
   end
1170
   endgenerate
1171
   genvar i;
1172
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
1173
      always @ (posedge clk)
1174
      if (we & be[i])
1175
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
1176
   end
1177
   endgenerate
1178
   always @ (posedge clk)
1179
      q <= ram[adr];
1180
endmodule
1181 6 unneback
// Dual port RAM
1182
// ACTEL FPGA should not use logic to handle rw collision
1183 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1184 6 unneback
   parameter data_width = 32;
1185
   parameter addr_width = 8;
1186
   input [(data_width-1):0]      d_a;
1187
   input [(addr_width-1):0]       adr_a;
1188
   input [(addr_width-1):0]       adr_b;
1189
   input                         we_a;
1190
   output [(data_width-1):0]      q_b;
1191
   input                         clk_a, clk_b;
1192
   reg [(addr_width-1):0]         adr_b_reg;
1193
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1194 7 unneback
   parameter init = 0;
1195
   parameter memory_file = "vl_ram.vmem";
1196
   generate if (init) begin : init_mem
1197
   initial
1198
     begin
1199
        $readmemh(memory_file, ram);
1200
     end
1201
   end
1202
   endgenerate
1203 6 unneback
   always @ (posedge clk_a)
1204
   if (we_a)
1205
     ram[adr_a] <= d_a;
1206
   always @ (posedge clk_b)
1207
   adr_b_reg <= adr_b;
1208
   assign q_b = ram[adr_b_reg];
1209
endmodule
1210 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1211 6 unneback
   parameter data_width = 32;
1212
   parameter addr_width = 8;
1213
   input [(data_width-1):0]      d_a;
1214
   input [(addr_width-1):0]       adr_a;
1215
   input [(addr_width-1):0]       adr_b;
1216
   input                         we_a;
1217
   output [(data_width-1):0]      q_b;
1218
   output reg [(data_width-1):0] q_a;
1219
   input                         clk_a, clk_b;
1220
   reg [(data_width-1):0]         q_b;
1221
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1222 7 unneback
   parameter init = 0;
1223
   parameter memory_file = "vl_ram.vmem";
1224
   generate if (init) begin : init_mem
1225
   initial
1226
     begin
1227
        $readmemh(memory_file, ram);
1228
     end
1229
   end
1230
   endgenerate
1231 6 unneback
   always @ (posedge clk_a)
1232
     begin
1233
        q_a <= ram[adr_a];
1234
        if (we_a)
1235
             ram[adr_a] <= d_a;
1236
     end
1237
   always @ (posedge clk_b)
1238
          q_b <= ram[adr_b];
1239
endmodule
1240 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
1241 6 unneback
   parameter data_width = 32;
1242
   parameter addr_width = 8;
1243
   input [(data_width-1):0]      d_a;
1244
   input [(addr_width-1):0]       adr_a;
1245
   input [(addr_width-1):0]       adr_b;
1246
   input                         we_a;
1247
   output [(data_width-1):0]      q_b;
1248
   input [(data_width-1):0]       d_b;
1249
   output reg [(data_width-1):0] q_a;
1250
   input                         we_b;
1251
   input                         clk_a, clk_b;
1252
   reg [(data_width-1):0]         q_b;
1253
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
1254 7 unneback
   parameter init = 0;
1255
   parameter memory_file = "vl_ram.vmem";
1256
   generate if (init) begin : init_mem
1257
   initial
1258
     begin
1259
        $readmemh(memory_file, ram);
1260
     end
1261
   end
1262
   endgenerate
1263 6 unneback
   always @ (posedge clk_a)
1264
     begin
1265
        q_a <= ram[adr_a];
1266
        if (we_a)
1267
             ram[adr_a] <= d_a;
1268
     end
1269
   always @ (posedge clk_b)
1270
     begin
1271
        q_b <= ram[adr_b];
1272
        if (we_b)
1273
          ram[adr_b] <= d_b;
1274
     end
1275
endmodule
1276
// Content addresable memory, CAM
1277
// FIFO
1278 25 unneback
module vl_fifo_1r1w_fill_level_sync (
1279
    d, wr, fifo_full,
1280
    q, rd, fifo_empty,
1281
    fill_level,
1282
    clk, rst
1283
    );
1284
parameter data_width = 18;
1285
parameter addr_width = 4;
1286
// write side
1287
input  [data_width-1:0] d;
1288
input                   wr;
1289
output                  fifo_full;
1290
// read side
1291
output [data_width-1:0] q;
1292
input                   rd;
1293
output                  fifo_empty;
1294
// common
1295
output [addr_width:0]   fill_level;
1296
input rst, clk;
1297
wire [addr_width:1] wadr, radr;
1298
vl_cnt_bin_ce
1299
    # ( .length(addr_width))
1300
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
1301
vl_cnt_bin_ce
1302
    # (.length(addr_width))
1303
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
1304
vl_dpram_1r1w
1305
    # (.data_width(data_width), .addr_width(addr_width))
1306
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
1307 31 unneback
vl_cnt_bin_ce_rew_q_zq_l1
1308 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
1309 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
1310
endmodule
1311 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
1312
// RAM is supposed to be larger than the two FIFOs
1313
// LFSR counters used adr pointers
1314
module vl_fifo_2r2w_sync_simplex (
1315
    // a side
1316
    a_d, a_wr, a_fifo_full,
1317
    a_q, a_rd, a_fifo_empty,
1318
    a_fill_level,
1319
    // b side
1320
    b_d, b_wr, b_fifo_full,
1321
    b_q, b_rd, b_fifo_empty,
1322
    b_fill_level,
1323
    // common
1324
    clk, rst
1325
    );
1326
parameter data_width = 8;
1327
parameter addr_width = 5;
1328
parameter fifo_full_level = (1<<addr_width)-1;
1329
// a side
1330
input  [data_width-1:0] a_d;
1331
input                   a_wr;
1332
output                  a_fifo_full;
1333
output [data_width-1:0] a_q;
1334
input                   a_rd;
1335
output                  a_fifo_empty;
1336
output [addr_width-1:0] a_fill_level;
1337
// b side
1338
input  [data_width-1:0] b_d;
1339
input                   b_wr;
1340
output                  b_fifo_full;
1341
output [data_width-1:0] b_q;
1342
input                   b_rd;
1343
output                  b_fifo_empty;
1344
output [addr_width-1:0] b_fill_level;
1345
input                   clk;
1346
input                   rst;
1347
// adr_gen
1348
wire [addr_width:1] a_wadr, a_radr;
1349
wire [addr_width:1] b_wadr, b_radr;
1350
// dpram
1351
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1352
vl_cnt_lfsr_ce
1353
    # ( .length(addr_width))
1354
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
1355
vl_cnt_lfsr_ce
1356
    # (.length(addr_width))
1357
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
1358
vl_cnt_lfsr_ce
1359
    # ( .length(addr_width))
1360
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
1361
vl_cnt_lfsr_ce
1362
    # (.length(addr_width))
1363
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
1364
// mux read or write adr to DPRAM
1365
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
1366
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
1367
vl_dpram_2r2w
1368
    # (.data_width(data_width), .addr_width(addr_width+1))
1369
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1370
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1371
vl_cnt_bin_ce_rew_zq_l1
1372 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
1373 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
1374
vl_cnt_bin_ce_rew_zq_l1
1375 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
1376 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
1377
endmodule
1378 6 unneback
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
1379 11 unneback
   parameter addr_width = 4;
1380
   parameter N = addr_width-1;
1381 6 unneback
   parameter Q1 = 2'b00;
1382
   parameter Q2 = 2'b01;
1383
   parameter Q3 = 2'b11;
1384
   parameter Q4 = 2'b10;
1385
   parameter going_empty = 1'b0;
1386
   parameter going_full  = 1'b1;
1387
   input [N:0]  wptr, rptr;
1388 14 unneback
   output       fifo_empty;
1389 6 unneback
   output       fifo_full;
1390
   input        wclk, rclk, rst;
1391
   wire direction;
1392
   reg  direction_set, direction_clr;
1393
   wire async_empty, async_full;
1394
   wire fifo_full2;
1395 14 unneback
   wire fifo_empty2;
1396 6 unneback
   // direction_set
1397
   always @ (wptr[N:N-1] or rptr[N:N-1])
1398
     case ({wptr[N:N-1],rptr[N:N-1]})
1399
       {Q1,Q2} : direction_set <= 1'b1;
1400
       {Q2,Q3} : direction_set <= 1'b1;
1401
       {Q3,Q4} : direction_set <= 1'b1;
1402
       {Q4,Q1} : direction_set <= 1'b1;
1403
       default : direction_set <= 1'b0;
1404
     endcase
1405
   // direction_clear
1406
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
1407
     if (rst)
1408
       direction_clr <= 1'b1;
1409
     else
1410
       case ({wptr[N:N-1],rptr[N:N-1]})
1411
         {Q2,Q1} : direction_clr <= 1'b1;
1412
         {Q3,Q2} : direction_clr <= 1'b1;
1413
         {Q4,Q3} : direction_clr <= 1'b1;
1414
         {Q1,Q4} : direction_clr <= 1'b1;
1415
         default : direction_clr <= 1'b0;
1416
       endcase
1417 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
1418 6 unneback
   assign async_empty = (wptr == rptr) && (direction==going_empty);
1419
   assign async_full  = (wptr == rptr) && (direction==going_full);
1420 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
1421
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
1422 6 unneback
/*
1423
   always @ (posedge wclk or posedge rst or posedge async_full)
1424
     if (rst)
1425
       {fifo_full, fifo_full2} <= 2'b00;
1426
     else if (async_full)
1427
       {fifo_full, fifo_full2} <= 2'b11;
1428
     else
1429
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
1430
*/
1431 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
1432 6 unneback
     if (async_empty)
1433
       {fifo_empty, fifo_empty2} <= 2'b11;
1434
     else
1435 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
1436 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
1437
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
1438 27 unneback
endmodule // async_compb
1439 6 unneback
module vl_fifo_1r1w_async (
1440
    d, wr, fifo_full, wr_clk, wr_rst,
1441
    q, rd, fifo_empty, rd_clk, rd_rst
1442
    );
1443
parameter data_width = 18;
1444
parameter addr_width = 4;
1445
// write side
1446
input  [data_width-1:0] d;
1447
input                   wr;
1448
output                  fifo_full;
1449
input                   wr_clk;
1450
input                   wr_rst;
1451
// read side
1452
output [data_width-1:0] q;
1453
input                   rd;
1454
output                  fifo_empty;
1455
input                   rd_clk;
1456
input                   rd_rst;
1457
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
1458 18 unneback
vl_cnt_gray_ce_bin
1459 6 unneback
    # ( .length(addr_width))
1460
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
1461 18 unneback
vl_cnt_gray_ce_bin
1462 6 unneback
    # (.length(addr_width))
1463 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
1464 7 unneback
vl_dpram_1r1w
1465 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
1466
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
1467
vl_fifo_cmp_async
1468
    # (.addr_width(addr_width))
1469
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
1470
endmodule
1471 8 unneback
module vl_fifo_2r2w_async (
1472 6 unneback
    // a side
1473
    a_d, a_wr, a_fifo_full,
1474
    a_q, a_rd, a_fifo_empty,
1475
    a_clk, a_rst,
1476
    // b side
1477
    b_d, b_wr, b_fifo_full,
1478
    b_q, b_rd, b_fifo_empty,
1479
    b_clk, b_rst
1480
    );
1481
parameter data_width = 18;
1482
parameter addr_width = 4;
1483
// a side
1484
input  [data_width-1:0] a_d;
1485
input                   a_wr;
1486
output                  a_fifo_full;
1487
output [data_width-1:0] a_q;
1488
input                   a_rd;
1489
output                  a_fifo_empty;
1490
input                   a_clk;
1491
input                   a_rst;
1492
// b side
1493
input  [data_width-1:0] b_d;
1494
input                   b_wr;
1495
output                  b_fifo_full;
1496
output [data_width-1:0] b_q;
1497
input                   b_rd;
1498
output                  b_fifo_empty;
1499
input                   b_clk;
1500
input                   b_rst;
1501
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1502
vl_fifo_1r1w_async_a (
1503
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
1504
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
1505
    );
1506
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1507
vl_fifo_1r1w_async_b (
1508
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
1509
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
1510
    );
1511
endmodule
1512 8 unneback
module vl_fifo_2r2w_async_simplex (
1513 6 unneback
    // a side
1514
    a_d, a_wr, a_fifo_full,
1515
    a_q, a_rd, a_fifo_empty,
1516
    a_clk, a_rst,
1517
    // b side
1518
    b_d, b_wr, b_fifo_full,
1519
    b_q, b_rd, b_fifo_empty,
1520
    b_clk, b_rst
1521
    );
1522
parameter data_width = 18;
1523
parameter addr_width = 4;
1524
// a side
1525
input  [data_width-1:0] a_d;
1526
input                   a_wr;
1527
output                  a_fifo_full;
1528
output [data_width-1:0] a_q;
1529
input                   a_rd;
1530
output                  a_fifo_empty;
1531
input                   a_clk;
1532
input                   a_rst;
1533
// b side
1534
input  [data_width-1:0] b_d;
1535
input                   b_wr;
1536
output                  b_fifo_full;
1537
output [data_width-1:0] b_q;
1538
input                   b_rd;
1539
output                  b_fifo_empty;
1540
input                   b_clk;
1541
input                   b_rst;
1542
// adr_gen
1543
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
1544
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
1545
// dpram
1546
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1547 18 unneback
vl_cnt_gray_ce_bin
1548 6 unneback
    # ( .length(addr_width))
1549
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
1550 18 unneback
vl_cnt_gray_ce_bin
1551 6 unneback
    # (.length(addr_width))
1552
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
1553 18 unneback
vl_cnt_gray_ce_bin
1554 6 unneback
    # ( .length(addr_width))
1555
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
1556 18 unneback
vl_cnt_gray_ce_bin
1557 6 unneback
    # (.length(addr_width))
1558
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
1559
// mux read or write adr to DPRAM
1560
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
1561
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
1562 11 unneback
vl_dpram_2r2w
1563 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
1564
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1565
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1566 11 unneback
vl_fifo_cmp_async
1567 6 unneback
    # (.addr_width(addr_width))
1568
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
1569 11 unneback
vl_fifo_cmp_async
1570 6 unneback
    # (.addr_width(addr_width))
1571
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
1572
endmodule
1573 12 unneback
//////////////////////////////////////////////////////////////////////
1574
////                                                              ////
1575
////  Versatile library, wishbone stuff                           ////
1576
////                                                              ////
1577
////  Description                                                 ////
1578
////  Wishbone compliant modules                                  ////
1579
////                                                              ////
1580
////                                                              ////
1581
////  To Do:                                                      ////
1582
////   -                                                          ////
1583
////                                                              ////
1584
////  Author(s):                                                  ////
1585
////      - Michael Unneback, unneback@opencores.org              ////
1586
////        ORSoC AB                                              ////
1587
////                                                              ////
1588
//////////////////////////////////////////////////////////////////////
1589
////                                                              ////
1590
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1591
////                                                              ////
1592
//// This source file may be used and distributed without         ////
1593
//// restriction provided that this copyright statement is not    ////
1594
//// removed from the file and that any derivative work contains  ////
1595
//// the original copyright notice and the associated disclaimer. ////
1596
////                                                              ////
1597
//// This source file is free software; you can redistribute it   ////
1598
//// and/or modify it under the terms of the GNU Lesser General   ////
1599
//// Public License as published by the Free Software Foundation; ////
1600
//// either version 2.1 of the License, or (at your option) any   ////
1601
//// later version.                                               ////
1602
////                                                              ////
1603
//// This source is distributed in the hope that it will be       ////
1604
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1605
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1606
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1607
//// details.                                                     ////
1608
////                                                              ////
1609
//// You should have received a copy of the GNU Lesser General    ////
1610
//// Public License along with this source; if not, download it   ////
1611
//// from http://www.opencores.org/lgpl.shtml                     ////
1612
////                                                              ////
1613
//////////////////////////////////////////////////////////////////////
1614
// async wb3 - wb3 bridge
1615
`timescale 1ns/1ns
1616 18 unneback
module vl_wb3wb3_bridge (
1617 12 unneback
        // wishbone slave side
1618
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
1619
        // wishbone master side
1620
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
1621
input [31:0] wbs_dat_i;
1622
input [31:2] wbs_adr_i;
1623
input [3:0]  wbs_sel_i;
1624
input [1:0]  wbs_bte_i;
1625
input [2:0]  wbs_cti_i;
1626
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
1627
output [31:0] wbs_dat_o;
1628 14 unneback
output wbs_ack_o;
1629 12 unneback
input wbs_clk, wbs_rst;
1630
output [31:0] wbm_dat_o;
1631
output reg [31:2] wbm_adr_o;
1632
output [3:0]  wbm_sel_o;
1633
output reg [1:0]  wbm_bte_o;
1634
output reg [2:0]  wbm_cti_o;
1635 14 unneback
output reg wbm_we_o;
1636
output wbm_cyc_o;
1637 12 unneback
output wbm_stb_o;
1638
input [31:0]  wbm_dat_i;
1639
input wbm_ack_i;
1640
input wbm_clk, wbm_rst;
1641
parameter addr_width = 4;
1642
// bte
1643
parameter linear       = 2'b00;
1644
parameter wrap4        = 2'b01;
1645
parameter wrap8        = 2'b10;
1646
parameter wrap16       = 2'b11;
1647
// cti
1648
parameter classic      = 3'b000;
1649
parameter incburst     = 3'b010;
1650
parameter endofburst   = 3'b111;
1651
parameter wbs_adr  = 1'b0;
1652
parameter wbs_data = 1'b1;
1653 33 unneback
parameter wbm_adr0      = 2'b00;
1654
parameter wbm_adr1      = 2'b01;
1655
parameter wbm_data      = 2'b10;
1656
parameter wbm_data_wait = 2'b11;
1657 12 unneback
reg [1:0] wbs_bte_reg;
1658
reg wbs;
1659
wire wbs_eoc_alert, wbm_eoc_alert;
1660
reg wbs_eoc, wbm_eoc;
1661
reg [1:0] wbm;
1662 14 unneback
wire [1:16] wbs_count, wbm_count;
1663 12 unneback
wire [35:0] a_d, a_q, b_d, b_q;
1664
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
1665
reg a_rd_reg;
1666
wire b_rd_adr, b_rd_data;
1667 14 unneback
wire b_rd_data_reg;
1668
wire [35:0] temp;
1669 12 unneback
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
1670
always @ (posedge wbs_clk or posedge wbs_rst)
1671
if (wbs_rst)
1672
        wbs_eoc <= 1'b0;
1673
else
1674
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
1675
                wbs_eoc <= wbs_bte_i==linear;
1676
        else if (wbs_eoc_alert & (a_rd | a_wr))
1677
                wbs_eoc <= 1'b1;
1678 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
1679 12 unneback
    cnt0 (
1680
        .cke(wbs_ack_o),
1681
        .clear(wbs_eoc),
1682
        .q(wbs_count),
1683
        .rst(wbs_rst),
1684
        .clk(wbs_clk));
1685
always @ (posedge wbs_clk or posedge wbs_rst)
1686
if (wbs_rst)
1687
        wbs <= wbs_adr;
1688
else
1689
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
1690
                wbs <= wbs_data;
1691
        else if (wbs_eoc & wbs_ack_o)
1692
                wbs <= wbs_adr;
1693
// wbs FIFO
1694
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
1695
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
1696
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
1697
              1'b0;
1698
assign a_rd = !a_fifo_empty;
1699
always @ (posedge wbs_clk or posedge wbs_rst)
1700
if (wbs_rst)
1701
        a_rd_reg <= 1'b0;
1702
else
1703
        a_rd_reg <= a_rd;
1704
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
1705
assign wbs_dat_o = a_q[35:4];
1706
always @ (posedge wbs_clk or posedge wbs_rst)
1707
if (wbs_rst)
1708 13 unneback
        wbs_bte_reg <= 2'b00;
1709 12 unneback
else
1710 13 unneback
        wbs_bte_reg <= wbs_bte_i;
1711 12 unneback
// wbm FIFO
1712
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
1713
always @ (posedge wbm_clk or posedge wbm_rst)
1714
if (wbm_rst)
1715
        wbm_eoc <= 1'b0;
1716
else
1717
        if (wbm==wbm_adr0 & !b_fifo_empty)
1718
                wbm_eoc <= b_q[4:3] == linear;
1719
        else if (wbm_eoc_alert & wbm_ack_i)
1720
                wbm_eoc <= 1'b1;
1721
always @ (posedge wbm_clk or posedge wbm_rst)
1722
if (wbm_rst)
1723
        wbm <= wbm_adr0;
1724
else
1725 33 unneback
/*
1726 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
1727
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
1728
        (wbm==wbm_adr1 & !wbm_we_o) |
1729
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
1730
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
1731 33 unneback
*/
1732
    case (wbm)
1733
    wbm_adr0:
1734
        if (!b_fifo_empty)
1735
            wbm <= wbm_adr1;
1736
    wbm_adr1:
1737
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
1738
            wbm <= wbm_data;
1739
    wbm_data:
1740
        if (wbm_ack_i & wbm_eoc)
1741
            wbm <= wbm_adr0;
1742
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
1743
            wbm <= wbm_data_wait;
1744
    wbm_data_wait:
1745
        if (!b_fifo_empty)
1746
            wbm <= wbm_data;
1747
    endcase
1748 12 unneback
assign b_d = {wbm_dat_i,4'b1111};
1749
assign b_wr = !wbm_we_o & wbm_ack_i;
1750
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
1751
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
1752
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
1753 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
1754 12 unneback
                   1'b0;
1755
assign b_rd = b_rd_adr | b_rd_data;
1756 18 unneback
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
1757
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
1758 12 unneback
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
1759 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
1760 12 unneback
    cnt1 (
1761
        .cke(wbm_ack_i),
1762
        .clear(wbm_eoc),
1763
        .q(wbm_count),
1764
        .rst(wbm_rst),
1765
        .clk(wbm_clk));
1766 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
1767
assign wbm_stb_o = (wbm==wbm_data);
1768 12 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
1769
if (wbm_rst)
1770
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
1771
else begin
1772
        if (wbm==wbm_adr0 & !b_fifo_empty)
1773
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
1774
        else if (wbm_eoc_alert & wbm_ack_i)
1775
                wbm_cti_o <= endofburst;
1776
end
1777
//async_fifo_dw_simplex_top
1778
vl_fifo_2r2w_async_simplex
1779
# ( .data_width(36), .addr_width(addr_width))
1780
fifo (
1781
    // a side
1782
    .a_d(a_d),
1783
    .a_wr(a_wr),
1784
    .a_fifo_full(a_fifo_full),
1785
    .a_q(a_q),
1786
    .a_rd(a_rd),
1787
    .a_fifo_empty(a_fifo_empty),
1788
    .a_clk(wbs_clk),
1789
    .a_rst(wbs_rst),
1790
    // b side
1791
    .b_d(b_d),
1792
    .b_wr(b_wr),
1793
    .b_fifo_full(b_fifo_full),
1794
    .b_q(b_q),
1795
    .b_rd(b_rd),
1796
    .b_fifo_empty(b_fifo_empty),
1797
    .b_clk(wbm_clk),
1798
    .b_rst(wbm_rst)
1799
    );
1800
endmodule
1801 39 unneback
module vl_wb3_arbiter_type1 (
1802
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
1803
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
1804
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
1805
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
1806
    wb_clk, wb_rst
1807
);
1808
parameter nr_of_ports = 3;
1809
parameter adr_size = 26;
1810
parameter adr_lo   = 2;
1811
parameter dat_size = 32;
1812
parameter sel_size = dat_size/8;
1813
localparam aw = (adr_size - adr_lo) * nr_of_ports;
1814
localparam dw = dat_size * nr_of_ports;
1815
localparam sw = sel_size * nr_of_ports;
1816
localparam cw = 3 * nr_of_ports;
1817
localparam bw = 2 * nr_of_ports;
1818
input  [dw-1:0] wbm_dat_o;
1819
input  [aw-1:0] wbm_adr_o;
1820
input  [sw-1:0] wbm_sel_o;
1821
input  [cw-1:0] wbm_cti_o;
1822
input  [bw-1:0] wbm_bte_o;
1823
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
1824
output [dw-1:0] wbm_dat_i;
1825
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
1826
output [dat_size-1:0] wbs_dat_i;
1827
output [adr_size-1:adr_lo] wbs_adr_i;
1828
output [sel_size-1:0] wbs_sel_i;
1829
output [2:0] wbs_cti_i;
1830
output [1:0] wbs_bte_i;
1831
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
1832
input  [dat_size-1:0] wbs_dat_o;
1833
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
1834
input wb_clk, wb_rst;
1835 44 unneback
reg  [nr_of_ports-1:0] select;
1836 39 unneback
wire [nr_of_ports-1:0] state;
1837
wire [nr_of_ports-1:0] eoc; // end-of-cycle
1838
wire [nr_of_ports-1:0] sel;
1839
wire idle;
1840
genvar i;
1841
assign idle = !(|state);
1842
generate
1843
if (nr_of_ports == 2) begin
1844
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
1845
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
1846 44 unneback
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
1847
    always @ (idle or wbm_cyc_o)
1848
    if (idle)
1849
        casex (wbm_cyc_o)
1850
        2'b1x : select = 2'b10;
1851
        2'b01 : select = 2'b01;
1852
        default : select = {nr_of_ports{1'b0}};
1853
        endcase
1854
    else
1855
        select = {nr_of_ports{1'b0}};
1856 39 unneback
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
1857
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
1858
end
1859
endgenerate
1860
generate
1861
if (nr_of_ports == 3) begin
1862
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
1863
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
1864 44 unneback
    always @ (idle or wbm_cyc_o)
1865
    if (idle)
1866
        casex (wbm_cyc_o)
1867
        3'b1xx : select = 3'b100;
1868
        3'b01x : select = 3'b010;
1869
        3'b001 : select = 3'b001;
1870
        default : select = {nr_of_ports{1'b0}};
1871
        endcase
1872
    else
1873
        select = {nr_of_ports{1'b0}};
1874
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
1875 39 unneback
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
1876
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
1877
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
1878
end
1879
endgenerate
1880
generate
1881 44 unneback
if (nr_of_ports == 4) begin
1882
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
1883
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
1884
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
1885
    always @ (idle or wbm_cyc_o)
1886
    if (idle)
1887
        casex (wbm_cyc_o)
1888
        4'b1xxx : select = 4'b1000;
1889
        4'b01xx : select = 4'b0100;
1890
        4'b001x : select = 4'b0010;
1891
        4'b0001 : select = 4'b0001;
1892
        default : select = {nr_of_ports{1'b0}};
1893
        endcase
1894
    else
1895
        select = {nr_of_ports{1'b0}};
1896
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
1897
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
1898
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
1899
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
1900
end
1901
endgenerate
1902
generate
1903
if (nr_of_ports == 5) begin
1904
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
1905
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
1906
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
1907
    always @ (idle or wbm_cyc_o)
1908
    if (idle)
1909
        casex (wbm_cyc_o)
1910
        5'b1xxxx : select = 5'b10000;
1911
        5'b01xxx : select = 5'b01000;
1912
        5'b001xx : select = 5'b00100;
1913
        5'b0001x : select = 5'b00010;
1914
        5'b00001 : select = 5'b00001;
1915
        default : select = {nr_of_ports{1'b0}};
1916
        endcase
1917
    else
1918
        select = {nr_of_ports{1'b0}};
1919
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
1920
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
1921
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
1922
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
1923
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
1924
end
1925
endgenerate
1926
generate
1927 39 unneback
for (i=0;i<nr_of_ports;i=i+1) begin
1928
    vl_spr sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
1929
end
1930
endgenerate
1931
    assign sel = select | state;
1932
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
1933
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
1934
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
1935
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
1936
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
1937
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
1938
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
1939
    assign wbs_cyc_i = |sel;
1940
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
1941
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
1942
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
1943
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
1944
endmodule
1945 17 unneback
// WB ROM
1946 18 unneback
module vl_wb_boot_rom (
1947 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
1948 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
1949
    parameter adr_hi = 31;
1950
    parameter adr_lo = 28;
1951
    parameter adr_sel = 4'hf;
1952
    parameter addr_width = 5;
1953 33 unneback
/*
1954 17 unneback
`ifndef BOOT_ROM
1955
`define BOOT_ROM "boot_rom.v"
1956
`endif
1957 33 unneback
*/
1958 18 unneback
    input [adr_hi:2]    wb_adr_i;
1959
    input               wb_stb_i;
1960
    input               wb_cyc_i;
1961
    output [31:0]        wb_dat_o;
1962
    output              wb_ack_o;
1963
    output              hit_o;
1964
    input               wb_clk;
1965
    input               wb_rst;
1966
    wire hit;
1967
    reg [31:0] wb_dat;
1968
    reg wb_ack;
1969
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
1970 17 unneback
always @ (posedge wb_clk or posedge wb_rst)
1971
    if (wb_rst)
1972 18 unneback
        wb_dat <= 32'h15000000;
1973 17 unneback
    else
1974 18 unneback
         case (wb_adr_i[addr_width-1:2])
1975 33 unneback
`ifdef BOOT_ROM
1976 17 unneback
`include `BOOT_ROM
1977 33 unneback
`endif
1978 17 unneback
           /*
1979
            // Zero r0 and jump to 0x00000100
1980 18 unneback
 
1981
            1 : wb_dat <= 32'hA8200000;
1982
            2 : wb_dat <= 32'hA8C00100;
1983
            3 : wb_dat <= 32'h44003000;
1984
            4 : wb_dat <= 32'h15000000;
1985 17 unneback
            */
1986
           default:
1987 18 unneback
             wb_dat <= 32'h00000000;
1988 17 unneback
         endcase // case (wb_adr_i)
1989
always @ (posedge wb_clk or posedge wb_rst)
1990
    if (wb_rst)
1991 18 unneback
        wb_ack <= 1'b0;
1992 17 unneback
    else
1993 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
1994
assign hit_o = hit;
1995
assign wb_dat_o = wb_dat & {32{wb_ack}};
1996
assign wb_ack_o = wb_ack;
1997 17 unneback
endmodule
1998 32 unneback
module vl_wb_dpram (
1999
        // wishbone slave side a
2000
        wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
2001
        wbsa_clk, wbsa_rst,
2002
        // wishbone slave side a
2003
        wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
2004
        wbsb_clk, wbsb_rst);
2005
parameter data_width = 32;
2006
parameter addr_width = 8;
2007
parameter dat_o_mask_a = 1;
2008
parameter dat_o_mask_b = 1;
2009
input [31:0] wbsa_dat_i;
2010
input [addr_width-1:2] wbsa_adr_i;
2011
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
2012
output [31:0] wbsa_dat_o;
2013
output wbsa_ack_o;
2014
input wbsa_clk, wbsa_rst;
2015
input [31:0] wbsb_dat_i;
2016
input [addr_width-1:2] wbsb_adr_i;
2017
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
2018
output [31:0] wbsb_dat_o;
2019
output wbsb_ack_o;
2020
input wbsb_clk, wbsb_rst;
2021
wire wbsa_dat_tmp, wbsb_dat_tmp;
2022
vl_dpram_2r2w # (
2023 33 unneback
    .data_width(data_width), .addr_width(addr_width) )
2024 32 unneback
dpram0(
2025
    .d_a(wbsa_dat_i),
2026
    .q_a(wbsa_dat_tmp),
2027
    .adr_a(wbsa_adr_i),
2028
    .we_a(wbsa_we_i),
2029
    .clk_a(wbsa_clk),
2030
    .d_b(wbsb_dat_i),
2031
    .q_b(wbsb_dat_tmp),
2032
    .adr_b(wbsb_adr_i),
2033
    .we_b(wbsb_we_i),
2034
    .clk_b(wbsb_clk) );
2035 33 unneback
generate if (dat_o_mask_a==1)
2036 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
2037
endgenerate
2038 33 unneback
generate if (dat_o_mask_a==0)
2039 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp;
2040
endgenerate
2041 33 unneback
generate if (dat_o_mask_b==1)
2042 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
2043
endgenerate
2044 33 unneback
generate if (dat_o_mask_b==0)
2045 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp;
2046
endgenerate
2047
vl_spr ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
2048
vl_spr ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
2049
endmodule
2050 18 unneback
//////////////////////////////////////////////////////////////////////
2051
////                                                              ////
2052
////  Arithmetic functions                                        ////
2053
////                                                              ////
2054
////  Description                                                 ////
2055
////  Arithmetic functions for ALU and DSP                        ////
2056
////                                                              ////
2057
////                                                              ////
2058
////  To Do:                                                      ////
2059
////   -                                                          ////
2060
////                                                              ////
2061
////  Author(s):                                                  ////
2062
////      - Michael Unneback, unneback@opencores.org              ////
2063
////        ORSoC AB                                              ////
2064
////                                                              ////
2065
//////////////////////////////////////////////////////////////////////
2066
////                                                              ////
2067
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2068
////                                                              ////
2069
//// This source file may be used and distributed without         ////
2070
//// restriction provided that this copyright statement is not    ////
2071
//// removed from the file and that any derivative work contains  ////
2072
//// the original copyright notice and the associated disclaimer. ////
2073
////                                                              ////
2074
//// This source file is free software; you can redistribute it   ////
2075
//// and/or modify it under the terms of the GNU Lesser General   ////
2076
//// Public License as published by the Free Software Foundation; ////
2077
//// either version 2.1 of the License, or (at your option) any   ////
2078
//// later version.                                               ////
2079
////                                                              ////
2080
//// This source is distributed in the hope that it will be       ////
2081
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2082
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2083
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2084
//// details.                                                     ////
2085
////                                                              ////
2086
//// You should have received a copy of the GNU Lesser General    ////
2087
//// Public License along with this source; if not, download it   ////
2088
//// from http://www.opencores.org/lgpl.shtml                     ////
2089
////                                                              ////
2090
//////////////////////////////////////////////////////////////////////
2091
// signed multiplication
2092
module vl_mults (a,b,p);
2093
parameter operand_a_width = 18;
2094
parameter operand_b_width = 18;
2095
parameter result_hi = 35;
2096
parameter result_lo = 0;
2097
input [operand_a_width-1:0] a;
2098
input [operand_b_width-1:0] b;
2099
output [result_hi:result_lo] p;
2100
wire signed [operand_a_width-1:0] ai;
2101
wire signed [operand_b_width-1:0] bi;
2102
wire signed [operand_a_width+operand_b_width-1:0] result;
2103
    assign ai = a;
2104
    assign bi = b;
2105
    assign result = ai * bi;
2106
    assign p = result[result_hi:result_lo];
2107
endmodule
2108
module vl_mults18x18 (a,b,p);
2109
input [17:0] a,b;
2110
output [35:0] p;
2111
vl_mult
2112
    # (.operand_a_width(18), .operand_b_width(18))
2113
    mult0 (.a(a), .b(b), .p(p));
2114
endmodule
2115
// unsigned multiplication
2116
module vl_mult (a,b,p);
2117
parameter operand_a_width = 18;
2118
parameter operand_b_width = 18;
2119
parameter result_hi = 35;
2120
parameter result_lo = 0;
2121
input [operand_a_width-1:0] a;
2122
input [operand_b_width-1:0] b;
2123
output [result_hi:result_hi] p;
2124
wire [operand_a_width+operand_b_width-1:0] result;
2125
    assign result = a * b;
2126
    assign p = result[result_hi:result_lo];
2127
endmodule
2128
// shift unit
2129
// supporting the following shift functions
2130
//   SLL
2131
//   SRL
2132
//   SRA
2133
module vl_shift_unit_32( din, s, dout, opcode);
2134
input [31:0] din; // data in operand
2135
input [4:0] s; // shift operand
2136
input [1:0] opcode;
2137
output [31:0] dout;
2138
parameter opcode_sll = 2'b00;
2139
//parameter opcode_srl = 2'b01;
2140
parameter opcode_sra = 2'b10;
2141
//parameter opcode_ror = 2'b11;
2142
wire sll, sra;
2143
assign sll = opcode == opcode_sll;
2144
assign sra = opcode == opcode_sra;
2145
wire [15:1] s1;
2146
wire [3:0] sign;
2147
wire [7:0] tmp [0:3];
2148
// first stage is multiplier based
2149
// shift operand as fractional 8.7
2150
assign s1[15] = sll & s[2:0]==3'd7;
2151
assign s1[14] = sll & s[2:0]==3'd6;
2152
assign s1[13] = sll & s[2:0]==3'd5;
2153
assign s1[12] = sll & s[2:0]==3'd4;
2154
assign s1[11] = sll & s[2:0]==3'd3;
2155
assign s1[10] = sll & s[2:0]==3'd2;
2156
assign s1[ 9] = sll & s[2:0]==3'd1;
2157
assign s1[ 8] = s[2:0]==3'd0;
2158
assign s1[ 7] = !sll & s[2:0]==3'd1;
2159
assign s1[ 6] = !sll & s[2:0]==3'd2;
2160
assign s1[ 5] = !sll & s[2:0]==3'd3;
2161
assign s1[ 4] = !sll & s[2:0]==3'd4;
2162
assign s1[ 3] = !sll & s[2:0]==3'd5;
2163
assign s1[ 2] = !sll & s[2:0]==3'd6;
2164
assign s1[ 1] = !sll & s[2:0]==3'd7;
2165
assign sign[3] = din[31] & sra;
2166
assign sign[2] = sign[3] & (&din[31:24]);
2167
assign sign[1] = sign[2] & (&din[23:16]);
2168
assign sign[0] = sign[1] & (&din[15:8]);
2169
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
2170
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
2171
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
2172
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
2173
// second stage is multiplexer based
2174
// shift on byte level
2175
// mux byte 3
2176
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
2177
                     (sll & s[4:3]==2'b01) ? tmp[2] :
2178
                     (sll & s[4:3]==2'b10) ? tmp[1] :
2179
                     (sll & s[4:3]==2'b11) ? tmp[0] :
2180
                     {8{sign[3]}};
2181
// mux byte 2
2182
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
2183
                     (sll & s[4:3]==2'b01) ? tmp[1] :
2184
                     (sll & s[4:3]==2'b10) ? tmp[0] :
2185
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
2186
                     (s[4:3]==2'b01) ? tmp[3] :
2187
                     {8{sign[3]}};
2188
// mux byte 1
2189
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
2190
                     (sll & s[4:3]==2'b01) ? tmp[0] :
2191
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
2192
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
2193
                     (s[4:3]==2'b01) ? tmp[2] :
2194
                     (s[4:3]==2'b10) ? tmp[3] :
2195
                     {8{sign[3]}};
2196
// mux byte 0
2197
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
2198
                     (sll) ?  {8{1'b0}}:
2199
                     (s[4:3]==2'b01) ? tmp[1] :
2200
                     (s[4:3]==2'b10) ? tmp[2] :
2201
                     tmp[3];
2202
endmodule
2203
// logic unit
2204
// supporting the following logic functions
2205
//    a and b
2206
//    a or  b
2207
//    a xor b
2208
//    not b
2209
module vl_logic_unit( a, b, result, opcode);
2210
parameter width = 32;
2211
parameter opcode_and = 2'b00;
2212
parameter opcode_or  = 2'b01;
2213
parameter opcode_xor = 2'b10;
2214
input [width-1:0] a,b;
2215
output [width-1:0] result;
2216
input [1:0] opcode;
2217
assign result = (opcode==opcode_and) ? a & b :
2218
                (opcode==opcode_or)  ? a | b :
2219
                (opcode==opcode_xor) ? a ^ b :
2220
                b;
2221
endmodule
2222
module vl_arith_unit ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
2223
parameter width = 32;
2224
parameter opcode_add = 1'b0;
2225
parameter opcode_sub = 1'b1;
2226
input [width-1:0] a,b;
2227
input c_in, add_sub, sign;
2228
output [width-1:0] result;
2229
output c_out, z, ovfl;
2230
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
2231
assign z = (result=={width{1'b0}});
2232
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
2233
               (~a[width-1] & ~b[width-1] &  result[width-1]);
2234
endmodule

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