1 |
60 |
unneback |
// default SYN_KEEP definition
|
2 |
6 |
unneback |
//////////////////////////////////////////////////////////////////////
|
3 |
|
|
//// ////
|
4 |
|
|
//// Versatile library, clock and reset ////
|
5 |
|
|
//// ////
|
6 |
|
|
//// Description ////
|
7 |
|
|
//// Logic related to clock and reset ////
|
8 |
|
|
//// ////
|
9 |
|
|
//// ////
|
10 |
|
|
//// To Do: ////
|
11 |
|
|
//// - add more different registers ////
|
12 |
|
|
//// ////
|
13 |
|
|
//// Author(s): ////
|
14 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
15 |
|
|
//// ORSoC AB ////
|
16 |
|
|
//// ////
|
17 |
|
|
//////////////////////////////////////////////////////////////////////
|
18 |
|
|
//// ////
|
19 |
|
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
20 |
|
|
//// ////
|
21 |
|
|
//// This source file may be used and distributed without ////
|
22 |
|
|
//// restriction provided that this copyright statement is not ////
|
23 |
|
|
//// removed from the file and that any derivative work contains ////
|
24 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
25 |
|
|
//// ////
|
26 |
|
|
//// This source file is free software; you can redistribute it ////
|
27 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
28 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
29 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
30 |
|
|
//// later version. ////
|
31 |
|
|
//// ////
|
32 |
|
|
//// This source is distributed in the hope that it will be ////
|
33 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
34 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
35 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
36 |
|
|
//// details. ////
|
37 |
|
|
//// ////
|
38 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
39 |
|
|
//// Public License along with this source; if not, download it ////
|
40 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
41 |
|
|
//// ////
|
42 |
|
|
//////////////////////////////////////////////////////////////////////
|
43 |
48 |
unneback |
`timescale 1 ns/100 ps
|
44 |
6 |
unneback |
// Global buffer
|
45 |
|
|
// usage:
|
46 |
|
|
// use to enable global buffers for high fan out signals such as clock and reset
|
47 |
|
|
// Version: 8.4 8.4.0.33
|
48 |
|
|
module gbuf(GL,CLK);
|
49 |
|
|
output GL;
|
50 |
|
|
input CLK;
|
51 |
|
|
wire GND;
|
52 |
|
|
GND GND_1_net(.Y(GND));
|
53 |
|
|
CLKDLY Inst1(.CLK(CLK), .GL(GL), .DLYGL0(GND), .DLYGL1(GND),
|
54 |
|
|
.DLYGL2(GND), .DLYGL3(GND), .DLYGL4(GND)) /* synthesis black_box */;
|
55 |
|
|
endmodule
|
56 |
|
|
`timescale 1 ns/1 ns
|
57 |
|
|
module vl_gbuf ( i, o);
|
58 |
|
|
input i;
|
59 |
|
|
output o;
|
60 |
|
|
`ifdef SIM_GBUF
|
61 |
|
|
assign o=i;
|
62 |
|
|
`else
|
63 |
|
|
gbuf gbuf_i0 ( .CLK(i), .GL(o));
|
64 |
|
|
`endif
|
65 |
|
|
endmodule
|
66 |
|
|
//ACTEL
|
67 |
|
|
// sync reset
|
68 |
17 |
unneback |
// input active lo async reset, normally from external reset generator and/or switch
|
69 |
6 |
unneback |
// output active high global reset sync with two DFFs
|
70 |
|
|
`timescale 1 ns/100 ps
|
71 |
|
|
module vl_sync_rst ( rst_n_i, rst_o, clk);
|
72 |
|
|
input rst_n_i, clk;
|
73 |
|
|
output rst_o;
|
74 |
18 |
unneback |
reg [1:0] tmp;
|
75 |
6 |
unneback |
always @ (posedge clk or negedge rst_n_i)
|
76 |
|
|
if (!rst_n_i)
|
77 |
17 |
unneback |
tmp <= 2'b11;
|
78 |
6 |
unneback |
else
|
79 |
33 |
unneback |
tmp <= {1'b0,tmp[1]};
|
80 |
17 |
unneback |
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
|
81 |
6 |
unneback |
endmodule
|
82 |
|
|
// vl_pll
|
83 |
32 |
unneback |
///////////////////////////////////////////////////////////////////////////////
|
84 |
17 |
unneback |
`timescale 1 ps/1 ps
|
85 |
6 |
unneback |
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
|
86 |
|
|
parameter index = 0;
|
87 |
|
|
parameter number_of_clk = 1;
|
88 |
17 |
unneback |
parameter period_time_0 = 20000;
|
89 |
|
|
parameter period_time_1 = 20000;
|
90 |
|
|
parameter period_time_2 = 20000;
|
91 |
|
|
parameter lock_delay = 2000000;
|
92 |
6 |
unneback |
input clk_i, rst_n_i;
|
93 |
|
|
output lock;
|
94 |
|
|
output reg [0:number_of_clk-1] clk_o;
|
95 |
|
|
output [0:number_of_clk-1] rst_o;
|
96 |
|
|
`ifdef SIM_PLL
|
97 |
|
|
always
|
98 |
|
|
#((period_time_0)/2) clk_o[0] <= (!rst_n_i) ? 0 : ~clk_o[0];
|
99 |
|
|
generate if (number_of_clk > 1)
|
100 |
|
|
always
|
101 |
|
|
#((period_time_1)/2) clk_o[1] <= (!rst_n_i) ? 0 : ~clk_o[1];
|
102 |
|
|
endgenerate
|
103 |
|
|
generate if (number_of_clk > 2)
|
104 |
|
|
always
|
105 |
|
|
#((period_time_2)/2) clk_o[2] <= (!rst_n_i) ? 0 : ~clk_o[2];
|
106 |
|
|
endgenerate
|
107 |
|
|
genvar i;
|
108 |
|
|
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
|
109 |
|
|
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
|
110 |
|
|
end
|
111 |
|
|
endgenerate
|
112 |
|
|
assign #lock_delay lock = rst_n_i;
|
113 |
|
|
endmodule
|
114 |
|
|
`else
|
115 |
|
|
generate if (number_of_clk==1 & index==0) begin
|
116 |
|
|
pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
|
117 |
|
|
end
|
118 |
|
|
endgenerate // index==0
|
119 |
|
|
generate if (number_of_clk==1 & index==1) begin
|
120 |
|
|
pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
|
121 |
|
|
end
|
122 |
|
|
endgenerate // index==1
|
123 |
|
|
generate if (number_of_clk==1 & index==2) begin
|
124 |
|
|
pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
|
125 |
|
|
end
|
126 |
|
|
endgenerate // index==2
|
127 |
|
|
generate if (number_of_clk==1 & index==3) begin
|
128 |
|
|
pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]));
|
129 |
|
|
end
|
130 |
|
|
endgenerate // index==0
|
131 |
|
|
generate if (number_of_clk==2 & index==0) begin
|
132 |
|
|
pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
|
133 |
|
|
end
|
134 |
|
|
endgenerate // index==0
|
135 |
|
|
generate if (number_of_clk==2 & index==1) begin
|
136 |
|
|
pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
|
137 |
|
|
end
|
138 |
|
|
endgenerate // index==1
|
139 |
|
|
generate if (number_of_clk==2 & index==2) begin
|
140 |
|
|
pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
|
141 |
|
|
end
|
142 |
|
|
endgenerate // index==2
|
143 |
|
|
generate if (number_of_clk==2 & index==3) begin
|
144 |
|
|
pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]));
|
145 |
|
|
end
|
146 |
|
|
endgenerate // index==0
|
147 |
|
|
generate if (number_of_clk==3 & index==0) begin
|
148 |
|
|
pll0 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
|
149 |
|
|
end
|
150 |
|
|
endgenerate // index==0
|
151 |
|
|
generate if (number_of_clk==3 & index==1) begin
|
152 |
|
|
pll1 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
|
153 |
|
|
end
|
154 |
|
|
endgenerate // index==1
|
155 |
|
|
generate if (number_of_clk==3 & index==2) begin
|
156 |
|
|
pll2 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
|
157 |
|
|
end
|
158 |
|
|
endgenerate // index==2
|
159 |
|
|
generate if (number_of_clk==3 & index==3) begin
|
160 |
|
|
pll3 pll_i0 (.POWERDOWN(1'b1), .CLKA(clk_i), .LOCK(lock), .GLA(clk_o[0]), .GLB(clk_o[1]), .GLC(clk_o[2]));
|
161 |
|
|
end
|
162 |
|
|
endgenerate // index==0
|
163 |
|
|
genvar i;
|
164 |
|
|
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
|
165 |
40 |
unneback |
vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o), .clk(clk_o[i]));
|
166 |
6 |
unneback |
end
|
167 |
|
|
endgenerate
|
168 |
|
|
endmodule
|
169 |
|
|
`endif
|
170 |
32 |
unneback |
///////////////////////////////////////////////////////////////////////////////
|
171 |
6 |
unneback |
//actel
|
172 |
|
|
//////////////////////////////////////////////////////////////////////
|
173 |
|
|
//// ////
|
174 |
|
|
//// Versatile library, registers ////
|
175 |
|
|
//// ////
|
176 |
|
|
//// Description ////
|
177 |
|
|
//// Different type of registers ////
|
178 |
|
|
//// ////
|
179 |
|
|
//// ////
|
180 |
|
|
//// To Do: ////
|
181 |
|
|
//// - add more different registers ////
|
182 |
|
|
//// ////
|
183 |
|
|
//// Author(s): ////
|
184 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
185 |
|
|
//// ORSoC AB ////
|
186 |
|
|
//// ////
|
187 |
|
|
//////////////////////////////////////////////////////////////////////
|
188 |
|
|
//// ////
|
189 |
|
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
190 |
|
|
//// ////
|
191 |
|
|
//// This source file may be used and distributed without ////
|
192 |
|
|
//// restriction provided that this copyright statement is not ////
|
193 |
|
|
//// removed from the file and that any derivative work contains ////
|
194 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
195 |
|
|
//// ////
|
196 |
|
|
//// This source file is free software; you can redistribute it ////
|
197 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
198 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
199 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
200 |
|
|
//// later version. ////
|
201 |
|
|
//// ////
|
202 |
|
|
//// This source is distributed in the hope that it will be ////
|
203 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
204 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
205 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
206 |
|
|
//// details. ////
|
207 |
|
|
//// ////
|
208 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
209 |
|
|
//// Public License along with this source; if not, download it ////
|
210 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
211 |
|
|
//// ////
|
212 |
|
|
//////////////////////////////////////////////////////////////////////
|
213 |
18 |
unneback |
module vl_dff ( d, q, clk, rst);
|
214 |
6 |
unneback |
parameter width = 1;
|
215 |
|
|
parameter reset_value = 0;
|
216 |
|
|
input [width-1:0] d;
|
217 |
|
|
input clk, rst;
|
218 |
|
|
output reg [width-1:0] q;
|
219 |
|
|
always @ (posedge clk or posedge rst)
|
220 |
|
|
if (rst)
|
221 |
|
|
q <= reset_value;
|
222 |
|
|
else
|
223 |
|
|
q <= d;
|
224 |
|
|
endmodule
|
225 |
18 |
unneback |
module vl_dff_array ( d, q, clk, rst);
|
226 |
6 |
unneback |
parameter width = 1;
|
227 |
|
|
parameter depth = 2;
|
228 |
|
|
parameter reset_value = 1'b0;
|
229 |
|
|
input [width-1:0] d;
|
230 |
|
|
input clk, rst;
|
231 |
|
|
output [width-1:0] q;
|
232 |
|
|
reg [0:depth-1] q_tmp [width-1:0];
|
233 |
|
|
integer i;
|
234 |
|
|
always @ (posedge clk or posedge rst)
|
235 |
|
|
if (rst) begin
|
236 |
|
|
for (i=0;i<depth;i=i+1)
|
237 |
|
|
q_tmp[i] <= {width{reset_value}};
|
238 |
|
|
end else begin
|
239 |
|
|
q_tmp[0] <= d;
|
240 |
|
|
for (i=1;i<depth;i=i+1)
|
241 |
|
|
q_tmp[i] <= q_tmp[i-1];
|
242 |
|
|
end
|
243 |
|
|
assign q = q_tmp[depth-1];
|
244 |
|
|
endmodule
|
245 |
18 |
unneback |
module vl_dff_ce ( d, ce, q, clk, rst);
|
246 |
6 |
unneback |
parameter width = 1;
|
247 |
|
|
parameter reset_value = 0;
|
248 |
|
|
input [width-1:0] d;
|
249 |
|
|
input ce, clk, rst;
|
250 |
|
|
output reg [width-1:0] q;
|
251 |
|
|
always @ (posedge clk or posedge rst)
|
252 |
|
|
if (rst)
|
253 |
|
|
q <= reset_value;
|
254 |
|
|
else
|
255 |
|
|
if (ce)
|
256 |
|
|
q <= d;
|
257 |
|
|
endmodule
|
258 |
18 |
unneback |
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
|
259 |
8 |
unneback |
parameter width = 1;
|
260 |
|
|
parameter reset_value = 0;
|
261 |
|
|
input [width-1:0] d;
|
262 |
10 |
unneback |
input ce, clear, clk, rst;
|
263 |
8 |
unneback |
output reg [width-1:0] q;
|
264 |
|
|
always @ (posedge clk or posedge rst)
|
265 |
|
|
if (rst)
|
266 |
|
|
q <= reset_value;
|
267 |
|
|
else
|
268 |
|
|
if (ce)
|
269 |
|
|
if (clear)
|
270 |
|
|
q <= {width{1'b0}};
|
271 |
|
|
else
|
272 |
|
|
q <= d;
|
273 |
|
|
endmodule
|
274 |
24 |
unneback |
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
|
275 |
|
|
parameter width = 1;
|
276 |
|
|
parameter reset_value = 0;
|
277 |
|
|
input [width-1:0] d;
|
278 |
|
|
input ce, set, clk, rst;
|
279 |
|
|
output reg [width-1:0] q;
|
280 |
|
|
always @ (posedge clk or posedge rst)
|
281 |
|
|
if (rst)
|
282 |
|
|
q <= reset_value;
|
283 |
|
|
else
|
284 |
|
|
if (ce)
|
285 |
|
|
if (set)
|
286 |
|
|
q <= {width{1'b1}};
|
287 |
|
|
else
|
288 |
|
|
q <= d;
|
289 |
|
|
endmodule
|
290 |
29 |
unneback |
module vl_spr ( sp, r, q, clk, rst);
|
291 |
64 |
unneback |
//parameter width = 1;
|
292 |
|
|
parameter reset_value = 1'b0;
|
293 |
29 |
unneback |
input sp, r;
|
294 |
|
|
output reg q;
|
295 |
|
|
input clk, rst;
|
296 |
|
|
always @ (posedge clk or posedge rst)
|
297 |
|
|
if (rst)
|
298 |
|
|
q <= reset_value;
|
299 |
|
|
else
|
300 |
|
|
if (sp)
|
301 |
|
|
q <= 1'b1;
|
302 |
|
|
else if (r)
|
303 |
|
|
q <= 1'b0;
|
304 |
|
|
endmodule
|
305 |
|
|
module vl_srp ( s, rp, q, clk, rst);
|
306 |
|
|
parameter width = 1;
|
307 |
|
|
parameter reset_value = 0;
|
308 |
|
|
input s, rp;
|
309 |
|
|
output reg q;
|
310 |
|
|
input clk, rst;
|
311 |
|
|
always @ (posedge clk or posedge rst)
|
312 |
|
|
if (rst)
|
313 |
|
|
q <= reset_value;
|
314 |
|
|
else
|
315 |
|
|
if (rp)
|
316 |
|
|
q <= 1'b0;
|
317 |
|
|
else if (s)
|
318 |
|
|
q <= 1'b1;
|
319 |
|
|
endmodule
|
320 |
18 |
unneback |
module vl_dff_sr ( aclr, aset, clock, data, q);
|
321 |
6 |
unneback |
input aclr;
|
322 |
|
|
input aset;
|
323 |
|
|
input clock;
|
324 |
|
|
input data;
|
325 |
|
|
output reg q;
|
326 |
|
|
always @ (posedge clock or posedge aclr or posedge aset)
|
327 |
|
|
if (aclr)
|
328 |
|
|
q <= 1'b0;
|
329 |
|
|
else if (aset)
|
330 |
|
|
q <= 1'b1;
|
331 |
|
|
else
|
332 |
|
|
q <= data;
|
333 |
|
|
endmodule
|
334 |
|
|
// LATCH
|
335 |
|
|
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
|
336 |
40 |
unneback |
module vl_latch ( d, le, q, clk);
|
337 |
6 |
unneback |
input d, le;
|
338 |
48 |
unneback |
input clk;
|
339 |
|
|
always @ (le or d)
|
340 |
60 |
unneback |
if (le)
|
341 |
48 |
unneback |
d <= q;
|
342 |
6 |
unneback |
endmodule
|
343 |
18 |
unneback |
module vl_shreg ( d, q, clk, rst);
|
344 |
17 |
unneback |
parameter depth = 10;
|
345 |
|
|
input d;
|
346 |
|
|
output q;
|
347 |
|
|
input clk, rst;
|
348 |
|
|
reg [1:depth] dffs;
|
349 |
|
|
always @ (posedge clk or posedge rst)
|
350 |
|
|
if (rst)
|
351 |
|
|
dffs <= {depth{1'b0}};
|
352 |
|
|
else
|
353 |
|
|
dffs <= {d,dffs[1:depth-1]};
|
354 |
|
|
assign q = dffs[depth];
|
355 |
|
|
endmodule
|
356 |
18 |
unneback |
module vl_shreg_ce ( d, ce, q, clk, rst);
|
357 |
17 |
unneback |
parameter depth = 10;
|
358 |
|
|
input d, ce;
|
359 |
|
|
output q;
|
360 |
|
|
input clk, rst;
|
361 |
|
|
reg [1:depth] dffs;
|
362 |
|
|
always @ (posedge clk or posedge rst)
|
363 |
|
|
if (rst)
|
364 |
|
|
dffs <= {depth{1'b0}};
|
365 |
|
|
else
|
366 |
|
|
if (ce)
|
367 |
|
|
dffs <= {d,dffs[1:depth-1]};
|
368 |
|
|
assign q = dffs[depth];
|
369 |
|
|
endmodule
|
370 |
18 |
unneback |
module vl_delay ( d, q, clk, rst);
|
371 |
15 |
unneback |
parameter depth = 10;
|
372 |
|
|
input d;
|
373 |
|
|
output q;
|
374 |
|
|
input clk, rst;
|
375 |
|
|
reg [1:depth] dffs;
|
376 |
|
|
always @ (posedge clk or posedge rst)
|
377 |
|
|
if (rst)
|
378 |
|
|
dffs <= {depth{1'b0}};
|
379 |
|
|
else
|
380 |
|
|
dffs <= {d,dffs[1:depth-1]};
|
381 |
|
|
assign q = dffs[depth];
|
382 |
|
|
endmodule
|
383 |
18 |
unneback |
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
|
384 |
17 |
unneback |
parameter depth = 10;
|
385 |
|
|
input d;
|
386 |
|
|
output q, emptyflag;
|
387 |
|
|
input clk, rst;
|
388 |
|
|
reg [1:depth] dffs;
|
389 |
|
|
always @ (posedge clk or posedge rst)
|
390 |
|
|
if (rst)
|
391 |
|
|
dffs <= {depth{1'b0}};
|
392 |
|
|
else
|
393 |
|
|
dffs <= {d,dffs[1:depth-1]};
|
394 |
|
|
assign q = dffs[depth];
|
395 |
|
|
assign emptyflag = !(|dffs);
|
396 |
|
|
endmodule
|
397 |
6 |
unneback |
//////////////////////////////////////////////////////////////////////
|
398 |
|
|
//// ////
|
399 |
18 |
unneback |
//// Logic functions ////
|
400 |
|
|
//// ////
|
401 |
|
|
//// Description ////
|
402 |
|
|
//// Logic functions such as multiplexers ////
|
403 |
|
|
//// ////
|
404 |
|
|
//// ////
|
405 |
|
|
//// To Do: ////
|
406 |
|
|
//// - ////
|
407 |
|
|
//// ////
|
408 |
|
|
//// Author(s): ////
|
409 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
410 |
|
|
//// ORSoC AB ////
|
411 |
|
|
//// ////
|
412 |
|
|
//////////////////////////////////////////////////////////////////////
|
413 |
|
|
//// ////
|
414 |
|
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
415 |
|
|
//// ////
|
416 |
|
|
//// This source file may be used and distributed without ////
|
417 |
|
|
//// restriction provided that this copyright statement is not ////
|
418 |
|
|
//// removed from the file and that any derivative work contains ////
|
419 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
420 |
|
|
//// ////
|
421 |
|
|
//// This source file is free software; you can redistribute it ////
|
422 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
423 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
424 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
425 |
|
|
//// later version. ////
|
426 |
|
|
//// ////
|
427 |
|
|
//// This source is distributed in the hope that it will be ////
|
428 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
429 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
430 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
431 |
|
|
//// details. ////
|
432 |
|
|
//// ////
|
433 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
434 |
|
|
//// Public License along with this source; if not, download it ////
|
435 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
436 |
|
|
//// ////
|
437 |
|
|
//////////////////////////////////////////////////////////////////////
|
438 |
36 |
unneback |
module vl_mux_andor ( a, sel, dout);
|
439 |
|
|
parameter width = 32;
|
440 |
|
|
parameter nr_of_ports = 4;
|
441 |
|
|
input [nr_of_ports*width-1:0] a;
|
442 |
|
|
input [nr_of_ports-1:0] sel;
|
443 |
|
|
output reg [width-1:0] dout;
|
444 |
38 |
unneback |
integer i,j;
|
445 |
36 |
unneback |
always @ (a, sel)
|
446 |
|
|
begin
|
447 |
|
|
dout = a[width-1:0] & {width{sel[0]}};
|
448 |
42 |
unneback |
for (i=1;i<nr_of_ports;i=i+1)
|
449 |
|
|
for (j=0;j<width;j=j+1)
|
450 |
|
|
dout[j] = (a[i*width + j] & sel[i]) | dout[j];
|
451 |
36 |
unneback |
end
|
452 |
|
|
endmodule
|
453 |
34 |
unneback |
module vl_mux2_andor ( a1, a0, sel, dout);
|
454 |
|
|
parameter width = 32;
|
455 |
35 |
unneback |
localparam nr_of_ports = 2;
|
456 |
34 |
unneback |
input [width-1:0] a1, a0;
|
457 |
|
|
input [nr_of_ports-1:0] sel;
|
458 |
|
|
output [width-1:0] dout;
|
459 |
36 |
unneback |
vl_mux_andor
|
460 |
38 |
unneback |
# ( .width(width), .nr_of_ports(nr_of_ports))
|
461 |
36 |
unneback |
mux0( .a({a1,a0}), .sel(sel), .dout(dout));
|
462 |
34 |
unneback |
endmodule
|
463 |
|
|
module vl_mux3_andor ( a2, a1, a0, sel, dout);
|
464 |
|
|
parameter width = 32;
|
465 |
35 |
unneback |
localparam nr_of_ports = 3;
|
466 |
34 |
unneback |
input [width-1:0] a2, a1, a0;
|
467 |
|
|
input [nr_of_ports-1:0] sel;
|
468 |
|
|
output [width-1:0] dout;
|
469 |
36 |
unneback |
vl_mux_andor
|
470 |
38 |
unneback |
# ( .width(width), .nr_of_ports(nr_of_ports))
|
471 |
36 |
unneback |
mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
|
472 |
34 |
unneback |
endmodule
|
473 |
18 |
unneback |
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
|
474 |
|
|
parameter width = 32;
|
475 |
35 |
unneback |
localparam nr_of_ports = 4;
|
476 |
18 |
unneback |
input [width-1:0] a3, a2, a1, a0;
|
477 |
|
|
input [nr_of_ports-1:0] sel;
|
478 |
22 |
unneback |
output [width-1:0] dout;
|
479 |
36 |
unneback |
vl_mux_andor
|
480 |
38 |
unneback |
# ( .width(width), .nr_of_ports(nr_of_ports))
|
481 |
36 |
unneback |
mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
|
482 |
18 |
unneback |
endmodule
|
483 |
|
|
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
|
484 |
|
|
parameter width = 32;
|
485 |
35 |
unneback |
localparam nr_of_ports = 5;
|
486 |
18 |
unneback |
input [width-1:0] a4, a3, a2, a1, a0;
|
487 |
|
|
input [nr_of_ports-1:0] sel;
|
488 |
22 |
unneback |
output [width-1:0] dout;
|
489 |
36 |
unneback |
vl_mux_andor
|
490 |
38 |
unneback |
# ( .width(width), .nr_of_ports(nr_of_ports))
|
491 |
36 |
unneback |
mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
|
492 |
18 |
unneback |
endmodule
|
493 |
|
|
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
|
494 |
|
|
parameter width = 32;
|
495 |
35 |
unneback |
localparam nr_of_ports = 6;
|
496 |
18 |
unneback |
input [width-1:0] a5, a4, a3, a2, a1, a0;
|
497 |
|
|
input [nr_of_ports-1:0] sel;
|
498 |
22 |
unneback |
output [width-1:0] dout;
|
499 |
36 |
unneback |
vl_mux_andor
|
500 |
38 |
unneback |
# ( .width(width), .nr_of_ports(nr_of_ports))
|
501 |
36 |
unneback |
mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
|
502 |
18 |
unneback |
endmodule
|
503 |
43 |
unneback |
module vl_parity_generate (data, parity);
|
504 |
|
|
parameter word_size = 32;
|
505 |
|
|
parameter chunk_size = 8;
|
506 |
|
|
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
|
507 |
|
|
input [word_size-1:0] data;
|
508 |
|
|
output reg [word_size/chunk_size-1:0] parity;
|
509 |
|
|
integer i,j;
|
510 |
|
|
always @ (data)
|
511 |
|
|
for (i=0;i<word_size/chunk_size;i=i+1) begin
|
512 |
|
|
parity[i] = parity_type;
|
513 |
|
|
for (j=0;j<chunk_size;j=j+1) begin
|
514 |
46 |
unneback |
parity[i] = data[i*chunk_size+j] ^ parity[i];
|
515 |
43 |
unneback |
end
|
516 |
|
|
end
|
517 |
|
|
endmodule
|
518 |
|
|
module vl_parity_check( data, parity, parity_error);
|
519 |
|
|
parameter word_size = 32;
|
520 |
|
|
parameter chunk_size = 8;
|
521 |
|
|
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
|
522 |
|
|
input [word_size-1:0] data;
|
523 |
|
|
input [word_size/chunk_size-1:0] parity;
|
524 |
|
|
output parity_error;
|
525 |
44 |
unneback |
reg [word_size/chunk_size-1:0] error_flag;
|
526 |
43 |
unneback |
integer i,j;
|
527 |
|
|
always @ (data or parity)
|
528 |
|
|
for (i=0;i<word_size/chunk_size;i=i+1) begin
|
529 |
|
|
error_flag[i] = parity[i] ^ parity_type;
|
530 |
|
|
for (j=0;j<chunk_size;j=j+1) begin
|
531 |
46 |
unneback |
error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
|
532 |
43 |
unneback |
end
|
533 |
|
|
end
|
534 |
|
|
assign parity_error = |error_flag;
|
535 |
|
|
endmodule
|
536 |
18 |
unneback |
//////////////////////////////////////////////////////////////////////
|
537 |
|
|
//// ////
|
538 |
44 |
unneback |
//// IO functions ////
|
539 |
|
|
//// ////
|
540 |
|
|
//// Description ////
|
541 |
|
|
//// IO functions such as IOB flip-flops ////
|
542 |
|
|
//// ////
|
543 |
|
|
//// ////
|
544 |
|
|
//// To Do: ////
|
545 |
|
|
//// - ////
|
546 |
|
|
//// ////
|
547 |
|
|
//// Author(s): ////
|
548 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
549 |
|
|
//// ORSoC AB ////
|
550 |
|
|
//// ////
|
551 |
|
|
//////////////////////////////////////////////////////////////////////
|
552 |
|
|
//// ////
|
553 |
|
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
554 |
|
|
//// ////
|
555 |
|
|
//// This source file may be used and distributed without ////
|
556 |
|
|
//// restriction provided that this copyright statement is not ////
|
557 |
|
|
//// removed from the file and that any derivative work contains ////
|
558 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
559 |
|
|
//// ////
|
560 |
|
|
//// This source file is free software; you can redistribute it ////
|
561 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
562 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
563 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
564 |
|
|
//// later version. ////
|
565 |
|
|
//// ////
|
566 |
|
|
//// This source is distributed in the hope that it will be ////
|
567 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
568 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
569 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
570 |
|
|
//// details. ////
|
571 |
|
|
//// ////
|
572 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
573 |
|
|
//// Public License along with this source; if not, download it ////
|
574 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
575 |
|
|
//// ////
|
576 |
|
|
//////////////////////////////////////////////////////////////////////
|
577 |
45 |
unneback |
`timescale 1ns/1ns
|
578 |
44 |
unneback |
module vl_o_dff (d_i, o_pad, clk, rst);
|
579 |
|
|
parameter width = 1;
|
580 |
45 |
unneback |
parameter reset_value = {width{1'b0}};
|
581 |
|
|
input [width-1:0] d_i;
|
582 |
44 |
unneback |
output [width-1:0] o_pad;
|
583 |
|
|
input clk, rst;
|
584 |
|
|
wire [width-1:0] d_i_int /*synthesis syn_keep = 1*/;
|
585 |
45 |
unneback |
reg [width-1:0] o_pad_int;
|
586 |
44 |
unneback |
assign d_i_int = d_i;
|
587 |
|
|
genvar i;
|
588 |
45 |
unneback |
generate
|
589 |
44 |
unneback |
for (i=0;i<width;i=i+1) begin
|
590 |
|
|
always @ (posedge clk or posedge rst)
|
591 |
|
|
if (rst)
|
592 |
45 |
unneback |
o_pad_int[i] <= reset_value[i];
|
593 |
44 |
unneback |
else
|
594 |
45 |
unneback |
o_pad_int[i] <= d_i_int[i];
|
595 |
|
|
assign #1 o_pad[i] = o_pad_int[i];
|
596 |
44 |
unneback |
end
|
597 |
|
|
endgenerate
|
598 |
|
|
endmodule
|
599 |
45 |
unneback |
`timescale 1ns/1ns
|
600 |
44 |
unneback |
module vl_io_dff_oe ( d_i, d_o, oe, io_pad, clk, rst);
|
601 |
|
|
parameter width = 1;
|
602 |
|
|
input [width-1:0] d_o;
|
603 |
|
|
output reg [width-1:0] d_i;
|
604 |
|
|
input oe;
|
605 |
|
|
inout [width-1:0] io_pad;
|
606 |
|
|
input clk, rst;
|
607 |
|
|
wire [width-1:0] oe_d /*synthesis syn_keep = 1*/;
|
608 |
|
|
reg [width-1:0] oe_q;
|
609 |
|
|
reg [width-1:0] d_o_q;
|
610 |
|
|
assign oe_d = {width{oe}};
|
611 |
|
|
genvar i;
|
612 |
|
|
generate
|
613 |
|
|
for (i=0;i<width;i=i+1) begin
|
614 |
|
|
always @ (posedge clk or posedge rst)
|
615 |
|
|
if (rst)
|
616 |
|
|
oe_q[i] <= 1'b0;
|
617 |
|
|
else
|
618 |
|
|
oe_q[i] <= oe_d[i];
|
619 |
|
|
always @ (posedge clk or posedge rst)
|
620 |
|
|
if (rst)
|
621 |
|
|
d_o_q[i] <= 1'b0;
|
622 |
|
|
else
|
623 |
|
|
d_o_q[i] <= d_o[i];
|
624 |
|
|
always @ (posedge clk or posedge rst)
|
625 |
|
|
if (rst)
|
626 |
|
|
d_i[i] <= 1'b0;
|
627 |
|
|
else
|
628 |
|
|
d_i[i] <= io_pad[i];
|
629 |
45 |
unneback |
assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
|
630 |
44 |
unneback |
end
|
631 |
|
|
endgenerate
|
632 |
|
|
endmodule
|
633 |
|
|
//////////////////////////////////////////////////////////////////////
|
634 |
|
|
//// ////
|
635 |
6 |
unneback |
//// Versatile counter ////
|
636 |
|
|
//// ////
|
637 |
|
|
//// Description ////
|
638 |
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
639 |
|
|
//// counter ////
|
640 |
|
|
//// ////
|
641 |
|
|
//// To Do: ////
|
642 |
|
|
//// - add LFSR with more taps ////
|
643 |
|
|
//// ////
|
644 |
|
|
//// Author(s): ////
|
645 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
646 |
|
|
//// ORSoC AB ////
|
647 |
|
|
//// ////
|
648 |
|
|
//////////////////////////////////////////////////////////////////////
|
649 |
|
|
//// ////
|
650 |
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
651 |
|
|
//// ////
|
652 |
|
|
//// This source file may be used and distributed without ////
|
653 |
|
|
//// restriction provided that this copyright statement is not ////
|
654 |
|
|
//// removed from the file and that any derivative work contains ////
|
655 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
656 |
|
|
//// ////
|
657 |
|
|
//// This source file is free software; you can redistribute it ////
|
658 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
659 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
660 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
661 |
|
|
//// later version. ////
|
662 |
|
|
//// ////
|
663 |
|
|
//// This source is distributed in the hope that it will be ////
|
664 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
665 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
666 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
667 |
|
|
//// details. ////
|
668 |
|
|
//// ////
|
669 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
670 |
|
|
//// Public License along with this source; if not, download it ////
|
671 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
672 |
|
|
//// ////
|
673 |
|
|
//////////////////////////////////////////////////////////////////////
|
674 |
|
|
// binary counter
|
675 |
40 |
unneback |
module vl_cnt_bin_ce (
|
676 |
|
|
cke, q, rst, clk);
|
677 |
22 |
unneback |
parameter length = 4;
|
678 |
6 |
unneback |
input cke;
|
679 |
|
|
output [length:1] q;
|
680 |
|
|
input rst;
|
681 |
|
|
input clk;
|
682 |
|
|
parameter clear_value = 0;
|
683 |
|
|
parameter set_value = 1;
|
684 |
|
|
parameter wrap_value = 0;
|
685 |
|
|
parameter level1_value = 15;
|
686 |
|
|
reg [length:1] qi;
|
687 |
|
|
wire [length:1] q_next;
|
688 |
|
|
assign q_next = qi + {{length-1{1'b0}},1'b1};
|
689 |
|
|
always @ (posedge clk or posedge rst)
|
690 |
|
|
if (rst)
|
691 |
|
|
qi <= {length{1'b0}};
|
692 |
|
|
else
|
693 |
|
|
if (cke)
|
694 |
|
|
qi <= q_next;
|
695 |
|
|
assign q = qi;
|
696 |
|
|
endmodule
|
697 |
|
|
//////////////////////////////////////////////////////////////////////
|
698 |
|
|
//// ////
|
699 |
|
|
//// Versatile counter ////
|
700 |
|
|
//// ////
|
701 |
|
|
//// Description ////
|
702 |
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
703 |
|
|
//// counter ////
|
704 |
|
|
//// ////
|
705 |
|
|
//// To Do: ////
|
706 |
|
|
//// - add LFSR with more taps ////
|
707 |
|
|
//// ////
|
708 |
|
|
//// Author(s): ////
|
709 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
710 |
|
|
//// ORSoC AB ////
|
711 |
|
|
//// ////
|
712 |
|
|
//////////////////////////////////////////////////////////////////////
|
713 |
|
|
//// ////
|
714 |
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
715 |
|
|
//// ////
|
716 |
|
|
//// This source file may be used and distributed without ////
|
717 |
|
|
//// restriction provided that this copyright statement is not ////
|
718 |
|
|
//// removed from the file and that any derivative work contains ////
|
719 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
720 |
|
|
//// ////
|
721 |
|
|
//// This source file is free software; you can redistribute it ////
|
722 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
723 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
724 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
725 |
|
|
//// later version. ////
|
726 |
|
|
//// ////
|
727 |
|
|
//// This source is distributed in the hope that it will be ////
|
728 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
729 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
730 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
731 |
|
|
//// details. ////
|
732 |
|
|
//// ////
|
733 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
734 |
|
|
//// Public License along with this source; if not, download it ////
|
735 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
736 |
|
|
//// ////
|
737 |
|
|
//////////////////////////////////////////////////////////////////////
|
738 |
|
|
// binary counter
|
739 |
40 |
unneback |
module vl_cnt_bin_ce_rew_zq_l1 (
|
740 |
|
|
cke, rew, zq, level1, rst, clk);
|
741 |
6 |
unneback |
parameter length = 4;
|
742 |
|
|
input cke;
|
743 |
|
|
input rew;
|
744 |
25 |
unneback |
output reg zq;
|
745 |
|
|
output reg level1;
|
746 |
|
|
input rst;
|
747 |
|
|
input clk;
|
748 |
|
|
parameter clear_value = 0;
|
749 |
|
|
parameter set_value = 1;
|
750 |
|
|
parameter wrap_value = 1;
|
751 |
|
|
parameter level1_value = 15;
|
752 |
29 |
unneback |
wire clear;
|
753 |
30 |
unneback |
assign clear = 1'b0;
|
754 |
25 |
unneback |
reg [length:1] qi;
|
755 |
|
|
wire [length:1] q_next, q_next_fw, q_next_rew;
|
756 |
|
|
assign q_next_fw = qi + {{length-1{1'b0}},1'b1};
|
757 |
|
|
assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
|
758 |
|
|
assign q_next = rew ? q_next_rew : q_next_fw;
|
759 |
|
|
always @ (posedge clk or posedge rst)
|
760 |
|
|
if (rst)
|
761 |
|
|
qi <= {length{1'b0}};
|
762 |
|
|
else
|
763 |
|
|
if (cke)
|
764 |
|
|
qi <= q_next;
|
765 |
|
|
always @ (posedge clk or posedge rst)
|
766 |
|
|
if (rst)
|
767 |
|
|
zq <= 1'b1;
|
768 |
|
|
else
|
769 |
|
|
if (cke)
|
770 |
|
|
zq <= q_next == {length{1'b0}};
|
771 |
|
|
always @ (posedge clk or posedge rst)
|
772 |
|
|
if (rst)
|
773 |
|
|
level1 <= 1'b0;
|
774 |
|
|
else
|
775 |
|
|
if (cke)
|
776 |
29 |
unneback |
if (clear)
|
777 |
|
|
level1 <= 1'b0;
|
778 |
|
|
else if (q_next == level1_value)
|
779 |
25 |
unneback |
level1 <= 1'b1;
|
780 |
|
|
else if (qi == level1_value & rew)
|
781 |
|
|
level1 <= 1'b0;
|
782 |
|
|
endmodule
|
783 |
|
|
//////////////////////////////////////////////////////////////////////
|
784 |
|
|
//// ////
|
785 |
|
|
//// Versatile counter ////
|
786 |
|
|
//// ////
|
787 |
|
|
//// Description ////
|
788 |
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
789 |
|
|
//// counter ////
|
790 |
|
|
//// ////
|
791 |
|
|
//// To Do: ////
|
792 |
|
|
//// - add LFSR with more taps ////
|
793 |
|
|
//// ////
|
794 |
|
|
//// Author(s): ////
|
795 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
796 |
|
|
//// ORSoC AB ////
|
797 |
|
|
//// ////
|
798 |
|
|
//////////////////////////////////////////////////////////////////////
|
799 |
|
|
//// ////
|
800 |
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
801 |
|
|
//// ////
|
802 |
|
|
//// This source file may be used and distributed without ////
|
803 |
|
|
//// restriction provided that this copyright statement is not ////
|
804 |
|
|
//// removed from the file and that any derivative work contains ////
|
805 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
806 |
|
|
//// ////
|
807 |
|
|
//// This source file is free software; you can redistribute it ////
|
808 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
809 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
810 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
811 |
|
|
//// later version. ////
|
812 |
|
|
//// ////
|
813 |
|
|
//// This source is distributed in the hope that it will be ////
|
814 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
815 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
816 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
817 |
|
|
//// details. ////
|
818 |
|
|
//// ////
|
819 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
820 |
|
|
//// Public License along with this source; if not, download it ////
|
821 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
822 |
|
|
//// ////
|
823 |
|
|
//////////////////////////////////////////////////////////////////////
|
824 |
|
|
// binary counter
|
825 |
40 |
unneback |
module vl_cnt_bin_ce_rew_q_zq_l1 (
|
826 |
|
|
cke, rew, q, zq, level1, rst, clk);
|
827 |
25 |
unneback |
parameter length = 4;
|
828 |
|
|
input cke;
|
829 |
|
|
input rew;
|
830 |
|
|
output [length:1] q;
|
831 |
|
|
output reg zq;
|
832 |
|
|
output reg level1;
|
833 |
|
|
input rst;
|
834 |
|
|
input clk;
|
835 |
|
|
parameter clear_value = 0;
|
836 |
|
|
parameter set_value = 1;
|
837 |
|
|
parameter wrap_value = 1;
|
838 |
|
|
parameter level1_value = 15;
|
839 |
29 |
unneback |
wire clear;
|
840 |
30 |
unneback |
assign clear = 1'b0;
|
841 |
25 |
unneback |
reg [length:1] qi;
|
842 |
|
|
wire [length:1] q_next, q_next_fw, q_next_rew;
|
843 |
|
|
assign q_next_fw = qi + {{length-1{1'b0}},1'b1};
|
844 |
|
|
assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
|
845 |
|
|
assign q_next = rew ? q_next_rew : q_next_fw;
|
846 |
|
|
always @ (posedge clk or posedge rst)
|
847 |
|
|
if (rst)
|
848 |
|
|
qi <= {length{1'b0}};
|
849 |
|
|
else
|
850 |
|
|
if (cke)
|
851 |
|
|
qi <= q_next;
|
852 |
|
|
assign q = qi;
|
853 |
|
|
always @ (posedge clk or posedge rst)
|
854 |
|
|
if (rst)
|
855 |
|
|
zq <= 1'b1;
|
856 |
|
|
else
|
857 |
|
|
if (cke)
|
858 |
|
|
zq <= q_next == {length{1'b0}};
|
859 |
|
|
always @ (posedge clk or posedge rst)
|
860 |
|
|
if (rst)
|
861 |
|
|
level1 <= 1'b0;
|
862 |
|
|
else
|
863 |
|
|
if (cke)
|
864 |
29 |
unneback |
if (clear)
|
865 |
|
|
level1 <= 1'b0;
|
866 |
|
|
else if (q_next == level1_value)
|
867 |
25 |
unneback |
level1 <= 1'b1;
|
868 |
|
|
else if (qi == level1_value & rew)
|
869 |
|
|
level1 <= 1'b0;
|
870 |
|
|
endmodule
|
871 |
|
|
//////////////////////////////////////////////////////////////////////
|
872 |
|
|
//// ////
|
873 |
|
|
//// Versatile counter ////
|
874 |
|
|
//// ////
|
875 |
|
|
//// Description ////
|
876 |
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
877 |
|
|
//// counter ////
|
878 |
|
|
//// ////
|
879 |
|
|
//// To Do: ////
|
880 |
|
|
//// - add LFSR with more taps ////
|
881 |
|
|
//// ////
|
882 |
|
|
//// Author(s): ////
|
883 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
884 |
|
|
//// ORSoC AB ////
|
885 |
|
|
//// ////
|
886 |
|
|
//////////////////////////////////////////////////////////////////////
|
887 |
|
|
//// ////
|
888 |
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
889 |
|
|
//// ////
|
890 |
|
|
//// This source file may be used and distributed without ////
|
891 |
|
|
//// restriction provided that this copyright statement is not ////
|
892 |
|
|
//// removed from the file and that any derivative work contains ////
|
893 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
894 |
|
|
//// ////
|
895 |
|
|
//// This source file is free software; you can redistribute it ////
|
896 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
897 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
898 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
899 |
|
|
//// later version. ////
|
900 |
|
|
//// ////
|
901 |
|
|
//// This source is distributed in the hope that it will be ////
|
902 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
903 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
904 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
905 |
|
|
//// details. ////
|
906 |
|
|
//// ////
|
907 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
908 |
|
|
//// Public License along with this source; if not, download it ////
|
909 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
910 |
|
|
//// ////
|
911 |
|
|
//////////////////////////////////////////////////////////////////////
|
912 |
75 |
unneback |
// LFSR counter
|
913 |
|
|
module vl_cnt_lfsr_ce (
|
914 |
|
|
cke, zq, rst, clk);
|
915 |
|
|
parameter length = 4;
|
916 |
|
|
input cke;
|
917 |
|
|
output reg zq;
|
918 |
|
|
input rst;
|
919 |
|
|
input clk;
|
920 |
|
|
parameter clear_value = 0;
|
921 |
|
|
parameter set_value = 1;
|
922 |
|
|
parameter wrap_value = 0;
|
923 |
|
|
parameter level1_value = 15;
|
924 |
|
|
reg [length:1] qi;
|
925 |
|
|
reg lfsr_fb;
|
926 |
|
|
wire [length:1] q_next;
|
927 |
|
|
reg [32:1] polynom;
|
928 |
|
|
integer i;
|
929 |
|
|
always @ (qi)
|
930 |
|
|
begin
|
931 |
|
|
case (length)
|
932 |
|
|
2: polynom = 32'b11; // 0x3
|
933 |
|
|
3: polynom = 32'b110; // 0x6
|
934 |
|
|
4: polynom = 32'b1100; // 0xC
|
935 |
|
|
5: polynom = 32'b10100; // 0x14
|
936 |
|
|
6: polynom = 32'b110000; // 0x30
|
937 |
|
|
7: polynom = 32'b1100000; // 0x60
|
938 |
|
|
8: polynom = 32'b10111000; // 0xb8
|
939 |
|
|
9: polynom = 32'b100010000; // 0x110
|
940 |
|
|
10: polynom = 32'b1001000000; // 0x240
|
941 |
|
|
11: polynom = 32'b10100000000; // 0x500
|
942 |
|
|
12: polynom = 32'b100000101001; // 0x829
|
943 |
|
|
13: polynom = 32'b1000000001100; // 0x100C
|
944 |
|
|
14: polynom = 32'b10000000010101; // 0x2015
|
945 |
|
|
15: polynom = 32'b110000000000000; // 0x6000
|
946 |
|
|
16: polynom = 32'b1101000000001000; // 0xD008
|
947 |
|
|
17: polynom = 32'b10010000000000000; // 0x12000
|
948 |
|
|
18: polynom = 32'b100000010000000000; // 0x20400
|
949 |
|
|
19: polynom = 32'b1000000000000100011; // 0x40023
|
950 |
|
|
20: polynom = 32'b10010000000000000000; // 0x90000
|
951 |
|
|
21: polynom = 32'b101000000000000000000; // 0x140000
|
952 |
|
|
22: polynom = 32'b1100000000000000000000; // 0x300000
|
953 |
|
|
23: polynom = 32'b10000100000000000000000; // 0x420000
|
954 |
|
|
24: polynom = 32'b111000010000000000000000; // 0xE10000
|
955 |
|
|
25: polynom = 32'b1001000000000000000000000; // 0x1200000
|
956 |
|
|
26: polynom = 32'b10000000000000000000100011; // 0x2000023
|
957 |
|
|
27: polynom = 32'b100000000000000000000010011; // 0x4000013
|
958 |
|
|
28: polynom = 32'b1100100000000000000000000000; // 0xC800000
|
959 |
|
|
29: polynom = 32'b10100000000000000000000000000; // 0x14000000
|
960 |
|
|
30: polynom = 32'b100000000000000000000000101001; // 0x20000029
|
961 |
|
|
31: polynom = 32'b1001000000000000000000000000000; // 0x48000000
|
962 |
|
|
32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
|
963 |
|
|
default: polynom = 32'b0;
|
964 |
|
|
endcase
|
965 |
|
|
lfsr_fb = qi[length];
|
966 |
|
|
for (i=length-1; i>=1; i=i-1) begin
|
967 |
|
|
if (polynom[i])
|
968 |
|
|
lfsr_fb = lfsr_fb ~^ qi[i];
|
969 |
|
|
end
|
970 |
|
|
end
|
971 |
|
|
assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
|
972 |
|
|
always @ (posedge clk or posedge rst)
|
973 |
|
|
if (rst)
|
974 |
|
|
qi <= {length{1'b0}};
|
975 |
|
|
else
|
976 |
|
|
if (cke)
|
977 |
|
|
qi <= q_next;
|
978 |
|
|
always @ (posedge clk or posedge rst)
|
979 |
|
|
if (rst)
|
980 |
|
|
zq <= 1'b1;
|
981 |
|
|
else
|
982 |
|
|
if (cke)
|
983 |
|
|
zq <= q_next == {length{1'b0}};
|
984 |
|
|
endmodule
|
985 |
|
|
//////////////////////////////////////////////////////////////////////
|
986 |
|
|
//// ////
|
987 |
|
|
//// Versatile counter ////
|
988 |
|
|
//// ////
|
989 |
|
|
//// Description ////
|
990 |
|
|
//// Versatile counter, a reconfigurable binary, gray or LFSR ////
|
991 |
|
|
//// counter ////
|
992 |
|
|
//// ////
|
993 |
|
|
//// To Do: ////
|
994 |
|
|
//// - add LFSR with more taps ////
|
995 |
|
|
//// ////
|
996 |
|
|
//// Author(s): ////
|
997 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
998 |
|
|
//// ORSoC AB ////
|
999 |
|
|
//// ////
|
1000 |
|
|
//////////////////////////////////////////////////////////////////////
|
1001 |
|
|
//// ////
|
1002 |
|
|
//// Copyright (C) 2009 Authors and OPENCORES.ORG ////
|
1003 |
|
|
//// ////
|
1004 |
|
|
//// This source file may be used and distributed without ////
|
1005 |
|
|
//// restriction provided that this copyright statement is not ////
|
1006 |
|
|
//// removed from the file and that any derivative work contains ////
|
1007 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
1008 |
|
|
//// ////
|
1009 |
|
|
//// This source file is free software; you can redistribute it ////
|
1010 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
1011 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
1012 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
1013 |
|
|
//// later version. ////
|
1014 |
|
|
//// ////
|
1015 |
|
|
//// This source is distributed in the hope that it will be ////
|
1016 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
1017 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
1018 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
1019 |
|
|
//// details. ////
|
1020 |
|
|
//// ////
|
1021 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
1022 |
|
|
//// Public License along with this source; if not, download it ////
|
1023 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
1024 |
|
|
//// ////
|
1025 |
|
|
//////////////////////////////////////////////////////////////////////
|
1026 |
6 |
unneback |
// GRAY counter
|
1027 |
40 |
unneback |
module vl_cnt_gray_ce_bin (
|
1028 |
|
|
cke, q, q_bin, rst, clk);
|
1029 |
6 |
unneback |
parameter length = 4;
|
1030 |
|
|
input cke;
|
1031 |
|
|
output reg [length:1] q;
|
1032 |
|
|
output [length:1] q_bin;
|
1033 |
|
|
input rst;
|
1034 |
|
|
input clk;
|
1035 |
|
|
parameter clear_value = 0;
|
1036 |
|
|
parameter set_value = 1;
|
1037 |
|
|
parameter wrap_value = 8;
|
1038 |
|
|
parameter level1_value = 15;
|
1039 |
|
|
reg [length:1] qi;
|
1040 |
|
|
wire [length:1] q_next;
|
1041 |
|
|
assign q_next = qi + {{length-1{1'b0}},1'b1};
|
1042 |
|
|
always @ (posedge clk or posedge rst)
|
1043 |
|
|
if (rst)
|
1044 |
|
|
qi <= {length{1'b0}};
|
1045 |
|
|
else
|
1046 |
|
|
if (cke)
|
1047 |
|
|
qi <= q_next;
|
1048 |
|
|
always @ (posedge clk or posedge rst)
|
1049 |
|
|
if (rst)
|
1050 |
|
|
q <= {length{1'b0}};
|
1051 |
|
|
else
|
1052 |
|
|
if (cke)
|
1053 |
|
|
q <= (q_next>>1) ^ q_next;
|
1054 |
|
|
assign q_bin = qi;
|
1055 |
|
|
endmodule
|
1056 |
|
|
//////////////////////////////////////////////////////////////////////
|
1057 |
|
|
//// ////
|
1058 |
|
|
//// Versatile library, counters ////
|
1059 |
|
|
//// ////
|
1060 |
|
|
//// Description ////
|
1061 |
|
|
//// counters ////
|
1062 |
|
|
//// ////
|
1063 |
|
|
//// ////
|
1064 |
|
|
//// To Do: ////
|
1065 |
|
|
//// - add more counters ////
|
1066 |
|
|
//// ////
|
1067 |
|
|
//// Author(s): ////
|
1068 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
1069 |
|
|
//// ORSoC AB ////
|
1070 |
|
|
//// ////
|
1071 |
|
|
//////////////////////////////////////////////////////////////////////
|
1072 |
|
|
//// ////
|
1073 |
|
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
1074 |
|
|
//// ////
|
1075 |
|
|
//// This source file may be used and distributed without ////
|
1076 |
|
|
//// restriction provided that this copyright statement is not ////
|
1077 |
|
|
//// removed from the file and that any derivative work contains ////
|
1078 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
1079 |
|
|
//// ////
|
1080 |
|
|
//// This source file is free software; you can redistribute it ////
|
1081 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
1082 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
1083 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
1084 |
|
|
//// later version. ////
|
1085 |
|
|
//// ////
|
1086 |
|
|
//// This source is distributed in the hope that it will be ////
|
1087 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
1088 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
1089 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
1090 |
|
|
//// details. ////
|
1091 |
|
|
//// ////
|
1092 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
1093 |
|
|
//// Public License along with this source; if not, download it ////
|
1094 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
1095 |
|
|
//// ////
|
1096 |
|
|
//////////////////////////////////////////////////////////////////////
|
1097 |
18 |
unneback |
module vl_cnt_shreg_wrap ( q, rst, clk);
|
1098 |
6 |
unneback |
parameter length = 4;
|
1099 |
|
|
output reg [0:length-1] q;
|
1100 |
|
|
input rst;
|
1101 |
|
|
input clk;
|
1102 |
|
|
always @ (posedge clk or posedge rst)
|
1103 |
|
|
if (rst)
|
1104 |
|
|
q <= {1'b1,{length-1{1'b0}}};
|
1105 |
|
|
else
|
1106 |
|
|
q <= {q[length-1],q[0:length-2]};
|
1107 |
|
|
endmodule
|
1108 |
18 |
unneback |
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
|
1109 |
6 |
unneback |
parameter length = 4;
|
1110 |
|
|
input cke;
|
1111 |
|
|
output reg [0:length-1] q;
|
1112 |
|
|
input rst;
|
1113 |
|
|
input clk;
|
1114 |
|
|
always @ (posedge clk or posedge rst)
|
1115 |
|
|
if (rst)
|
1116 |
|
|
q <= {1'b1,{length-1{1'b0}}};
|
1117 |
|
|
else
|
1118 |
|
|
if (cke)
|
1119 |
|
|
q <= {q[length-1],q[0:length-2]};
|
1120 |
|
|
endmodule
|
1121 |
18 |
unneback |
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
|
1122 |
6 |
unneback |
parameter length = 4;
|
1123 |
|
|
input cke, clear;
|
1124 |
|
|
output reg [0:length-1] q;
|
1125 |
|
|
input rst;
|
1126 |
|
|
input clk;
|
1127 |
|
|
always @ (posedge clk or posedge rst)
|
1128 |
|
|
if (rst)
|
1129 |
|
|
q <= {1'b1,{length-1{1'b0}}};
|
1130 |
|
|
else
|
1131 |
|
|
if (cke)
|
1132 |
|
|
if (clear)
|
1133 |
|
|
q <= {1'b1,{length-1{1'b0}}};
|
1134 |
|
|
else
|
1135 |
|
|
q <= q >> 1;
|
1136 |
|
|
endmodule
|
1137 |
18 |
unneback |
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
|
1138 |
6 |
unneback |
parameter length = 4;
|
1139 |
|
|
input cke, clear;
|
1140 |
|
|
output reg [0:length-1] q;
|
1141 |
|
|
input rst;
|
1142 |
|
|
input clk;
|
1143 |
|
|
always @ (posedge clk or posedge rst)
|
1144 |
|
|
if (rst)
|
1145 |
|
|
q <= {1'b1,{length-1{1'b0}}};
|
1146 |
|
|
else
|
1147 |
|
|
if (cke)
|
1148 |
|
|
if (clear)
|
1149 |
|
|
q <= {1'b1,{length-1{1'b0}}};
|
1150 |
|
|
else
|
1151 |
|
|
q <= {q[length-1],q[0:length-2]};
|
1152 |
|
|
endmodule
|
1153 |
|
|
//////////////////////////////////////////////////////////////////////
|
1154 |
|
|
//// ////
|
1155 |
|
|
//// Versatile library, memories ////
|
1156 |
|
|
//// ////
|
1157 |
|
|
//// Description ////
|
1158 |
|
|
//// memories ////
|
1159 |
|
|
//// ////
|
1160 |
|
|
//// ////
|
1161 |
|
|
//// To Do: ////
|
1162 |
|
|
//// - add more memory types ////
|
1163 |
|
|
//// ////
|
1164 |
|
|
//// Author(s): ////
|
1165 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
1166 |
|
|
//// ORSoC AB ////
|
1167 |
|
|
//// ////
|
1168 |
|
|
//////////////////////////////////////////////////////////////////////
|
1169 |
|
|
//// ////
|
1170 |
|
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
1171 |
|
|
//// ////
|
1172 |
|
|
//// This source file may be used and distributed without ////
|
1173 |
|
|
//// restriction provided that this copyright statement is not ////
|
1174 |
|
|
//// removed from the file and that any derivative work contains ////
|
1175 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
1176 |
|
|
//// ////
|
1177 |
|
|
//// This source file is free software; you can redistribute it ////
|
1178 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
1179 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
1180 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
1181 |
|
|
//// later version. ////
|
1182 |
|
|
//// ////
|
1183 |
|
|
//// This source is distributed in the hope that it will be ////
|
1184 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
1185 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
1186 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
1187 |
|
|
//// details. ////
|
1188 |
|
|
//// ////
|
1189 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
1190 |
|
|
//// Public License along with this source; if not, download it ////
|
1191 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
1192 |
|
|
//// ////
|
1193 |
|
|
//////////////////////////////////////////////////////////////////////
|
1194 |
|
|
/// ROM
|
1195 |
7 |
unneback |
module vl_rom_init ( adr, q, clk);
|
1196 |
|
|
parameter data_width = 32;
|
1197 |
|
|
parameter addr_width = 8;
|
1198 |
75 |
unneback |
parameter mem_size = 1<<addr_width;
|
1199 |
7 |
unneback |
input [(addr_width-1):0] adr;
|
1200 |
|
|
output reg [(data_width-1):0] q;
|
1201 |
|
|
input clk;
|
1202 |
75 |
unneback |
reg [data_width-1:0] rom [mem_size-1:0];
|
1203 |
7 |
unneback |
parameter memory_file = "vl_rom.vmem";
|
1204 |
|
|
initial
|
1205 |
|
|
begin
|
1206 |
|
|
$readmemh(memory_file, rom);
|
1207 |
|
|
end
|
1208 |
|
|
always @ (posedge clk)
|
1209 |
|
|
q <= rom[adr];
|
1210 |
|
|
endmodule
|
1211 |
6 |
unneback |
// Single port RAM
|
1212 |
|
|
module vl_ram ( d, adr, we, q, clk);
|
1213 |
|
|
parameter data_width = 32;
|
1214 |
|
|
parameter addr_width = 8;
|
1215 |
75 |
unneback |
parameter mem_size = 1<<addr_width;
|
1216 |
6 |
unneback |
input [(data_width-1):0] d;
|
1217 |
|
|
input [(addr_width-1):0] adr;
|
1218 |
|
|
input we;
|
1219 |
7 |
unneback |
output reg [(data_width-1):0] q;
|
1220 |
6 |
unneback |
input clk;
|
1221 |
75 |
unneback |
reg [data_width-1:0] ram [mem_szie-1:0];
|
1222 |
7 |
unneback |
parameter init = 0;
|
1223 |
|
|
parameter memory_file = "vl_ram.vmem";
|
1224 |
|
|
generate if (init) begin : init_mem
|
1225 |
|
|
initial
|
1226 |
|
|
begin
|
1227 |
|
|
$readmemh(memory_file, ram);
|
1228 |
|
|
end
|
1229 |
|
|
end
|
1230 |
|
|
endgenerate
|
1231 |
6 |
unneback |
always @ (posedge clk)
|
1232 |
|
|
begin
|
1233 |
|
|
if (we)
|
1234 |
|
|
ram[adr] <= d;
|
1235 |
|
|
q <= ram[adr];
|
1236 |
|
|
end
|
1237 |
|
|
endmodule
|
1238 |
7 |
unneback |
module vl_ram_be ( d, adr, be, we, q, clk);
|
1239 |
|
|
parameter data_width = 32;
|
1240 |
72 |
unneback |
parameter addr_width = 6;
|
1241 |
75 |
unneback |
parameter mem_size = 1<<addr_width;
|
1242 |
7 |
unneback |
input [(data_width-1):0] d;
|
1243 |
|
|
input [(addr_width-1):0] adr;
|
1244 |
73 |
unneback |
input [(data_width/8)-1:0] be;
|
1245 |
7 |
unneback |
input we;
|
1246 |
|
|
output reg [(data_width-1):0] q;
|
1247 |
|
|
input clk;
|
1248 |
65 |
unneback |
`ifdef SYSTEMVERILOG
|
1249 |
68 |
unneback |
logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
|
1250 |
65 |
unneback |
`else
|
1251 |
85 |
unneback |
reg [data_width-1:0] ram [mem_size-1:0];
|
1252 |
|
|
wire [data_width/8-1:0] cke;
|
1253 |
65 |
unneback |
`endif
|
1254 |
60 |
unneback |
parameter memory_init = 0;
|
1255 |
7 |
unneback |
parameter memory_file = "vl_ram.vmem";
|
1256 |
60 |
unneback |
generate if (memory_init) begin : init_mem
|
1257 |
7 |
unneback |
initial
|
1258 |
|
|
begin
|
1259 |
|
|
$readmemh(memory_file, ram);
|
1260 |
|
|
end
|
1261 |
|
|
end
|
1262 |
|
|
endgenerate
|
1263 |
60 |
unneback |
`ifdef SYSTEMVERILOG
|
1264 |
|
|
// use a multi-dimensional packed array
|
1265 |
|
|
//to model individual bytes within the word
|
1266 |
|
|
always_ff@(posedge clk)
|
1267 |
|
|
begin
|
1268 |
|
|
if(we) begin // note: we should have a for statement to support any bus width
|
1269 |
85 |
unneback |
if(be[3]) ram[adr[3] <= d[31:24];
|
1270 |
|
|
if(be[2]) ram[adr[2] <= d[23:16];
|
1271 |
|
|
if(be[1]) ram[adr[1] <= d[15:8];
|
1272 |
|
|
if(be[0]) ram[adr[0] <= d[7:0];
|
1273 |
60 |
unneback |
end
|
1274 |
65 |
unneback |
q <= ram[adr];
|
1275 |
60 |
unneback |
end
|
1276 |
|
|
`else
|
1277 |
85 |
unneback |
assign cke = {data_width/8{we}} & be;
|
1278 |
7 |
unneback |
genvar i;
|
1279 |
85 |
unneback |
generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
|
1280 |
7 |
unneback |
always @ (posedge clk)
|
1281 |
85 |
unneback |
if (cke[i])
|
1282 |
7 |
unneback |
ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
|
1283 |
|
|
end
|
1284 |
|
|
endgenerate
|
1285 |
|
|
always @ (posedge clk)
|
1286 |
|
|
q <= ram[adr];
|
1287 |
60 |
unneback |
`endif
|
1288 |
85 |
unneback |
// Function to access RAM (for use by Verilator).
|
1289 |
|
|
function [31:0] get_mem;
|
1290 |
|
|
// verilator public
|
1291 |
|
|
input [aw-1:0] addr;
|
1292 |
|
|
get_mem = ram[addr];
|
1293 |
|
|
endfunction // get_mem
|
1294 |
|
|
// Function to write RAM (for use by Verilator).
|
1295 |
|
|
function set_mem;
|
1296 |
|
|
// verilator public
|
1297 |
|
|
input [aw-1:0] addr;
|
1298 |
|
|
input [dw-1:0] data;
|
1299 |
|
|
ram[addr] = data;
|
1300 |
|
|
endfunction // set_mem
|
1301 |
7 |
unneback |
endmodule
|
1302 |
48 |
unneback |
// ACTEL FPGA should not use logic to handle rw collision
|
1303 |
7 |
unneback |
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
|
1304 |
6 |
unneback |
parameter data_width = 32;
|
1305 |
|
|
parameter addr_width = 8;
|
1306 |
75 |
unneback |
parameter mem_size = 1<<addr_width;
|
1307 |
6 |
unneback |
input [(data_width-1):0] d_a;
|
1308 |
|
|
input [(addr_width-1):0] adr_a;
|
1309 |
|
|
input [(addr_width-1):0] adr_b;
|
1310 |
|
|
input we_a;
|
1311 |
|
|
output [(data_width-1):0] q_b;
|
1312 |
|
|
input clk_a, clk_b;
|
1313 |
|
|
reg [(addr_width-1):0] adr_b_reg;
|
1314 |
75 |
unneback |
reg [data_width-1:0] ram [mem_szie-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
|
1315 |
7 |
unneback |
parameter init = 0;
|
1316 |
|
|
parameter memory_file = "vl_ram.vmem";
|
1317 |
|
|
generate if (init) begin : init_mem
|
1318 |
|
|
initial
|
1319 |
|
|
begin
|
1320 |
|
|
$readmemh(memory_file, ram);
|
1321 |
|
|
end
|
1322 |
|
|
end
|
1323 |
|
|
endgenerate
|
1324 |
6 |
unneback |
always @ (posedge clk_a)
|
1325 |
|
|
if (we_a)
|
1326 |
|
|
ram[adr_a] <= d_a;
|
1327 |
|
|
always @ (posedge clk_b)
|
1328 |
|
|
adr_b_reg <= adr_b;
|
1329 |
|
|
assign q_b = ram[adr_b_reg];
|
1330 |
|
|
endmodule
|
1331 |
7 |
unneback |
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
|
1332 |
6 |
unneback |
parameter data_width = 32;
|
1333 |
|
|
parameter addr_width = 8;
|
1334 |
75 |
unneback |
parameter mem_size = 1<<addr_width;
|
1335 |
6 |
unneback |
input [(data_width-1):0] d_a;
|
1336 |
|
|
input [(addr_width-1):0] adr_a;
|
1337 |
|
|
input [(addr_width-1):0] adr_b;
|
1338 |
|
|
input we_a;
|
1339 |
|
|
output [(data_width-1):0] q_b;
|
1340 |
|
|
output reg [(data_width-1):0] q_a;
|
1341 |
|
|
input clk_a, clk_b;
|
1342 |
|
|
reg [(data_width-1):0] q_b;
|
1343 |
75 |
unneback |
reg [data_width-1:0] ram [mem_szie-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
|
1344 |
7 |
unneback |
parameter init = 0;
|
1345 |
|
|
parameter memory_file = "vl_ram.vmem";
|
1346 |
|
|
generate if (init) begin : init_mem
|
1347 |
|
|
initial
|
1348 |
|
|
begin
|
1349 |
|
|
$readmemh(memory_file, ram);
|
1350 |
|
|
end
|
1351 |
|
|
end
|
1352 |
|
|
endgenerate
|
1353 |
6 |
unneback |
always @ (posedge clk_a)
|
1354 |
|
|
begin
|
1355 |
|
|
q_a <= ram[adr_a];
|
1356 |
|
|
if (we_a)
|
1357 |
|
|
ram[adr_a] <= d_a;
|
1358 |
|
|
end
|
1359 |
|
|
always @ (posedge clk_b)
|
1360 |
|
|
q_b <= ram[adr_b];
|
1361 |
|
|
endmodule
|
1362 |
7 |
unneback |
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
|
1363 |
6 |
unneback |
parameter data_width = 32;
|
1364 |
|
|
parameter addr_width = 8;
|
1365 |
75 |
unneback |
parameter mem_size = 1<<addr_width;
|
1366 |
6 |
unneback |
input [(data_width-1):0] d_a;
|
1367 |
|
|
input [(addr_width-1):0] adr_a;
|
1368 |
|
|
input [(addr_width-1):0] adr_b;
|
1369 |
|
|
input we_a;
|
1370 |
|
|
output [(data_width-1):0] q_b;
|
1371 |
|
|
input [(data_width-1):0] d_b;
|
1372 |
|
|
output reg [(data_width-1):0] q_a;
|
1373 |
|
|
input we_b;
|
1374 |
|
|
input clk_a, clk_b;
|
1375 |
|
|
reg [(data_width-1):0] q_b;
|
1376 |
75 |
unneback |
reg [data_width-1:0] ram [mem_size-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
|
1377 |
7 |
unneback |
parameter init = 0;
|
1378 |
|
|
parameter memory_file = "vl_ram.vmem";
|
1379 |
|
|
generate if (init) begin : init_mem
|
1380 |
|
|
initial
|
1381 |
|
|
begin
|
1382 |
|
|
$readmemh(memory_file, ram);
|
1383 |
|
|
end
|
1384 |
|
|
end
|
1385 |
|
|
endgenerate
|
1386 |
6 |
unneback |
always @ (posedge clk_a)
|
1387 |
|
|
begin
|
1388 |
|
|
q_a <= ram[adr_a];
|
1389 |
|
|
if (we_a)
|
1390 |
|
|
ram[adr_a] <= d_a;
|
1391 |
|
|
end
|
1392 |
|
|
always @ (posedge clk_b)
|
1393 |
|
|
begin
|
1394 |
|
|
q_b <= ram[adr_b];
|
1395 |
|
|
if (we_b)
|
1396 |
|
|
ram[adr_b] <= d_b;
|
1397 |
|
|
end
|
1398 |
|
|
endmodule
|
1399 |
75 |
unneback |
module vl_dpram_be_2r2w ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
|
1400 |
|
|
parameter a_data_width = 32;
|
1401 |
|
|
parameter a_addr_width = 8;
|
1402 |
|
|
parameter b_data_width = 64;
|
1403 |
|
|
parameter b_addr_width = 7;
|
1404 |
|
|
//parameter mem_size = (a_addr_width>b_addr_width) ? (1<<a_addr_width) : (1<<b_addr_width);
|
1405 |
|
|
parameter mem_size = 1024;
|
1406 |
|
|
input [(a_data_width-1):0] d_a;
|
1407 |
|
|
input [(a_addr_width-1):0] adr_a;
|
1408 |
|
|
input [(b_addr_width-1):0] adr_b;
|
1409 |
|
|
input [(a_data_width/4-1):0] be_a;
|
1410 |
|
|
input we_a;
|
1411 |
|
|
output [(b_data_width-1):0] q_b;
|
1412 |
|
|
input [(b_data_width-1):0] d_b;
|
1413 |
|
|
output reg [(a_data_width-1):0] q_a;
|
1414 |
|
|
input [(b_data_width/4-1):0] be_b;
|
1415 |
|
|
input we_b;
|
1416 |
|
|
input clk_a, clk_b;
|
1417 |
|
|
reg [(b_data_width-1):0] q_b;
|
1418 |
|
|
generate
|
1419 |
|
|
if (a_data_width==32 & b_data_width==64) begin : inst32to64
|
1420 |
77 |
unneback |
wire [63:0] tmp;
|
1421 |
75 |
unneback |
vl_dpram_2r2w
|
1422 |
|
|
# (.data_width(8), .addr_width(b_addr_width-3))
|
1423 |
|
|
ram0 (
|
1424 |
|
|
.d_a(d_a[7:0]),
|
1425 |
|
|
.q_a(tmp[7:0]),
|
1426 |
|
|
.adr_a(adr_a[a_addr_width-3-1:0]),
|
1427 |
|
|
.we_a(we_a & be_a[0] & !adr_a[0]),
|
1428 |
|
|
.clk_a(clk_a),
|
1429 |
|
|
.d_b(d_b[7:0]),
|
1430 |
|
|
.q_b(q_b[7:0]),
|
1431 |
|
|
.adr_b(adr_b[b_addr_width-3-1:0]),
|
1432 |
|
|
.we_b(we_b),
|
1433 |
|
|
.clk_b(clk_b) );
|
1434 |
|
|
vl_dpram_2r2w
|
1435 |
|
|
# (.data_width(8), .addr_width(b_addr_width-3))
|
1436 |
|
|
ram1 (
|
1437 |
|
|
.d_a(d_a[7:0]),
|
1438 |
|
|
.q_a(tmp[7:0]),
|
1439 |
|
|
.adr_a(adr_a[a_addr_width-3-1:0]),
|
1440 |
|
|
.we_a(we_a),
|
1441 |
|
|
.clk_a(clk_a),
|
1442 |
|
|
.d_b(d_b[7:0]),
|
1443 |
|
|
.q_b(q_b[7:0]),
|
1444 |
|
|
.adr_b(adr_b[b_addr_width-3-1:0]),
|
1445 |
|
|
.we_b(we_b),
|
1446 |
|
|
.clk_b(clk_b) );
|
1447 |
|
|
vl_dpram_2r2w
|
1448 |
|
|
# (.data_width(8), .addr_width(b_addr_width-3))
|
1449 |
|
|
ram2 (
|
1450 |
|
|
.d_a(d_a[15:8]),
|
1451 |
|
|
.q_a(tmp[7:0]),
|
1452 |
|
|
.adr_a(adr_a[a_addr_width-3-1:0]),
|
1453 |
|
|
.we_a(we_a),
|
1454 |
|
|
.clk_a(clk_a),
|
1455 |
|
|
.d_b(d_b[7:0]),
|
1456 |
|
|
.q_b(q_b[7:0]),
|
1457 |
|
|
.adr_b(adr_b[b_addr_width-3-1:0]),
|
1458 |
|
|
.we_b(we_b),
|
1459 |
|
|
.clk_b(clk_b) );
|
1460 |
|
|
vl_dpram_2r2w
|
1461 |
|
|
# (.data_width(8), .addr_width(b_addr_width-3))
|
1462 |
|
|
ram3 (
|
1463 |
|
|
.d_a(d_a[15:8]),
|
1464 |
|
|
.q_a(tmp[7:0]),
|
1465 |
|
|
.adr_a(adr_a[a_addr_width-3-1:0]),
|
1466 |
|
|
.we_a(we_a),
|
1467 |
|
|
.clk_a(clk_a),
|
1468 |
|
|
.d_b(d_b[7:0]),
|
1469 |
|
|
.q_b(q_b[7:0]),
|
1470 |
|
|
.adr_b(adr_b[b_addr_width-3-1:0]),
|
1471 |
|
|
.we_b(we_b),
|
1472 |
|
|
.clk_b(clk_b) );
|
1473 |
|
|
vl_dpram_2r2w
|
1474 |
|
|
# (.data_width(8), .addr_width(b_addr_width-3))
|
1475 |
|
|
ram4 (
|
1476 |
|
|
.d_a(d_a[23:16]),
|
1477 |
|
|
.q_a(tmp[7:0]),
|
1478 |
|
|
.adr_a(adr_a[a_addr_width-3-1:0]),
|
1479 |
|
|
.we_a(we_a),
|
1480 |
|
|
.clk_a(clk_a),
|
1481 |
|
|
.d_b(d_b[7:0]),
|
1482 |
|
|
.q_b(q_b[7:0]),
|
1483 |
|
|
.adr_b(adr_b[b_addr_width-3-1:0]),
|
1484 |
|
|
.we_b(we_b),
|
1485 |
|
|
.clk_b(clk_b) );
|
1486 |
|
|
vl_dpram_2r2w
|
1487 |
|
|
# (.data_width(8), .addr_width(b_addr_width-3))
|
1488 |
|
|
ram5 (
|
1489 |
|
|
.d_a(d_a[23:16]),
|
1490 |
|
|
.q_a(tmp[7:0]),
|
1491 |
|
|
.adr_a(adr_a[a_addr_width-3-1:0]),
|
1492 |
|
|
.we_a(we_a),
|
1493 |
|
|
.clk_a(clk_a),
|
1494 |
|
|
.d_b(d_b[7:0]),
|
1495 |
|
|
.q_b(q_b[7:0]),
|
1496 |
|
|
.adr_b(adr_b[b_addr_width-3-1:0]),
|
1497 |
|
|
.we_b(we_b),
|
1498 |
|
|
.clk_b(clk_b) );
|
1499 |
|
|
vl_dpram_2r2w
|
1500 |
|
|
# (.data_width(8), .addr_width(b_addr_width-3))
|
1501 |
|
|
ram6 (
|
1502 |
|
|
.d_a(d_a[31:24]),
|
1503 |
|
|
.q_a(tmp[7:0]),
|
1504 |
|
|
.adr_a(adr_a[a_addr_width-3-1:0]),
|
1505 |
|
|
.we_a(we_a),
|
1506 |
|
|
.clk_a(clk_a),
|
1507 |
|
|
.d_b(d_b[7:0]),
|
1508 |
|
|
.q_b(q_b[7:0]),
|
1509 |
|
|
.adr_b(adr_b[b_addr_width-3-1:0]),
|
1510 |
|
|
.we_b(we_b),
|
1511 |
|
|
.clk_b(clk_b) );
|
1512 |
|
|
vl_dpram_2r2w
|
1513 |
|
|
# (.data_width(8), .addr_width(b_addr_width-3))
|
1514 |
|
|
ram7 (
|
1515 |
|
|
.d_a(d_a[31:24]),
|
1516 |
|
|
.q_a(tmp[7:0]),
|
1517 |
|
|
.adr_a(adr_a[a_addr_width-3-1:0]),
|
1518 |
|
|
.we_a(we_a),
|
1519 |
|
|
.clk_a(clk_a),
|
1520 |
|
|
.d_b(d_b[7:0]),
|
1521 |
|
|
.q_b(q_b[7:0]),
|
1522 |
|
|
.adr_b(adr_b[b_addr_width-3-1:0]),
|
1523 |
|
|
.we_b(we_b),
|
1524 |
|
|
.clk_b(clk_b) );
|
1525 |
|
|
/*
|
1526 |
|
|
reg [7:0] ram0 [mem_size/8-1:0];
|
1527 |
|
|
wire [7:0] wea, web;
|
1528 |
|
|
assign wea = we_a & be_a[0];
|
1529 |
|
|
assign web = we_b & be_b[0];
|
1530 |
|
|
always @ (posedge clk_a)
|
1531 |
|
|
if (wea)
|
1532 |
|
|
ram0[adr_a] <= d_a[7:0];
|
1533 |
|
|
always @ (posedge clk_a)
|
1534 |
|
|
q_a[7:0] <= ram0[adr_a];
|
1535 |
|
|
always @ (posedge clk_a)
|
1536 |
|
|
if (web)
|
1537 |
|
|
ram0[adr_b] <= d_b[7:0];
|
1538 |
|
|
always @ (posedge clk_b)
|
1539 |
|
|
q_b[7:0] <= ram0[adr_b];
|
1540 |
|
|
*/
|
1541 |
|
|
end
|
1542 |
|
|
endgenerate
|
1543 |
|
|
/*
|
1544 |
|
|
generate for (i=0;i<addr_width/4;i=i+1) begin : be_rama
|
1545 |
|
|
always @ (posedge clk_a)
|
1546 |
|
|
if (we_a & be_a[i])
|
1547 |
|
|
ram[adr_a][(i+1)*8-1:i*8] <= d_a[(i+1)*8-1:i*8];
|
1548 |
|
|
end
|
1549 |
|
|
endgenerate
|
1550 |
|
|
always @ (posedge clk_a)
|
1551 |
|
|
q_a <= ram[adr_a];
|
1552 |
|
|
genvar i;
|
1553 |
|
|
generate for (i=0;i<addr_width/4;i=i+1) begin : be_ramb
|
1554 |
|
|
always @ (posedge clk_a)
|
1555 |
|
|
if (we_b & be_b[i])
|
1556 |
|
|
ram[adr_b][(i+1)*8-1:i*8] <= d_b[(i+1)*8-1:i*8];
|
1557 |
|
|
end
|
1558 |
|
|
endgenerate
|
1559 |
|
|
always @ (posedge clk_b)
|
1560 |
|
|
q_b <= ram[adr_b];
|
1561 |
|
|
*/
|
1562 |
|
|
/*
|
1563 |
|
|
always @ (posedge clk_a)
|
1564 |
|
|
begin
|
1565 |
|
|
q_a <= ram[adr_a];
|
1566 |
|
|
if (we_a)
|
1567 |
|
|
ram[adr_a] <= d_a;
|
1568 |
|
|
end
|
1569 |
|
|
always @ (posedge clk_b)
|
1570 |
|
|
begin
|
1571 |
|
|
q_b <= ram[adr_b];
|
1572 |
|
|
if (we_b)
|
1573 |
|
|
ram[adr_b] <= d_b;
|
1574 |
|
|
end
|
1575 |
|
|
*/
|
1576 |
|
|
endmodule
|
1577 |
6 |
unneback |
// Content addresable memory, CAM
|
1578 |
|
|
// FIFO
|
1579 |
25 |
unneback |
module vl_fifo_1r1w_fill_level_sync (
|
1580 |
|
|
d, wr, fifo_full,
|
1581 |
|
|
q, rd, fifo_empty,
|
1582 |
|
|
fill_level,
|
1583 |
|
|
clk, rst
|
1584 |
|
|
);
|
1585 |
|
|
parameter data_width = 18;
|
1586 |
|
|
parameter addr_width = 4;
|
1587 |
|
|
// write side
|
1588 |
|
|
input [data_width-1:0] d;
|
1589 |
|
|
input wr;
|
1590 |
|
|
output fifo_full;
|
1591 |
|
|
// read side
|
1592 |
|
|
output [data_width-1:0] q;
|
1593 |
|
|
input rd;
|
1594 |
|
|
output fifo_empty;
|
1595 |
|
|
// common
|
1596 |
|
|
output [addr_width:0] fill_level;
|
1597 |
|
|
input rst, clk;
|
1598 |
|
|
wire [addr_width:1] wadr, radr;
|
1599 |
|
|
vl_cnt_bin_ce
|
1600 |
|
|
# ( .length(addr_width))
|
1601 |
|
|
fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
|
1602 |
|
|
vl_cnt_bin_ce
|
1603 |
|
|
# (.length(addr_width))
|
1604 |
|
|
fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
|
1605 |
|
|
vl_dpram_1r1w
|
1606 |
|
|
# (.data_width(data_width), .addr_width(addr_width))
|
1607 |
|
|
dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
|
1608 |
31 |
unneback |
vl_cnt_bin_ce_rew_q_zq_l1
|
1609 |
27 |
unneback |
# (.length(addr_width+1), .level1_value(1<<addr_width))
|
1610 |
25 |
unneback |
fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
|
1611 |
|
|
endmodule
|
1612 |
27 |
unneback |
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
|
1613 |
|
|
// RAM is supposed to be larger than the two FIFOs
|
1614 |
|
|
// LFSR counters used adr pointers
|
1615 |
|
|
module vl_fifo_2r2w_sync_simplex (
|
1616 |
|
|
// a side
|
1617 |
|
|
a_d, a_wr, a_fifo_full,
|
1618 |
|
|
a_q, a_rd, a_fifo_empty,
|
1619 |
|
|
a_fill_level,
|
1620 |
|
|
// b side
|
1621 |
|
|
b_d, b_wr, b_fifo_full,
|
1622 |
|
|
b_q, b_rd, b_fifo_empty,
|
1623 |
|
|
b_fill_level,
|
1624 |
|
|
// common
|
1625 |
|
|
clk, rst
|
1626 |
|
|
);
|
1627 |
|
|
parameter data_width = 8;
|
1628 |
|
|
parameter addr_width = 5;
|
1629 |
|
|
parameter fifo_full_level = (1<<addr_width)-1;
|
1630 |
|
|
// a side
|
1631 |
|
|
input [data_width-1:0] a_d;
|
1632 |
|
|
input a_wr;
|
1633 |
|
|
output a_fifo_full;
|
1634 |
|
|
output [data_width-1:0] a_q;
|
1635 |
|
|
input a_rd;
|
1636 |
|
|
output a_fifo_empty;
|
1637 |
|
|
output [addr_width-1:0] a_fill_level;
|
1638 |
|
|
// b side
|
1639 |
|
|
input [data_width-1:0] b_d;
|
1640 |
|
|
input b_wr;
|
1641 |
|
|
output b_fifo_full;
|
1642 |
|
|
output [data_width-1:0] b_q;
|
1643 |
|
|
input b_rd;
|
1644 |
|
|
output b_fifo_empty;
|
1645 |
|
|
output [addr_width-1:0] b_fill_level;
|
1646 |
|
|
input clk;
|
1647 |
|
|
input rst;
|
1648 |
|
|
// adr_gen
|
1649 |
|
|
wire [addr_width:1] a_wadr, a_radr;
|
1650 |
|
|
wire [addr_width:1] b_wadr, b_radr;
|
1651 |
|
|
// dpram
|
1652 |
|
|
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
|
1653 |
|
|
vl_cnt_lfsr_ce
|
1654 |
|
|
# ( .length(addr_width))
|
1655 |
|
|
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
|
1656 |
|
|
vl_cnt_lfsr_ce
|
1657 |
|
|
# (.length(addr_width))
|
1658 |
|
|
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
|
1659 |
|
|
vl_cnt_lfsr_ce
|
1660 |
|
|
# ( .length(addr_width))
|
1661 |
|
|
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
|
1662 |
|
|
vl_cnt_lfsr_ce
|
1663 |
|
|
# (.length(addr_width))
|
1664 |
|
|
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
|
1665 |
|
|
// mux read or write adr to DPRAM
|
1666 |
|
|
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
|
1667 |
|
|
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
|
1668 |
|
|
vl_dpram_2r2w
|
1669 |
|
|
# (.data_width(data_width), .addr_width(addr_width+1))
|
1670 |
|
|
dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
|
1671 |
|
|
.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
|
1672 |
|
|
vl_cnt_bin_ce_rew_zq_l1
|
1673 |
28 |
unneback |
# (.length(addr_width), .level1_value(fifo_full_level))
|
1674 |
27 |
unneback |
a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
|
1675 |
|
|
vl_cnt_bin_ce_rew_zq_l1
|
1676 |
28 |
unneback |
# (.length(addr_width), .level1_value(fifo_full_level))
|
1677 |
27 |
unneback |
b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
|
1678 |
|
|
endmodule
|
1679 |
6 |
unneback |
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
|
1680 |
11 |
unneback |
parameter addr_width = 4;
|
1681 |
|
|
parameter N = addr_width-1;
|
1682 |
6 |
unneback |
parameter Q1 = 2'b00;
|
1683 |
|
|
parameter Q2 = 2'b01;
|
1684 |
|
|
parameter Q3 = 2'b11;
|
1685 |
|
|
parameter Q4 = 2'b10;
|
1686 |
|
|
parameter going_empty = 1'b0;
|
1687 |
|
|
parameter going_full = 1'b1;
|
1688 |
|
|
input [N:0] wptr, rptr;
|
1689 |
14 |
unneback |
output fifo_empty;
|
1690 |
6 |
unneback |
output fifo_full;
|
1691 |
|
|
input wclk, rclk, rst;
|
1692 |
|
|
wire direction;
|
1693 |
|
|
reg direction_set, direction_clr;
|
1694 |
|
|
wire async_empty, async_full;
|
1695 |
|
|
wire fifo_full2;
|
1696 |
14 |
unneback |
wire fifo_empty2;
|
1697 |
6 |
unneback |
// direction_set
|
1698 |
|
|
always @ (wptr[N:N-1] or rptr[N:N-1])
|
1699 |
|
|
case ({wptr[N:N-1],rptr[N:N-1]})
|
1700 |
|
|
{Q1,Q2} : direction_set <= 1'b1;
|
1701 |
|
|
{Q2,Q3} : direction_set <= 1'b1;
|
1702 |
|
|
{Q3,Q4} : direction_set <= 1'b1;
|
1703 |
|
|
{Q4,Q1} : direction_set <= 1'b1;
|
1704 |
|
|
default : direction_set <= 1'b0;
|
1705 |
|
|
endcase
|
1706 |
|
|
// direction_clear
|
1707 |
|
|
always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
|
1708 |
|
|
if (rst)
|
1709 |
|
|
direction_clr <= 1'b1;
|
1710 |
|
|
else
|
1711 |
|
|
case ({wptr[N:N-1],rptr[N:N-1]})
|
1712 |
|
|
{Q2,Q1} : direction_clr <= 1'b1;
|
1713 |
|
|
{Q3,Q2} : direction_clr <= 1'b1;
|
1714 |
|
|
{Q4,Q3} : direction_clr <= 1'b1;
|
1715 |
|
|
{Q1,Q4} : direction_clr <= 1'b1;
|
1716 |
|
|
default : direction_clr <= 1'b0;
|
1717 |
|
|
endcase
|
1718 |
18 |
unneback |
vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
|
1719 |
6 |
unneback |
assign async_empty = (wptr == rptr) && (direction==going_empty);
|
1720 |
|
|
assign async_full = (wptr == rptr) && (direction==going_full);
|
1721 |
18 |
unneback |
vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
|
1722 |
|
|
vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
|
1723 |
6 |
unneback |
/*
|
1724 |
|
|
always @ (posedge wclk or posedge rst or posedge async_full)
|
1725 |
|
|
if (rst)
|
1726 |
|
|
{fifo_full, fifo_full2} <= 2'b00;
|
1727 |
|
|
else if (async_full)
|
1728 |
|
|
{fifo_full, fifo_full2} <= 2'b11;
|
1729 |
|
|
else
|
1730 |
|
|
{fifo_full, fifo_full2} <= {fifo_full2, async_full};
|
1731 |
|
|
*/
|
1732 |
14 |
unneback |
/* always @ (posedge rclk or posedge async_empty)
|
1733 |
6 |
unneback |
if (async_empty)
|
1734 |
|
|
{fifo_empty, fifo_empty2} <= 2'b11;
|
1735 |
|
|
else
|
1736 |
14 |
unneback |
{fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
|
1737 |
18 |
unneback |
vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
|
1738 |
|
|
vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty), .clk(rclk), .rst(async_empty));
|
1739 |
27 |
unneback |
endmodule // async_compb
|
1740 |
6 |
unneback |
module vl_fifo_1r1w_async (
|
1741 |
|
|
d, wr, fifo_full, wr_clk, wr_rst,
|
1742 |
|
|
q, rd, fifo_empty, rd_clk, rd_rst
|
1743 |
|
|
);
|
1744 |
|
|
parameter data_width = 18;
|
1745 |
|
|
parameter addr_width = 4;
|
1746 |
|
|
// write side
|
1747 |
|
|
input [data_width-1:0] d;
|
1748 |
|
|
input wr;
|
1749 |
|
|
output fifo_full;
|
1750 |
|
|
input wr_clk;
|
1751 |
|
|
input wr_rst;
|
1752 |
|
|
// read side
|
1753 |
|
|
output [data_width-1:0] q;
|
1754 |
|
|
input rd;
|
1755 |
|
|
output fifo_empty;
|
1756 |
|
|
input rd_clk;
|
1757 |
|
|
input rd_rst;
|
1758 |
|
|
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
|
1759 |
18 |
unneback |
vl_cnt_gray_ce_bin
|
1760 |
6 |
unneback |
# ( .length(addr_width))
|
1761 |
|
|
fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
|
1762 |
18 |
unneback |
vl_cnt_gray_ce_bin
|
1763 |
6 |
unneback |
# (.length(addr_width))
|
1764 |
23 |
unneback |
fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
|
1765 |
7 |
unneback |
vl_dpram_1r1w
|
1766 |
6 |
unneback |
# (.data_width(data_width), .addr_width(addr_width))
|
1767 |
|
|
dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
|
1768 |
|
|
vl_fifo_cmp_async
|
1769 |
|
|
# (.addr_width(addr_width))
|
1770 |
|
|
cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
|
1771 |
|
|
endmodule
|
1772 |
8 |
unneback |
module vl_fifo_2r2w_async (
|
1773 |
6 |
unneback |
// a side
|
1774 |
|
|
a_d, a_wr, a_fifo_full,
|
1775 |
|
|
a_q, a_rd, a_fifo_empty,
|
1776 |
|
|
a_clk, a_rst,
|
1777 |
|
|
// b side
|
1778 |
|
|
b_d, b_wr, b_fifo_full,
|
1779 |
|
|
b_q, b_rd, b_fifo_empty,
|
1780 |
|
|
b_clk, b_rst
|
1781 |
|
|
);
|
1782 |
|
|
parameter data_width = 18;
|
1783 |
|
|
parameter addr_width = 4;
|
1784 |
|
|
// a side
|
1785 |
|
|
input [data_width-1:0] a_d;
|
1786 |
|
|
input a_wr;
|
1787 |
|
|
output a_fifo_full;
|
1788 |
|
|
output [data_width-1:0] a_q;
|
1789 |
|
|
input a_rd;
|
1790 |
|
|
output a_fifo_empty;
|
1791 |
|
|
input a_clk;
|
1792 |
|
|
input a_rst;
|
1793 |
|
|
// b side
|
1794 |
|
|
input [data_width-1:0] b_d;
|
1795 |
|
|
input b_wr;
|
1796 |
|
|
output b_fifo_full;
|
1797 |
|
|
output [data_width-1:0] b_q;
|
1798 |
|
|
input b_rd;
|
1799 |
|
|
output b_fifo_empty;
|
1800 |
|
|
input b_clk;
|
1801 |
|
|
input b_rst;
|
1802 |
|
|
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
|
1803 |
|
|
vl_fifo_1r1w_async_a (
|
1804 |
|
|
.d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
|
1805 |
|
|
.q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
|
1806 |
|
|
);
|
1807 |
|
|
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
|
1808 |
|
|
vl_fifo_1r1w_async_b (
|
1809 |
|
|
.d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
|
1810 |
|
|
.q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
|
1811 |
|
|
);
|
1812 |
|
|
endmodule
|
1813 |
8 |
unneback |
module vl_fifo_2r2w_async_simplex (
|
1814 |
6 |
unneback |
// a side
|
1815 |
|
|
a_d, a_wr, a_fifo_full,
|
1816 |
|
|
a_q, a_rd, a_fifo_empty,
|
1817 |
|
|
a_clk, a_rst,
|
1818 |
|
|
// b side
|
1819 |
|
|
b_d, b_wr, b_fifo_full,
|
1820 |
|
|
b_q, b_rd, b_fifo_empty,
|
1821 |
|
|
b_clk, b_rst
|
1822 |
|
|
);
|
1823 |
|
|
parameter data_width = 18;
|
1824 |
|
|
parameter addr_width = 4;
|
1825 |
|
|
// a side
|
1826 |
|
|
input [data_width-1:0] a_d;
|
1827 |
|
|
input a_wr;
|
1828 |
|
|
output a_fifo_full;
|
1829 |
|
|
output [data_width-1:0] a_q;
|
1830 |
|
|
input a_rd;
|
1831 |
|
|
output a_fifo_empty;
|
1832 |
|
|
input a_clk;
|
1833 |
|
|
input a_rst;
|
1834 |
|
|
// b side
|
1835 |
|
|
input [data_width-1:0] b_d;
|
1836 |
|
|
input b_wr;
|
1837 |
|
|
output b_fifo_full;
|
1838 |
|
|
output [data_width-1:0] b_q;
|
1839 |
|
|
input b_rd;
|
1840 |
|
|
output b_fifo_empty;
|
1841 |
|
|
input b_clk;
|
1842 |
|
|
input b_rst;
|
1843 |
|
|
// adr_gen
|
1844 |
|
|
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
|
1845 |
|
|
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
|
1846 |
|
|
// dpram
|
1847 |
|
|
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
|
1848 |
18 |
unneback |
vl_cnt_gray_ce_bin
|
1849 |
6 |
unneback |
# ( .length(addr_width))
|
1850 |
|
|
fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
|
1851 |
18 |
unneback |
vl_cnt_gray_ce_bin
|
1852 |
6 |
unneback |
# (.length(addr_width))
|
1853 |
|
|
fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
|
1854 |
18 |
unneback |
vl_cnt_gray_ce_bin
|
1855 |
6 |
unneback |
# ( .length(addr_width))
|
1856 |
|
|
fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
|
1857 |
18 |
unneback |
vl_cnt_gray_ce_bin
|
1858 |
6 |
unneback |
# (.length(addr_width))
|
1859 |
|
|
fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
|
1860 |
|
|
// mux read or write adr to DPRAM
|
1861 |
|
|
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
|
1862 |
|
|
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
|
1863 |
11 |
unneback |
vl_dpram_2r2w
|
1864 |
6 |
unneback |
# (.data_width(data_width), .addr_width(addr_width+1))
|
1865 |
|
|
dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
|
1866 |
|
|
.d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
|
1867 |
11 |
unneback |
vl_fifo_cmp_async
|
1868 |
6 |
unneback |
# (.addr_width(addr_width))
|
1869 |
|
|
cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
|
1870 |
11 |
unneback |
vl_fifo_cmp_async
|
1871 |
6 |
unneback |
# (.addr_width(addr_width))
|
1872 |
|
|
cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
|
1873 |
|
|
endmodule
|
1874 |
48 |
unneback |
module vl_reg_file (
|
1875 |
|
|
a1, a2, a3, wd3, we3, rd1, rd2, clk
|
1876 |
|
|
);
|
1877 |
|
|
parameter data_width = 32;
|
1878 |
|
|
parameter addr_width = 5;
|
1879 |
|
|
input [addr_width-1:0] a1, a2, a3;
|
1880 |
|
|
input [data_width-1:0] wd3;
|
1881 |
|
|
input we3;
|
1882 |
|
|
output [data_width-1:0] rd1, rd2;
|
1883 |
|
|
input clk;
|
1884 |
|
|
reg [data_width-1:0] wd3_reg;
|
1885 |
|
|
reg [addr_width-1:0] a1_reg, a2_reg, a3_reg;
|
1886 |
|
|
reg we3_reg;
|
1887 |
|
|
reg [data_width-1:0] ram1 [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
|
1888 |
|
|
reg [data_width-1:0] ram2 [(1<<addr_width)-1:0] /*synthesis syn_ramstyle = "no_rw_check"*/;
|
1889 |
|
|
always @ (posedge clk or posedge rst)
|
1890 |
|
|
if (rst)
|
1891 |
|
|
{wd3_reg, a3_reg, we3_reg} <= {(data_width+addr_width+1){1'b0}};
|
1892 |
|
|
else
|
1893 |
|
|
{wd3_reg, a3_reg, we3_reg} <= {wd3,a3,wd3};
|
1894 |
|
|
always @ (negedge clk)
|
1895 |
|
|
if (we3_reg)
|
1896 |
|
|
ram1[a3_reg] <= wd3;
|
1897 |
|
|
always @ (posedge clk)
|
1898 |
|
|
a1_reg <= a1;
|
1899 |
|
|
assign rd1 = ram1[a1_reg];
|
1900 |
|
|
always @ (negedge clk)
|
1901 |
|
|
if (we3_reg)
|
1902 |
|
|
ram2[a3_reg] <= wd3;
|
1903 |
|
|
always @ (posedge clk)
|
1904 |
|
|
a2_reg <= a2;
|
1905 |
|
|
assign rd2 = ram2[a2_reg];
|
1906 |
|
|
endmodule
|
1907 |
12 |
unneback |
//////////////////////////////////////////////////////////////////////
|
1908 |
|
|
//// ////
|
1909 |
|
|
//// Versatile library, wishbone stuff ////
|
1910 |
|
|
//// ////
|
1911 |
|
|
//// Description ////
|
1912 |
|
|
//// Wishbone compliant modules ////
|
1913 |
|
|
//// ////
|
1914 |
|
|
//// ////
|
1915 |
|
|
//// To Do: ////
|
1916 |
|
|
//// - ////
|
1917 |
|
|
//// ////
|
1918 |
|
|
//// Author(s): ////
|
1919 |
|
|
//// - Michael Unneback, unneback@opencores.org ////
|
1920 |
|
|
//// ORSoC AB ////
|
1921 |
|
|
//// ////
|
1922 |
|
|
//////////////////////////////////////////////////////////////////////
|
1923 |
|
|
//// ////
|
1924 |
|
|
//// Copyright (C) 2010 Authors and OPENCORES.ORG ////
|
1925 |
|
|
//// ////
|
1926 |
|
|
//// This source file may be used and distributed without ////
|
1927 |
|
|
//// restriction provided that this copyright statement is not ////
|
1928 |
|
|
//// removed from the file and that any derivative work contains ////
|
1929 |
|
|
//// the original copyright notice and the associated disclaimer. ////
|
1930 |
|
|
//// ////
|
1931 |
|
|
//// This source file is free software; you can redistribute it ////
|
1932 |
|
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
1933 |
|
|
//// Public License as published by the Free Software Foundation; ////
|
1934 |
|
|
//// either version 2.1 of the License, or (at your option) any ////
|
1935 |
|
|
//// later version. ////
|
1936 |
|
|
//// ////
|
1937 |
|
|
//// This source is distributed in the hope that it will be ////
|
1938 |
|
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
1939 |
|
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
1940 |
|
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
1941 |
|
|
//// details. ////
|
1942 |
|
|
//// ////
|
1943 |
|
|
//// You should have received a copy of the GNU Lesser General ////
|
1944 |
|
|
//// Public License along with this source; if not, download it ////
|
1945 |
|
|
//// from http://www.opencores.org/lgpl.shtml ////
|
1946 |
|
|
//// ////
|
1947 |
|
|
//////////////////////////////////////////////////////////////////////
|
1948 |
|
|
// async wb3 - wb3 bridge
|
1949 |
|
|
`timescale 1ns/1ns
|
1950 |
85 |
unneback |
module vl_wb_adr_inc ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
|
1951 |
83 |
unneback |
parameter adr_width = 10;
|
1952 |
|
|
parameter max_burst_width = 4;
|
1953 |
85 |
unneback |
input cyc_i, stb_i, we_i;
|
1954 |
83 |
unneback |
input [2:0] cti_i;
|
1955 |
|
|
input [1:0] bte_i;
|
1956 |
|
|
input [adr_width-1:0] adr_i;
|
1957 |
|
|
output [adr_width-1:0] adr_o;
|
1958 |
|
|
output ack_o;
|
1959 |
|
|
input clk, rst;
|
1960 |
|
|
reg [adr_width-1:0] adr;
|
1961 |
|
|
generate
|
1962 |
|
|
if (max_burst_width==0) begin : inst_0
|
1963 |
|
|
reg ack_o;
|
1964 |
|
|
assign adr_o = adr_i;
|
1965 |
|
|
always @ (posedge clk or posedge rst)
|
1966 |
|
|
if (rst)
|
1967 |
|
|
ack_o <= 1'b0;
|
1968 |
|
|
else
|
1969 |
|
|
ack_o <= cyc_i & stb_i & !ack_o;
|
1970 |
|
|
end else begin
|
1971 |
|
|
wire [max_burst_width-1:0] to_adr;
|
1972 |
|
|
reg [1:0] last_cycle;
|
1973 |
|
|
localparam idle = 2'b00;
|
1974 |
|
|
localparam cyc = 2'b01;
|
1975 |
|
|
localparam ws = 2'b10;
|
1976 |
|
|
localparam eoc = 2'b11;
|
1977 |
|
|
always @ (posedge clk or posedge rst)
|
1978 |
|
|
if (rst)
|
1979 |
|
|
last_cycle <= idle;
|
1980 |
|
|
else
|
1981 |
|
|
last_cycle <= (!cyc_i) ? idle :
|
1982 |
|
|
(cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? eoc :
|
1983 |
|
|
(cyc_i & !stb_i) ? ws :
|
1984 |
|
|
cyc;
|
1985 |
|
|
assign to_adr = (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
|
1986 |
85 |
unneback |
assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
|
1987 |
|
|
(last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] :
|
1988 |
|
|
adr[max_burst_width-1:0];
|
1989 |
83 |
unneback |
assign ack_o = last_cycle == cyc;
|
1990 |
|
|
end
|
1991 |
|
|
endgenerate
|
1992 |
|
|
generate
|
1993 |
|
|
if (max_burst_width==2) begin : inst_2
|
1994 |
|
|
always @ (posedge clk or posedge rst)
|
1995 |
|
|
if (rst)
|
1996 |
|
|
adr <= 2'h0;
|
1997 |
|
|
else
|
1998 |
|
|
if (cyc_i & stb_i)
|
1999 |
|
|
adr[1:0] <= to_adr[1:0] + 2'd1;
|
2000 |
|
|
else
|
2001 |
|
|
adr <= to_adr[1:0];
|
2002 |
|
|
end
|
2003 |
|
|
endgenerate
|
2004 |
|
|
generate
|
2005 |
|
|
if (max_burst_width==3) begin : inst_3
|
2006 |
|
|
always @ (posedge clk or posedge rst)
|
2007 |
|
|
if (rst)
|
2008 |
|
|
adr <= 3'h0;
|
2009 |
|
|
else
|
2010 |
|
|
if (cyc_i & stb_i)
|
2011 |
|
|
case (bte_i)
|
2012 |
|
|
2'b01: adr[2:0] <= {to_adr[2],to_adr[1:0] + 2'd1};
|
2013 |
|
|
default: adr[3:0] <= to_adr[2:0] + 3'd1;
|
2014 |
|
|
endcase
|
2015 |
|
|
else
|
2016 |
|
|
adr <= to_adr[2:0];
|
2017 |
|
|
end
|
2018 |
|
|
endgenerate
|
2019 |
|
|
generate
|
2020 |
|
|
if (max_burst_width==4) begin : inst_4
|
2021 |
|
|
always @ (posedge clk or posedge rst)
|
2022 |
|
|
if (rst)
|
2023 |
|
|
adr <= 4'h0;
|
2024 |
|
|
else
|
2025 |
|
|
if (cyc_i & stb_i)
|
2026 |
|
|
case (bte_i)
|
2027 |
|
|
2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
|
2028 |
|
|
2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
|
2029 |
|
|
default: adr[3:0] <= to_adr + 4'd1;
|
2030 |
|
|
endcase
|
2031 |
|
|
else
|
2032 |
|
|
adr <= to_adr[3:0];
|
2033 |
|
|
end
|
2034 |
|
|
endgenerate
|
2035 |
|
|
generate
|
2036 |
|
|
if (adr_width > max_burst_width) begin : pass_through
|
2037 |
|
|
assign adr_o[adr_width-1:max_burst_width] = adr_i[adr_width-1:max_burst_width];
|
2038 |
|
|
end
|
2039 |
|
|
endgenerate
|
2040 |
|
|
endmodule
|
2041 |
|
|
// async wb3 - wb3 bridge
|
2042 |
|
|
`timescale 1ns/1ns
|
2043 |
18 |
unneback |
module vl_wb3wb3_bridge (
|
2044 |
12 |
unneback |
// wishbone slave side
|
2045 |
|
|
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
|
2046 |
|
|
// wishbone master side
|
2047 |
|
|
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
|
2048 |
|
|
input [31:0] wbs_dat_i;
|
2049 |
|
|
input [31:2] wbs_adr_i;
|
2050 |
|
|
input [3:0] wbs_sel_i;
|
2051 |
|
|
input [1:0] wbs_bte_i;
|
2052 |
|
|
input [2:0] wbs_cti_i;
|
2053 |
|
|
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
|
2054 |
|
|
output [31:0] wbs_dat_o;
|
2055 |
14 |
unneback |
output wbs_ack_o;
|
2056 |
12 |
unneback |
input wbs_clk, wbs_rst;
|
2057 |
|
|
output [31:0] wbm_dat_o;
|
2058 |
|
|
output reg [31:2] wbm_adr_o;
|
2059 |
|
|
output [3:0] wbm_sel_o;
|
2060 |
|
|
output reg [1:0] wbm_bte_o;
|
2061 |
|
|
output reg [2:0] wbm_cti_o;
|
2062 |
14 |
unneback |
output reg wbm_we_o;
|
2063 |
|
|
output wbm_cyc_o;
|
2064 |
12 |
unneback |
output wbm_stb_o;
|
2065 |
|
|
input [31:0] wbm_dat_i;
|
2066 |
|
|
input wbm_ack_i;
|
2067 |
|
|
input wbm_clk, wbm_rst;
|
2068 |
|
|
parameter addr_width = 4;
|
2069 |
|
|
// bte
|
2070 |
|
|
parameter linear = 2'b00;
|
2071 |
|
|
parameter wrap4 = 2'b01;
|
2072 |
|
|
parameter wrap8 = 2'b10;
|
2073 |
|
|
parameter wrap16 = 2'b11;
|
2074 |
|
|
// cti
|
2075 |
|
|
parameter classic = 3'b000;
|
2076 |
|
|
parameter incburst = 3'b010;
|
2077 |
|
|
parameter endofburst = 3'b111;
|
2078 |
|
|
parameter wbs_adr = 1'b0;
|
2079 |
|
|
parameter wbs_data = 1'b1;
|
2080 |
33 |
unneback |
parameter wbm_adr0 = 2'b00;
|
2081 |
|
|
parameter wbm_adr1 = 2'b01;
|
2082 |
|
|
parameter wbm_data = 2'b10;
|
2083 |
|
|
parameter wbm_data_wait = 2'b11;
|
2084 |
12 |
unneback |
reg [1:0] wbs_bte_reg;
|
2085 |
|
|
reg wbs;
|
2086 |
|
|
wire wbs_eoc_alert, wbm_eoc_alert;
|
2087 |
|
|
reg wbs_eoc, wbm_eoc;
|
2088 |
|
|
reg [1:0] wbm;
|
2089 |
14 |
unneback |
wire [1:16] wbs_count, wbm_count;
|
2090 |
12 |
unneback |
wire [35:0] a_d, a_q, b_d, b_q;
|
2091 |
|
|
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
|
2092 |
|
|
reg a_rd_reg;
|
2093 |
|
|
wire b_rd_adr, b_rd_data;
|
2094 |
14 |
unneback |
wire b_rd_data_reg;
|
2095 |
|
|
wire [35:0] temp;
|
2096 |
12 |
unneback |
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
|
2097 |
|
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
2098 |
|
|
if (wbs_rst)
|
2099 |
|
|
wbs_eoc <= 1'b0;
|
2100 |
|
|
else
|
2101 |
|
|
if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
|
2102 |
78 |
unneback |
wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111);
|
2103 |
12 |
unneback |
else if (wbs_eoc_alert & (a_rd | a_wr))
|
2104 |
|
|
wbs_eoc <= 1'b1;
|
2105 |
18 |
unneback |
vl_cnt_shreg_ce_clear # ( .length(16))
|
2106 |
12 |
unneback |
cnt0 (
|
2107 |
|
|
.cke(wbs_ack_o),
|
2108 |
|
|
.clear(wbs_eoc),
|
2109 |
|
|
.q(wbs_count),
|
2110 |
|
|
.rst(wbs_rst),
|
2111 |
|
|
.clk(wbs_clk));
|
2112 |
|
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
2113 |
|
|
if (wbs_rst)
|
2114 |
|
|
wbs <= wbs_adr;
|
2115 |
|
|
else
|
2116 |
75 |
unneback |
if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)
|
2117 |
12 |
unneback |
wbs <= wbs_data;
|
2118 |
|
|
else if (wbs_eoc & wbs_ack_o)
|
2119 |
|
|
wbs <= wbs_adr;
|
2120 |
|
|
// wbs FIFO
|
2121 |
75 |
unneback |
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};
|
2122 |
|
|
assign a_wr = (wbs==wbs_adr) ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :
|
2123 |
12 |
unneback |
(wbs==wbs_data) ? wbs_we_i & wbs_stb_i & !a_fifo_full :
|
2124 |
|
|
1'b0;
|
2125 |
|
|
assign a_rd = !a_fifo_empty;
|
2126 |
|
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
2127 |
|
|
if (wbs_rst)
|
2128 |
|
|
a_rd_reg <= 1'b0;
|
2129 |
|
|
else
|
2130 |
|
|
a_rd_reg <= a_rd;
|
2131 |
|
|
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
|
2132 |
|
|
assign wbs_dat_o = a_q[35:4];
|
2133 |
|
|
always @ (posedge wbs_clk or posedge wbs_rst)
|
2134 |
|
|
if (wbs_rst)
|
2135 |
13 |
unneback |
wbs_bte_reg <= 2'b00;
|
2136 |
12 |
unneback |
else
|
2137 |
13 |
unneback |
wbs_bte_reg <= wbs_bte_i;
|
2138 |
12 |
unneback |
// wbm FIFO
|
2139 |
|
|
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
|
2140 |
|
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
2141 |
|
|
if (wbm_rst)
|
2142 |
|
|
wbm_eoc <= 1'b0;
|
2143 |
|
|
else
|
2144 |
|
|
if (wbm==wbm_adr0 & !b_fifo_empty)
|
2145 |
|
|
wbm_eoc <= b_q[4:3] == linear;
|
2146 |
|
|
else if (wbm_eoc_alert & wbm_ack_i)
|
2147 |
|
|
wbm_eoc <= 1'b1;
|
2148 |
|
|
always @ (posedge wbm_clk or posedge wbm_rst)
|
2149 |
|
|
if (wbm_rst)
|
2150 |
|
|
wbm <= wbm_adr0;
|
2151 |
|
|
else
|
2152 |
33 |
unneback |
/*
|
2153 |
12 |
unneback |
if ((wbm==wbm_adr0 & !b_fifo_empty) |
|
2154 |
|
|
(wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
|
2155 |
|
|
(wbm==wbm_adr1 & !wbm_we_o) |
|
2156 |
|
|
(wbm==wbm_data & wbm_ack_i & wbm_eoc))
|
2157 |
|
|
wbm <= {wbm[0],!(wbm[1] ^ wbm[0])}; // count sequence 00,01,10
|
2158 |
33 |
unneback |
*/
|
2159 |
|
|
case (wbm)
|
2160 |
|
|
wbm_adr0:
|
2161 |
|
|
if (!b_fifo_empty)
|
2162 |
|
|
wbm <= wbm_adr1;
|
2163 |
|
|
wbm_adr1:
|
2164 |
|
|
if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
|
2165 |
|
|
wbm <= wbm_data;
|
2166 |
|
|
wbm_data:
|
2167 |
|
|
if (wbm_ack_i & wbm_eoc)
|
2168 |
|
|
wbm <= wbm_adr0;
|
2169 |
|
|
else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
|
2170 |
|
|
wbm <= wbm_data_wait;
|
2171 |
|
|
wbm_data_wait:
|
2172 |
|
|
if (!b_fifo_empty)
|
2173 |
|
|
wbm <= wbm_data;
|
2174 |
|
|
endcase
|
2175 |
12 |
unneback |
assign b_d = {wbm_dat_i,4'b1111};
|
2176 |
|
|
assign b_wr = !wbm_we_o & wbm_ack_i;
|
2177 |
|
|
assign b_rd_adr = (wbm==wbm_adr0 & !b_fifo_empty);
|
2178 |
|
|
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
|
2179 |
|
|
(wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
|
2180 |
33 |
unneback |
(wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
|
2181 |
12 |
unneback |
1'b0;
|
2182 |
|
|
assign b_rd = b_rd_adr | b_rd_data;
|
2183 |
18 |
unneback |
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
|
2184 |
|
|
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
|
2185 |
12 |
unneback |
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
|
2186 |
18 |
unneback |
vl_cnt_shreg_ce_clear # ( .length(16))
|
2187 |
12 |
unneback |
cnt1 (
|
2188 |
|
|
.cke(wbm_ack_i),
|
2189 |
|
|
.clear(wbm_eoc),
|
2190 |
|
|
.q(wbm_count),
|
2191 |
|
|
.rst(wbm_rst),
|
2192 |
|
|
.clk(wbm_clk));
|
2193 |
33 |
unneback |
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
|
2194 |
|
|
assign wbm_stb_o = (wbm==wbm_data);
|
2195 |
12 |
unneback |
always @ (posedge wbm_clk or posedge wbm_rst)
|
2196 |
|
|
if (wbm_rst)
|
2197 |
|
|
{wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
|
2198 |
|
|
else begin
|
2199 |
|
|
if (wbm==wbm_adr0 & !b_fifo_empty)
|
2200 |
|
|
{wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
|
2201 |
|
|
else if (wbm_eoc_alert & wbm_ack_i)
|
2202 |
|
|
wbm_cti_o <= endofburst;
|
2203 |
|
|
end
|
2204 |
|
|
//async_fifo_dw_simplex_top
|
2205 |
|
|
vl_fifo_2r2w_async_simplex
|
2206 |
|
|
# ( .data_width(36), .addr_width(addr_width))
|
2207 |
|
|
fifo (
|
2208 |
|
|
// a side
|
2209 |
|
|
.a_d(a_d),
|
2210 |
|
|
.a_wr(a_wr),
|
2211 |
|
|
.a_fifo_full(a_fifo_full),
|
2212 |
|
|
.a_q(a_q),
|
2213 |
|
|
.a_rd(a_rd),
|
2214 |
|
|
.a_fifo_empty(a_fifo_empty),
|
2215 |
|
|
.a_clk(wbs_clk),
|
2216 |
|
|
.a_rst(wbs_rst),
|
2217 |
|
|
// b side
|
2218 |
|
|
.b_d(b_d),
|
2219 |
|
|
.b_wr(b_wr),
|
2220 |
|
|
.b_fifo_full(b_fifo_full),
|
2221 |
|
|
.b_q(b_q),
|
2222 |
|
|
.b_rd(b_rd),
|
2223 |
|
|
.b_fifo_empty(b_fifo_empty),
|
2224 |
|
|
.b_clk(wbm_clk),
|
2225 |
|
|
.b_rst(wbm_rst)
|
2226 |
|
|
);
|
2227 |
|
|
endmodule
|
2228 |
75 |
unneback |
module vl_wb3avalon_bridge (
|
2229 |
|
|
// wishbone slave side
|
2230 |
|
|
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
|
2231 |
77 |
unneback |
// avalon master side
|
2232 |
75 |
unneback |
readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
|
2233 |
85 |
unneback |
parameter linewrapburst = 1'b0;
|
2234 |
75 |
unneback |
input [31:0] wbs_dat_i;
|
2235 |
|
|
input [31:2] wbs_adr_i;
|
2236 |
|
|
input [3:0] wbs_sel_i;
|
2237 |
|
|
input [1:0] wbs_bte_i;
|
2238 |
|
|
input [2:0] wbs_cti_i;
|
2239 |
83 |
unneback |
input wbs_we_i;
|
2240 |
|
|
input wbs_cyc_i;
|
2241 |
|
|
input wbs_stb_i;
|
2242 |
75 |
unneback |
output [31:0] wbs_dat_o;
|
2243 |
|
|
output wbs_ack_o;
|
2244 |
|
|
input wbs_clk, wbs_rst;
|
2245 |
|
|
input [31:0] readdata;
|
2246 |
|
|
output [31:0] writedata;
|
2247 |
|
|
output [31:2] address;
|
2248 |
|
|
output [3:0] be;
|
2249 |
|
|
output write;
|
2250 |
81 |
unneback |
output read;
|
2251 |
75 |
unneback |
output beginbursttransfer;
|
2252 |
|
|
output [3:0] burstcount;
|
2253 |
|
|
input readdatavalid;
|
2254 |
|
|
input waitrequest;
|
2255 |
|
|
input clk;
|
2256 |
|
|
input rst;
|
2257 |
|
|
wire [1:0] wbm_bte_o;
|
2258 |
|
|
wire [2:0] wbm_cti_o;
|
2259 |
|
|
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
|
2260 |
|
|
reg last_cyc;
|
2261 |
79 |
unneback |
reg [3:0] counter;
|
2262 |
82 |
unneback |
reg read_busy;
|
2263 |
75 |
unneback |
always @ (posedge clk or posedge rst)
|
2264 |
|
|
if (rst)
|
2265 |
|
|
last_cyc <= 1'b0;
|
2266 |
|
|
else
|
2267 |
|
|
last_cyc <= wbm_cyc_o;
|
2268 |
79 |
unneback |
always @ (posedge clk or posedge rst)
|
2269 |
|
|
if (rst)
|
2270 |
82 |
unneback |
read_busy <= 1'b0;
|
2271 |
79 |
unneback |
else
|
2272 |
82 |
unneback |
if (read & !waitrequest)
|
2273 |
|
|
read_busy <= 1'b1;
|
2274 |
|
|
else if (wbm_ack_i & wbm_cti_o!=3'b010)
|
2275 |
|
|
read_busy <= 1'b0;
|
2276 |
|
|
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;
|
2277 |
75 |
unneback |
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
|
2278 |
|
|
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
|
2279 |
|
|
(wbm_bte_o==2'b10) ? 4'd8 :
|
2280 |
78 |
unneback |
(wbm_bte_o==2'b11) ? 4'd16:
|
2281 |
|
|
4'd1;
|
2282 |
82 |
unneback |
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);
|
2283 |
79 |
unneback |
always @ (posedge clk or posedge rst)
|
2284 |
|
|
if (rst) begin
|
2285 |
|
|
counter <= 4'd0;
|
2286 |
|
|
end else
|
2287 |
80 |
unneback |
if (wbm_we_o) begin
|
2288 |
|
|
if (!waitrequest & !last_cyc & wbm_cyc_o) begin
|
2289 |
85 |
unneback |
counter <= burstcount -4'd1;
|
2290 |
80 |
unneback |
end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
|
2291 |
|
|
counter <= burstcount;
|
2292 |
|
|
end else if (!waitrequest & wbm_stb_o) begin
|
2293 |
|
|
counter <= counter - 4'd1;
|
2294 |
|
|
end
|
2295 |
82 |
unneback |
end
|
2296 |
81 |
unneback |
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
|
2297 |
77 |
unneback |
vl_wb3wb3_bridge wbwb3inst (
|
2298 |
75 |
unneback |
// wishbone slave side
|
2299 |
|
|
.wbs_dat_i(wbs_dat_i),
|
2300 |
|
|
.wbs_adr_i(wbs_adr_i),
|
2301 |
|
|
.wbs_sel_i(wbs_sel_i),
|
2302 |
|
|
.wbs_bte_i(wbs_bte_i),
|
2303 |
|
|
.wbs_cti_i(wbs_cti_i),
|
2304 |
|
|
.wbs_we_i(wbs_we_i),
|
2305 |
|
|
.wbs_cyc_i(wbs_cyc_i),
|
2306 |
|
|
.wbs_stb_i(wbs_stb_i),
|
2307 |
|
|
.wbs_dat_o(wbs_dat_o),
|
2308 |
|
|
.wbs_ack_o(wbs_ack_o),
|
2309 |
|
|
.wbs_clk(wbs_clk),
|
2310 |
|
|
.wbs_rst(wbs_rst),
|
2311 |
|
|
// wishbone master side
|
2312 |
|
|
.wbm_dat_o(writedata),
|
2313 |
78 |
unneback |
.wbm_adr_o(address),
|
2314 |
75 |
unneback |
.wbm_sel_o(be),
|
2315 |
|
|
.wbm_bte_o(wbm_bte_o),
|
2316 |
|
|
.wbm_cti_o(wbm_cti_o),
|
2317 |
|
|
.wbm_we_o(wbm_we_o),
|
2318 |
|
|
.wbm_cyc_o(wbm_cyc_o),
|
2319 |
|
|
.wbm_stb_o(wbm_stb_o),
|
2320 |
|
|
.wbm_dat_i(readdata),
|
2321 |
|
|
.wbm_ack_i(wbm_ack_i),
|
2322 |
|
|
.wbm_clk(clk),
|
2323 |
|
|
.wbm_rst(rst));
|
2324 |
|
|
endmodule
|
2325 |
39 |
unneback |
module vl_wb3_arbiter_type1 (
|
2326 |
|
|
wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
|
2327 |
|
|
wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
|
2328 |
|
|
wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
|
2329 |
|
|
wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
|
2330 |
|
|
wb_clk, wb_rst
|
2331 |
|
|
);
|
2332 |
|
|
parameter nr_of_ports = 3;
|
2333 |
|
|
parameter adr_size = 26;
|
2334 |
|
|
parameter adr_lo = 2;
|
2335 |
|
|
parameter dat_size = 32;
|
2336 |
|
|
parameter sel_size = dat_size/8;
|
2337 |
|
|
localparam aw = (adr_size - adr_lo) * nr_of_ports;
|
2338 |
|
|
localparam dw = dat_size * nr_of_ports;
|
2339 |
|
|
localparam sw = sel_size * nr_of_ports;
|
2340 |
|
|
localparam cw = 3 * nr_of_ports;
|
2341 |
|
|
localparam bw = 2 * nr_of_ports;
|
2342 |
|
|
input [dw-1:0] wbm_dat_o;
|
2343 |
|
|
input [aw-1:0] wbm_adr_o;
|
2344 |
|
|
input [sw-1:0] wbm_sel_o;
|
2345 |
|
|
input [cw-1:0] wbm_cti_o;
|
2346 |
|
|
input [bw-1:0] wbm_bte_o;
|
2347 |
|
|
input [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
|
2348 |
|
|
output [dw-1:0] wbm_dat_i;
|
2349 |
|
|
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
|
2350 |
|
|
output [dat_size-1:0] wbs_dat_i;
|
2351 |
|
|
output [adr_size-1:adr_lo] wbs_adr_i;
|
2352 |
|
|
output [sel_size-1:0] wbs_sel_i;
|
2353 |
|
|
output [2:0] wbs_cti_i;
|
2354 |
|
|
output [1:0] wbs_bte_i;
|
2355 |
|
|
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
|
2356 |
|
|
input [dat_size-1:0] wbs_dat_o;
|
2357 |
|
|
input wbs_ack_o, wbs_err_o, wbs_rty_o;
|
2358 |
|
|
input wb_clk, wb_rst;
|
2359 |
44 |
unneback |
reg [nr_of_ports-1:0] select;
|
2360 |
39 |
unneback |
wire [nr_of_ports-1:0] state;
|
2361 |
|
|
wire [nr_of_ports-1:0] eoc; // end-of-cycle
|
2362 |
|
|
wire [nr_of_ports-1:0] sel;
|
2363 |
|
|
wire idle;
|
2364 |
|
|
genvar i;
|
2365 |
|
|
assign idle = !(|state);
|
2366 |
|
|
generate
|
2367 |
|
|
if (nr_of_ports == 2) begin
|
2368 |
|
|
wire [2:0] wbm1_cti_o, wbm0_cti_o;
|
2369 |
|
|
assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
|
2370 |
44 |
unneback |
//assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
|
2371 |
|
|
always @ (idle or wbm_cyc_o)
|
2372 |
|
|
if (idle)
|
2373 |
|
|
casex (wbm_cyc_o)
|
2374 |
|
|
2'b1x : select = 2'b10;
|
2375 |
|
|
2'b01 : select = 2'b01;
|
2376 |
|
|
default : select = {nr_of_ports{1'b0}};
|
2377 |
|
|
endcase
|
2378 |
|
|
else
|
2379 |
|
|
select = {nr_of_ports{1'b0}};
|
2380 |
39 |
unneback |
assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
|
2381 |
|
|
assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
|
2382 |
|
|
end
|
2383 |
|
|
endgenerate
|
2384 |
|
|
generate
|
2385 |
|
|
if (nr_of_ports == 3) begin
|
2386 |
|
|
wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
|
2387 |
|
|
assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
|
2388 |
44 |
unneback |
always @ (idle or wbm_cyc_o)
|
2389 |
|
|
if (idle)
|
2390 |
|
|
casex (wbm_cyc_o)
|
2391 |
|
|
3'b1xx : select = 3'b100;
|
2392 |
|
|
3'b01x : select = 3'b010;
|
2393 |
|
|
3'b001 : select = 3'b001;
|
2394 |
|
|
default : select = {nr_of_ports{1'b0}};
|
2395 |
|
|
endcase
|
2396 |
|
|
else
|
2397 |
|
|
select = {nr_of_ports{1'b0}};
|
2398 |
|
|
// assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
|
2399 |
39 |
unneback |
assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
|
2400 |
|
|
assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
|
2401 |
|
|
assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
|
2402 |
|
|
end
|
2403 |
|
|
endgenerate
|
2404 |
|
|
generate
|
2405 |
44 |
unneback |
if (nr_of_ports == 4) begin
|
2406 |
|
|
wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o
|