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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Blame information for rev 111

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1 60 unneback
// default SYN_KEEP definition
2 97 unneback
// size to width
3 6 unneback
//////////////////////////////////////////////////////////////////////
4
////                                                              ////
5
////  Versatile library, clock and reset                          ////
6
////                                                              ////
7
////  Description                                                 ////
8
////  Logic related to clock and reset                            ////
9
////                                                              ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   - add more different registers                             ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Michael Unneback, unneback@opencores.org              ////
16
////        ORSoC AB                                              ////
17
////                                                              ////
18
//////////////////////////////////////////////////////////////////////
19
////                                                              ////
20
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
21
////                                                              ////
22
//// This source file may be used and distributed without         ////
23
//// restriction provided that this copyright statement is not    ////
24
//// removed from the file and that any derivative work contains  ////
25
//// the original copyright notice and the associated disclaimer. ////
26
////                                                              ////
27
//// This source file is free software; you can redistribute it   ////
28
//// and/or modify it under the terms of the GNU Lesser General   ////
29
//// Public License as published by the Free Software Foundation; ////
30
//// either version 2.1 of the License, or (at your option) any   ////
31
//// later version.                                               ////
32
////                                                              ////
33
//// This source is distributed in the hope that it will be       ////
34
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
35
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
36
//// PURPOSE.  See the GNU Lesser General Public License for more ////
37
//// details.                                                     ////
38
////                                                              ////
39
//// You should have received a copy of the GNU Lesser General    ////
40
//// Public License along with this source; if not, download it   ////
41
//// from http://www.opencores.org/lgpl.shtml                     ////
42
////                                                              ////
43
//////////////////////////////////////////////////////////////////////
44 21 unneback
//altera
45 33 unneback
module vl_gbuf ( i, o);
46
input i;
47
output o;
48
assign o = i;
49
endmodule
50 6 unneback
 // ALTERA
51
 //ACTEL
52
// sync reset
53 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
54 6 unneback
// output active high global reset sync with two DFFs 
55
`timescale 1 ns/100 ps
56
module vl_sync_rst ( rst_n_i, rst_o, clk);
57
input rst_n_i, clk;
58
output rst_o;
59 18 unneback
reg [1:0] tmp;
60 6 unneback
always @ (posedge clk or negedge rst_n_i)
61
if (!rst_n_i)
62 17 unneback
        tmp <= 2'b11;
63 6 unneback
else
64 33 unneback
        tmp <= {1'b0,tmp[1]};
65 17 unneback
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
66 6 unneback
endmodule
67
// vl_pll
68 32 unneback
///////////////////////////////////////////////////////////////////////////////
69
`timescale 1 ps/1 ps
70
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
71
parameter index = 0;
72
parameter number_of_clk = 1;
73
parameter period_time_0 = 20000;
74
parameter period_time_1 = 20000;
75
parameter period_time_2 = 20000;
76
parameter period_time_3 = 20000;
77
parameter period_time_4 = 20000;
78
parameter lock_delay = 2000000;
79
input clk_i, rst_n_i;
80
output lock;
81
output reg [0:number_of_clk-1] clk_o;
82
output [0:number_of_clk-1] rst_o;
83 33 unneback
`ifdef SIM_PLL
84 32 unneback
always
85
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
86
generate if (number_of_clk > 1)
87
always
88
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
89
endgenerate
90
generate if (number_of_clk > 2)
91
always
92
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
93
endgenerate
94 33 unneback
generate if (number_of_clk > 3)
95 32 unneback
always
96
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
97
endgenerate
98 33 unneback
generate if (number_of_clk > 4)
99 32 unneback
always
100
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
101
endgenerate
102
genvar i;
103
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
104
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
105
end
106
endgenerate
107 33 unneback
//assign #lock_delay lock = rst_n_i;
108
assign lock = rst_n_i;
109 32 unneback
endmodule
110 33 unneback
`else
111
`ifdef VL_PLL0
112
`ifdef VL_PLL0_CLK1
113
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
114
`endif
115
`ifdef VL_PLL0_CLK2
116
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
117
`endif
118
`ifdef VL_PLL0_CLK3
119
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
120
`endif
121
`ifdef VL_PLL0_CLK4
122
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
123
`endif
124
`ifdef VL_PLL0_CLK5
125
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
126
`endif
127
`endif
128
`ifdef VL_PLL1
129
`ifdef VL_PLL1_CLK1
130
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
131
`endif
132
`ifdef VL_PLL1_CLK2
133
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
134
`endif
135
`ifdef VL_PLL1_CLK3
136
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
137
`endif
138
`ifdef VL_PLL1_CLK4
139
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
140
`endif
141
`ifdef VL_PLL1_CLK5
142
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
143
`endif
144
`endif
145
`ifdef VL_PLL2
146
`ifdef VL_PLL2_CLK1
147
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
148
`endif
149
`ifdef VL_PLL2_CLK2
150
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
151
`endif
152
`ifdef VL_PLL2_CLK3
153
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
154
`endif
155
`ifdef VL_PLL2_CLK4
156
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
157
`endif
158
`ifdef VL_PLL2_CLK5
159
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
160
`endif
161
`endif
162
`ifdef VL_PLL3
163
`ifdef VL_PLL3_CLK1
164
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
165
`endif
166
`ifdef VL_PLL3_CLK2
167
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
168
`endif
169
`ifdef VL_PLL3_CLK3
170
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
171
`endif
172
`ifdef VL_PLL3_CLK4
173
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
174
`endif
175
`ifdef VL_PLL3_CLK5
176
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
177
`endif
178
`endif
179 32 unneback
genvar i;
180
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
181 40 unneback
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
182 32 unneback
end
183
endgenerate
184
endmodule
185 33 unneback
`endif
186 32 unneback
///////////////////////////////////////////////////////////////////////////////
187 6 unneback
 //altera
188
 //actel
189
//////////////////////////////////////////////////////////////////////
190
////                                                              ////
191
////  Versatile library, registers                                ////
192
////                                                              ////
193
////  Description                                                 ////
194
////  Different type of registers                                 ////
195
////                                                              ////
196
////                                                              ////
197
////  To Do:                                                      ////
198
////   - add more different registers                             ////
199
////                                                              ////
200
////  Author(s):                                                  ////
201
////      - Michael Unneback, unneback@opencores.org              ////
202
////        ORSoC AB                                              ////
203
////                                                              ////
204
//////////////////////////////////////////////////////////////////////
205
////                                                              ////
206
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
207
////                                                              ////
208
//// This source file may be used and distributed without         ////
209
//// restriction provided that this copyright statement is not    ////
210
//// removed from the file and that any derivative work contains  ////
211
//// the original copyright notice and the associated disclaimer. ////
212
////                                                              ////
213
//// This source file is free software; you can redistribute it   ////
214
//// and/or modify it under the terms of the GNU Lesser General   ////
215
//// Public License as published by the Free Software Foundation; ////
216
//// either version 2.1 of the License, or (at your option) any   ////
217
//// later version.                                               ////
218
////                                                              ////
219
//// This source is distributed in the hope that it will be       ////
220
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
221
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
222
//// PURPOSE.  See the GNU Lesser General Public License for more ////
223
//// details.                                                     ////
224
////                                                              ////
225
//// You should have received a copy of the GNU Lesser General    ////
226
//// Public License along with this source; if not, download it   ////
227
//// from http://www.opencores.org/lgpl.shtml                     ////
228
////                                                              ////
229
//////////////////////////////////////////////////////////////////////
230 18 unneback
module vl_dff ( d, q, clk, rst);
231 6 unneback
        parameter width = 1;
232
        parameter reset_value = 0;
233
        input [width-1:0] d;
234
        input clk, rst;
235
        output reg [width-1:0] q;
236
        always @ (posedge clk or posedge rst)
237
        if (rst)
238
                q <= reset_value;
239
        else
240
                q <= d;
241
endmodule
242 18 unneback
module vl_dff_array ( d, q, clk, rst);
243 6 unneback
        parameter width = 1;
244
        parameter depth = 2;
245
        parameter reset_value = 1'b0;
246
        input [width-1:0] d;
247
        input clk, rst;
248
        output [width-1:0] q;
249
        reg  [0:depth-1] q_tmp [width-1:0];
250
        integer i;
251
        always @ (posedge clk or posedge rst)
252
        if (rst) begin
253
            for (i=0;i<depth;i=i+1)
254
                q_tmp[i] <= {width{reset_value}};
255
        end else begin
256
            q_tmp[0] <= d;
257
            for (i=1;i<depth;i=i+1)
258
                q_tmp[i] <= q_tmp[i-1];
259
        end
260
    assign q = q_tmp[depth-1];
261
endmodule
262 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
263 6 unneback
        parameter width = 1;
264
        parameter reset_value = 0;
265
        input [width-1:0] d;
266
        input ce, clk, rst;
267
        output reg [width-1:0] q;
268
        always @ (posedge clk or posedge rst)
269
        if (rst)
270
                q <= reset_value;
271
        else
272
                if (ce)
273
                        q <= d;
274
endmodule
275 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
276 8 unneback
        parameter width = 1;
277
        parameter reset_value = 0;
278
        input [width-1:0] d;
279 10 unneback
        input ce, clear, clk, rst;
280 8 unneback
        output reg [width-1:0] q;
281
        always @ (posedge clk or posedge rst)
282
        if (rst)
283
            q <= reset_value;
284
        else
285
            if (ce)
286
                if (clear)
287
                    q <= {width{1'b0}};
288
                else
289
                    q <= d;
290
endmodule
291 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
292
        parameter width = 1;
293
        parameter reset_value = 0;
294
        input [width-1:0] d;
295
        input ce, set, clk, rst;
296
        output reg [width-1:0] q;
297
        always @ (posedge clk or posedge rst)
298
        if (rst)
299
            q <= reset_value;
300
        else
301
            if (ce)
302
                if (set)
303
                    q <= {width{1'b1}};
304
                else
305
                    q <= d;
306
endmodule
307 29 unneback
module vl_spr ( sp, r, q, clk, rst);
308 64 unneback
        //parameter width = 1;
309
        parameter reset_value = 1'b0;
310 29 unneback
        input sp, r;
311
        output reg q;
312
        input clk, rst;
313
        always @ (posedge clk or posedge rst)
314
        if (rst)
315
            q <= reset_value;
316
        else
317
            if (sp)
318
                q <= 1'b1;
319
            else if (r)
320
                q <= 1'b0;
321
endmodule
322
module vl_srp ( s, rp, q, clk, rst);
323
        parameter width = 1;
324
        parameter reset_value = 0;
325
        input s, rp;
326
        output reg q;
327
        input clk, rst;
328
        always @ (posedge clk or posedge rst)
329
        if (rst)
330
            q <= reset_value;
331
        else
332
            if (rp)
333
                q <= 1'b0;
334
            else if (s)
335
                q <= 1'b1;
336
endmodule
337 6 unneback
// megafunction wizard: %LPM_FF%
338
// GENERATION: STANDARD
339
// VERSION: WM1.0
340
// MODULE: lpm_ff 
341
// ============================================================
342
// File Name: dff_sr.v
343
// Megafunction Name(s):
344
//                      lpm_ff
345
//
346
// Simulation Library Files(s):
347
//                      lpm
348
// ============================================================
349
// ************************************************************
350
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
351
//
352
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
353
// ************************************************************
354
//Copyright (C) 1991-2010 Altera Corporation
355
//Your use of Altera Corporation's design tools, logic functions 
356
//and other software and tools, and its AMPP partner logic 
357
//functions, and any output files from any of the foregoing 
358
//(including device programming or simulation files), and any 
359
//associated documentation or information are expressly subject 
360
//to the terms and conditions of the Altera Program License 
361
//Subscription Agreement, Altera MegaCore Function License 
362
//Agreement, or other applicable license agreement, including, 
363
//without limitation, that your use is for the sole purpose of 
364
//programming logic devices manufactured by Altera and sold by 
365
//Altera or its authorized distributors.  Please refer to the 
366
//applicable agreement for further details.
367
// synopsys translate_off
368
`timescale 1 ps / 1 ps
369
// synopsys translate_on
370 18 unneback
module vl_dff_sr (
371 6 unneback
        aclr,
372
        aset,
373
        clock,
374
        data,
375
        q);
376
        input     aclr;
377
        input     aset;
378
        input     clock;
379
        input     data;
380
        output    q;
381
        wire [0:0] sub_wire0;
382
        wire [0:0] sub_wire1 = sub_wire0[0:0];
383
        wire  q = sub_wire1;
384
        wire  sub_wire2 = data;
385
        wire  sub_wire3 = sub_wire2;
386
        lpm_ff  lpm_ff_component (
387
                                .aclr (aclr),
388
                                .clock (clock),
389
                                .data (sub_wire3),
390
                                .aset (aset),
391
                                .q (sub_wire0)
392
                                // synopsys translate_off
393
                                ,
394
                                .aload (),
395
                                .enable (),
396
                                .sclr (),
397
                                .sload (),
398
                                .sset ()
399
                                // synopsys translate_on
400
                                );
401
        defparam
402
                lpm_ff_component.lpm_fftype = "DFF",
403
                lpm_ff_component.lpm_type = "LPM_FF",
404
                lpm_ff_component.lpm_width = 1;
405
endmodule
406
// ============================================================
407
// CNX file retrieval info
408
// ============================================================
409
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
410
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
411
// Retrieval info: PRIVATE: ASET NUMERIC "1"
412
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
413
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
414
// Retrieval info: PRIVATE: DFF NUMERIC "1"
415
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
416
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
417
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
418
// Retrieval info: PRIVATE: SSET NUMERIC "0"
419
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
420
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
421
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
422
// Retrieval info: PRIVATE: nBit NUMERIC "1"
423
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
424
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
425
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
426
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
427
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
428
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
429
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
430
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
431
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
432
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
433
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
434
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
435
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
436
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
437
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
438
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
439
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
440
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
441
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
442
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
443
// Retrieval info: LIB_FILE: lpm
444
// LATCH
445
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
446 18 unneback
module vl_latch ( d, le, q, clk);
447 6 unneback
input d, le;
448
output q;
449
input clk;
450
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
451
endmodule
452 18 unneback
module vl_shreg ( d, q, clk, rst);
453 17 unneback
parameter depth = 10;
454
input d;
455
output q;
456
input clk, rst;
457
reg [1:depth] dffs;
458
always @ (posedge clk or posedge rst)
459
if (rst)
460
    dffs <= {depth{1'b0}};
461
else
462
    dffs <= {d,dffs[1:depth-1]};
463
assign q = dffs[depth];
464
endmodule
465 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
466 17 unneback
parameter depth = 10;
467
input d, ce;
468
output q;
469
input clk, rst;
470
reg [1:depth] dffs;
471
always @ (posedge clk or posedge rst)
472
if (rst)
473
    dffs <= {depth{1'b0}};
474
else
475
    if (ce)
476
        dffs <= {d,dffs[1:depth-1]};
477
assign q = dffs[depth];
478
endmodule
479 18 unneback
module vl_delay ( d, q, clk, rst);
480 15 unneback
parameter depth = 10;
481
input d;
482
output q;
483
input clk, rst;
484
reg [1:depth] dffs;
485
always @ (posedge clk or posedge rst)
486
if (rst)
487
    dffs <= {depth{1'b0}};
488
else
489
    dffs <= {d,dffs[1:depth-1]};
490
assign q = dffs[depth];
491
endmodule
492 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
493 17 unneback
parameter depth = 10;
494
input d;
495
output q, emptyflag;
496
input clk, rst;
497
reg [1:depth] dffs;
498
always @ (posedge clk or posedge rst)
499
if (rst)
500
    dffs <= {depth{1'b0}};
501
else
502
    dffs <= {d,dffs[1:depth-1]};
503
assign q = dffs[depth];
504
assign emptyflag = !(|dffs);
505
endmodule
506 98 unneback
module vl_pulse2toggle ( pl, q, clk, rst);
507 94 unneback
input pl;
508 98 unneback
output reg q;
509 94 unneback
input clk, rst;
510
always @ (posedge clk or posedge rst)
511
if (rst)
512
    q <= 1'b0;
513
else
514
    q <= pl ^ q;
515
endmodule
516 98 unneback
module vl_toggle2pulse (d, pl, clk, rst);
517 94 unneback
input d;
518
output pl;
519
input clk, rst;
520
reg dff;
521
always @ (posedge clk or posedge rst)
522
if (rst)
523
    dff <= 1'b0;
524
else
525
    dff <= d;
526 98 unneback
assign pl = d ^ dff;
527 94 unneback
endmodule
528
module vl_synchronizer (d, q, clk, rst);
529
input d;
530
output reg q;
531
output clk, rst;
532
reg dff;
533
always @ (posedge clk or posedge rst)
534
if (rst)
535 100 unneback
    {q,dff} <= 2'b00;
536 94 unneback
else
537 100 unneback
    {q,dff} <= {dff,d};
538 94 unneback
endmodule
539 97 unneback
module vl_cdc ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst);
540 94 unneback
input start_pl;
541
output take_it_pl;
542
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
543
output got_it_pl;
544
input clk_src, rst_src;
545
input clk_dst, rst_dst;
546
wire take_it_tg, take_it_tg_sync;
547
wire got_it_tg, got_it_tg_sync;
548
// src -> dst
549
vl_pulse2toggle p2t0 (
550
    .pl(start_pl),
551
    .q(take_it_tg),
552
    .clk(clk_src),
553
    .rst(rst_src));
554
vl_synchronizer sync0 (
555
    .d(take_it_tg),
556
    .q(take_it_tg_sync),
557
    .clk(clk_dst),
558
    .rst(rst_dst));
559
vl_toggle2pulse t2p0 (
560 100 unneback
    .d(take_it_tg_sync),
561 94 unneback
    .pl(take_it_pl),
562
    .clk(clk_dst),
563
    .rst(rst_dst));
564
// dst -> src
565 98 unneback
vl_pulse2toggle p2t1 (
566 94 unneback
    .pl(take_it_grant_pl),
567
    .q(got_it_tg),
568
    .clk(clk_dst),
569
    .rst(rst_dst));
570
vl_synchronizer sync1 (
571
    .d(got_it_tg),
572
    .q(got_it_tg_sync),
573
    .clk(clk_src),
574
    .rst(rst_src));
575
vl_toggle2pulse t2p1 (
576 100 unneback
    .d(got_it_tg_sync),
577 94 unneback
    .pl(got_it_pl),
578
    .clk(clk_src),
579
    .rst(rst_src));
580
endmodule
581 6 unneback
//////////////////////////////////////////////////////////////////////
582
////                                                              ////
583 18 unneback
////  Logic functions                                             ////
584
////                                                              ////
585
////  Description                                                 ////
586
////  Logic functions such as multiplexers                        ////
587
////                                                              ////
588
////                                                              ////
589
////  To Do:                                                      ////
590
////   -                                                          ////
591
////                                                              ////
592
////  Author(s):                                                  ////
593
////      - Michael Unneback, unneback@opencores.org              ////
594
////        ORSoC AB                                              ////
595
////                                                              ////
596
//////////////////////////////////////////////////////////////////////
597
////                                                              ////
598
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
599
////                                                              ////
600
//// This source file may be used and distributed without         ////
601
//// restriction provided that this copyright statement is not    ////
602
//// removed from the file and that any derivative work contains  ////
603
//// the original copyright notice and the associated disclaimer. ////
604
////                                                              ////
605
//// This source file is free software; you can redistribute it   ////
606
//// and/or modify it under the terms of the GNU Lesser General   ////
607
//// Public License as published by the Free Software Foundation; ////
608
//// either version 2.1 of the License, or (at your option) any   ////
609
//// later version.                                               ////
610
////                                                              ////
611
//// This source is distributed in the hope that it will be       ////
612
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
613
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
614
//// PURPOSE.  See the GNU Lesser General Public License for more ////
615
//// details.                                                     ////
616
////                                                              ////
617
//// You should have received a copy of the GNU Lesser General    ////
618
//// Public License along with this source; if not, download it   ////
619
//// from http://www.opencores.org/lgpl.shtml                     ////
620
////                                                              ////
621
//////////////////////////////////////////////////////////////////////
622 36 unneback
module vl_mux_andor ( a, sel, dout);
623
parameter width = 32;
624
parameter nr_of_ports = 4;
625
input [nr_of_ports*width-1:0] a;
626
input [nr_of_ports-1:0] sel;
627
output reg [width-1:0] dout;
628 38 unneback
integer i,j;
629 36 unneback
always @ (a, sel)
630
begin
631
    dout = a[width-1:0] & {width{sel[0]}};
632 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
633
        for (j=0;j<width;j=j+1)
634
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
635 36 unneback
end
636
endmodule
637 34 unneback
module vl_mux2_andor ( a1, a0, sel, dout);
638
parameter width = 32;
639 35 unneback
localparam nr_of_ports = 2;
640 34 unneback
input [width-1:0] a1, a0;
641
input [nr_of_ports-1:0] sel;
642
output [width-1:0] dout;
643 36 unneback
vl_mux_andor
644 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
645 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
646 34 unneback
endmodule
647
module vl_mux3_andor ( a2, a1, a0, sel, dout);
648
parameter width = 32;
649 35 unneback
localparam nr_of_ports = 3;
650 34 unneback
input [width-1:0] a2, a1, a0;
651
input [nr_of_ports-1:0] sel;
652
output [width-1:0] dout;
653 36 unneback
vl_mux_andor
654 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
655 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
656 34 unneback
endmodule
657 18 unneback
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
658
parameter width = 32;
659 35 unneback
localparam nr_of_ports = 4;
660 18 unneback
input [width-1:0] a3, a2, a1, a0;
661
input [nr_of_ports-1:0] sel;
662 22 unneback
output [width-1:0] dout;
663 36 unneback
vl_mux_andor
664 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
665 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
666 18 unneback
endmodule
667
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
668
parameter width = 32;
669 35 unneback
localparam nr_of_ports = 5;
670 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
671
input [nr_of_ports-1:0] sel;
672 22 unneback
output [width-1:0] dout;
673 36 unneback
vl_mux_andor
674 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
675 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
676 18 unneback
endmodule
677
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
678
parameter width = 32;
679 35 unneback
localparam nr_of_ports = 6;
680 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
681
input [nr_of_ports-1:0] sel;
682 22 unneback
output [width-1:0] dout;
683 36 unneback
vl_mux_andor
684 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
685 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
686 18 unneback
endmodule
687 43 unneback
module vl_parity_generate (data, parity);
688
parameter word_size = 32;
689
parameter chunk_size = 8;
690
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
691
input [word_size-1:0] data;
692
output reg [word_size/chunk_size-1:0] parity;
693
integer i,j;
694
always @ (data)
695
for (i=0;i<word_size/chunk_size;i=i+1) begin
696
    parity[i] = parity_type;
697
    for (j=0;j<chunk_size;j=j+1) begin
698 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
699 43 unneback
    end
700
end
701
endmodule
702
module vl_parity_check( data, parity, parity_error);
703
parameter word_size = 32;
704
parameter chunk_size = 8;
705
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
706
input [word_size-1:0] data;
707
input [word_size/chunk_size-1:0] parity;
708
output parity_error;
709 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
710 43 unneback
integer i,j;
711
always @ (data or parity)
712
for (i=0;i<word_size/chunk_size;i=i+1) begin
713
    error_flag[i] = parity[i] ^ parity_type;
714
    for (j=0;j<chunk_size;j=j+1) begin
715 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
716 43 unneback
    end
717
end
718
assign parity_error = |error_flag;
719
endmodule
720 18 unneback
//////////////////////////////////////////////////////////////////////
721
////                                                              ////
722 44 unneback
////  IO functions                                                ////
723
////                                                              ////
724
////  Description                                                 ////
725
////  IO functions such as IOB flip-flops                         ////
726
////                                                              ////
727
////                                                              ////
728
////  To Do:                                                      ////
729
////   -                                                          ////
730
////                                                              ////
731
////  Author(s):                                                  ////
732
////      - Michael Unneback, unneback@opencores.org              ////
733
////        ORSoC AB                                              ////
734
////                                                              ////
735
//////////////////////////////////////////////////////////////////////
736
////                                                              ////
737
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
738
////                                                              ////
739
//// This source file may be used and distributed without         ////
740
//// restriction provided that this copyright statement is not    ////
741
//// removed from the file and that any derivative work contains  ////
742
//// the original copyright notice and the associated disclaimer. ////
743
////                                                              ////
744
//// This source file is free software; you can redistribute it   ////
745
//// and/or modify it under the terms of the GNU Lesser General   ////
746
//// Public License as published by the Free Software Foundation; ////
747
//// either version 2.1 of the License, or (at your option) any   ////
748
//// later version.                                               ////
749
////                                                              ////
750
//// This source is distributed in the hope that it will be       ////
751
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
752
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
753
//// PURPOSE.  See the GNU Lesser General Public License for more ////
754
//// details.                                                     ////
755
////                                                              ////
756
//// You should have received a copy of the GNU Lesser General    ////
757
//// Public License along with this source; if not, download it   ////
758
//// from http://www.opencores.org/lgpl.shtml                     ////
759
////                                                              ////
760
//////////////////////////////////////////////////////////////////////
761 45 unneback
`timescale 1ns/1ns
762 44 unneback
module vl_o_dff (d_i, o_pad, clk, rst);
763
parameter width = 1;
764 45 unneback
parameter reset_value = {width{1'b0}};
765
input  [width-1:0]  d_i;
766 44 unneback
output [width-1:0] o_pad;
767
input clk, rst;
768 60 unneback
wire [width-1:0] d_i_int /*synthesis syn_keep = 1*/;
769 45 unneback
reg  [width-1:0] o_pad_int;
770 44 unneback
assign d_i_int = d_i;
771
genvar i;
772 45 unneback
generate
773 44 unneback
for (i=0;i<width;i=i+1) begin
774
    always @ (posedge clk or posedge rst)
775
    if (rst)
776 45 unneback
        o_pad_int[i] <= reset_value[i];
777 44 unneback
    else
778 45 unneback
        o_pad_int[i] <= d_i_int[i];
779
    assign #1 o_pad[i] = o_pad_int[i];
780 44 unneback
end
781
endgenerate
782
endmodule
783 45 unneback
`timescale 1ns/1ns
784 44 unneback
module vl_io_dff_oe ( d_i, d_o, oe, io_pad, clk, rst);
785
parameter width = 1;
786
input  [width-1:0] d_o;
787
output reg [width-1:0] d_i;
788
input oe;
789
inout [width-1:0] io_pad;
790
input clk, rst;
791 60 unneback
wire [width-1:0] oe_d /*synthesis syn_keep = 1*/;
792 44 unneback
reg [width-1:0] oe_q;
793
reg [width-1:0] d_o_q;
794
assign oe_d = {width{oe}};
795
genvar i;
796
generate
797
for (i=0;i<width;i=i+1) begin
798
    always @ (posedge clk or posedge rst)
799
    if (rst)
800
        oe_q[i] <= 1'b0;
801
    else
802
        oe_q[i] <= oe_d[i];
803
    always @ (posedge clk or posedge rst)
804
    if (rst)
805
        d_o_q[i] <= 1'b0;
806
    else
807
        d_o_q[i] <= d_o[i];
808
    always @ (posedge clk or posedge rst)
809
    if (rst)
810
        d_i[i] <= 1'b0;
811
    else
812
        d_i[i] <= io_pad[i];
813 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
814 44 unneback
end
815
endgenerate
816
endmodule
817
//////////////////////////////////////////////////////////////////////
818
////                                                              ////
819 6 unneback
////  Versatile counter                                           ////
820
////                                                              ////
821
////  Description                                                 ////
822
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
823
////  counter                                                     ////
824
////                                                              ////
825
////  To Do:                                                      ////
826
////   - add LFSR with more taps                                  ////
827
////                                                              ////
828
////  Author(s):                                                  ////
829
////      - Michael Unneback, unneback@opencores.org              ////
830
////        ORSoC AB                                              ////
831
////                                                              ////
832
//////////////////////////////////////////////////////////////////////
833
////                                                              ////
834
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
835
////                                                              ////
836
//// This source file may be used and distributed without         ////
837
//// restriction provided that this copyright statement is not    ////
838
//// removed from the file and that any derivative work contains  ////
839
//// the original copyright notice and the associated disclaimer. ////
840
////                                                              ////
841
//// This source file is free software; you can redistribute it   ////
842
//// and/or modify it under the terms of the GNU Lesser General   ////
843
//// Public License as published by the Free Software Foundation; ////
844
//// either version 2.1 of the License, or (at your option) any   ////
845
//// later version.                                               ////
846
////                                                              ////
847
//// This source is distributed in the hope that it will be       ////
848
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
849
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
850
//// PURPOSE.  See the GNU Lesser General Public License for more ////
851
//// details.                                                     ////
852
////                                                              ////
853
//// You should have received a copy of the GNU Lesser General    ////
854
//// Public License along with this source; if not, download it   ////
855
//// from http://www.opencores.org/lgpl.shtml                     ////
856
////                                                              ////
857
//////////////////////////////////////////////////////////////////////
858
// binary counter
859 40 unneback
module vl_cnt_bin_ce (
860
 cke, q, rst, clk);
861 22 unneback
   parameter length = 4;
862 6 unneback
   input cke;
863
   output [length:1] q;
864
   input rst;
865
   input clk;
866
   parameter clear_value = 0;
867
   parameter set_value = 1;
868
   parameter wrap_value = 0;
869
   parameter level1_value = 15;
870
   reg  [length:1] qi;
871
   wire [length:1] q_next;
872
   assign q_next = qi + {{length-1{1'b0}},1'b1};
873
   always @ (posedge clk or posedge rst)
874
     if (rst)
875
       qi <= {length{1'b0}};
876
     else
877
     if (cke)
878
       qi <= q_next;
879
   assign q = qi;
880
endmodule
881
//////////////////////////////////////////////////////////////////////
882
////                                                              ////
883
////  Versatile counter                                           ////
884
////                                                              ////
885
////  Description                                                 ////
886
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
887
////  counter                                                     ////
888
////                                                              ////
889
////  To Do:                                                      ////
890
////   - add LFSR with more taps                                  ////
891
////                                                              ////
892
////  Author(s):                                                  ////
893
////      - Michael Unneback, unneback@opencores.org              ////
894
////        ORSoC AB                                              ////
895
////                                                              ////
896
//////////////////////////////////////////////////////////////////////
897
////                                                              ////
898
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
899
////                                                              ////
900
//// This source file may be used and distributed without         ////
901
//// restriction provided that this copyright statement is not    ////
902
//// removed from the file and that any derivative work contains  ////
903
//// the original copyright notice and the associated disclaimer. ////
904
////                                                              ////
905
//// This source file is free software; you can redistribute it   ////
906
//// and/or modify it under the terms of the GNU Lesser General   ////
907
//// Public License as published by the Free Software Foundation; ////
908
//// either version 2.1 of the License, or (at your option) any   ////
909
//// later version.                                               ////
910
////                                                              ////
911
//// This source is distributed in the hope that it will be       ////
912
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
913
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
914
//// PURPOSE.  See the GNU Lesser General Public License for more ////
915
//// details.                                                     ////
916
////                                                              ////
917
//// You should have received a copy of the GNU Lesser General    ////
918
//// Public License along with this source; if not, download it   ////
919
//// from http://www.opencores.org/lgpl.shtml                     ////
920
////                                                              ////
921
//////////////////////////////////////////////////////////////////////
922
// binary counter
923 40 unneback
module vl_cnt_bin_ce_rew_zq_l1 (
924
 cke, rew, zq, level1, rst, clk);
925 6 unneback
   parameter length = 4;
926
   input cke;
927
   input rew;
928 25 unneback
   output reg zq;
929
   output reg level1;
930
   input rst;
931
   input clk;
932
   parameter clear_value = 0;
933
   parameter set_value = 1;
934
   parameter wrap_value = 1;
935
   parameter level1_value = 15;
936 29 unneback
   wire clear;
937 30 unneback
   assign clear = 1'b0;
938 25 unneback
   reg  [length:1] qi;
939
   wire  [length:1] q_next, q_next_fw, q_next_rew;
940
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
941
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
942
   assign q_next = rew ? q_next_rew : q_next_fw;
943
   always @ (posedge clk or posedge rst)
944
     if (rst)
945
       qi <= {length{1'b0}};
946
     else
947
     if (cke)
948
       qi <= q_next;
949
   always @ (posedge clk or posedge rst)
950
     if (rst)
951
       zq <= 1'b1;
952
     else
953
     if (cke)
954
       zq <= q_next == {length{1'b0}};
955
    always @ (posedge clk or posedge rst)
956
    if (rst)
957
        level1 <= 1'b0;
958
    else
959
    if (cke)
960 29 unneback
    if (clear)
961
        level1 <= 1'b0;
962
    else if (q_next == level1_value)
963 25 unneback
        level1 <= 1'b1;
964
    else if (qi == level1_value & rew)
965
        level1 <= 1'b0;
966
endmodule
967
//////////////////////////////////////////////////////////////////////
968
////                                                              ////
969
////  Versatile counter                                           ////
970
////                                                              ////
971
////  Description                                                 ////
972
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
973
////  counter                                                     ////
974
////                                                              ////
975
////  To Do:                                                      ////
976
////   - add LFSR with more taps                                  ////
977
////                                                              ////
978
////  Author(s):                                                  ////
979
////      - Michael Unneback, unneback@opencores.org              ////
980
////        ORSoC AB                                              ////
981
////                                                              ////
982
//////////////////////////////////////////////////////////////////////
983
////                                                              ////
984
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
985
////                                                              ////
986
//// This source file may be used and distributed without         ////
987
//// restriction provided that this copyright statement is not    ////
988
//// removed from the file and that any derivative work contains  ////
989
//// the original copyright notice and the associated disclaimer. ////
990
////                                                              ////
991
//// This source file is free software; you can redistribute it   ////
992
//// and/or modify it under the terms of the GNU Lesser General   ////
993
//// Public License as published by the Free Software Foundation; ////
994
//// either version 2.1 of the License, or (at your option) any   ////
995
//// later version.                                               ////
996
////                                                              ////
997
//// This source is distributed in the hope that it will be       ////
998
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
999
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1000
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1001
//// details.                                                     ////
1002
////                                                              ////
1003
//// You should have received a copy of the GNU Lesser General    ////
1004
//// Public License along with this source; if not, download it   ////
1005
//// from http://www.opencores.org/lgpl.shtml                     ////
1006
////                                                              ////
1007
//////////////////////////////////////////////////////////////////////
1008
// binary counter
1009 40 unneback
module vl_cnt_bin_ce_rew_q_zq_l1 (
1010
 cke, rew, q, zq, level1, rst, clk);
1011 25 unneback
   parameter length = 4;
1012
   input cke;
1013
   input rew;
1014
   output [length:1] q;
1015
   output reg zq;
1016
   output reg level1;
1017
   input rst;
1018
   input clk;
1019
   parameter clear_value = 0;
1020
   parameter set_value = 1;
1021
   parameter wrap_value = 1;
1022
   parameter level1_value = 15;
1023 29 unneback
   wire clear;
1024 30 unneback
   assign clear = 1'b0;
1025 25 unneback
   reg  [length:1] qi;
1026
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1027
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1028
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1029
   assign q_next = rew ? q_next_rew : q_next_fw;
1030
   always @ (posedge clk or posedge rst)
1031
     if (rst)
1032
       qi <= {length{1'b0}};
1033
     else
1034
     if (cke)
1035
       qi <= q_next;
1036
   assign q = qi;
1037
   always @ (posedge clk or posedge rst)
1038
     if (rst)
1039
       zq <= 1'b1;
1040
     else
1041
     if (cke)
1042
       zq <= q_next == {length{1'b0}};
1043
    always @ (posedge clk or posedge rst)
1044
    if (rst)
1045
        level1 <= 1'b0;
1046
    else
1047
    if (cke)
1048 29 unneback
    if (clear)
1049
        level1 <= 1'b0;
1050
    else if (q_next == level1_value)
1051 25 unneback
        level1 <= 1'b1;
1052
    else if (qi == level1_value & rew)
1053
        level1 <= 1'b0;
1054
endmodule
1055
//////////////////////////////////////////////////////////////////////
1056
////                                                              ////
1057
////  Versatile counter                                           ////
1058
////                                                              ////
1059
////  Description                                                 ////
1060
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1061
////  counter                                                     ////
1062
////                                                              ////
1063
////  To Do:                                                      ////
1064
////   - add LFSR with more taps                                  ////
1065
////                                                              ////
1066
////  Author(s):                                                  ////
1067
////      - Michael Unneback, unneback@opencores.org              ////
1068
////        ORSoC AB                                              ////
1069
////                                                              ////
1070
//////////////////////////////////////////////////////////////////////
1071
////                                                              ////
1072
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1073
////                                                              ////
1074
//// This source file may be used and distributed without         ////
1075
//// restriction provided that this copyright statement is not    ////
1076
//// removed from the file and that any derivative work contains  ////
1077
//// the original copyright notice and the associated disclaimer. ////
1078
////                                                              ////
1079
//// This source file is free software; you can redistribute it   ////
1080
//// and/or modify it under the terms of the GNU Lesser General   ////
1081
//// Public License as published by the Free Software Foundation; ////
1082
//// either version 2.1 of the License, or (at your option) any   ////
1083
//// later version.                                               ////
1084
////                                                              ////
1085
//// This source is distributed in the hope that it will be       ////
1086
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1087
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1088
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1089
//// details.                                                     ////
1090
////                                                              ////
1091
//// You should have received a copy of the GNU Lesser General    ////
1092
//// Public License along with this source; if not, download it   ////
1093
//// from http://www.opencores.org/lgpl.shtml                     ////
1094
////                                                              ////
1095
//////////////////////////////////////////////////////////////////////
1096 75 unneback
// LFSR counter
1097
module vl_cnt_lfsr_ce (
1098
 cke, zq, rst, clk);
1099
   parameter length = 4;
1100
   input cke;
1101
   output reg zq;
1102
   input rst;
1103
   input clk;
1104
   parameter clear_value = 0;
1105
   parameter set_value = 1;
1106
   parameter wrap_value = 0;
1107
   parameter level1_value = 15;
1108
   reg  [length:1] qi;
1109
   reg lfsr_fb;
1110
   wire [length:1] q_next;
1111
   reg [32:1] polynom;
1112
   integer i;
1113
   always @ (qi)
1114
   begin
1115
        case (length)
1116
         2: polynom = 32'b11;                               // 0x3
1117
         3: polynom = 32'b110;                              // 0x6
1118
         4: polynom = 32'b1100;                             // 0xC
1119
         5: polynom = 32'b10100;                            // 0x14
1120
         6: polynom = 32'b110000;                           // 0x30
1121
         7: polynom = 32'b1100000;                          // 0x60
1122
         8: polynom = 32'b10111000;                         // 0xb8
1123
         9: polynom = 32'b100010000;                        // 0x110
1124
        10: polynom = 32'b1001000000;                       // 0x240
1125
        11: polynom = 32'b10100000000;                      // 0x500
1126
        12: polynom = 32'b100000101001;                     // 0x829
1127
        13: polynom = 32'b1000000001100;                    // 0x100C
1128
        14: polynom = 32'b10000000010101;                   // 0x2015
1129
        15: polynom = 32'b110000000000000;                  // 0x6000
1130
        16: polynom = 32'b1101000000001000;                 // 0xD008
1131
        17: polynom = 32'b10010000000000000;                // 0x12000
1132
        18: polynom = 32'b100000010000000000;               // 0x20400
1133
        19: polynom = 32'b1000000000000100011;              // 0x40023
1134
        20: polynom = 32'b10010000000000000000;             // 0x90000
1135
        21: polynom = 32'b101000000000000000000;            // 0x140000
1136
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1137
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1138
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1139
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1140
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1141
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1142
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1143
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1144
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1145
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1146
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1147
        default: polynom = 32'b0;
1148
        endcase
1149
        lfsr_fb = qi[length];
1150
        for (i=length-1; i>=1; i=i-1) begin
1151
            if (polynom[i])
1152
                lfsr_fb = lfsr_fb  ~^ qi[i];
1153
        end
1154
    end
1155
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1156
   always @ (posedge clk or posedge rst)
1157
     if (rst)
1158
       qi <= {length{1'b0}};
1159
     else
1160
     if (cke)
1161
       qi <= q_next;
1162
   always @ (posedge clk or posedge rst)
1163
     if (rst)
1164
       zq <= 1'b1;
1165
     else
1166
     if (cke)
1167
       zq <= q_next == {length{1'b0}};
1168
endmodule
1169
//////////////////////////////////////////////////////////////////////
1170
////                                                              ////
1171
////  Versatile counter                                           ////
1172
////                                                              ////
1173
////  Description                                                 ////
1174
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1175
////  counter                                                     ////
1176
////                                                              ////
1177
////  To Do:                                                      ////
1178
////   - add LFSR with more taps                                  ////
1179
////                                                              ////
1180
////  Author(s):                                                  ////
1181
////      - Michael Unneback, unneback@opencores.org              ////
1182
////        ORSoC AB                                              ////
1183
////                                                              ////
1184
//////////////////////////////////////////////////////////////////////
1185
////                                                              ////
1186
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1187
////                                                              ////
1188
//// This source file may be used and distributed without         ////
1189
//// restriction provided that this copyright statement is not    ////
1190
//// removed from the file and that any derivative work contains  ////
1191
//// the original copyright notice and the associated disclaimer. ////
1192
////                                                              ////
1193
//// This source file is free software; you can redistribute it   ////
1194
//// and/or modify it under the terms of the GNU Lesser General   ////
1195
//// Public License as published by the Free Software Foundation; ////
1196
//// either version 2.1 of the License, or (at your option) any   ////
1197
//// later version.                                               ////
1198
////                                                              ////
1199
//// This source is distributed in the hope that it will be       ////
1200
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1201
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1202
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1203
//// details.                                                     ////
1204
////                                                              ////
1205
//// You should have received a copy of the GNU Lesser General    ////
1206
//// Public License along with this source; if not, download it   ////
1207
//// from http://www.opencores.org/lgpl.shtml                     ////
1208
////                                                              ////
1209
//////////////////////////////////////////////////////////////////////
1210 6 unneback
// GRAY counter
1211 40 unneback
module vl_cnt_gray_ce_bin (
1212
 cke, q, q_bin, rst, clk);
1213 6 unneback
   parameter length = 4;
1214
   input cke;
1215
   output reg [length:1] q;
1216
   output [length:1] q_bin;
1217
   input rst;
1218
   input clk;
1219
   parameter clear_value = 0;
1220
   parameter set_value = 1;
1221
   parameter wrap_value = 8;
1222
   parameter level1_value = 15;
1223
   reg  [length:1] qi;
1224
   wire [length:1] q_next;
1225
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1226
   always @ (posedge clk or posedge rst)
1227
     if (rst)
1228
       qi <= {length{1'b0}};
1229
     else
1230
     if (cke)
1231
       qi <= q_next;
1232
   always @ (posedge clk or posedge rst)
1233
     if (rst)
1234
       q <= {length{1'b0}};
1235
     else
1236
       if (cke)
1237
         q <= (q_next>>1) ^ q_next;
1238
   assign q_bin = qi;
1239
endmodule
1240
//////////////////////////////////////////////////////////////////////
1241
////                                                              ////
1242
////  Versatile library, counters                                 ////
1243
////                                                              ////
1244
////  Description                                                 ////
1245
////  counters                                                    ////
1246
////                                                              ////
1247
////                                                              ////
1248
////  To Do:                                                      ////
1249
////   - add more counters                                        ////
1250
////                                                              ////
1251
////  Author(s):                                                  ////
1252
////      - Michael Unneback, unneback@opencores.org              ////
1253
////        ORSoC AB                                              ////
1254
////                                                              ////
1255
//////////////////////////////////////////////////////////////////////
1256
////                                                              ////
1257
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1258
////                                                              ////
1259
//// This source file may be used and distributed without         ////
1260
//// restriction provided that this copyright statement is not    ////
1261
//// removed from the file and that any derivative work contains  ////
1262
//// the original copyright notice and the associated disclaimer. ////
1263
////                                                              ////
1264
//// This source file is free software; you can redistribute it   ////
1265
//// and/or modify it under the terms of the GNU Lesser General   ////
1266
//// Public License as published by the Free Software Foundation; ////
1267
//// either version 2.1 of the License, or (at your option) any   ////
1268
//// later version.                                               ////
1269
////                                                              ////
1270
//// This source is distributed in the hope that it will be       ////
1271
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1272
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1273
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1274
//// details.                                                     ////
1275
////                                                              ////
1276
//// You should have received a copy of the GNU Lesser General    ////
1277
//// Public License along with this source; if not, download it   ////
1278
//// from http://www.opencores.org/lgpl.shtml                     ////
1279
////                                                              ////
1280
//////////////////////////////////////////////////////////////////////
1281 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
1282 6 unneback
   parameter length = 4;
1283
   output reg [0:length-1] q;
1284
   input rst;
1285
   input clk;
1286
    always @ (posedge clk or posedge rst)
1287
    if (rst)
1288
        q <= {1'b1,{length-1{1'b0}}};
1289
    else
1290
        q <= {q[length-1],q[0:length-2]};
1291
endmodule
1292 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
1293 6 unneback
   parameter length = 4;
1294
   input cke;
1295
   output reg [0:length-1] q;
1296
   input rst;
1297
   input clk;
1298
    always @ (posedge clk or posedge rst)
1299
    if (rst)
1300
        q <= {1'b1,{length-1{1'b0}}};
1301
    else
1302
        if (cke)
1303
            q <= {q[length-1],q[0:length-2]};
1304
endmodule
1305 105 unneback
module vl_cnt_shreg_clear ( clear, q, rst, clk);
1306
   parameter length = 4;
1307
   input clear;
1308
   output reg [0:length-1] q;
1309
   input rst;
1310
   input clk;
1311
    always @ (posedge clk or posedge rst)
1312
    if (rst)
1313
        q <= {1'b1,{length-1{1'b0}}};
1314
    else
1315
        if (clear)
1316
            q <= {1'b1,{length-1{1'b0}}};
1317
        else
1318
            q <= q >> 1;
1319
endmodule
1320 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1321 6 unneback
   parameter length = 4;
1322
   input cke, clear;
1323
   output reg [0:length-1] q;
1324
   input rst;
1325
   input clk;
1326
    always @ (posedge clk or posedge rst)
1327
    if (rst)
1328
        q <= {1'b1,{length-1{1'b0}}};
1329
    else
1330
        if (cke)
1331
            if (clear)
1332
                q <= {1'b1,{length-1{1'b0}}};
1333
            else
1334
                q <= q >> 1;
1335
endmodule
1336 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
1337 6 unneback
   parameter length = 4;
1338
   input cke, clear;
1339
   output reg [0:length-1] q;
1340
   input rst;
1341
   input clk;
1342
    always @ (posedge clk or posedge rst)
1343
    if (rst)
1344
        q <= {1'b1,{length-1{1'b0}}};
1345
    else
1346
        if (cke)
1347
            if (clear)
1348
                q <= {1'b1,{length-1{1'b0}}};
1349
            else
1350
            q <= {q[length-1],q[0:length-2]};
1351
endmodule
1352
//////////////////////////////////////////////////////////////////////
1353
////                                                              ////
1354
////  Versatile library, memories                                 ////
1355
////                                                              ////
1356
////  Description                                                 ////
1357
////  memories                                                    ////
1358
////                                                              ////
1359
////                                                              ////
1360
////  To Do:                                                      ////
1361
////   - add more memory types                                    ////
1362
////                                                              ////
1363
////  Author(s):                                                  ////
1364
////      - Michael Unneback, unneback@opencores.org              ////
1365
////        ORSoC AB                                              ////
1366
////                                                              ////
1367
//////////////////////////////////////////////////////////////////////
1368
////                                                              ////
1369
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1370
////                                                              ////
1371
//// This source file may be used and distributed without         ////
1372
//// restriction provided that this copyright statement is not    ////
1373
//// removed from the file and that any derivative work contains  ////
1374
//// the original copyright notice and the associated disclaimer. ////
1375
////                                                              ////
1376
//// This source file is free software; you can redistribute it   ////
1377
//// and/or modify it under the terms of the GNU Lesser General   ////
1378
//// Public License as published by the Free Software Foundation; ////
1379
//// either version 2.1 of the License, or (at your option) any   ////
1380
//// later version.                                               ////
1381
////                                                              ////
1382
//// This source is distributed in the hope that it will be       ////
1383
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1384
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1385
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1386
//// details.                                                     ////
1387
////                                                              ////
1388
//// You should have received a copy of the GNU Lesser General    ////
1389
//// Public License along with this source; if not, download it   ////
1390
//// from http://www.opencores.org/lgpl.shtml                     ////
1391
////                                                              ////
1392
//////////////////////////////////////////////////////////////////////
1393
/// ROM
1394 7 unneback
module vl_rom_init ( adr, q, clk);
1395
   parameter data_width = 32;
1396
   parameter addr_width = 8;
1397 75 unneback
   parameter mem_size = 1<<addr_width;
1398 7 unneback
   input [(addr_width-1):0]       adr;
1399
   output reg [(data_width-1):0] q;
1400
   input                         clk;
1401 75 unneback
   reg [data_width-1:0] rom [mem_size-1:0];
1402 7 unneback
   parameter memory_file = "vl_rom.vmem";
1403
   initial
1404
     begin
1405
        $readmemh(memory_file, rom);
1406
     end
1407
   always @ (posedge clk)
1408
     q <= rom[adr];
1409
endmodule
1410 6 unneback
// Single port RAM
1411
module vl_ram ( d, adr, we, q, clk);
1412
   parameter data_width = 32;
1413
   parameter addr_width = 8;
1414 75 unneback
   parameter mem_size = 1<<addr_width;
1415 100 unneback
   parameter debug = 0;
1416 6 unneback
   input [(data_width-1):0]      d;
1417
   input [(addr_width-1):0]       adr;
1418
   input                         we;
1419 7 unneback
   output reg [(data_width-1):0] q;
1420 6 unneback
   input                         clk;
1421 98 unneback
   reg [data_width-1:0] ram [mem_size-1:0];
1422 100 unneback
    parameter memory_init = 0;
1423
    parameter memory_file = "vl_ram.vmem";
1424
    generate
1425
    if (memory_init == 1) begin : init_mem
1426
        initial
1427
            $readmemh(memory_file, ram);
1428
   end else if (memory_init == 2) begin : init_zero
1429
        integer k;
1430
        initial
1431
            for (k = 0; k < mem_size; k = k + 1)
1432
                ram[k] = 0;
1433 7 unneback
   end
1434
   endgenerate
1435 100 unneback
    generate
1436
    if (debug==1) begin : debug_we
1437
        always @ (posedge clk)
1438
        if (we)
1439
            $display ("Value %h written at address %h : time %t", d, adr, $time);
1440
    end
1441
    endgenerate
1442 6 unneback
   always @ (posedge clk)
1443
   begin
1444
   if (we)
1445
     ram[adr] <= d;
1446
   q <= ram[adr];
1447
   end
1448
endmodule
1449 91 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
1450 7 unneback
   parameter data_width = 32;
1451 72 unneback
   parameter addr_width = 6;
1452 75 unneback
   parameter mem_size = 1<<addr_width;
1453 7 unneback
   input [(data_width-1):0]      d;
1454
   input [(addr_width-1):0]       adr;
1455 73 unneback
   input [(data_width/8)-1:0]    be;
1456 7 unneback
   input                         we;
1457
   output reg [(data_width-1):0] q;
1458
   input                         clk;
1459 65 unneback
`ifdef SYSTEMVERILOG
1460 95 unneback
    // use a multi-dimensional packed array
1461
    //t o model individual bytes within the word
1462
    logic [data_width/8-1:0][7:0] ram [0:mem_size-1];// # words = 1 << address width
1463 65 unneback
`else
1464 85 unneback
    reg [data_width-1:0] ram [mem_size-1:0];
1465
    wire [data_width/8-1:0] cke;
1466 65 unneback
`endif
1467 100 unneback
    parameter memory_init = 0;
1468
    parameter memory_file = "vl_ram.vmem";
1469
    generate
1470
    if (memory_init == 1) begin : init_mem
1471
        initial
1472
            $readmemh(memory_file, ram);
1473
    end else if (memory_init == 2) begin : init_zero
1474
        integer k;
1475
        initial
1476
            for (k = 0; k < mem_size; k = k + 1)
1477
                ram[k] = 0;
1478
    end
1479 7 unneback
   endgenerate
1480 60 unneback
`ifdef SYSTEMVERILOG
1481
always_ff@(posedge clk)
1482
begin
1483 95 unneback
    if(we) begin
1484 86 unneback
        if(be[3]) ram[adr][3] <= d[31:24];
1485
        if(be[2]) ram[adr][2] <= d[23:16];
1486
        if(be[1]) ram[adr][1] <= d[15:8];
1487
        if(be[0]) ram[adr][0] <= d[7:0];
1488 60 unneback
    end
1489 90 unneback
        q <= ram[adr];
1490 60 unneback
end
1491
`else
1492 85 unneback
assign cke = {data_width/8{we}} & be;
1493 7 unneback
   genvar i;
1494 85 unneback
   generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
1495 7 unneback
      always @ (posedge clk)
1496 85 unneback
      if (cke[i])
1497 7 unneback
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
1498
   end
1499
   endgenerate
1500
   always @ (posedge clk)
1501
      q <= ram[adr];
1502 60 unneback
`endif
1503 93 unneback
`ifdef verilator
1504 85 unneback
   // Function to access RAM (for use by Verilator).
1505
   function [31:0] get_mem;
1506
      // verilator public
1507 90 unneback
      input [addr_width-1:0]             addr;
1508 85 unneback
      get_mem = ram[addr];
1509
   endfunction // get_mem
1510
   // Function to write RAM (for use by Verilator).
1511
   function set_mem;
1512
      // verilator public
1513 90 unneback
      input [addr_width-1:0]             addr;
1514
      input [data_width-1:0]             data;
1515 85 unneback
      ram[addr] = data;
1516
   endfunction // set_mem
1517 93 unneback
`endif
1518 7 unneback
endmodule
1519
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1520 6 unneback
   parameter data_width = 32;
1521
   parameter addr_width = 8;
1522 75 unneback
   parameter mem_size = 1<<addr_width;
1523 6 unneback
   input [(data_width-1):0]      d_a;
1524
   input [(addr_width-1):0]       adr_a;
1525
   input [(addr_width-1):0]       adr_b;
1526
   input                         we_a;
1527
   output [(data_width-1):0]      q_b;
1528
   input                         clk_a, clk_b;
1529
   reg [(addr_width-1):0]         adr_b_reg;
1530 100 unneback
   reg [data_width-1:0] ram [mem_size-1:0] ;
1531
    parameter memory_init = 0;
1532
    parameter memory_file = "vl_ram.vmem";
1533
    parameter debug = 0;
1534
    generate
1535
    if (memory_init == 1) begin : init_mem
1536
        initial
1537
            $readmemh(memory_file, ram);
1538
    end else if (memory_init == 2) begin : init_zero
1539
        integer k;
1540
        initial
1541
            for (k = 0; k < mem_size; k = k + 1)
1542
                ram[k] = 0;
1543
    end
1544 7 unneback
   endgenerate
1545 100 unneback
    generate
1546
    if (debug==1) begin : debug_we
1547
        always @ (posedge clk_a)
1548
        if (we_a)
1549
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
1550
    end
1551
    endgenerate
1552 6 unneback
   always @ (posedge clk_a)
1553
   if (we_a)
1554
     ram[adr_a] <= d_a;
1555
   always @ (posedge clk_b)
1556
   adr_b_reg <= adr_b;
1557
   assign q_b = ram[adr_b_reg];
1558
endmodule
1559 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1560 6 unneback
   parameter data_width = 32;
1561
   parameter addr_width = 8;
1562 75 unneback
   parameter mem_size = 1<<addr_width;
1563 6 unneback
   input [(data_width-1):0]      d_a;
1564
   input [(addr_width-1):0]       adr_a;
1565
   input [(addr_width-1):0]       adr_b;
1566
   input                         we_a;
1567
   output [(data_width-1):0]      q_b;
1568
   output reg [(data_width-1):0] q_a;
1569
   input                         clk_a, clk_b;
1570
   reg [(data_width-1):0]         q_b;
1571 75 unneback
   reg [data_width-1:0] ram [mem_szie-1:0] ;
1572 100 unneback
    parameter memory_init = 0;
1573
    parameter memory_file = "vl_ram.vmem";
1574
    parameter debug = 0;
1575
    generate
1576
    if (memory_init == 1) begin : init_mem
1577
        initial
1578
            $readmemh(memory_file, ram);
1579
    end else if (memory_init == 2) begin : init_zero
1580
        integer k;
1581
        initial
1582
            for (k = 0; k < mem_size; k = k + 1)
1583
                ram[k] = 0;
1584
    end
1585 7 unneback
   endgenerate
1586 100 unneback
    generate
1587
    if (debug==1) begin : debug_we
1588
        always @ (posedge clk_a)
1589
        if (we_a)
1590
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
1591
    end
1592
    endgenerate
1593 6 unneback
   always @ (posedge clk_a)
1594
     begin
1595
        q_a <= ram[adr_a];
1596
        if (we_a)
1597
             ram[adr_a] <= d_a;
1598
     end
1599
   always @ (posedge clk_b)
1600
          q_b <= ram[adr_b];
1601
endmodule
1602 100 unneback
module vl_dpram_1r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, adr_b, we_b, clk_b );
1603
   parameter data_width = 32;
1604
   parameter addr_width = 8;
1605
   parameter mem_size = 1<<addr_width;
1606
   input [(data_width-1):0]      d_a;
1607
   input [(addr_width-1):0]       adr_a;
1608
   input [(addr_width-1):0]       adr_b;
1609
   input                         we_a;
1610
   input [(data_width-1):0]       d_b;
1611
   output reg [(data_width-1):0] q_a;
1612
   input                         we_b;
1613
   input                         clk_a, clk_b;
1614
   reg [(data_width-1):0]         q_b;
1615
   reg [data_width-1:0] ram [mem_size-1:0] ;
1616
    parameter memory_init = 0;
1617
    parameter memory_file = "vl_ram.vmem";
1618
    parameter debug = 0;
1619
    generate
1620
    if (memory_init == 1) begin : init_mem
1621
        initial
1622
            $readmemh(memory_file, ram);
1623
    end else if (memory_init == 2) begin : init_zero
1624
        integer k;
1625
        initial
1626
            for (k = 0; k < mem_size; k = k + 1)
1627
                ram[k] = 0;
1628
    end
1629
   endgenerate
1630
    generate
1631
    if (debug==1) begin : debug_we
1632
        always @ (posedge clk_a)
1633
        if (we_a)
1634
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
1635
        always @ (posedge clk_b)
1636
        if (we_b)
1637
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
1638
    end
1639
    endgenerate
1640
   always @ (posedge clk_a)
1641
     begin
1642
        q_a <= ram[adr_a];
1643
        if (we_a)
1644
             ram[adr_a] <= d_a;
1645
     end
1646
   always @ (posedge clk_b)
1647
     begin
1648
        if (we_b)
1649
          ram[adr_b] <= d_b;
1650
     end
1651
endmodule
1652 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
1653 6 unneback
   parameter data_width = 32;
1654
   parameter addr_width = 8;
1655 75 unneback
   parameter mem_size = 1<<addr_width;
1656 6 unneback
   input [(data_width-1):0]      d_a;
1657
   input [(addr_width-1):0]       adr_a;
1658
   input [(addr_width-1):0]       adr_b;
1659
   input                         we_a;
1660
   output [(data_width-1):0]      q_b;
1661
   input [(data_width-1):0]       d_b;
1662
   output reg [(data_width-1):0] q_a;
1663
   input                         we_b;
1664
   input                         clk_a, clk_b;
1665
   reg [(data_width-1):0]         q_b;
1666 75 unneback
   reg [data_width-1:0] ram [mem_size-1:0] ;
1667 100 unneback
    parameter memory_init = 0;
1668
    parameter memory_file = "vl_ram.vmem";
1669
    parameter debug = 0;
1670
    generate
1671
    if (memory_init) begin : init_mem
1672
        initial
1673
            $readmemh(memory_file, ram);
1674
    end else if (memory_init == 2) begin : init_zero
1675
        integer k;
1676
        initial
1677
            for (k = 0; k < mem_size; k = k + 1)
1678
                ram[k] = 0;
1679
    end
1680 7 unneback
   endgenerate
1681 100 unneback
    generate
1682
    if (debug==1) begin : debug_we
1683
        always @ (posedge clk_a)
1684
        if (we_a)
1685
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
1686
        always @ (posedge clk_b)
1687
        if (we_b)
1688
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
1689
    end
1690
    endgenerate
1691 6 unneback
   always @ (posedge clk_a)
1692
     begin
1693
        q_a <= ram[adr_a];
1694
        if (we_a)
1695
             ram[adr_a] <= d_a;
1696
     end
1697
   always @ (posedge clk_b)
1698
     begin
1699
        q_b <= ram[adr_b];
1700
        if (we_b)
1701
          ram[adr_b] <= d_b;
1702
     end
1703
endmodule
1704 92 unneback
module vl_dpram_be_2r2w ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
1705 75 unneback
   parameter a_data_width = 32;
1706
   parameter a_addr_width = 8;
1707 95 unneback
   parameter b_data_width = 64; //a_data_width;
1708 91 unneback
   localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
1709 95 unneback
   localparam ratio = (a_addr_width>b_addr_width) ? (a_addr_width/b_addr_width) : (b_addr_width/a_addr_width);
1710
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<b_addr_width) : (1<<a_addr_width);
1711 100 unneback
   parameter memory_init = 0;
1712 95 unneback
   parameter memory_file = "vl_ram.vmem";
1713 100 unneback
   parameter debug = 0;
1714 75 unneback
   input [(a_data_width-1):0]      d_a;
1715 91 unneback
   input [(a_addr_width-1):0]       adr_a;
1716
   input [(a_data_width/8-1):0]    be_a;
1717
   input                           we_a;
1718 75 unneback
   output reg [(a_data_width-1):0] q_a;
1719 91 unneback
   input [(b_data_width-1):0]       d_b;
1720
   input [(b_addr_width-1):0]       adr_b;
1721 92 unneback
   input [(b_data_width/8-1):0]    be_b;
1722
   input                           we_b;
1723
   output reg [(b_data_width-1):0]          q_b;
1724 91 unneback
   input                           clk_a, clk_b;
1725 100 unneback
    generate
1726
    if (debug==1) begin : debug_we
1727
        always @ (posedge clk_a)
1728
        if (we_a)
1729
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
1730
        always @ (posedge clk_b)
1731
        if (we_b)
1732
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
1733
    end
1734
    endgenerate
1735 91 unneback
`ifdef SYSTEMVERILOG
1736
// use a multi-dimensional packed array
1737
//to model individual bytes within the word
1738 75 unneback
generate
1739 91 unneback
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
1740 98 unneback
    logic [0:3][7:0] ram [0:mem_size-1] ;
1741 95 unneback
    initial
1742 100 unneback
        if (memory_init==1)
1743 95 unneback
            $readmemh(memory_file, ram);
1744 100 unneback
    integer k;
1745
    initial
1746
        if (memory_init==2)
1747
            for (k = 0; k < mem_size; k = k + 1)
1748
                ram[k] = 0;
1749 91 unneback
    always_ff@(posedge clk_a)
1750
    begin
1751
        if(we_a) begin
1752 100 unneback
            if(be_a[3]) ram[adr_a][0] <= d_a[31:24];
1753
            if(be_a[2]) ram[adr_a][1] <= d_a[23:16];
1754
            if(be_a[1]) ram[adr_a][2] <= d_a[15:8];
1755
            if(be_a[0]) ram[adr_a][3] <= d_a[7:0];
1756 91 unneback
        end
1757
    end
1758 92 unneback
    always@(posedge clk_a)
1759
        q_a = ram[adr_a];
1760 91 unneback
    always_ff@(posedge clk_b)
1761 92 unneback
    begin
1762
        if(we_b) begin
1763 100 unneback
            if(be_b[3]) ram[adr_b][0] <= d_b[31:24];
1764
            if(be_b[2]) ram[adr_b][1] <= d_b[23:16];
1765
            if(be_b[1]) ram[adr_b][2] <= d_b[15:8];
1766
            if(be_b[0]) ram[adr_b][3] <= d_b[7:0];
1767 92 unneback
        end
1768
    end
1769
    always@(posedge clk_b)
1770
        q_b = ram[adr_b];
1771 75 unneback
end
1772
endgenerate
1773 95 unneback
generate
1774
if (a_data_width==64 & b_data_width==64) begin : dpram_6464
1775 98 unneback
    logic [0:7][7:0] ram [0:mem_size-1] ;
1776 95 unneback
    initial
1777 100 unneback
        if (memory_init==1)
1778 95 unneback
            $readmemh(memory_file, ram);
1779 100 unneback
    integer k;
1780
    initial
1781
        if (memory_init==2)
1782
            for (k = 0; k < mem_size; k = k + 1)
1783
                ram[k] = 0;
1784 95 unneback
    always_ff@(posedge clk_a)
1785
    begin
1786
        if(we_a) begin
1787
            if(be_a[7]) ram[adr_a][7] <= d_a[63:56];
1788
            if(be_a[6]) ram[adr_a][6] <= d_a[55:48];
1789
            if(be_a[5]) ram[adr_a][5] <= d_a[47:40];
1790
            if(be_a[4]) ram[adr_a][4] <= d_a[39:32];
1791
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
1792
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
1793
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
1794
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
1795
        end
1796
    end
1797
    always@(posedge clk_a)
1798
        q_a = ram[adr_a];
1799
    always_ff@(posedge clk_b)
1800
    begin
1801
        if(we_b) begin
1802
            if(be_b[7]) ram[adr_b][7] <= d_b[63:56];
1803
            if(be_b[6]) ram[adr_b][6] <= d_b[55:48];
1804
            if(be_b[5]) ram[adr_b][5] <= d_b[47:40];
1805
            if(be_b[4]) ram[adr_b][4] <= d_b[39:32];
1806
            if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
1807
            if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
1808
            if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
1809
            if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
1810
        end
1811
    end
1812
    always@(posedge clk_b)
1813
        q_b = ram[adr_b];
1814
end
1815
endgenerate
1816
generate
1817
if (a_data_width==32 & b_data_width==16) begin : dpram_3216
1818
logic [31:0] temp;
1819 111 unneback
vl_dpram_be_2r2w # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
1820 95 unneback
dpram6464 (
1821
    .d_a(d_a),
1822
    .q_a(q_a),
1823
    .adr_a(adr_a),
1824
    .be_a(be_a),
1825
    .we_a(we_a),
1826
    .clk_a(clk_a),
1827
    .d_b({d_b,d_b}),
1828
    .q_b(temp),
1829
    .adr_b(adr_b),
1830
    .be_b({be_b,be_b} & {{2{adr_b[0]}},{2{!adr_b[0]}}}),
1831
    .we_b(we_b),
1832
    .clk_b(clk_b)
1833
);
1834 100 unneback
always @ (adr_b[0] or temp)
1835 95 unneback
    if (adr_b[0])
1836
        q_b = temp[31:16];
1837
    else
1838
        q_b = temp[15:0];
1839
end
1840
endgenerate
1841
generate
1842
if (a_data_width==32 & b_data_width==64) begin : dpram_3264
1843
logic [63:0] temp;
1844 111 unneback
vl_dpram_be_2r2w # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
1845 95 unneback
dpram6464 (
1846
    .d_a({d_a,d_a}),
1847
    .q_a(temp),
1848
    .adr_a(adr_a[a_addr_width-1:1]),
1849
    .be_a({be_a,be_a} & {{4{adr_a[0]}},{4{!adr_a[0]}}}),
1850
    .we_a(we_a),
1851
    .clk_a(clk_a),
1852
    .d_b(d_b),
1853
    .q_b(q_b),
1854
    .adr_b(adr_b),
1855
    .be_b(be_b),
1856
    .we_b(we_b),
1857
    .clk_b(clk_b)
1858
);
1859 100 unneback
always @ (adr_a[0] or temp)
1860 95 unneback
    if (adr_a[0])
1861
        q_a = temp[63:32];
1862
    else
1863
        q_a = temp[31:0];
1864
end
1865
endgenerate
1866 91 unneback
`else
1867 92 unneback
    // This modules requires SystemVerilog
1868 98 unneback
    // at this point anyway
1869 91 unneback
`endif
1870 75 unneback
endmodule
1871 6 unneback
// FIFO
1872 25 unneback
module vl_fifo_1r1w_fill_level_sync (
1873
    d, wr, fifo_full,
1874
    q, rd, fifo_empty,
1875
    fill_level,
1876
    clk, rst
1877
    );
1878
parameter data_width = 18;
1879
parameter addr_width = 4;
1880
// write side
1881
input  [data_width-1:0] d;
1882
input                   wr;
1883
output                  fifo_full;
1884
// read side
1885
output [data_width-1:0] q;
1886
input                   rd;
1887
output                  fifo_empty;
1888
// common
1889
output [addr_width:0]   fill_level;
1890
input rst, clk;
1891
wire [addr_width:1] wadr, radr;
1892
vl_cnt_bin_ce
1893
    # ( .length(addr_width))
1894
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
1895
vl_cnt_bin_ce
1896
    # (.length(addr_width))
1897
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
1898
vl_dpram_1r1w
1899
    # (.data_width(data_width), .addr_width(addr_width))
1900
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
1901 31 unneback
vl_cnt_bin_ce_rew_q_zq_l1
1902 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
1903 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
1904
endmodule
1905 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
1906
// RAM is supposed to be larger than the two FIFOs
1907
// LFSR counters used adr pointers
1908
module vl_fifo_2r2w_sync_simplex (
1909
    // a side
1910
    a_d, a_wr, a_fifo_full,
1911
    a_q, a_rd, a_fifo_empty,
1912
    a_fill_level,
1913
    // b side
1914
    b_d, b_wr, b_fifo_full,
1915
    b_q, b_rd, b_fifo_empty,
1916
    b_fill_level,
1917
    // common
1918
    clk, rst
1919
    );
1920
parameter data_width = 8;
1921
parameter addr_width = 5;
1922
parameter fifo_full_level = (1<<addr_width)-1;
1923
// a side
1924
input  [data_width-1:0] a_d;
1925
input                   a_wr;
1926
output                  a_fifo_full;
1927
output [data_width-1:0] a_q;
1928
input                   a_rd;
1929
output                  a_fifo_empty;
1930
output [addr_width-1:0] a_fill_level;
1931
// b side
1932
input  [data_width-1:0] b_d;
1933
input                   b_wr;
1934
output                  b_fifo_full;
1935
output [data_width-1:0] b_q;
1936
input                   b_rd;
1937
output                  b_fifo_empty;
1938
output [addr_width-1:0] b_fill_level;
1939
input                   clk;
1940
input                   rst;
1941
// adr_gen
1942
wire [addr_width:1] a_wadr, a_radr;
1943
wire [addr_width:1] b_wadr, b_radr;
1944
// dpram
1945
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1946
vl_cnt_lfsr_ce
1947
    # ( .length(addr_width))
1948
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
1949
vl_cnt_lfsr_ce
1950
    # (.length(addr_width))
1951
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
1952
vl_cnt_lfsr_ce
1953
    # ( .length(addr_width))
1954
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
1955
vl_cnt_lfsr_ce
1956
    # (.length(addr_width))
1957
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
1958
// mux read or write adr to DPRAM
1959
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
1960
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
1961
vl_dpram_2r2w
1962
    # (.data_width(data_width), .addr_width(addr_width+1))
1963
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1964
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1965
vl_cnt_bin_ce_rew_zq_l1
1966 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
1967 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
1968
vl_cnt_bin_ce_rew_zq_l1
1969 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
1970 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
1971
endmodule
1972 6 unneback
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
1973 11 unneback
   parameter addr_width = 4;
1974
   parameter N = addr_width-1;
1975 6 unneback
   parameter Q1 = 2'b00;
1976
   parameter Q2 = 2'b01;
1977
   parameter Q3 = 2'b11;
1978
   parameter Q4 = 2'b10;
1979
   parameter going_empty = 1'b0;
1980
   parameter going_full  = 1'b1;
1981
   input [N:0]  wptr, rptr;
1982 14 unneback
   output       fifo_empty;
1983 6 unneback
   output       fifo_full;
1984
   input        wclk, rclk, rst;
1985
   wire direction;
1986
   reg  direction_set, direction_clr;
1987
   wire async_empty, async_full;
1988
   wire fifo_full2;
1989 14 unneback
   wire fifo_empty2;
1990 6 unneback
   // direction_set
1991
   always @ (wptr[N:N-1] or rptr[N:N-1])
1992
     case ({wptr[N:N-1],rptr[N:N-1]})
1993
       {Q1,Q2} : direction_set <= 1'b1;
1994
       {Q2,Q3} : direction_set <= 1'b1;
1995
       {Q3,Q4} : direction_set <= 1'b1;
1996
       {Q4,Q1} : direction_set <= 1'b1;
1997
       default : direction_set <= 1'b0;
1998
     endcase
1999
   // direction_clear
2000
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
2001
     if (rst)
2002
       direction_clr <= 1'b1;
2003
     else
2004
       case ({wptr[N:N-1],rptr[N:N-1]})
2005
         {Q2,Q1} : direction_clr <= 1'b1;
2006
         {Q3,Q2} : direction_clr <= 1'b1;
2007
         {Q4,Q3} : direction_clr <= 1'b1;
2008
         {Q1,Q4} : direction_clr <= 1'b1;
2009
         default : direction_clr <= 1'b0;
2010
       endcase
2011 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
2012 6 unneback
   assign async_empty = (wptr == rptr) && (direction==going_empty);
2013
   assign async_full  = (wptr == rptr) && (direction==going_full);
2014 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
2015
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
2016 6 unneback
/*
2017
   always @ (posedge wclk or posedge rst or posedge async_full)
2018
     if (rst)
2019
       {fifo_full, fifo_full2} <= 2'b00;
2020
     else if (async_full)
2021
       {fifo_full, fifo_full2} <= 2'b11;
2022
     else
2023
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
2024
*/
2025 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
2026 6 unneback
     if (async_empty)
2027
       {fifo_empty, fifo_empty2} <= 2'b11;
2028
     else
2029 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
2030 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
2031
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
2032 27 unneback
endmodule // async_compb
2033 6 unneback
module vl_fifo_1r1w_async (
2034
    d, wr, fifo_full, wr_clk, wr_rst,
2035
    q, rd, fifo_empty, rd_clk, rd_rst
2036
    );
2037
parameter data_width = 18;
2038
parameter addr_width = 4;
2039
// write side
2040
input  [data_width-1:0] d;
2041
input                   wr;
2042
output                  fifo_full;
2043
input                   wr_clk;
2044
input                   wr_rst;
2045
// read side
2046
output [data_width-1:0] q;
2047
input                   rd;
2048
output                  fifo_empty;
2049
input                   rd_clk;
2050
input                   rd_rst;
2051
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
2052 18 unneback
vl_cnt_gray_ce_bin
2053 6 unneback
    # ( .length(addr_width))
2054
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
2055 18 unneback
vl_cnt_gray_ce_bin
2056 6 unneback
    # (.length(addr_width))
2057 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
2058 7 unneback
vl_dpram_1r1w
2059 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
2060
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
2061
vl_fifo_cmp_async
2062
    # (.addr_width(addr_width))
2063
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
2064
endmodule
2065 8 unneback
module vl_fifo_2r2w_async (
2066 6 unneback
    // a side
2067
    a_d, a_wr, a_fifo_full,
2068
    a_q, a_rd, a_fifo_empty,
2069
    a_clk, a_rst,
2070
    // b side
2071
    b_d, b_wr, b_fifo_full,
2072
    b_q, b_rd, b_fifo_empty,
2073
    b_clk, b_rst
2074
    );
2075
parameter data_width = 18;
2076
parameter addr_width = 4;
2077
// a side
2078
input  [data_width-1:0] a_d;
2079
input                   a_wr;
2080
output                  a_fifo_full;
2081
output [data_width-1:0] a_q;
2082
input                   a_rd;
2083
output                  a_fifo_empty;
2084
input                   a_clk;
2085
input                   a_rst;
2086
// b side
2087
input  [data_width-1:0] b_d;
2088
input                   b_wr;
2089
output                  b_fifo_full;
2090
output [data_width-1:0] b_q;
2091
input                   b_rd;
2092
output                  b_fifo_empty;
2093
input                   b_clk;
2094
input                   b_rst;
2095
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
2096
vl_fifo_1r1w_async_a (
2097
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
2098
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
2099
    );
2100
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
2101
vl_fifo_1r1w_async_b (
2102
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
2103
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
2104
    );
2105
endmodule
2106 8 unneback
module vl_fifo_2r2w_async_simplex (
2107 6 unneback
    // a side
2108
    a_d, a_wr, a_fifo_full,
2109
    a_q, a_rd, a_fifo_empty,
2110
    a_clk, a_rst,
2111
    // b side
2112
    b_d, b_wr, b_fifo_full,
2113
    b_q, b_rd, b_fifo_empty,
2114
    b_clk, b_rst
2115
    );
2116
parameter data_width = 18;
2117
parameter addr_width = 4;
2118
// a side
2119
input  [data_width-1:0] a_d;
2120
input                   a_wr;
2121
output                  a_fifo_full;
2122
output [data_width-1:0] a_q;
2123
input                   a_rd;
2124
output                  a_fifo_empty;
2125
input                   a_clk;
2126
input                   a_rst;
2127
// b side
2128
input  [data_width-1:0] b_d;
2129
input                   b_wr;
2130
output                  b_fifo_full;
2131
output [data_width-1:0] b_q;
2132
input                   b_rd;
2133
output                  b_fifo_empty;
2134
input                   b_clk;
2135
input                   b_rst;
2136
// adr_gen
2137
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
2138
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
2139
// dpram
2140
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
2141 18 unneback
vl_cnt_gray_ce_bin
2142 6 unneback
    # ( .length(addr_width))
2143
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
2144 18 unneback
vl_cnt_gray_ce_bin
2145 6 unneback
    # (.length(addr_width))
2146
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
2147 18 unneback
vl_cnt_gray_ce_bin
2148 6 unneback
    # ( .length(addr_width))
2149
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
2150 18 unneback
vl_cnt_gray_ce_bin
2151 6 unneback
    # (.length(addr_width))
2152
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
2153
// mux read or write adr to DPRAM
2154
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
2155
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
2156 11 unneback
vl_dpram_2r2w
2157 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
2158
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
2159
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
2160 11 unneback
vl_fifo_cmp_async
2161 6 unneback
    # (.addr_width(addr_width))
2162
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
2163 11 unneback
vl_fifo_cmp_async
2164 6 unneback
    # (.addr_width(addr_width))
2165
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
2166
endmodule
2167 48 unneback
module vl_reg_file (
2168
    a1, a2, a3, wd3, we3, rd1, rd2, clk
2169
);
2170
parameter data_width = 32;
2171
parameter addr_width = 5;
2172
input [addr_width-1:0] a1, a2, a3;
2173
input [data_width-1:0] wd3;
2174
input we3;
2175
output [data_width-1:0] rd1, rd2;
2176
input clk;
2177
vl_dpram_1r1w
2178
    # ( .data_width(data_width), .addr_width(addr_width))
2179
    ram1 (
2180
        .d_a(wd3),
2181
        .adr_a(a3),
2182
        .we_a(we3),
2183
        .clk_a(clk),
2184
        .q_b(rd1),
2185
        .adr_b(a1),
2186
        .clk_b(clk) );
2187
vl_dpram_1r1w
2188
    # ( .data_width(data_width), .addr_width(addr_width))
2189
    ram2 (
2190
        .d_a(wd3),
2191
        .adr_a(a3),
2192
        .we_a(we3),
2193
        .clk_a(clk),
2194
        .q_b(rd2),
2195
        .adr_b(a2),
2196
        .clk_b(clk) );
2197
endmodule
2198 12 unneback
//////////////////////////////////////////////////////////////////////
2199
////                                                              ////
2200
////  Versatile library, wishbone stuff                           ////
2201
////                                                              ////
2202
////  Description                                                 ////
2203
////  Wishbone compliant modules                                  ////
2204
////                                                              ////
2205
////                                                              ////
2206
////  To Do:                                                      ////
2207
////   -                                                          ////
2208
////                                                              ////
2209
////  Author(s):                                                  ////
2210
////      - Michael Unneback, unneback@opencores.org              ////
2211
////        ORSoC AB                                              ////
2212
////                                                              ////
2213
//////////////////////////////////////////////////////////////////////
2214
////                                                              ////
2215
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2216
////                                                              ////
2217
//// This source file may be used and distributed without         ////
2218
//// restriction provided that this copyright statement is not    ////
2219
//// removed from the file and that any derivative work contains  ////
2220
//// the original copyright notice and the associated disclaimer. ////
2221
////                                                              ////
2222
//// This source file is free software; you can redistribute it   ////
2223
//// and/or modify it under the terms of the GNU Lesser General   ////
2224
//// Public License as published by the Free Software Foundation; ////
2225
//// either version 2.1 of the License, or (at your option) any   ////
2226
//// later version.                                               ////
2227
////                                                              ////
2228
//// This source is distributed in the hope that it will be       ////
2229
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2230
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2231
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2232
//// details.                                                     ////
2233
////                                                              ////
2234
//// You should have received a copy of the GNU Lesser General    ////
2235
//// Public License along with this source; if not, download it   ////
2236
//// from http://www.opencores.org/lgpl.shtml                     ////
2237
////                                                              ////
2238
//////////////////////////////////////////////////////////////////////
2239
`timescale 1ns/1ns
2240 85 unneback
module vl_wb_adr_inc ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
2241 83 unneback
parameter adr_width = 10;
2242
parameter max_burst_width = 4;
2243 85 unneback
input cyc_i, stb_i, we_i;
2244 83 unneback
input [2:0] cti_i;
2245
input [1:0] bte_i;
2246
input [adr_width-1:0] adr_i;
2247
output [adr_width-1:0] adr_o;
2248
output ack_o;
2249
input clk, rst;
2250
reg [adr_width-1:0] adr;
2251 90 unneback
wire [max_burst_width-1:0] to_adr;
2252 91 unneback
reg [max_burst_width-1:0] last_adr;
2253 92 unneback
reg last_cycle;
2254
localparam idle_or_eoc = 1'b0;
2255
localparam cyc_or_ws   = 1'b1;
2256 91 unneback
always @ (posedge clk or posedge rst)
2257
if (rst)
2258
    last_adr <= {max_burst_width{1'b0}};
2259
else
2260
    if (stb_i)
2261 92 unneback
        last_adr <=adr_o[max_burst_width-1:0];
2262 83 unneback
generate
2263
if (max_burst_width==0) begin : inst_0
2264 97 unneback
        reg ack_o;
2265
        assign adr_o = adr_i;
2266
        always @ (posedge clk or posedge rst)
2267
        if (rst)
2268
            ack_o <= 1'b0;
2269
        else
2270
            ack_o <= cyc_i & stb_i & !ack_o;
2271 83 unneback
end else begin
2272
    always @ (posedge clk or posedge rst)
2273
    if (rst)
2274 92 unneback
        last_cycle <= idle_or_eoc;
2275 83 unneback
    else
2276 92 unneback
        last_cycle <= (!cyc_i) ? idle_or_eoc : //idle
2277
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? idle_or_eoc : // eoc
2278
                      (cyc_i & !stb_i) ? cyc_or_ws : //ws
2279
                      cyc_or_ws; // cyc
2280
    assign to_adr = (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
2281 85 unneback
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
2282 91 unneback
                                        (!stb_i) ? last_adr :
2283 92 unneback
                                        (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] :
2284 85 unneback
                                        adr[max_burst_width-1:0];
2285 92 unneback
    assign ack_o = (last_cycle==cyc_or_ws) & stb_i;
2286 83 unneback
end
2287
endgenerate
2288
generate
2289
if (max_burst_width==2) begin : inst_2
2290
    always @ (posedge clk or posedge rst)
2291
    if (rst)
2292
        adr <= 2'h0;
2293
    else
2294
        if (cyc_i & stb_i)
2295
            adr[1:0] <= to_adr[1:0] + 2'd1;
2296
        else
2297
            adr <= to_adr[1:0];
2298
end
2299
endgenerate
2300
generate
2301
if (max_burst_width==3) begin : inst_3
2302
    always @ (posedge clk or posedge rst)
2303
    if (rst)
2304
        adr <= 3'h0;
2305
    else
2306
        if (cyc_i & stb_i)
2307
            case (bte_i)
2308
            2'b01: adr[2:0] <= {to_adr[2],to_adr[1:0] + 2'd1};
2309
            default: adr[3:0] <= to_adr[2:0] + 3'd1;
2310
            endcase
2311
        else
2312
            adr <= to_adr[2:0];
2313
end
2314
endgenerate
2315
generate
2316
if (max_burst_width==4) begin : inst_4
2317
    always @ (posedge clk or posedge rst)
2318
    if (rst)
2319
        adr <= 4'h0;
2320
    else
2321 91 unneback
        if (stb_i) // | (!stb_i & last_cycle!=ws)) // for !stb_i restart with adr_i +1, only inc once
2322 83 unneback
            case (bte_i)
2323
            2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
2324
            2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
2325
            default: adr[3:0] <= to_adr + 4'd1;
2326
            endcase
2327
        else
2328
            adr <= to_adr[3:0];
2329
end
2330
endgenerate
2331
generate
2332
if (adr_width > max_burst_width) begin : pass_through
2333
    assign adr_o[adr_width-1:max_burst_width] = adr_i[adr_width-1:max_burst_width];
2334
end
2335
endgenerate
2336
endmodule
2337
// async wb3 - wb3 bridge
2338
`timescale 1ns/1ns
2339 18 unneback
module vl_wb3wb3_bridge (
2340 12 unneback
        // wishbone slave side
2341
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
2342
        // wishbone master side
2343
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
2344 95 unneback
parameter style = "FIFO"; // valid: simple, FIFO
2345
parameter addr_width = 4;
2346 12 unneback
input [31:0] wbs_dat_i;
2347
input [31:2] wbs_adr_i;
2348
input [3:0]  wbs_sel_i;
2349
input [1:0]  wbs_bte_i;
2350
input [2:0]  wbs_cti_i;
2351
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
2352
output [31:0] wbs_dat_o;
2353 14 unneback
output wbs_ack_o;
2354 12 unneback
input wbs_clk, wbs_rst;
2355
output [31:0] wbm_dat_o;
2356
output reg [31:2] wbm_adr_o;
2357
output [3:0]  wbm_sel_o;
2358
output reg [1:0]  wbm_bte_o;
2359
output reg [2:0]  wbm_cti_o;
2360 14 unneback
output reg wbm_we_o;
2361
output wbm_cyc_o;
2362 12 unneback
output wbm_stb_o;
2363
input [31:0]  wbm_dat_i;
2364
input wbm_ack_i;
2365
input wbm_clk, wbm_rst;
2366
// bte
2367
parameter linear       = 2'b00;
2368
parameter wrap4        = 2'b01;
2369
parameter wrap8        = 2'b10;
2370
parameter wrap16       = 2'b11;
2371
// cti
2372
parameter classic      = 3'b000;
2373
parameter incburst     = 3'b010;
2374
parameter endofburst   = 3'b111;
2375 95 unneback
localparam wbs_adr  = 1'b0;
2376
localparam wbs_data = 1'b1;
2377
localparam wbm_adr0      = 2'b00;
2378
localparam wbm_adr1      = 2'b01;
2379
localparam wbm_data      = 2'b10;
2380
localparam wbm_data_wait = 2'b11;
2381 12 unneback
reg [1:0] wbs_bte_reg;
2382
reg wbs;
2383
wire wbs_eoc_alert, wbm_eoc_alert;
2384
reg wbs_eoc, wbm_eoc;
2385
reg [1:0] wbm;
2386 14 unneback
wire [1:16] wbs_count, wbm_count;
2387 12 unneback
wire [35:0] a_d, a_q, b_d, b_q;
2388
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
2389
reg a_rd_reg;
2390
wire b_rd_adr, b_rd_data;
2391 14 unneback
wire b_rd_data_reg;
2392
wire [35:0] temp;
2393 12 unneback
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
2394
always @ (posedge wbs_clk or posedge wbs_rst)
2395
if (wbs_rst)
2396
        wbs_eoc <= 1'b0;
2397
else
2398
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
2399 78 unneback
                wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111);
2400 12 unneback
        else if (wbs_eoc_alert & (a_rd | a_wr))
2401
                wbs_eoc <= 1'b1;
2402 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
2403 12 unneback
    cnt0 (
2404
        .cke(wbs_ack_o),
2405
        .clear(wbs_eoc),
2406
        .q(wbs_count),
2407
        .rst(wbs_rst),
2408
        .clk(wbs_clk));
2409
always @ (posedge wbs_clk or posedge wbs_rst)
2410
if (wbs_rst)
2411
        wbs <= wbs_adr;
2412
else
2413 75 unneback
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)
2414 12 unneback
                wbs <= wbs_data;
2415
        else if (wbs_eoc & wbs_ack_o)
2416
                wbs <= wbs_adr;
2417
// wbs FIFO
2418 75 unneback
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};
2419
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :
2420 12 unneback
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
2421
              1'b0;
2422
assign a_rd = !a_fifo_empty;
2423
always @ (posedge wbs_clk or posedge wbs_rst)
2424
if (wbs_rst)
2425
        a_rd_reg <= 1'b0;
2426
else
2427
        a_rd_reg <= a_rd;
2428
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
2429
assign wbs_dat_o = a_q[35:4];
2430
always @ (posedge wbs_clk or posedge wbs_rst)
2431
if (wbs_rst)
2432 13 unneback
        wbs_bte_reg <= 2'b00;
2433 12 unneback
else
2434 13 unneback
        wbs_bte_reg <= wbs_bte_i;
2435 12 unneback
// wbm FIFO
2436
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
2437
always @ (posedge wbm_clk or posedge wbm_rst)
2438
if (wbm_rst)
2439
        wbm_eoc <= 1'b0;
2440
else
2441
        if (wbm==wbm_adr0 & !b_fifo_empty)
2442
                wbm_eoc <= b_q[4:3] == linear;
2443
        else if (wbm_eoc_alert & wbm_ack_i)
2444
                wbm_eoc <= 1'b1;
2445
always @ (posedge wbm_clk or posedge wbm_rst)
2446
if (wbm_rst)
2447
        wbm <= wbm_adr0;
2448
else
2449 33 unneback
/*
2450 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
2451
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
2452
        (wbm==wbm_adr1 & !wbm_we_o) |
2453
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
2454
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
2455 33 unneback
*/
2456
    case (wbm)
2457
    wbm_adr0:
2458
        if (!b_fifo_empty)
2459
            wbm <= wbm_adr1;
2460
    wbm_adr1:
2461
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
2462
            wbm <= wbm_data;
2463
    wbm_data:
2464
        if (wbm_ack_i & wbm_eoc)
2465
            wbm <= wbm_adr0;
2466
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
2467
            wbm <= wbm_data_wait;
2468
    wbm_data_wait:
2469
        if (!b_fifo_empty)
2470
            wbm <= wbm_data;
2471
    endcase
2472 12 unneback
assign b_d = {wbm_dat_i,4'b1111};
2473
assign b_wr = !wbm_we_o & wbm_ack_i;
2474
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
2475
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
2476
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
2477 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
2478 12 unneback
                   1'b0;
2479
assign b_rd = b_rd_adr | b_rd_data;
2480 18 unneback
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
2481
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
2482 12 unneback
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
2483 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
2484 12 unneback
    cnt1 (
2485
        .cke(wbm_ack_i),
2486
        .clear(wbm_eoc),
2487
        .q(wbm_count),
2488
        .rst(wbm_rst),
2489
        .clk(wbm_clk));
2490 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
2491
assign wbm_stb_o = (wbm==wbm_data);
2492 12 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
2493
if (wbm_rst)
2494
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
2495
else begin
2496
        if (wbm==wbm_adr0 & !b_fifo_empty)
2497
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
2498
        else if (wbm_eoc_alert & wbm_ack_i)
2499
                wbm_cti_o <= endofburst;
2500
end
2501
//async_fifo_dw_simplex_top
2502
vl_fifo_2r2w_async_simplex
2503
# ( .data_width(36), .addr_width(addr_width))
2504
fifo (
2505
    // a side
2506
    .a_d(a_d),
2507
    .a_wr(a_wr),
2508
    .a_fifo_full(a_fifo_full),
2509
    .a_q(a_q),
2510
    .a_rd(a_rd),
2511
    .a_fifo_empty(a_fifo_empty),
2512
    .a_clk(wbs_clk),
2513
    .a_rst(wbs_rst),
2514
    // b side
2515
    .b_d(b_d),
2516
    .b_wr(b_wr),
2517
    .b_fifo_full(b_fifo_full),
2518
    .b_q(b_q),
2519
    .b_rd(b_rd),
2520
    .b_fifo_empty(b_fifo_empty),
2521
    .b_clk(wbm_clk),
2522
    .b_rst(wbm_rst)
2523
    );
2524
endmodule
2525 75 unneback
module vl_wb3avalon_bridge (
2526
        // wishbone slave side
2527
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
2528 77 unneback
        // avalon master side
2529 75 unneback
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
2530 85 unneback
parameter linewrapburst = 1'b0;
2531 75 unneback
input [31:0] wbs_dat_i;
2532
input [31:2] wbs_adr_i;
2533
input [3:0]  wbs_sel_i;
2534
input [1:0]  wbs_bte_i;
2535
input [2:0]  wbs_cti_i;
2536 83 unneback
input wbs_we_i;
2537
input wbs_cyc_i;
2538
input wbs_stb_i;
2539 75 unneback
output [31:0] wbs_dat_o;
2540
output wbs_ack_o;
2541
input wbs_clk, wbs_rst;
2542
input [31:0] readdata;
2543
output [31:0] writedata;
2544
output [31:2] address;
2545
output [3:0]  be;
2546
output write;
2547 81 unneback
output read;
2548 75 unneback
output beginbursttransfer;
2549
output [3:0] burstcount;
2550
input readdatavalid;
2551
input waitrequest;
2552
input clk;
2553
input rst;
2554
wire [1:0] wbm_bte_o;
2555
wire [2:0] wbm_cti_o;
2556
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
2557
reg last_cyc;
2558 79 unneback
reg [3:0] counter;
2559 82 unneback
reg read_busy;
2560 75 unneback
always @ (posedge clk or posedge rst)
2561
if (rst)
2562
    last_cyc <= 1'b0;
2563
else
2564
    last_cyc <= wbm_cyc_o;
2565 79 unneback
always @ (posedge clk or posedge rst)
2566
if (rst)
2567 82 unneback
    read_busy <= 1'b0;
2568 79 unneback
else
2569 82 unneback
    if (read & !waitrequest)
2570
        read_busy <= 1'b1;
2571
    else if (wbm_ack_i & wbm_cti_o!=3'b010)
2572
        read_busy <= 1'b0;
2573
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;
2574 75 unneback
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
2575
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
2576
                    (wbm_bte_o==2'b10) ? 4'd8 :
2577 78 unneback
                    (wbm_bte_o==2'b11) ? 4'd16:
2578
                    4'd1;
2579 82 unneback
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);
2580 79 unneback
always @ (posedge clk or posedge rst)
2581
if (rst) begin
2582
    counter <= 4'd0;
2583
end else
2584 80 unneback
    if (wbm_we_o) begin
2585
        if (!waitrequest & !last_cyc & wbm_cyc_o) begin
2586 85 unneback
            counter <= burstcount -4'd1;
2587 80 unneback
        end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
2588
            counter <= burstcount;
2589
        end else if (!waitrequest & wbm_stb_o) begin
2590
            counter <= counter - 4'd1;
2591
        end
2592 82 unneback
    end
2593 81 unneback
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
2594 77 unneback
vl_wb3wb3_bridge wbwb3inst (
2595 75 unneback
    // wishbone slave side
2596
    .wbs_dat_i(wbs_dat_i),
2597
    .wbs_adr_i(wbs_adr_i),
2598
    .wbs_sel_i(wbs_sel_i),
2599
    .wbs_bte_i(wbs_bte_i),
2600
    .wbs_cti_i(wbs_cti_i),
2601
    .wbs_we_i(wbs_we_i),
2602
    .wbs_cyc_i(wbs_cyc_i),
2603
    .wbs_stb_i(wbs_stb_i),
2604
    .wbs_dat_o(wbs_dat_o),
2605
    .wbs_ack_o(wbs_ack_o),
2606
    .wbs_clk(wbs_clk),
2607
    .wbs_rst(wbs_rst),
2608
    // wishbone master side
2609
    .wbm_dat_o(writedata),
2610 78 unneback
    .wbm_adr_o(address),
2611 75 unneback
    .wbm_sel_o(be),
2612
    .wbm_bte_o(wbm_bte_o),
2613
    .wbm_cti_o(wbm_cti_o),
2614
    .wbm_we_o(wbm_we_o),
2615
    .wbm_cyc_o(wbm_cyc_o),
2616
    .wbm_stb_o(wbm_stb_o),
2617
    .wbm_dat_i(readdata),
2618
    .wbm_ack_i(wbm_ack_i),
2619
    .wbm_clk(clk),
2620
    .wbm_rst(rst));
2621
endmodule
2622 49 unneback
// WB RAM with byte enable
2623 101 unneback
module vl_wb_ram (
2624 69 unneback
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
2625 101 unneback
    wbs_dat_o, wbs_ack_o, wbs_stall_o, wb_clk, wb_rst);
2626
parameter adr_width = 16;
2627
parameter mem_size = 1<<adr_width;
2628
parameter dat_width = 32;
2629
parameter max_burst_width = 4; // only used for B3
2630
parameter mode = "B3"; // valid options: B3, B4
2631 60 unneback
parameter memory_init = 1;
2632
parameter memory_file = "vl_ram.vmem";
2633 101 unneback
input [dat_width-1:0] wbs_dat_i;
2634
input [adr_width-1:0] wbs_adr_i;
2635
input [2:0] wbs_cti_i;
2636
input [1:0] wbs_bte_i;
2637
input [dat_width/8-1:0] wbs_sel_i;
2638 70 unneback
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
2639 101 unneback
output [dat_width-1:0] wbs_dat_o;
2640 70 unneback
output wbs_ack_o;
2641 101 unneback
output wbs_stall_o;
2642 71 unneback
input wb_clk, wb_rst;
2643 101 unneback
wire [adr_width-1:0] adr;
2644
wire we;
2645
generate
2646
if (mode=="B3") begin : B3_inst
2647
vl_wb_adr_inc # ( .adr_width(adr_width), .max_burst_width(max_burst_width)) adr_inc0 (
2648 83 unneback
    .cyc_i(wbs_cyc_i),
2649
    .stb_i(wbs_stb_i),
2650
    .cti_i(wbs_cti_i),
2651
    .bte_i(wbs_bte_i),
2652
    .adr_i(wbs_adr_i),
2653 85 unneback
    .we_i(wbs_we_i),
2654 83 unneback
    .ack_o(wbs_ack_o),
2655
    .adr_o(adr),
2656
    .clk(wb_clk),
2657
    .rst(wb_rst));
2658 101 unneback
assign we = wbs_we_i & wbs_ack_o;
2659
end else if (mode=="B4") begin : B4_inst
2660
reg wbs_ack_o_reg;
2661
always @ (posedge wb_clk or posedge wb_rst)
2662
    if (wb_rst)
2663
        wbs_ack_o_reg <= 1'b0;
2664
    else
2665
        wbs_ack_o_reg <= wbs_stb_i & wbs_cyc_i;
2666
assign wbs_ack_o = wbs_ack_o_reg;
2667
assign wbs_stall_o = 1'b0;
2668
assign adr = wbs_adr_i;
2669
assign we = wbs_we_i & wbs_cyc_i & wbs_stb_i;
2670
end
2671
endgenerate
2672 100 unneback
vl_ram_be # (
2673
    .data_width(dat_width),
2674
    .addr_width(adr_width),
2675
    .mem_size(mem_size),
2676
    .memory_init(memory_init),
2677
    .memory_file(memory_file))
2678
ram0(
2679 101 unneback
    .d(wbs_dat_i),
2680
    .adr(adr),
2681
    .be(wbs_sel_i),
2682
    .we(we),
2683
    .q(wbs_dat_o),
2684 100 unneback
    .clk(wb_clk)
2685
);
2686 49 unneback
endmodule
2687 103 unneback
// A wishbone compliant RAM module that can be placed in front of other memory controllers
2688
module vl_wb_shadow_ram (
2689
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
2690
    wbs_dat_o, wbs_ack_o, wbs_stall_o,
2691
    wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
2692
    wbm_dat_i, wbm_ack_i, wbm_stall_i,
2693
    wb_clk, wb_rst);
2694
parameter dat_width = 32;
2695
parameter mode = "B4";
2696
parameter max_burst_width = 4; // only used for B3
2697
parameter shadow_mem_adr_width = 10;
2698
parameter shadow_mem_size = 1024;
2699
parameter shadow_mem_init = 2;
2700
parameter shadow_mem_file = "vl_ram.v";
2701
parameter main_mem_adr_width = 24;
2702
input [dat_width-1:0] wbs_dat_i;
2703
input [main_mem_adr_width-1:0] wbs_adr_i;
2704
input [2:0] wbs_cti_i;
2705
input [1:0] wbs_bte_i;
2706
input [dat_width/8-1:0] wbs_sel_i;
2707
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
2708
output [dat_width-1:0] wbs_dat_o;
2709
output wbs_ack_o;
2710
output wbs_stall_o;
2711
output [dat_width-1:0] wbm_dat_o;
2712
output [main_mem_adr_width-1:0] wbm_adr_o;
2713
output [2:0] wbm_cti_o;
2714
output [1:0] wbm_bte_o;
2715
output [dat_width/8-1:0] wbm_sel_o;
2716
output wbm_we_o, wbm_stb_o, wbm_cyc_o;
2717
input [dat_width-1:0] wbm_dat_i;
2718
input wbm_ack_i, wbm_stall_i;
2719
input wb_clk, wb_rst;
2720
generate
2721
if (shadow_mem_size>0) begin : shadow_ram_inst
2722
wire cyc;
2723
wire [dat_width-1:0] dat;
2724
wire stall, ack;
2725
assign cyc = wbs_cyc_i & (wbs_adr_i<=shadow_mem_size);
2726
vl_wb_ram # (
2727
    .dat_width(dat_width),
2728
    .adr_width(shadow_mem_adr_width),
2729
    .mem_size(shadow_mem_size),
2730
    .memory_init(shadow_mem_init),
2731
    .mode(mode))
2732
shadow_mem0 (
2733
    .wbs_dat_i(wbs_dat_i),
2734
    .wbs_adr_i(wbs_adr_i[shadow_mem_adr_width-1:0]),
2735
    .wbs_sel_i(wbs_sel_i),
2736
    .wbs_we_i (wbs_we_i),
2737
    .wbs_bte_i(wbs_bte_i),
2738
    .wbs_cti_i(wbs_cti_i),
2739
    .wbs_stb_i(wbs_stb_i),
2740
    .wbs_cyc_i(cyc),
2741
    .wbs_dat_o(dat),
2742
    .wbs_stall_o(stall),
2743
    .wbs_ack_o(ack),
2744
    .wb_clk(wb_clk),
2745
    .wb_rst(wb_rst));
2746
assign {wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o} =
2747
       {wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i};
2748
assign wbm_cyc_o = wbs_cyc_i & (wbs_adr_i>shadow_mem_size);
2749
assign wbs_dat_o = (dat & {dat_width{cyc}}) | (wbm_dat_i & {dat_width{wbm_cyc_o}});
2750
assign wbs_ack_o = (ack & cyc) | (wbm_ack_i & wbm_cyc_o);
2751
assign wbs_stall_o = (stall & cyc) | (wbm_stall_i & wbm_cyc_o);
2752
end else begin : no_shadow_ram_inst
2753
assign {wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o, wbm_cyc_o} =
2754
       {wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i};
2755
assign {wbs_dat_o, wbs_ack_o, wbs_stall_o} = {wbm_dat_i, wbm_ack_i, wbm_stall_i};
2756
end
2757
endgenerate
2758
endmodule
2759 17 unneback
// WB ROM
2760 48 unneback
module vl_wb_b4_rom (
2761
    wb_adr_i, wb_stb_i, wb_cyc_i,
2762
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
2763
    parameter dat_width = 32;
2764
    parameter dat_default = 32'h15000000;
2765
    parameter adr_width = 32;
2766
/*
2767
`ifndef ROM
2768
`define ROM "rom.v"
2769
`endif
2770
*/
2771
    input [adr_width-1:2]   wb_adr_i;
2772
    input                   wb_stb_i;
2773
    input                   wb_cyc_i;
2774
    output [dat_width-1:0]  wb_dat_o;
2775
    reg [dat_width-1:0]     wb_dat_o;
2776
    output                  wb_ack_o;
2777
    reg                     wb_ack_o;
2778
    output                  stall_o;
2779
    input                   wb_clk;
2780
    input                   wb_rst;
2781
always @ (posedge wb_clk or posedge wb_rst)
2782
    if (wb_rst)
2783
        wb_dat_o <= {dat_width{1'b0}};
2784
    else
2785
         case (wb_adr_i[adr_width-1:2])
2786
`ifdef ROM
2787
`include `ROM
2788
`endif
2789
           default:
2790
             wb_dat_o <= dat_default;
2791
         endcase // case (wb_adr_i)
2792
always @ (posedge wb_clk or posedge wb_rst)
2793
    if (wb_rst)
2794
        wb_ack_o <= 1'b0;
2795
    else
2796
        wb_ack_o <= wb_stb_i & wb_cyc_i;
2797
assign stall_o = 1'b0;
2798
endmodule
2799
// WB ROM
2800 18 unneback
module vl_wb_boot_rom (
2801 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
2802 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
2803
    parameter adr_hi = 31;
2804
    parameter adr_lo = 28;
2805
    parameter adr_sel = 4'hf;
2806
    parameter addr_width = 5;
2807 33 unneback
/*
2808
`ifndef BOOT_ROM
2809
`define BOOT_ROM "boot_rom.v"
2810
`endif
2811
*/
2812 18 unneback
    input [adr_hi:2]    wb_adr_i;
2813
    input               wb_stb_i;
2814
    input               wb_cyc_i;
2815
    output [31:0]        wb_dat_o;
2816
    output              wb_ack_o;
2817
    output              hit_o;
2818
    input               wb_clk;
2819
    input               wb_rst;
2820
    wire hit;
2821
    reg [31:0] wb_dat;
2822
    reg wb_ack;
2823
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
2824 17 unneback
always @ (posedge wb_clk or posedge wb_rst)
2825
    if (wb_rst)
2826 18 unneback
        wb_dat <= 32'h15000000;
2827 17 unneback
    else
2828 18 unneback
         case (wb_adr_i[addr_width-1:2])
2829 33 unneback
`ifdef BOOT_ROM
2830
`include `BOOT_ROM
2831
`endif
2832 17 unneback
           /*
2833
            // Zero r0 and jump to 0x00000100
2834 18 unneback
 
2835
            1 : wb_dat <= 32'hA8200000;
2836
            2 : wb_dat <= 32'hA8C00100;
2837
            3 : wb_dat <= 32'h44003000;
2838
            4 : wb_dat <= 32'h15000000;
2839 17 unneback
            */
2840
           default:
2841 18 unneback
             wb_dat <= 32'h00000000;
2842 17 unneback
         endcase // case (wb_adr_i)
2843
always @ (posedge wb_clk or posedge wb_rst)
2844
    if (wb_rst)
2845 18 unneback
        wb_ack <= 1'b0;
2846 17 unneback
    else
2847 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
2848
assign hit_o = hit;
2849
assign wb_dat_o = wb_dat & {32{wb_ack}};
2850
assign wb_ack_o = wb_ack;
2851 17 unneback
endmodule
2852 106 unneback
module vl_wb_dpram (
2853
        // wishbone slave side a
2854
        wbsa_dat_i, wbsa_adr_i, wbsa_sel_i, wbsa_cti_i, wbsa_bte_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o, wbsa_stall_o,
2855
        wbsa_clk, wbsa_rst,
2856
        // wishbone slave side b
2857
        wbsb_dat_i, wbsb_adr_i, wbsb_sel_i, wbsb_cti_i, wbsb_bte_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o, wbsb_stall_o,
2858
        wbsb_clk, wbsb_rst);
2859
parameter data_width_a = 32;
2860
parameter data_width_b = data_width_a;
2861
parameter addr_width_a = 8;
2862
localparam addr_width_b = data_width_a * addr_width_a / data_width_b;
2863
parameter mem_size = (addr_width_a>addr_width_b) ? (1<<addr_width_a) : (1<<addr_width_b);
2864
parameter max_burst_width_a = 4;
2865
parameter max_burst_width_b = max_burst_width_a;
2866
parameter mode = "B3";
2867 109 unneback
parameter memory_init = 0;
2868
parameter memory_file = "vl_ram.v";
2869 106 unneback
input [data_width_a-1:0] wbsa_dat_i;
2870
input [addr_width_a-1:0] wbsa_adr_i;
2871
input [data_width_a/8-1:0] wbsa_sel_i;
2872
input [2:0] wbsa_cti_i;
2873
input [1:0] wbsa_bte_i;
2874
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
2875
output [data_width_a-1:0] wbsa_dat_o;
2876 109 unneback
output wbsa_ack_o;
2877 106 unneback
output wbsa_stall_o;
2878
input wbsa_clk, wbsa_rst;
2879
input [data_width_b-1:0] wbsb_dat_i;
2880
input [addr_width_b-1:0] wbsb_adr_i;
2881
input [data_width_b/8-1:0] wbsb_sel_i;
2882
input [2:0] wbsb_cti_i;
2883
input [1:0] wbsb_bte_i;
2884
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
2885
output [data_width_b-1:0] wbsb_dat_o;
2886 109 unneback
output wbsb_ack_o;
2887 106 unneback
output wbsb_stall_o;
2888
input wbsb_clk, wbsb_rst;
2889
wire [addr_width_a-1:0] adr_a;
2890
wire [addr_width_b-1:0] adr_b;
2891
wire we_a, we_b;
2892
generate
2893
if (mode=="B3") begin : b3_inst
2894
vl_wb_adr_inc # ( .adr_width(addr_width_a), .max_burst_width(max_burst_width_a)) adr_inc0 (
2895
    .cyc_i(wbsa_cyc_i),
2896
    .stb_i(wbsa_stb_i),
2897
    .cti_i(wbsa_cti_i),
2898
    .bte_i(wbsa_bte_i),
2899
    .adr_i(wbsa_adr_i),
2900
    .we_i(wbsa_we_i),
2901
    .ack_o(wbsa_ack_o),
2902
    .adr_o(adr_a),
2903
    .clk(wbsa_clk),
2904
    .rst(wbsa_rst));
2905
assign we_a = wbsa_we_i & wbsa_ack_o;
2906
vl_wb_adr_inc # ( .adr_width(addr_width_b), .max_burst_width(max_burst_width_b)) adr_inc1 (
2907
    .cyc_i(wbsb_cyc_i),
2908
    .stb_i(wbsb_stb_i),
2909
    .cti_i(wbsb_cti_i),
2910
    .bte_i(wbsb_bte_i),
2911
    .adr_i(wbsb_adr_i),
2912
    .we_i(wbsb_we_i),
2913
    .ack_o(wbsb_ack_o),
2914
    .adr_o(adr_b),
2915
    .clk(wbsb_clk),
2916
    .rst(wbsb_rst));
2917
assign we_b = wbsb_we_i & wbsb_ack_o;
2918
end else if (mode=="B4") begin : b4_inst
2919 109 unneback
vl_dff dffacka ( .d(wbsa_stb_i & wbsa_cyc_i), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
2920 106 unneback
assign wbsa_stall_o = 1'b0;
2921
assign we_a = wbsa_we_i & wbsa_cyc_i & wbsa_stb_i;
2922 109 unneback
vl_dff dffackb ( .d(wbsb_stb_i & wbsb_cyc_i), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
2923 106 unneback
assign wbsb_stall_o = 1'b0;
2924
assign we_b = wbsb_we_i & wbsb_cyc_i & wbsb_stb_i;
2925
end
2926
endgenerate
2927 109 unneback
vl_dpram_be_2r2w # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size),
2928 110 unneback
                 .b_data_width(data_width_b),
2929 109 unneback
                 .memory_init(memory_init), .memory_file(memory_file))
2930 106 unneback
ram_i (
2931
    .d_a(wbsa_dat_i),
2932
    .q_a(wbsa_dat_o),
2933
    .adr_a(adr_a),
2934
    .be_a(wbsa_sel_i),
2935
    .we_a(we_a),
2936
    .clk_a(wbsa_clk),
2937
    .d_b(wbsb_dat_i),
2938
    .q_b(wbsb_dat_o),
2939
    .adr_b(adr_b),
2940
    .be_b(wbsb_sel_i),
2941
    .we_b(we_b),
2942
    .clk_b(wbsb_clk) );
2943
endmodule
2944 101 unneback
module vl_wb_cache (
2945 103 unneback
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_stall_o, wbs_clk, wbs_rst,
2946 98 unneback
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
2947 97 unneback
);
2948
parameter dw_s = 32;
2949
parameter aw_s = 24;
2950
parameter dw_m = dw_s;
2951 100 unneback
localparam aw_m = dw_s * aw_s / dw_m;
2952
parameter wbs_max_burst_width = 4;
2953 103 unneback
parameter wbs_mode = "B3";
2954 97 unneback
parameter async = 1; // wbs_clk != wbm_clk
2955
parameter nr_of_ways = 1;
2956
parameter aw_offset = 4; // 4 => 16 words per cache line
2957
parameter aw_slot = 10;
2958 100 unneback
parameter valid_mem = 0;
2959
parameter debug = 0;
2960
localparam aw_b_offset = aw_offset * dw_s / dw_m;
2961 98 unneback
localparam aw_tag = aw_s - aw_slot - aw_offset;
2962 97 unneback
parameter wbm_burst_size = 4; // valid options 4,8,16
2963 98 unneback
localparam bte = (wbm_burst_size==4) ? 2'b01 : (wbm_burst_size==8) ? 2'b10 : 2'b11;
2964 100 unneback
localparam wbm_burst_width = (wbm_burst_size==1) ? 0 : (wbm_burst_size==2) ? 1 : (wbm_burst_size==4) ? 2 : (wbm_burst_size==8) ? 3 : (wbm_burst_size==16) ? 4 : (wbm_burst_size==32) ? 5 : (wbm_burst_size==64) ? 6 : (wbm_burst_size==128) ? 7 : 8;
2965 97 unneback
localparam nr_of_wbm_burst = ((1<<aw_offset)/wbm_burst_size) * dw_s / dw_m;
2966 100 unneback
localparam nr_of_wbm_burst_width = (nr_of_wbm_burst==1) ? 0 : (nr_of_wbm_burst==2) ? 1 : (nr_of_wbm_burst==4) ? 2 : (nr_of_wbm_burst==8) ? 3 : (nr_of_wbm_burst==16) ? 4 : (nr_of_wbm_burst==32) ? 5 : (nr_of_wbm_burst==64) ? 6 : (nr_of_wbm_burst==128) ? 7 : 8;
2967 97 unneback
input [dw_s-1:0] wbs_dat_i;
2968
input [aw_s-1:0] wbs_adr_i; // dont include a1,a0
2969 98 unneback
input [dw_s/8-1:0] wbs_sel_i;
2970 97 unneback
input [2:0] wbs_cti_i;
2971
input [1:0] wbs_bte_i;
2972 98 unneback
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
2973 97 unneback
output [dw_s-1:0] wbs_dat_o;
2974
output wbs_ack_o;
2975 103 unneback
output wbs_stall_o;
2976 97 unneback
input wbs_clk, wbs_rst;
2977
output [dw_m-1:0] wbm_dat_o;
2978
output [aw_m-1:0] wbm_adr_o;
2979
output [dw_m/8-1:0] wbm_sel_o;
2980
output [2:0] wbm_cti_o;
2981
output [1:0] wbm_bte_o;
2982 98 unneback
output wbm_stb_o, wbm_cyc_o, wbm_we_o;
2983 97 unneback
input [dw_m-1:0] wbm_dat_i;
2984
input wbm_ack_i;
2985
input wbm_stall_i;
2986
input wbm_clk, wbm_rst;
2987 100 unneback
wire valid, dirty, hit;
2988 97 unneback
wire [aw_tag-1:0] tag;
2989
wire tag_mem_we;
2990
wire [aw_tag-1:0] wbs_adr_tag;
2991
wire [aw_slot-1:0] wbs_adr_slot;
2992 98 unneback
wire [aw_offset-1:0] wbs_adr_word;
2993
wire [aw_s-1:0] wbs_adr;
2994 97 unneback
reg [1:0] state;
2995
localparam idle = 2'h0;
2996
localparam rdwr = 2'h1;
2997
localparam push = 2'h2;
2998
localparam pull = 2'h3;
2999
wire eoc;
3000 103 unneback
wire we;
3001 97 unneback
// cdc
3002
wire done, mem_alert, mem_done;
3003 98 unneback
// wbm side
3004
reg [aw_m-1:0] wbm_radr;
3005
reg [aw_m-1:0] wbm_wadr;
3006 100 unneback
wire [aw_slot-1:0] wbm_adr;
3007 98 unneback
wire wbm_radr_cke, wbm_wadr_cke;
3008 100 unneback
reg [2:0] phase;
3009
// phase = {we,stb,cyc}
3010
localparam wbm_wait     = 3'b000;
3011
localparam wbm_wr       = 3'b111;
3012
localparam wbm_wr_drain = 3'b101;
3013
localparam wbm_rd       = 3'b011;
3014
localparam wbm_rd_drain = 3'b001;
3015 97 unneback
assign {wbs_adr_tag, wbs_adr_slot, wbs_adr_word} = wbs_adr_i;
3016 100 unneback
generate
3017
if (valid_mem==0) begin : no_valid_mem
3018
assign valid = 1'b1;
3019
end else begin : valid_mem_inst
3020
vl_dpram_1r1w
3021
    # ( .data_width(1), .addr_width(aw_slot), .memory_init(2), .debug(debug))
3022
    valid_mem ( .d_a(1'b1), .adr_a(wbs_adr_slot), .we_a(mem_done), .clk_a(wbm_clk),
3023
                .q_b(valid), .adr_b(wbs_adr_slot), .clk_b(wbs_clk));
3024
end
3025
endgenerate
3026
vl_dpram_1r1w
3027
    # ( .data_width(aw_tag), .addr_width(aw_slot), .memory_init(2), .debug(debug))
3028
    tag_mem ( .d_a(wbs_adr_tag), .adr_a(wbs_adr_slot), .we_a(mem_done), .clk_a(wbm_clk),
3029
              .q_b(tag), .adr_b(wbs_adr_slot), .clk_b(wbs_clk));
3030
assign hit = wbs_adr_tag == tag;
3031
vl_dpram_1r2w
3032
    # ( .data_width(1), .addr_width(aw_slot), .memory_init(2), .debug(debug))
3033
    dirty_mem (
3034
        .d_a(1'b1), .q_a(dirty), .adr_a(wbs_adr_slot), .we_a(wbs_cyc_i & wbs_we_i & wbs_ack_o), .clk_a(wbs_clk),
3035
        .d_b(1'b0), .adr_b(wbs_adr_slot), .we_b(mem_done), .clk_b(wbm_clk));
3036 103 unneback
generate
3037
if (wbs_mode=="B3") begin : inst_b3
3038 100 unneback
vl_wb_adr_inc # ( .adr_width(aw_s), .max_burst_width(wbs_max_burst_width)) adr_inc0 (
3039
    .cyc_i(wbs_cyc_i & (state==rdwr) & hit & valid),
3040
    .stb_i(wbs_stb_i & (state==rdwr) & hit & valid), // throttle depending on valid
3041 97 unneback
    .cti_i(wbs_cti_i),
3042
    .bte_i(wbs_bte_i),
3043
    .adr_i(wbs_adr_i),
3044
    .we_i (wbs_we_i),
3045
    .ack_o(wbs_ack_o),
3046
    .adr_o(wbs_adr),
3047 100 unneback
    .clk(wbs_clk),
3048
    .rst(wbs_rst));
3049 103 unneback
assign eoc = (wbs_cti_i==3'b000 | wbs_cti_i==3'b111) & wbs_ack_o;
3050
assign we = wbs_cyc_i &  wbs_we_i & wbs_ack_o;
3051
end else if (wbs_mode=="B4") begin : inst_b4
3052
end
3053
endgenerate
3054 97 unneback
vl_dpram_be_2r2w
3055 100 unneback
    # ( .a_data_width(dw_s), .a_addr_width(aw_slot+aw_offset), .b_data_width(dw_m), .debug(debug))
3056 103 unneback
    cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr[aw_slot+aw_offset-1:0]),   .be_a(wbs_sel_i), .we_a(we), .q_a(wbs_dat_o), .clk_a(wbs_clk),
3057 100 unneback
                .d_b(wbm_dat_i), .adr_b(wbm_adr_o[aw_slot+aw_offset-1:0]), .be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbs_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
3058 97 unneback
always @ (posedge wbs_clk or posedge wbs_rst)
3059
if (wbs_rst)
3060 98 unneback
    state <= idle;
3061 97 unneback
else
3062
    case (state)
3063
    idle:
3064
        if (wbs_cyc_i)
3065
            state <= rdwr;
3066
    rdwr:
3067 100 unneback
        casex ({valid, hit, dirty, eoc})
3068
        4'b0xxx: state <= pull;
3069
        4'b11x1: state <= idle;
3070
        4'b101x: state <= push;
3071
        4'b100x: state <= pull;
3072
        endcase
3073 97 unneback
    push:
3074
        if (done)
3075
            state <= rdwr;
3076
    pull:
3077
        if (done)
3078
            state <= rdwr;
3079
    default: state <= idle;
3080
    endcase
3081
// cdc
3082
generate
3083
if (async==1) begin : cdc0
3084 100 unneback
vl_cdc cdc0 ( .start_pl(state==rdwr & (!valid | !hit)), .take_it_pl(mem_alert), .take_it_grant_pl(mem_done), .got_it_pl(done), .clk_src(wbs_clk), .rst_src(wbs_rst), .clk_dst(wbm_clk), .rst_dst(wbm_rst));
3085 97 unneback
end
3086
else begin : nocdc
3087 100 unneback
    assign mem_alert = state==rdwr & (!valid | !hit);
3088 97 unneback
    assign done = mem_done;
3089
end
3090
endgenerate
3091
// FSM generating a number of burts 4 cycles
3092
// actual number depends on data width ratio
3093
// nr_of_wbm_burst
3094 101 unneback
reg [nr_of_wbm_burst_width+wbm_burst_width-1:0]       cnt_rw, cnt_ack;
3095 97 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
3096
if (wbm_rst)
3097 100 unneback
    cnt_rw <= {wbm_burst_width{1'b0}};
3098 97 unneback
else
3099 100 unneback
    if (wbm_cyc_o & wbm_stb_o & !wbm_stall_i)
3100
        cnt_rw <= cnt_rw + 1;
3101 98 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
3102
if (wbm_rst)
3103 100 unneback
    cnt_ack <= {wbm_burst_width{1'b0}};
3104 98 unneback
else
3105 100 unneback
    if (wbm_ack_i)
3106
        cnt_ack <= cnt_ack + 1;
3107
generate
3108 101 unneback
if (nr_of_wbm_burst==1) begin : one_burst
3109 98 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
3110
if (wbm_rst)
3111
    phase <= wbm_wait;
3112
else
3113
    case (phase)
3114
    wbm_wait:
3115
        if (mem_alert)
3116 100 unneback
            if (state==push)
3117
                phase <= wbm_wr;
3118
            else
3119
                phase <= wbm_rd;
3120 98 unneback
    wbm_wr:
3121 100 unneback
        if (&cnt_rw)
3122
            phase <= wbm_wr_drain;
3123
    wbm_wr_drain:
3124
        if (&cnt_ack)
3125 98 unneback
            phase <= wbm_rd;
3126
    wbm_rd:
3127 100 unneback
        if (&cnt_rw)
3128
            phase <= wbm_rd_drain;
3129
    wbm_rd_drain:
3130
        if (&cnt_ack)
3131
            phase <= wbm_wait;
3132 98 unneback
    default: phase <= wbm_wait;
3133
    endcase
3134 100 unneback
end else begin : multiple_burst
3135 101 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
3136
if (wbm_rst)
3137
    phase <= wbm_wait;
3138
else
3139
    case (phase)
3140
    wbm_wait:
3141
        if (mem_alert)
3142
            if (state==push)
3143
                phase <= wbm_wr;
3144
            else
3145
                phase <= wbm_rd;
3146
    wbm_wr:
3147
        if (&cnt_rw[wbm_burst_width-1:0])
3148
            phase <= wbm_wr_drain;
3149
    wbm_wr_drain:
3150
        if (&cnt_ack)
3151
            phase <= wbm_rd;
3152
        else if (&cnt_ack[wbm_burst_width-1:0])
3153
            phase <= wbm_wr;
3154
    wbm_rd:
3155
        if (&cnt_rw[wbm_burst_width-1:0])
3156
            phase <= wbm_rd_drain;
3157
    wbm_rd_drain:
3158
        if (&cnt_ack)
3159
            phase <= wbm_wait;
3160
        else if (&cnt_ack[wbm_burst_width-1:0])
3161
            phase <= wbm_rd;
3162
    default: phase <= wbm_wait;
3163
    endcase
3164 100 unneback
end
3165
endgenerate
3166 101 unneback
assign mem_done = phase==wbm_rd_drain & (&cnt_ack) & wbm_ack_i;
3167 100 unneback
assign wbm_adr_o = (phase[2]) ? {tag, wbs_adr_slot, cnt_rw} : {wbs_adr_tag, wbs_adr_slot, cnt_rw};
3168
assign wbm_adr   = (phase[2]) ? {wbs_adr_slot, cnt_rw} : {wbs_adr_slot, cnt_rw};
3169
assign wbm_sel_o = {dw_m/8{1'b1}};
3170
assign wbm_cti_o = (&cnt_rw | !wbm_stb_o) ? 3'b111 : 3'b010;
3171 98 unneback
assign wbm_bte_o = bte;
3172 100 unneback
assign {wbm_we_o, wbm_stb_o, wbm_cyc_o}  = phase;
3173 97 unneback
endmodule
3174 103 unneback
// Wishbone to avalon bridge supporting one type of burst transfer only
3175
// intended use is together with cache above
3176
// WB B4 -> pipelined avalon
3177
module vl_wb_avalon_bridge (
3178
        // wishbone slave side
3179
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_stall_o,
3180
        // avalon master side
3181
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer,
3182
        // common
3183
        clk, rst);
3184
parameter adr_width = 30;
3185
parameter dat_width = 32;
3186
parameter burst_size = 4;
3187
input [dat_width-1:0] wbs_dat_i;
3188
input [adr_width-1:0] wbs_adr_i;
3189
input [dat_width/8-1:0]  wbs_sel_i;
3190
input [1:0]  wbs_bte_i;
3191
input [2:0]  wbs_cti_i;
3192
input wbs_we_i;
3193
input wbs_cyc_i;
3194
input wbs_stb_i;
3195
output [dat_width:0] wbs_dat_o;
3196
output wbs_ack_o;
3197
output wbs_stall_o;
3198
input [dat_width-1:0] readdata;
3199
input readdatavalid;
3200
output [dat_width-1:0] writedata;
3201
output [adr_width-1:0] address;
3202
output [dat_width/8-1:0]  be;
3203
output write;
3204
output read;
3205
output beginbursttransfer;
3206
output [3:0] burstcount;
3207
input waitrequest;
3208
input clk, rst;
3209
reg last_cyc_idle_or_eoc;
3210
reg [3:0] cnt;
3211
always @ (posedge clk or posedge rst)
3212
if (rst)
3213
    cnt <= 4'h0;
3214
else
3215
    if (beginbursttransfer & waitrequest)
3216
        cnt <= burst_size - 1;
3217
    else if (beginbursttransfer & !waitrequest)
3218
        cnt <= burst_size - 2;
3219
    else if (wbs_ack_o)
3220
        cnt <= cnt - 1;
3221
reg wr_ack;
3222
always @ (posedge clk or posedge rst)
3223
if (rst)
3224
    wr_ack <= 1'b0;
3225
else
3226
    wr_ack <=  (wbs_we_i & wbs_cyc_i & wbs_stb_i & !wbs_stall_o);
3227
// to avalon
3228
assign writedata = wbs_dat_i;
3229
assign address = wbs_adr_i;
3230
assign be = wbs_sel_i;
3231
assign write = cnt==(burst_size-1) & wbs_cyc_i &  wbs_we_i;
3232
assign read  = cnt==(burst_size-1) & wbs_cyc_i & !wbs_we_i;
3233
assign beginbursttransfer = cnt==4'h0 & wbs_cyc_i;
3234
assign burstcount = burst_size;
3235
// to wishbone
3236
assign wbs_dat_o = readdata;
3237
assign wbs_ack_o = wr_ack | readdatavalid;
3238
assign wbs_stall_o = waitrequest;
3239
endmodule
3240
module vl_wb_avalon_mem_cache (
3241
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_stall_o, wbs_clk, wbs_rst,
3242
    readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst
3243
);
3244
// wishbone
3245
parameter wb_dat_width = 32;
3246
parameter wb_adr_width = 22;
3247
parameter wb_max_burst_width = 4;
3248
parameter wb_mode = "B4";
3249
// avalon
3250
parameter avalon_dat_width = 32;
3251
localparam avalon_adr_width = wb_dat_width * wb_adr_width / avalon_dat_width;
3252
parameter avalon_burst_size = 4;
3253
// cache
3254
parameter async = 1;
3255
parameter nr_of_ways = 1;
3256
parameter aw_offset = 4;
3257
parameter aw_slot = 10;
3258
parameter valid_mem = 1;
3259
// shadow RAM
3260
parameter shadow_ram = 0;
3261
parameter shadow_ram_adr_width = 10;
3262
parameter shadow_ram_size = 1024;
3263
parameter shadow_ram_init = 2; // 0: no init, 1: from file, 2: with zero
3264
parameter shadow_ram_file = "vl_ram.v";
3265
input [wb_dat_width-1:0] wbs_dat_i;
3266
input [wb_adr_width-1:0] wbs_adr_i; // dont include a1,a0
3267
input [wb_dat_width/8-1:0] wbs_sel_i;
3268
input [2:0] wbs_cti_i;
3269
input [1:0] wbs_bte_i;
3270
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
3271
output [wb_dat_width-1:0] wbs_dat_o;
3272
output wbs_ack_o;
3273
output wbs_stall_o;
3274
input wbs_clk, wbs_rst;
3275
input [avalon_dat_width-1:0] readdata;
3276
input readdatavalid;
3277
output [avalon_dat_width-1:0] writedata;
3278
output [avalon_adr_width-1:0] address;
3279
output [avalon_dat_width/8-1:0]  be;
3280
output write;
3281
output read;
3282
output beginbursttransfer;
3283
output [3:0] burstcount;
3284
input waitrequest;
3285
input clk, rst;
3286
wire [wb_dat_width-1:0] wb1_dat_o;
3287
wire [wb_adr_width-1:0] wb1_adr_o;
3288
wire [wb_dat_width/8-1:0] wb1_sel_o;
3289
wire [2:0] wb1_cti_o;
3290
wire [1:0] wb1_bte_o;
3291
wire wb1_we_o;
3292
wire wb1_stb_o;
3293
wire wb1_cyc_o;
3294
wire wb1_stall_i;
3295
wire [wb_dat_width-1:0] wb1_dat_i;
3296
wire wb1_ack_i;
3297
wire [wb_dat_width-1:0] wb2_dat_o;
3298
wire [wb_adr_width-1:0] wb2_adr_o;
3299
wire [wb_dat_width/8-1:0] wb2_sel_o;
3300
wire [2:0] wb2_cti_o;
3301
wire [1:0] wb2_bte_o;
3302
wire wb2_we_o;
3303
wire wb2_stb_o;
3304
wire wb2_cyc_o;
3305
wire wb2_stall_i;
3306
wire [wb_dat_width-1:0] wb2_dat_i;
3307
wire wb2_ack_i;
3308
vl_wb_shadow_ram # ( .dat_width(wb_dat_width), .mode(wb_mode), .max_burst_width(wb_max_burst_width),
3309
                 .shadow_mem_adr_width(shadow_ram_adr_width), .shadow_mem_size(shadow_ram_adr_width), .shadow_mem_init(shadow_ram_init), .shadow_mem_file(shadow_ram_file),
3310
                 .main_mem_adr_width(wb_adr_width))
3311
shadow_ram0 (
3312
    .wbs_dat_i(wbs_dat_i), .wbs_adr_i(wbs_adr_i), .wbs_cti_i(wbs_cti_i), .wbs_bte_i(wbs_bte_i), .wbs_sel_i(wbs_sel_i), .wbs_we_i(wbs_we_i), .wbs_stb_i(wbs_stb_i), .wbs_cyc_i(wbs_cyc_i),
3313
    .wbs_dat_o(wbs_dat_o), .wbs_ack_o(wbs_ack_o), .wbs_stall_o(wbs_stall_o),
3314
    .wbm_dat_o(wb1_dat_o), .wbm_adr_o(wb1_adr_o), .wbm_cti_o(wb1_cti_o), .wbm_bte_o(wb1_bte_o), .wbm_sel_o(wb1_sel_o), .wbm_we_o(wb1_we_o), .wbm_stb_o(wb1_stb_o), .wbm_cyc_o(wb1_cyc_o),
3315
    .wbm_dat_i(wb1_dat_i), .wbm_ack_i(wb1_ack_i), .wbm_stall_i(wb1_stall_i),
3316
    .wb_clk(wbs_clk), .wb_rst(wbs_rst));
3317
vl_wb_cache
3318
# ( .dw_s(wb_dat_width), .aw_s(wb_adr_width), .dw_m(avalon_dat_width), .wbs_mode(wb_mode), .wbs_max_burst_width(wb_max_burst_width), .async(async), .nr_of_ways(nr_of_ways), .aw_offset(aw_offset), .aw_slot(aw_slot), .valid_mem(valid_mem))
3319
cache0 (
3320
    .wbs_dat_i(wb1_dat_o), .wbs_adr_i(wb1_adr_o), .wbs_sel_i(wb1_sel_o), .wbs_cti_i(wb1_cti_o), .wbs_bte_i(wb1_bte_o), .wbs_we_i(wb1_we_o), .wbs_stb_i(wb1_stb_o), .wbs_cyc_i(wb1_cyc_o),
3321
    .wbs_dat_o(wb1_dat_i), .wbs_ack_o(wb1_ack_i), .wbs_stall_o(wb1_stall_i), .wbs_clk(wbs_clk), .wbs_rst(wbs_rst),
3322
    .wbm_dat_o(wb2_dat_o), .wbm_adr_o(wb2_adr_o), .wbm_sel_o(wb2_sel_o), .wbm_cti_o(wb2_cti_o), .wbm_bte_o(wb2_bte_o), .wbm_we_o(wb2_we_o), .wbm_stb_o(wb2_stb_o), .wbm_cyc_o(wb2_cyc_o),
3323
    .wbm_dat_i(wb2_dat_i), .wbm_ack_i(wb2_ack_i), .wbm_stall_i(wb2_stall_i), .wbm_clk(clk), .wbm_rst(rst));
3324
vl_wb_avalon_bridge # ( .adr_width(avalon_adr_width), .dat_width(avalon_dat_width), .burst_size(avalon_burst_size))
3325
bridge0 (
3326
        // wishbone slave side
3327
        .wbs_dat_i(wb2_dat_o), .wbs_adr_i(wb2_adr_o), .wbs_sel_i(wb2_sel_o), .wbs_bte_i(wb2_bte_o), .wbs_cti_i(wb2_cti_o), .wbs_we_i(wb2_we_o), .wbs_cyc_i(wb2_cyc_o), .wbs_stb_i(wb2_stb_o),
3328
        .wbs_dat_o(wb2_dat_i), .wbs_ack_o(wb2_ack_i), .wbs_stall_o(wb2_stall_i),
3329
        // avalon master side
3330
        .readdata(readdata), .readdatavalid(readdatavalid), .address(address), .read(read), .be(be), .write(write), .burstcount(burstcount), .writedata(writedata), .waitrequest(waitrequest), .beginbursttransfer(beginbursttransfer),
3331
        // common
3332
        .clk(clk), .rst(rst));
3333
endmodule
3334 18 unneback
//////////////////////////////////////////////////////////////////////
3335
////                                                              ////
3336
////  Arithmetic functions                                        ////
3337
////                                                              ////
3338
////  Description                                                 ////
3339
////  Arithmetic functions for ALU and DSP                        ////
3340
////                                                              ////
3341
////                                                              ////
3342
////  To Do:                                                      ////
3343
////   -                                                          ////
3344
////                                                              ////
3345
////  Author(s):                                                  ////
3346
////      - Michael Unneback, unneback@opencores.org              ////
3347
////        ORSoC AB                                              ////
3348
////                                                              ////
3349
//////////////////////////////////////////////////////////////////////
3350
////                                                              ////
3351
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3352
////                                                              ////
3353
//// This source file may be used and distributed without         ////
3354
//// restriction provided that this copyright statement is not    ////
3355
//// removed from the file and that any derivative work contains  ////
3356
//// the original copyright notice and the associated disclaimer. ////
3357
////                                                              ////
3358
//// This source file is free software; you can redistribute it   ////
3359
//// and/or modify it under the terms of the GNU Lesser General   ////
3360
//// Public License as published by the Free Software Foundation; ////
3361
//// either version 2.1 of the License, or (at your option) any   ////
3362
//// later version.                                               ////
3363
////                                                              ////
3364
//// This source is distributed in the hope that it will be       ////
3365
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3366
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3367
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3368
//// details.                                                     ////
3369
////                                                              ////
3370
//// You should have received a copy of the GNU Lesser General    ////
3371
//// Public License along with this source; if not, download it   ////
3372
//// from http://www.opencores.org/lgpl.shtml                     ////
3373
////                                                              ////
3374
//////////////////////////////////////////////////////////////////////
3375
// signed multiplication
3376
module vl_mults (a,b,p);
3377
parameter operand_a_width = 18;
3378
parameter operand_b_width = 18;
3379
parameter result_hi = 35;
3380
parameter result_lo = 0;
3381
input [operand_a_width-1:0] a;
3382
input [operand_b_width-1:0] b;
3383
output [result_hi:result_lo] p;
3384
wire signed [operand_a_width-1:0] ai;
3385
wire signed [operand_b_width-1:0] bi;
3386
wire signed [operand_a_width+operand_b_width-1:0] result;
3387
    assign ai = a;
3388
    assign bi = b;
3389
    assign result = ai * bi;
3390
    assign p = result[result_hi:result_lo];
3391
endmodule
3392
module vl_mults18x18 (a,b,p);
3393
input [17:0] a,b;
3394
output [35:0] p;
3395
vl_mult
3396
    # (.operand_a_width(18), .operand_b_width(18))
3397
    mult0 (.a(a), .b(b), .p(p));
3398
endmodule
3399
// unsigned multiplication
3400
module vl_mult (a,b,p);
3401
parameter operand_a_width = 18;
3402
parameter operand_b_width = 18;
3403
parameter result_hi = 35;
3404
parameter result_lo = 0;
3405
input [operand_a_width-1:0] a;
3406
input [operand_b_width-1:0] b;
3407
output [result_hi:result_hi] p;
3408
wire [operand_a_width+operand_b_width-1:0] result;
3409
    assign result = a * b;
3410
    assign p = result[result_hi:result_lo];
3411
endmodule
3412
// shift unit
3413
// supporting the following shift functions
3414
//   SLL
3415
//   SRL
3416
//   SRA
3417
module vl_shift_unit_32( din, s, dout, opcode);
3418
input [31:0] din; // data in operand
3419
input [4:0] s; // shift operand
3420
input [1:0] opcode;
3421
output [31:0] dout;
3422
parameter opcode_sll = 2'b00;
3423
//parameter opcode_srl = 2'b01;
3424
parameter opcode_sra = 2'b10;
3425
//parameter opcode_ror = 2'b11;
3426
wire sll, sra;
3427
assign sll = opcode == opcode_sll;
3428
assign sra = opcode == opcode_sra;
3429
wire [15:1] s1;
3430
wire [3:0] sign;
3431
wire [7:0] tmp [0:3];
3432
// first stage is multiplier based
3433
// shift operand as fractional 8.7
3434
assign s1[15] = sll & s[2:0]==3'd7;
3435
assign s1[14] = sll & s[2:0]==3'd6;
3436
assign s1[13] = sll & s[2:0]==3'd5;
3437
assign s1[12] = sll & s[2:0]==3'd4;
3438
assign s1[11] = sll & s[2:0]==3'd3;
3439
assign s1[10] = sll & s[2:0]==3'd2;
3440
assign s1[ 9] = sll & s[2:0]==3'd1;
3441
assign s1[ 8] = s[2:0]==3'd0;
3442
assign s1[ 7] = !sll & s[2:0]==3'd1;
3443
assign s1[ 6] = !sll & s[2:0]==3'd2;
3444
assign s1[ 5] = !sll & s[2:0]==3'd3;
3445
assign s1[ 4] = !sll & s[2:0]==3'd4;
3446
assign s1[ 3] = !sll & s[2:0]==3'd5;
3447
assign s1[ 2] = !sll & s[2:0]==3'd6;
3448
assign s1[ 1] = !sll & s[2:0]==3'd7;
3449
assign sign[3] = din[31] & sra;
3450
assign sign[2] = sign[3] & (&din[31:24]);
3451
assign sign[1] = sign[2] & (&din[23:16]);
3452
assign sign[0] = sign[1] & (&din[15:8]);
3453
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
3454
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
3455
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
3456
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
3457
// second stage is multiplexer based
3458
// shift on byte level
3459
// mux byte 3
3460
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
3461
                     (sll & s[4:3]==2'b01) ? tmp[2] :
3462
                     (sll & s[4:3]==2'b10) ? tmp[1] :
3463
                     (sll & s[4:3]==2'b11) ? tmp[0] :
3464
                     {8{sign[3]}};
3465
// mux byte 2
3466
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
3467
                     (sll & s[4:3]==2'b01) ? tmp[1] :
3468
                     (sll & s[4:3]==2'b10) ? tmp[0] :
3469
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
3470
                     (s[4:3]==2'b01) ? tmp[3] :
3471
                     {8{sign[3]}};
3472
// mux byte 1
3473
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
3474
                     (sll & s[4:3]==2'b01) ? tmp[0] :
3475
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
3476
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
3477
                     (s[4:3]==2'b01) ? tmp[2] :
3478
                     (s[4:3]==2'b10) ? tmp[3] :
3479
                     {8{sign[3]}};
3480
// mux byte 0
3481
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
3482
                     (sll) ?  {8{1'b0}}:
3483
                     (s[4:3]==2'b01) ? tmp[1] :
3484
                     (s[4:3]==2'b10) ? tmp[2] :
3485
                     tmp[3];
3486
endmodule
3487
// logic unit
3488
// supporting the following logic functions
3489
//    a and b
3490
//    a or  b
3491
//    a xor b
3492
//    not b
3493
module vl_logic_unit( a, b, result, opcode);
3494
parameter width = 32;
3495
parameter opcode_and = 2'b00;
3496
parameter opcode_or  = 2'b01;
3497
parameter opcode_xor = 2'b10;
3498
input [width-1:0] a,b;
3499
output [width-1:0] result;
3500
input [1:0] opcode;
3501
assign result = (opcode==opcode_and) ? a & b :
3502
                (opcode==opcode_or)  ? a | b :
3503
                (opcode==opcode_xor) ? a ^ b :
3504
                b;
3505
endmodule

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