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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Blame information for rev 139

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1 60 unneback
// default SYN_KEEP definition
2 136 unneback
///////////////////////////////////////
3
// dependencies
4
///////////////////////////////////////
5 97 unneback
// size to width
6 6 unneback
//////////////////////////////////////////////////////////////////////
7
////                                                              ////
8
////  Versatile library, clock and reset                          ////
9
////                                                              ////
10
////  Description                                                 ////
11
////  Logic related to clock and reset                            ////
12
////                                                              ////
13
////                                                              ////
14
////  To Do:                                                      ////
15
////   - add more different registers                             ////
16
////                                                              ////
17
////  Author(s):                                                  ////
18
////      - Michael Unneback, unneback@opencores.org              ////
19
////        ORSoC AB                                              ////
20
////                                                              ////
21
//////////////////////////////////////////////////////////////////////
22
////                                                              ////
23
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
24
////                                                              ////
25
//// This source file may be used and distributed without         ////
26
//// restriction provided that this copyright statement is not    ////
27
//// removed from the file and that any derivative work contains  ////
28
//// the original copyright notice and the associated disclaimer. ////
29
////                                                              ////
30
//// This source file is free software; you can redistribute it   ////
31
//// and/or modify it under the terms of the GNU Lesser General   ////
32
//// Public License as published by the Free Software Foundation; ////
33
//// either version 2.1 of the License, or (at your option) any   ////
34
//// later version.                                               ////
35
////                                                              ////
36
//// This source is distributed in the hope that it will be       ////
37
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
38
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
39
//// PURPOSE.  See the GNU Lesser General Public License for more ////
40
//// details.                                                     ////
41
////                                                              ////
42
//// You should have received a copy of the GNU Lesser General    ////
43
//// Public License along with this source; if not, download it   ////
44
//// from http://www.opencores.org/lgpl.shtml                     ////
45
////                                                              ////
46
//////////////////////////////////////////////////////////////////////
47 21 unneback
//altera
48 33 unneback
module vl_gbuf ( i, o);
49
input i;
50
output o;
51
assign o = i;
52
endmodule
53 6 unneback
 // ALTERA
54
 //ACTEL
55
// sync reset
56 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
57 6 unneback
// output active high global reset sync with two DFFs 
58
`timescale 1 ns/100 ps
59
module vl_sync_rst ( rst_n_i, rst_o, clk);
60
input rst_n_i, clk;
61
output rst_o;
62 18 unneback
reg [1:0] tmp;
63 6 unneback
always @ (posedge clk or negedge rst_n_i)
64
if (!rst_n_i)
65 17 unneback
        tmp <= 2'b11;
66 6 unneback
else
67 33 unneback
        tmp <= {1'b0,tmp[1]};
68 17 unneback
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
69 6 unneback
endmodule
70
// vl_pll
71 32 unneback
///////////////////////////////////////////////////////////////////////////////
72
`timescale 1 ps/1 ps
73
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
74
parameter index = 0;
75
parameter number_of_clk = 1;
76
parameter period_time_0 = 20000;
77
parameter period_time_1 = 20000;
78
parameter period_time_2 = 20000;
79
parameter period_time_3 = 20000;
80
parameter period_time_4 = 20000;
81
parameter lock_delay = 2000000;
82
input clk_i, rst_n_i;
83
output lock;
84
output reg [0:number_of_clk-1] clk_o;
85
output [0:number_of_clk-1] rst_o;
86 33 unneback
`ifdef SIM_PLL
87 32 unneback
always
88
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
89
generate if (number_of_clk > 1)
90
always
91
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
92
endgenerate
93
generate if (number_of_clk > 2)
94
always
95
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
96
endgenerate
97 33 unneback
generate if (number_of_clk > 3)
98 32 unneback
always
99
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
100
endgenerate
101 33 unneback
generate if (number_of_clk > 4)
102 32 unneback
always
103
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
104
endgenerate
105
genvar i;
106
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
107
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
108
end
109
endgenerate
110 33 unneback
//assign #lock_delay lock = rst_n_i;
111
assign lock = rst_n_i;
112 32 unneback
endmodule
113 33 unneback
`else
114
`ifdef VL_PLL0
115
`ifdef VL_PLL0_CLK1
116
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
117
`endif
118
`ifdef VL_PLL0_CLK2
119
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
120
`endif
121
`ifdef VL_PLL0_CLK3
122
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
123
`endif
124
`ifdef VL_PLL0_CLK4
125
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
126
`endif
127
`ifdef VL_PLL0_CLK5
128
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
129
`endif
130
`endif
131
`ifdef VL_PLL1
132
`ifdef VL_PLL1_CLK1
133
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
134
`endif
135
`ifdef VL_PLL1_CLK2
136
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
137
`endif
138
`ifdef VL_PLL1_CLK3
139
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
140
`endif
141
`ifdef VL_PLL1_CLK4
142
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
143
`endif
144
`ifdef VL_PLL1_CLK5
145
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
146
`endif
147
`endif
148
`ifdef VL_PLL2
149
`ifdef VL_PLL2_CLK1
150
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
151
`endif
152
`ifdef VL_PLL2_CLK2
153
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
154
`endif
155
`ifdef VL_PLL2_CLK3
156
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
157
`endif
158
`ifdef VL_PLL2_CLK4
159
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
160
`endif
161
`ifdef VL_PLL2_CLK5
162
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
163
`endif
164
`endif
165
`ifdef VL_PLL3
166
`ifdef VL_PLL3_CLK1
167
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
168
`endif
169
`ifdef VL_PLL3_CLK2
170
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
171
`endif
172
`ifdef VL_PLL3_CLK3
173
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
174
`endif
175
`ifdef VL_PLL3_CLK4
176
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
177
`endif
178
`ifdef VL_PLL3_CLK5
179
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
180
`endif
181
`endif
182 32 unneback
genvar i;
183
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
184 40 unneback
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
185 32 unneback
end
186
endgenerate
187
endmodule
188 33 unneback
`endif
189 32 unneback
///////////////////////////////////////////////////////////////////////////////
190 6 unneback
 //altera
191
 //actel
192
//////////////////////////////////////////////////////////////////////
193
////                                                              ////
194
////  Versatile library, registers                                ////
195
////                                                              ////
196
////  Description                                                 ////
197
////  Different type of registers                                 ////
198
////                                                              ////
199
////                                                              ////
200
////  To Do:                                                      ////
201
////   - add more different registers                             ////
202
////                                                              ////
203
////  Author(s):                                                  ////
204
////      - Michael Unneback, unneback@opencores.org              ////
205
////        ORSoC AB                                              ////
206
////                                                              ////
207
//////////////////////////////////////////////////////////////////////
208
////                                                              ////
209
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
210
////                                                              ////
211
//// This source file may be used and distributed without         ////
212
//// restriction provided that this copyright statement is not    ////
213
//// removed from the file and that any derivative work contains  ////
214
//// the original copyright notice and the associated disclaimer. ////
215
////                                                              ////
216
//// This source file is free software; you can redistribute it   ////
217
//// and/or modify it under the terms of the GNU Lesser General   ////
218
//// Public License as published by the Free Software Foundation; ////
219
//// either version 2.1 of the License, or (at your option) any   ////
220
//// later version.                                               ////
221
////                                                              ////
222
//// This source is distributed in the hope that it will be       ////
223
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
224
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
225
//// PURPOSE.  See the GNU Lesser General Public License for more ////
226
//// details.                                                     ////
227
////                                                              ////
228
//// You should have received a copy of the GNU Lesser General    ////
229
//// Public License along with this source; if not, download it   ////
230
//// from http://www.opencores.org/lgpl.shtml                     ////
231
////                                                              ////
232
//////////////////////////////////////////////////////////////////////
233 18 unneback
module vl_dff ( d, q, clk, rst);
234 6 unneback
        parameter width = 1;
235 139 unneback
        parameter reset_value = {width{1'b0}};
236 6 unneback
        input [width-1:0] d;
237
        input clk, rst;
238
        output reg [width-1:0] q;
239
        always @ (posedge clk or posedge rst)
240
        if (rst)
241
                q <= reset_value;
242
        else
243
                q <= d;
244
endmodule
245 18 unneback
module vl_dff_array ( d, q, clk, rst);
246 6 unneback
        parameter width = 1;
247
        parameter depth = 2;
248
        parameter reset_value = 1'b0;
249
        input [width-1:0] d;
250
        input clk, rst;
251
        output [width-1:0] q;
252
        reg  [0:depth-1] q_tmp [width-1:0];
253
        integer i;
254
        always @ (posedge clk or posedge rst)
255
        if (rst) begin
256
            for (i=0;i<depth;i=i+1)
257
                q_tmp[i] <= {width{reset_value}};
258
        end else begin
259
            q_tmp[0] <= d;
260
            for (i=1;i<depth;i=i+1)
261
                q_tmp[i] <= q_tmp[i-1];
262
        end
263
    assign q = q_tmp[depth-1];
264
endmodule
265 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
266 6 unneback
        parameter width = 1;
267 139 unneback
        parameter reset_value = {width{1'b0}};
268 6 unneback
        input [width-1:0] d;
269
        input ce, clk, rst;
270
        output reg [width-1:0] q;
271
        always @ (posedge clk or posedge rst)
272
        if (rst)
273
                q <= reset_value;
274
        else
275
                if (ce)
276
                        q <= d;
277
endmodule
278 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
279 8 unneback
        parameter width = 1;
280 139 unneback
        parameter reset_value = {width{1'b0}};
281 8 unneback
        input [width-1:0] d;
282 10 unneback
        input ce, clear, clk, rst;
283 8 unneback
        output reg [width-1:0] q;
284
        always @ (posedge clk or posedge rst)
285
        if (rst)
286
            q <= reset_value;
287
        else
288
            if (ce)
289
                if (clear)
290
                    q <= {width{1'b0}};
291
                else
292
                    q <= d;
293
endmodule
294 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
295
        parameter width = 1;
296 139 unneback
        parameter reset_value = {width{1'b0}};
297 24 unneback
        input [width-1:0] d;
298
        input ce, set, clk, rst;
299
        output reg [width-1:0] q;
300
        always @ (posedge clk or posedge rst)
301
        if (rst)
302
            q <= reset_value;
303
        else
304
            if (ce)
305
                if (set)
306
                    q <= {width{1'b1}};
307
                else
308
                    q <= d;
309
endmodule
310 29 unneback
module vl_spr ( sp, r, q, clk, rst);
311 64 unneback
        //parameter width = 1;
312
        parameter reset_value = 1'b0;
313 29 unneback
        input sp, r;
314
        output reg q;
315
        input clk, rst;
316
        always @ (posedge clk or posedge rst)
317
        if (rst)
318
            q <= reset_value;
319
        else
320
            if (sp)
321
                q <= 1'b1;
322
            else if (r)
323
                q <= 1'b0;
324
endmodule
325
module vl_srp ( s, rp, q, clk, rst);
326
        parameter width = 1;
327
        parameter reset_value = 0;
328
        input s, rp;
329
        output reg q;
330
        input clk, rst;
331
        always @ (posedge clk or posedge rst)
332
        if (rst)
333
            q <= reset_value;
334
        else
335
            if (rp)
336
                q <= 1'b0;
337
            else if (s)
338
                q <= 1'b1;
339
endmodule
340 6 unneback
// megafunction wizard: %LPM_FF%
341
// GENERATION: STANDARD
342
// VERSION: WM1.0
343
// MODULE: lpm_ff 
344
// ============================================================
345
// File Name: dff_sr.v
346
// Megafunction Name(s):
347
//                      lpm_ff
348
//
349
// Simulation Library Files(s):
350
//                      lpm
351
// ============================================================
352
// ************************************************************
353
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
354
//
355
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
356
// ************************************************************
357
//Copyright (C) 1991-2010 Altera Corporation
358
//Your use of Altera Corporation's design tools, logic functions 
359
//and other software and tools, and its AMPP partner logic 
360
//functions, and any output files from any of the foregoing 
361
//(including device programming or simulation files), and any 
362
//associated documentation or information are expressly subject 
363
//to the terms and conditions of the Altera Program License 
364
//Subscription Agreement, Altera MegaCore Function License 
365
//Agreement, or other applicable license agreement, including, 
366
//without limitation, that your use is for the sole purpose of 
367
//programming logic devices manufactured by Altera and sold by 
368
//Altera or its authorized distributors.  Please refer to the 
369
//applicable agreement for further details.
370
// synopsys translate_off
371
`timescale 1 ps / 1 ps
372
// synopsys translate_on
373 18 unneback
module vl_dff_sr (
374 6 unneback
        aclr,
375
        aset,
376
        clock,
377
        data,
378
        q);
379
        input     aclr;
380
        input     aset;
381
        input     clock;
382
        input     data;
383
        output    q;
384
        wire [0:0] sub_wire0;
385
        wire [0:0] sub_wire1 = sub_wire0[0:0];
386
        wire  q = sub_wire1;
387
        wire  sub_wire2 = data;
388
        wire  sub_wire3 = sub_wire2;
389
        lpm_ff  lpm_ff_component (
390
                                .aclr (aclr),
391
                                .clock (clock),
392
                                .data (sub_wire3),
393
                                .aset (aset),
394
                                .q (sub_wire0)
395
                                // synopsys translate_off
396
                                ,
397
                                .aload (),
398
                                .enable (),
399
                                .sclr (),
400
                                .sload (),
401
                                .sset ()
402
                                // synopsys translate_on
403
                                );
404
        defparam
405
                lpm_ff_component.lpm_fftype = "DFF",
406
                lpm_ff_component.lpm_type = "LPM_FF",
407
                lpm_ff_component.lpm_width = 1;
408
endmodule
409
// ============================================================
410
// CNX file retrieval info
411
// ============================================================
412
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
413
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
414
// Retrieval info: PRIVATE: ASET NUMERIC "1"
415
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
416
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
417
// Retrieval info: PRIVATE: DFF NUMERIC "1"
418
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
419
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
420
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
421
// Retrieval info: PRIVATE: SSET NUMERIC "0"
422
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
423
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
424
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
425
// Retrieval info: PRIVATE: nBit NUMERIC "1"
426
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
427
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
428
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
429
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
430
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
431
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
432
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
433
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
434
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
435
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
436
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
437
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
438
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
439
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
440
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
441
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
442
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
443
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
444
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
445
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
446
// Retrieval info: LIB_FILE: lpm
447
// LATCH
448
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
449 18 unneback
module vl_latch ( d, le, q, clk);
450 6 unneback
input d, le;
451
output q;
452
input clk;
453
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
454
endmodule
455 18 unneback
module vl_shreg ( d, q, clk, rst);
456 17 unneback
parameter depth = 10;
457
input d;
458
output q;
459
input clk, rst;
460
reg [1:depth] dffs;
461
always @ (posedge clk or posedge rst)
462
if (rst)
463
    dffs <= {depth{1'b0}};
464
else
465
    dffs <= {d,dffs[1:depth-1]};
466
assign q = dffs[depth];
467
endmodule
468 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
469 17 unneback
parameter depth = 10;
470
input d, ce;
471
output q;
472
input clk, rst;
473
reg [1:depth] dffs;
474
always @ (posedge clk or posedge rst)
475
if (rst)
476
    dffs <= {depth{1'b0}};
477
else
478
    if (ce)
479
        dffs <= {d,dffs[1:depth-1]};
480
assign q = dffs[depth];
481
endmodule
482 18 unneback
module vl_delay ( d, q, clk, rst);
483 15 unneback
parameter depth = 10;
484
input d;
485
output q;
486
input clk, rst;
487
reg [1:depth] dffs;
488
always @ (posedge clk or posedge rst)
489
if (rst)
490
    dffs <= {depth{1'b0}};
491
else
492
    dffs <= {d,dffs[1:depth-1]};
493
assign q = dffs[depth];
494
endmodule
495 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
496 17 unneback
parameter depth = 10;
497
input d;
498
output q, emptyflag;
499
input clk, rst;
500
reg [1:depth] dffs;
501
always @ (posedge clk or posedge rst)
502
if (rst)
503
    dffs <= {depth{1'b0}};
504
else
505
    dffs <= {d,dffs[1:depth-1]};
506
assign q = dffs[depth];
507
assign emptyflag = !(|dffs);
508
endmodule
509 98 unneback
module vl_pulse2toggle ( pl, q, clk, rst);
510 94 unneback
input pl;
511 98 unneback
output reg q;
512 94 unneback
input clk, rst;
513
always @ (posedge clk or posedge rst)
514
if (rst)
515
    q <= 1'b0;
516
else
517
    q <= pl ^ q;
518
endmodule
519 98 unneback
module vl_toggle2pulse (d, pl, clk, rst);
520 94 unneback
input d;
521
output pl;
522
input clk, rst;
523
reg dff;
524
always @ (posedge clk or posedge rst)
525
if (rst)
526
    dff <= 1'b0;
527
else
528
    dff <= d;
529 98 unneback
assign pl = d ^ dff;
530 94 unneback
endmodule
531
module vl_synchronizer (d, q, clk, rst);
532
input d;
533
output reg q;
534 116 unneback
input clk, rst;
535 94 unneback
reg dff;
536
always @ (posedge clk or posedge rst)
537
if (rst)
538 100 unneback
    {q,dff} <= 2'b00;
539 94 unneback
else
540 100 unneback
    {q,dff} <= {dff,d};
541 94 unneback
endmodule
542 97 unneback
module vl_cdc ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst);
543 94 unneback
input start_pl;
544
output take_it_pl;
545
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
546
output got_it_pl;
547
input clk_src, rst_src;
548
input clk_dst, rst_dst;
549
wire take_it_tg, take_it_tg_sync;
550
wire got_it_tg, got_it_tg_sync;
551
// src -> dst
552
vl_pulse2toggle p2t0 (
553
    .pl(start_pl),
554
    .q(take_it_tg),
555
    .clk(clk_src),
556
    .rst(rst_src));
557
vl_synchronizer sync0 (
558
    .d(take_it_tg),
559
    .q(take_it_tg_sync),
560
    .clk(clk_dst),
561
    .rst(rst_dst));
562
vl_toggle2pulse t2p0 (
563 100 unneback
    .d(take_it_tg_sync),
564 94 unneback
    .pl(take_it_pl),
565
    .clk(clk_dst),
566
    .rst(rst_dst));
567
// dst -> src
568 98 unneback
vl_pulse2toggle p2t1 (
569 94 unneback
    .pl(take_it_grant_pl),
570
    .q(got_it_tg),
571
    .clk(clk_dst),
572
    .rst(rst_dst));
573
vl_synchronizer sync1 (
574
    .d(got_it_tg),
575
    .q(got_it_tg_sync),
576
    .clk(clk_src),
577
    .rst(rst_src));
578
vl_toggle2pulse t2p1 (
579 100 unneback
    .d(got_it_tg_sync),
580 94 unneback
    .pl(got_it_pl),
581
    .clk(clk_src),
582
    .rst(rst_src));
583
endmodule
584 6 unneback
//////////////////////////////////////////////////////////////////////
585
////                                                              ////
586 18 unneback
////  Logic functions                                             ////
587
////                                                              ////
588
////  Description                                                 ////
589
////  Logic functions such as multiplexers                        ////
590
////                                                              ////
591
////                                                              ////
592
////  To Do:                                                      ////
593
////   -                                                          ////
594
////                                                              ////
595
////  Author(s):                                                  ////
596
////      - Michael Unneback, unneback@opencores.org              ////
597
////        ORSoC AB                                              ////
598
////                                                              ////
599
//////////////////////////////////////////////////////////////////////
600
////                                                              ////
601
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
602
////                                                              ////
603
//// This source file may be used and distributed without         ////
604
//// restriction provided that this copyright statement is not    ////
605
//// removed from the file and that any derivative work contains  ////
606
//// the original copyright notice and the associated disclaimer. ////
607
////                                                              ////
608
//// This source file is free software; you can redistribute it   ////
609
//// and/or modify it under the terms of the GNU Lesser General   ////
610
//// Public License as published by the Free Software Foundation; ////
611
//// either version 2.1 of the License, or (at your option) any   ////
612
//// later version.                                               ////
613
////                                                              ////
614
//// This source is distributed in the hope that it will be       ////
615
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
616
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
617
//// PURPOSE.  See the GNU Lesser General Public License for more ////
618
//// details.                                                     ////
619
////                                                              ////
620
//// You should have received a copy of the GNU Lesser General    ////
621
//// Public License along with this source; if not, download it   ////
622
//// from http://www.opencores.org/lgpl.shtml                     ////
623
////                                                              ////
624
//////////////////////////////////////////////////////////////////////
625 36 unneback
module vl_mux_andor ( a, sel, dout);
626
parameter width = 32;
627
parameter nr_of_ports = 4;
628
input [nr_of_ports*width-1:0] a;
629
input [nr_of_ports-1:0] sel;
630
output reg [width-1:0] dout;
631 38 unneback
integer i,j;
632 36 unneback
always @ (a, sel)
633
begin
634
    dout = a[width-1:0] & {width{sel[0]}};
635 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
636
        for (j=0;j<width;j=j+1)
637
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
638 36 unneback
end
639
endmodule
640 34 unneback
module vl_mux2_andor ( a1, a0, sel, dout);
641
parameter width = 32;
642 35 unneback
localparam nr_of_ports = 2;
643 34 unneback
input [width-1:0] a1, a0;
644
input [nr_of_ports-1:0] sel;
645
output [width-1:0] dout;
646 36 unneback
vl_mux_andor
647 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
648 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
649 34 unneback
endmodule
650
module vl_mux3_andor ( a2, a1, a0, sel, dout);
651
parameter width = 32;
652 35 unneback
localparam nr_of_ports = 3;
653 34 unneback
input [width-1:0] a2, a1, a0;
654
input [nr_of_ports-1:0] sel;
655
output [width-1:0] dout;
656 36 unneback
vl_mux_andor
657 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
658 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
659 34 unneback
endmodule
660 18 unneback
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
661
parameter width = 32;
662 35 unneback
localparam nr_of_ports = 4;
663 18 unneback
input [width-1:0] a3, a2, a1, a0;
664
input [nr_of_ports-1:0] sel;
665 22 unneback
output [width-1:0] dout;
666 36 unneback
vl_mux_andor
667 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
668 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
669 18 unneback
endmodule
670
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
671
parameter width = 32;
672 35 unneback
localparam nr_of_ports = 5;
673 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
674
input [nr_of_ports-1:0] sel;
675 22 unneback
output [width-1:0] dout;
676 36 unneback
vl_mux_andor
677 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
678 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
679 18 unneback
endmodule
680
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
681
parameter width = 32;
682 35 unneback
localparam nr_of_ports = 6;
683 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
684
input [nr_of_ports-1:0] sel;
685 22 unneback
output [width-1:0] dout;
686 36 unneback
vl_mux_andor
687 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
688 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
689 18 unneback
endmodule
690 43 unneback
module vl_parity_generate (data, parity);
691
parameter word_size = 32;
692
parameter chunk_size = 8;
693
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
694
input [word_size-1:0] data;
695
output reg [word_size/chunk_size-1:0] parity;
696
integer i,j;
697
always @ (data)
698
for (i=0;i<word_size/chunk_size;i=i+1) begin
699
    parity[i] = parity_type;
700
    for (j=0;j<chunk_size;j=j+1) begin
701 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
702 43 unneback
    end
703
end
704
endmodule
705
module vl_parity_check( data, parity, parity_error);
706
parameter word_size = 32;
707
parameter chunk_size = 8;
708
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
709
input [word_size-1:0] data;
710
input [word_size/chunk_size-1:0] parity;
711
output parity_error;
712 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
713 43 unneback
integer i,j;
714
always @ (data or parity)
715
for (i=0;i<word_size/chunk_size;i=i+1) begin
716
    error_flag[i] = parity[i] ^ parity_type;
717
    for (j=0;j<chunk_size;j=j+1) begin
718 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
719 43 unneback
    end
720
end
721
assign parity_error = |error_flag;
722
endmodule
723 18 unneback
//////////////////////////////////////////////////////////////////////
724
////                                                              ////
725 44 unneback
////  IO functions                                                ////
726
////                                                              ////
727
////  Description                                                 ////
728
////  IO functions such as IOB flip-flops                         ////
729
////                                                              ////
730
////                                                              ////
731
////  To Do:                                                      ////
732
////   -                                                          ////
733
////                                                              ////
734
////  Author(s):                                                  ////
735
////      - Michael Unneback, unneback@opencores.org              ////
736
////        ORSoC AB                                              ////
737
////                                                              ////
738
//////////////////////////////////////////////////////////////////////
739
////                                                              ////
740
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
741
////                                                              ////
742
//// This source file may be used and distributed without         ////
743
//// restriction provided that this copyright statement is not    ////
744
//// removed from the file and that any derivative work contains  ////
745
//// the original copyright notice and the associated disclaimer. ////
746
////                                                              ////
747
//// This source file is free software; you can redistribute it   ////
748
//// and/or modify it under the terms of the GNU Lesser General   ////
749
//// Public License as published by the Free Software Foundation; ////
750
//// either version 2.1 of the License, or (at your option) any   ////
751
//// later version.                                               ////
752
////                                                              ////
753
//// This source is distributed in the hope that it will be       ////
754
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
755
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
756
//// PURPOSE.  See the GNU Lesser General Public License for more ////
757
//// details.                                                     ////
758
////                                                              ////
759
//// You should have received a copy of the GNU Lesser General    ////
760
//// Public License along with this source; if not, download it   ////
761
//// from http://www.opencores.org/lgpl.shtml                     ////
762
////                                                              ////
763
//////////////////////////////////////////////////////////////////////
764 45 unneback
`timescale 1ns/1ns
765 44 unneback
module vl_o_dff (d_i, o_pad, clk, rst);
766
parameter width = 1;
767 45 unneback
parameter reset_value = {width{1'b0}};
768
input  [width-1:0]  d_i;
769 44 unneback
output [width-1:0] o_pad;
770
input clk, rst;
771 60 unneback
wire [width-1:0] d_i_int /*synthesis syn_keep = 1*/;
772 45 unneback
reg  [width-1:0] o_pad_int;
773 44 unneback
assign d_i_int = d_i;
774
genvar i;
775 45 unneback
generate
776 136 unneback
for (i=0;i<width;i=i+1) begin : dffs
777 44 unneback
    always @ (posedge clk or posedge rst)
778
    if (rst)
779 45 unneback
        o_pad_int[i] <= reset_value[i];
780 44 unneback
    else
781 45 unneback
        o_pad_int[i] <= d_i_int[i];
782
    assign #1 o_pad[i] = o_pad_int[i];
783 44 unneback
end
784
endgenerate
785
endmodule
786 45 unneback
`timescale 1ns/1ns
787 44 unneback
module vl_io_dff_oe ( d_i, d_o, oe, io_pad, clk, rst);
788
parameter width = 1;
789
input  [width-1:0] d_o;
790
output reg [width-1:0] d_i;
791
input oe;
792
inout [width-1:0] io_pad;
793
input clk, rst;
794 60 unneback
wire [width-1:0] oe_d /*synthesis syn_keep = 1*/;
795 44 unneback
reg [width-1:0] oe_q;
796
reg [width-1:0] d_o_q;
797
assign oe_d = {width{oe}};
798
genvar i;
799
generate
800 136 unneback
for (i=0;i<width;i=i+1) begin : dffs
801 44 unneback
    always @ (posedge clk or posedge rst)
802
    if (rst)
803
        oe_q[i] <= 1'b0;
804
    else
805
        oe_q[i] <= oe_d[i];
806
    always @ (posedge clk or posedge rst)
807
    if (rst)
808
        d_o_q[i] <= 1'b0;
809
    else
810
        d_o_q[i] <= d_o[i];
811
    always @ (posedge clk or posedge rst)
812
    if (rst)
813
        d_i[i] <= 1'b0;
814
    else
815
        d_i[i] <= io_pad[i];
816 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
817 44 unneback
end
818
endgenerate
819
endmodule
820 136 unneback
module vl_o_ddr (d_h_i, d_l_i, o_pad, clk, rst);
821
parameter width = 1;
822
input  [width-1:0] d_h_i, d_l_i;
823
output [width-1:0] o_pad;
824
input clk, rst;
825
genvar i;
826
generate
827
for (i=0;i<width;i=i+1) begin : ddr
828
    ddio_out ddio_out0( .aclr(rst), .datain_h(d_h_i[i]), .datain_l(d_l_i[i]), .outclock(clk), .dataout(o_pad[i]) );
829
end
830
endgenerate
831
endmodule
832
module vl_o_clk ( clk_o_pad, clk, rst);
833
input clk, rst;
834
output clk_o_pad;
835
vl_o_ddr o_ddr0( .d_h_i(1'b1), .d_l_i(1'b0), .o_pad(clk_o_pad), .clk(clk), .rst(rst));
836
endmodule
837 44 unneback
//////////////////////////////////////////////////////////////////////
838
////                                                              ////
839 6 unneback
////  Versatile counter                                           ////
840
////                                                              ////
841
////  Description                                                 ////
842
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
843
////  counter                                                     ////
844
////                                                              ////
845
////  To Do:                                                      ////
846
////   - add LFSR with more taps                                  ////
847
////                                                              ////
848
////  Author(s):                                                  ////
849
////      - Michael Unneback, unneback@opencores.org              ////
850
////        ORSoC AB                                              ////
851
////                                                              ////
852
//////////////////////////////////////////////////////////////////////
853
////                                                              ////
854
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
855
////                                                              ////
856
//// This source file may be used and distributed without         ////
857
//// restriction provided that this copyright statement is not    ////
858
//// removed from the file and that any derivative work contains  ////
859
//// the original copyright notice and the associated disclaimer. ////
860
////                                                              ////
861
//// This source file is free software; you can redistribute it   ////
862
//// and/or modify it under the terms of the GNU Lesser General   ////
863
//// Public License as published by the Free Software Foundation; ////
864
//// either version 2.1 of the License, or (at your option) any   ////
865
//// later version.                                               ////
866
////                                                              ////
867
//// This source is distributed in the hope that it will be       ////
868
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
869
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
870
//// PURPOSE.  See the GNU Lesser General Public License for more ////
871
//// details.                                                     ////
872
////                                                              ////
873
//// You should have received a copy of the GNU Lesser General    ////
874
//// Public License along with this source; if not, download it   ////
875
//// from http://www.opencores.org/lgpl.shtml                     ////
876
////                                                              ////
877
//////////////////////////////////////////////////////////////////////
878
// binary counter
879 139 unneback
module vl_cnt_bin (
880
 q, rst, clk);
881
   parameter length = 4;
882
   output [length:1] q;
883
   input rst;
884
   input clk;
885
   parameter clear_value = 0;
886
   parameter set_value = 1;
887
   parameter wrap_value = 0;
888
   parameter level1_value = 15;
889
   reg  [length:1] qi;
890
   wire [length:1] q_next;
891
   assign q_next = qi + {{length-1{1'b0}},1'b1};
892
   always @ (posedge clk or posedge rst)
893
     if (rst)
894
       qi <= {length{1'b0}};
895
     else
896
       qi <= q_next;
897
   assign q = qi;
898
endmodule
899
//////////////////////////////////////////////////////////////////////
900
////                                                              ////
901
////  Versatile counter                                           ////
902
////                                                              ////
903
////  Description                                                 ////
904
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
905
////  counter                                                     ////
906
////                                                              ////
907
////  To Do:                                                      ////
908
////   - add LFSR with more taps                                  ////
909
////                                                              ////
910
////  Author(s):                                                  ////
911
////      - Michael Unneback, unneback@opencores.org              ////
912
////        ORSoC AB                                              ////
913
////                                                              ////
914
//////////////////////////////////////////////////////////////////////
915
////                                                              ////
916
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
917
////                                                              ////
918
//// This source file may be used and distributed without         ////
919
//// restriction provided that this copyright statement is not    ////
920
//// removed from the file and that any derivative work contains  ////
921
//// the original copyright notice and the associated disclaimer. ////
922
////                                                              ////
923
//// This source file is free software; you can redistribute it   ////
924
//// and/or modify it under the terms of the GNU Lesser General   ////
925
//// Public License as published by the Free Software Foundation; ////
926
//// either version 2.1 of the License, or (at your option) any   ////
927
//// later version.                                               ////
928
////                                                              ////
929
//// This source is distributed in the hope that it will be       ////
930
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
931
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
932
//// PURPOSE.  See the GNU Lesser General Public License for more ////
933
//// details.                                                     ////
934
////                                                              ////
935
//// You should have received a copy of the GNU Lesser General    ////
936
//// Public License along with this source; if not, download it   ////
937
//// from http://www.opencores.org/lgpl.shtml                     ////
938
////                                                              ////
939
//////////////////////////////////////////////////////////////////////
940
// binary counter
941
module vl_cnt_bin_clear (
942
 clear, q, rst, clk);
943
   parameter length = 4;
944
   input clear;
945
   output [length:1] q;
946
   input rst;
947
   input clk;
948
   parameter clear_value = 0;
949
   parameter set_value = 1;
950
   parameter wrap_value = 0;
951
   parameter level1_value = 15;
952
   reg  [length:1] qi;
953
   wire [length:1] q_next;
954
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
955
   always @ (posedge clk or posedge rst)
956
     if (rst)
957
       qi <= {length{1'b0}};
958
     else
959
       qi <= q_next;
960
   assign q = qi;
961
endmodule
962
//////////////////////////////////////////////////////////////////////
963
////                                                              ////
964
////  Versatile counter                                           ////
965
////                                                              ////
966
////  Description                                                 ////
967
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
968
////  counter                                                     ////
969
////                                                              ////
970
////  To Do:                                                      ////
971
////   - add LFSR with more taps                                  ////
972
////                                                              ////
973
////  Author(s):                                                  ////
974
////      - Michael Unneback, unneback@opencores.org              ////
975
////        ORSoC AB                                              ////
976
////                                                              ////
977
//////////////////////////////////////////////////////////////////////
978
////                                                              ////
979
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
980
////                                                              ////
981
//// This source file may be used and distributed without         ////
982
//// restriction provided that this copyright statement is not    ////
983
//// removed from the file and that any derivative work contains  ////
984
//// the original copyright notice and the associated disclaimer. ////
985
////                                                              ////
986
//// This source file is free software; you can redistribute it   ////
987
//// and/or modify it under the terms of the GNU Lesser General   ////
988
//// Public License as published by the Free Software Foundation; ////
989
//// either version 2.1 of the License, or (at your option) any   ////
990
//// later version.                                               ////
991
////                                                              ////
992
//// This source is distributed in the hope that it will be       ////
993
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
994
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
995
//// PURPOSE.  See the GNU Lesser General Public License for more ////
996
//// details.                                                     ////
997
////                                                              ////
998
//// You should have received a copy of the GNU Lesser General    ////
999
//// Public License along with this source; if not, download it   ////
1000
//// from http://www.opencores.org/lgpl.shtml                     ////
1001
////                                                              ////
1002
//////////////////////////////////////////////////////////////////////
1003
// binary counter
1004 40 unneback
module vl_cnt_bin_ce (
1005
 cke, q, rst, clk);
1006 22 unneback
   parameter length = 4;
1007 6 unneback
   input cke;
1008
   output [length:1] q;
1009
   input rst;
1010
   input clk;
1011
   parameter clear_value = 0;
1012
   parameter set_value = 1;
1013
   parameter wrap_value = 0;
1014
   parameter level1_value = 15;
1015
   reg  [length:1] qi;
1016
   wire [length:1] q_next;
1017
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1018
   always @ (posedge clk or posedge rst)
1019
     if (rst)
1020
       qi <= {length{1'b0}};
1021
     else
1022
     if (cke)
1023
       qi <= q_next;
1024
   assign q = qi;
1025
endmodule
1026
//////////////////////////////////////////////////////////////////////
1027
////                                                              ////
1028
////  Versatile counter                                           ////
1029
////                                                              ////
1030
////  Description                                                 ////
1031
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1032
////  counter                                                     ////
1033
////                                                              ////
1034
////  To Do:                                                      ////
1035
////   - add LFSR with more taps                                  ////
1036
////                                                              ////
1037
////  Author(s):                                                  ////
1038
////      - Michael Unneback, unneback@opencores.org              ////
1039
////        ORSoC AB                                              ////
1040
////                                                              ////
1041
//////////////////////////////////////////////////////////////////////
1042
////                                                              ////
1043
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1044
////                                                              ////
1045
//// This source file may be used and distributed without         ////
1046
//// restriction provided that this copyright statement is not    ////
1047
//// removed from the file and that any derivative work contains  ////
1048
//// the original copyright notice and the associated disclaimer. ////
1049
////                                                              ////
1050
//// This source file is free software; you can redistribute it   ////
1051
//// and/or modify it under the terms of the GNU Lesser General   ////
1052
//// Public License as published by the Free Software Foundation; ////
1053
//// either version 2.1 of the License, or (at your option) any   ////
1054
//// later version.                                               ////
1055
////                                                              ////
1056
//// This source is distributed in the hope that it will be       ////
1057
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1058
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1059
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1060
//// details.                                                     ////
1061
////                                                              ////
1062
//// You should have received a copy of the GNU Lesser General    ////
1063
//// Public License along with this source; if not, download it   ////
1064
//// from http://www.opencores.org/lgpl.shtml                     ////
1065
////                                                              ////
1066
//////////////////////////////////////////////////////////////////////
1067
// binary counter
1068 139 unneback
module vl_cnt_bin_ce_clear (
1069
 clear, cke, q, rst, clk);
1070
   parameter length = 4;
1071
   input clear;
1072
   input cke;
1073
   output [length:1] q;
1074
   input rst;
1075
   input clk;
1076
   parameter clear_value = 0;
1077
   parameter set_value = 1;
1078
   parameter wrap_value = 0;
1079
   parameter level1_value = 15;
1080
   reg  [length:1] qi;
1081
   wire [length:1] q_next;
1082
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1083
   always @ (posedge clk or posedge rst)
1084
     if (rst)
1085
       qi <= {length{1'b0}};
1086
     else
1087
     if (cke)
1088
       qi <= q_next;
1089
   assign q = qi;
1090
endmodule
1091
//////////////////////////////////////////////////////////////////////
1092
////                                                              ////
1093
////  Versatile counter                                           ////
1094
////                                                              ////
1095
////  Description                                                 ////
1096
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1097
////  counter                                                     ////
1098
////                                                              ////
1099
////  To Do:                                                      ////
1100
////   - add LFSR with more taps                                  ////
1101
////                                                              ////
1102
////  Author(s):                                                  ////
1103
////      - Michael Unneback, unneback@opencores.org              ////
1104
////        ORSoC AB                                              ////
1105
////                                                              ////
1106
//////////////////////////////////////////////////////////////////////
1107
////                                                              ////
1108
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1109
////                                                              ////
1110
//// This source file may be used and distributed without         ////
1111
//// restriction provided that this copyright statement is not    ////
1112
//// removed from the file and that any derivative work contains  ////
1113
//// the original copyright notice and the associated disclaimer. ////
1114
////                                                              ////
1115
//// This source file is free software; you can redistribute it   ////
1116
//// and/or modify it under the terms of the GNU Lesser General   ////
1117
//// Public License as published by the Free Software Foundation; ////
1118
//// either version 2.1 of the License, or (at your option) any   ////
1119
//// later version.                                               ////
1120
////                                                              ////
1121
//// This source is distributed in the hope that it will be       ////
1122
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1123
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1124
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1125
//// details.                                                     ////
1126
////                                                              ////
1127
//// You should have received a copy of the GNU Lesser General    ////
1128
//// Public License along with this source; if not, download it   ////
1129
//// from http://www.opencores.org/lgpl.shtml                     ////
1130
////                                                              ////
1131
//////////////////////////////////////////////////////////////////////
1132
// binary counter
1133
module vl_cnt_bin_ce_clear_l1_l2 (
1134
 clear, cke, q, level1, level2, rst, clk);
1135
   parameter length = 4;
1136
   input clear;
1137
   input cke;
1138
   output [length:1] q;
1139
   output reg level1;
1140
   output reg level2;
1141
   input rst;
1142
   input clk;
1143
   parameter clear_value = 0;
1144
   parameter set_value = 1;
1145
   parameter wrap_value = 15;
1146
   parameter level1_value = 8;
1147
   parameter level2_value = 15;
1148
   wire rew;
1149
   assign rew = 1'b0;
1150
   reg  [length:1] qi;
1151
   wire [length:1] q_next;
1152
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1153
   always @ (posedge clk or posedge rst)
1154
     if (rst)
1155
       qi <= {length{1'b0}};
1156
     else
1157
     if (cke)
1158
       qi <= q_next;
1159
   assign q = qi;
1160
    always @ (posedge clk or posedge rst)
1161
    if (rst)
1162
        level1 <= 1'b0;
1163
    else
1164
    if (cke)
1165
    if (clear)
1166
        level1 <= 1'b0;
1167
    else if (q_next == level1_value)
1168
        level1 <= 1'b1;
1169
    else if (qi == level1_value & rew)
1170
        level1 <= 1'b0;
1171
    always @ (posedge clk or posedge rst)
1172
    if (rst)
1173
        level2 <= 1'b0;
1174
    else
1175
    if (cke)
1176
    if (clear)
1177
        level2 <= 1'b0;
1178
    else if (q_next == level2_value)
1179
        level2 <= 1'b1;
1180
    else if (qi == level2_value & rew)
1181
        level2 <= 1'b0;
1182
endmodule
1183
//////////////////////////////////////////////////////////////////////
1184
////                                                              ////
1185
////  Versatile counter                                           ////
1186
////                                                              ////
1187
////  Description                                                 ////
1188
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1189
////  counter                                                     ////
1190
////                                                              ////
1191
////  To Do:                                                      ////
1192
////   - add LFSR with more taps                                  ////
1193
////                                                              ////
1194
////  Author(s):                                                  ////
1195
////      - Michael Unneback, unneback@opencores.org              ////
1196
////        ORSoC AB                                              ////
1197
////                                                              ////
1198
//////////////////////////////////////////////////////////////////////
1199
////                                                              ////
1200
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1201
////                                                              ////
1202
//// This source file may be used and distributed without         ////
1203
//// restriction provided that this copyright statement is not    ////
1204
//// removed from the file and that any derivative work contains  ////
1205
//// the original copyright notice and the associated disclaimer. ////
1206
////                                                              ////
1207
//// This source file is free software; you can redistribute it   ////
1208
//// and/or modify it under the terms of the GNU Lesser General   ////
1209
//// Public License as published by the Free Software Foundation; ////
1210
//// either version 2.1 of the License, or (at your option) any   ////
1211
//// later version.                                               ////
1212
////                                                              ////
1213
//// This source is distributed in the hope that it will be       ////
1214
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1215
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1216
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1217
//// details.                                                     ////
1218
////                                                              ////
1219
//// You should have received a copy of the GNU Lesser General    ////
1220
//// Public License along with this source; if not, download it   ////
1221
//// from http://www.opencores.org/lgpl.shtml                     ////
1222
////                                                              ////
1223
//////////////////////////////////////////////////////////////////////
1224
// binary counter
1225
module vl_cnt_bin_ce_clear_set_rew (
1226
 clear, set, cke, rew, q, rst, clk);
1227
   parameter length = 4;
1228
   input clear;
1229
   input set;
1230
   input cke;
1231
   input rew;
1232
   output [length:1] q;
1233
   input rst;
1234
   input clk;
1235
   parameter clear_value = 0;
1236
   parameter set_value = 1;
1237
   parameter wrap_value = 0;
1238
   parameter level1_value = 15;
1239
   reg  [length:1] qi;
1240
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1241
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1242
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1243
   assign q_next = rew ? q_next_rew : q_next_fw;
1244
   always @ (posedge clk or posedge rst)
1245
     if (rst)
1246
       qi <= {length{1'b0}};
1247
     else
1248
     if (cke)
1249
       qi <= q_next;
1250
   assign q = qi;
1251
endmodule
1252
//////////////////////////////////////////////////////////////////////
1253
////                                                              ////
1254
////  Versatile counter                                           ////
1255
////                                                              ////
1256
////  Description                                                 ////
1257
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1258
////  counter                                                     ////
1259
////                                                              ////
1260
////  To Do:                                                      ////
1261
////   - add LFSR with more taps                                  ////
1262
////                                                              ////
1263
////  Author(s):                                                  ////
1264
////      - Michael Unneback, unneback@opencores.org              ////
1265
////        ORSoC AB                                              ////
1266
////                                                              ////
1267
//////////////////////////////////////////////////////////////////////
1268
////                                                              ////
1269
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1270
////                                                              ////
1271
//// This source file may be used and distributed without         ////
1272
//// restriction provided that this copyright statement is not    ////
1273
//// removed from the file and that any derivative work contains  ////
1274
//// the original copyright notice and the associated disclaimer. ////
1275
////                                                              ////
1276
//// This source file is free software; you can redistribute it   ////
1277
//// and/or modify it under the terms of the GNU Lesser General   ////
1278
//// Public License as published by the Free Software Foundation; ////
1279
//// either version 2.1 of the License, or (at your option) any   ////
1280
//// later version.                                               ////
1281
////                                                              ////
1282
//// This source is distributed in the hope that it will be       ////
1283
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1284
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1285
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1286
//// details.                                                     ////
1287
////                                                              ////
1288
//// You should have received a copy of the GNU Lesser General    ////
1289
//// Public License along with this source; if not, download it   ////
1290
//// from http://www.opencores.org/lgpl.shtml                     ////
1291
////                                                              ////
1292
//////////////////////////////////////////////////////////////////////
1293
// binary counter
1294
module vl_cnt_bin_ce_rew_l1 (
1295
 cke, rew, level1, rst, clk);
1296
   parameter length = 4;
1297
   input cke;
1298
   input rew;
1299
   output reg level1;
1300
   input rst;
1301
   input clk;
1302
   parameter clear_value = 0;
1303
   parameter set_value = 1;
1304
   parameter wrap_value = 1;
1305
   parameter level1_value = 15;
1306
   wire clear;
1307
   assign clear = 1'b0;
1308
   reg  [length:1] qi;
1309
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1310
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1311
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1312
   assign q_next = rew ? q_next_rew : q_next_fw;
1313
   always @ (posedge clk or posedge rst)
1314
     if (rst)
1315
       qi <= {length{1'b0}};
1316
     else
1317
     if (cke)
1318
       qi <= q_next;
1319
    always @ (posedge clk or posedge rst)
1320
    if (rst)
1321
        level1 <= 1'b0;
1322
    else
1323
    if (cke)
1324
    if (clear)
1325
        level1 <= 1'b0;
1326
    else if (q_next == level1_value)
1327
        level1 <= 1'b1;
1328
    else if (qi == level1_value & rew)
1329
        level1 <= 1'b0;
1330
endmodule
1331
//////////////////////////////////////////////////////////////////////
1332
////                                                              ////
1333
////  Versatile counter                                           ////
1334
////                                                              ////
1335
////  Description                                                 ////
1336
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1337
////  counter                                                     ////
1338
////                                                              ////
1339
////  To Do:                                                      ////
1340
////   - add LFSR with more taps                                  ////
1341
////                                                              ////
1342
////  Author(s):                                                  ////
1343
////      - Michael Unneback, unneback@opencores.org              ////
1344
////        ORSoC AB                                              ////
1345
////                                                              ////
1346
//////////////////////////////////////////////////////////////////////
1347
////                                                              ////
1348
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1349
////                                                              ////
1350
//// This source file may be used and distributed without         ////
1351
//// restriction provided that this copyright statement is not    ////
1352
//// removed from the file and that any derivative work contains  ////
1353
//// the original copyright notice and the associated disclaimer. ////
1354
////                                                              ////
1355
//// This source file is free software; you can redistribute it   ////
1356
//// and/or modify it under the terms of the GNU Lesser General   ////
1357
//// Public License as published by the Free Software Foundation; ////
1358
//// either version 2.1 of the License, or (at your option) any   ////
1359
//// later version.                                               ////
1360
////                                                              ////
1361
//// This source is distributed in the hope that it will be       ////
1362
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1363
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1364
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1365
//// details.                                                     ////
1366
////                                                              ////
1367
//// You should have received a copy of the GNU Lesser General    ////
1368
//// Public License along with this source; if not, download it   ////
1369
//// from http://www.opencores.org/lgpl.shtml                     ////
1370
////                                                              ////
1371
//////////////////////////////////////////////////////////////////////
1372
// binary counter
1373 40 unneback
module vl_cnt_bin_ce_rew_zq_l1 (
1374
 cke, rew, zq, level1, rst, clk);
1375 6 unneback
   parameter length = 4;
1376
   input cke;
1377
   input rew;
1378 25 unneback
   output reg zq;
1379
   output reg level1;
1380
   input rst;
1381
   input clk;
1382
   parameter clear_value = 0;
1383
   parameter set_value = 1;
1384
   parameter wrap_value = 1;
1385
   parameter level1_value = 15;
1386 29 unneback
   wire clear;
1387 30 unneback
   assign clear = 1'b0;
1388 25 unneback
   reg  [length:1] qi;
1389
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1390
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1391
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1392
   assign q_next = rew ? q_next_rew : q_next_fw;
1393
   always @ (posedge clk or posedge rst)
1394
     if (rst)
1395
       qi <= {length{1'b0}};
1396
     else
1397
     if (cke)
1398
       qi <= q_next;
1399
   always @ (posedge clk or posedge rst)
1400
     if (rst)
1401
       zq <= 1'b1;
1402
     else
1403
     if (cke)
1404
       zq <= q_next == {length{1'b0}};
1405
    always @ (posedge clk or posedge rst)
1406
    if (rst)
1407
        level1 <= 1'b0;
1408
    else
1409
    if (cke)
1410 29 unneback
    if (clear)
1411
        level1 <= 1'b0;
1412
    else if (q_next == level1_value)
1413 25 unneback
        level1 <= 1'b1;
1414
    else if (qi == level1_value & rew)
1415
        level1 <= 1'b0;
1416
endmodule
1417
//////////////////////////////////////////////////////////////////////
1418
////                                                              ////
1419
////  Versatile counter                                           ////
1420
////                                                              ////
1421
////  Description                                                 ////
1422
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1423
////  counter                                                     ////
1424
////                                                              ////
1425
////  To Do:                                                      ////
1426
////   - add LFSR with more taps                                  ////
1427
////                                                              ////
1428
////  Author(s):                                                  ////
1429
////      - Michael Unneback, unneback@opencores.org              ////
1430
////        ORSoC AB                                              ////
1431
////                                                              ////
1432
//////////////////////////////////////////////////////////////////////
1433
////                                                              ////
1434
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1435
////                                                              ////
1436
//// This source file may be used and distributed without         ////
1437
//// restriction provided that this copyright statement is not    ////
1438
//// removed from the file and that any derivative work contains  ////
1439
//// the original copyright notice and the associated disclaimer. ////
1440
////                                                              ////
1441
//// This source file is free software; you can redistribute it   ////
1442
//// and/or modify it under the terms of the GNU Lesser General   ////
1443
//// Public License as published by the Free Software Foundation; ////
1444
//// either version 2.1 of the License, or (at your option) any   ////
1445
//// later version.                                               ////
1446
////                                                              ////
1447
//// This source is distributed in the hope that it will be       ////
1448
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1449
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1450
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1451
//// details.                                                     ////
1452
////                                                              ////
1453
//// You should have received a copy of the GNU Lesser General    ////
1454
//// Public License along with this source; if not, download it   ////
1455
//// from http://www.opencores.org/lgpl.shtml                     ////
1456
////                                                              ////
1457
//////////////////////////////////////////////////////////////////////
1458
// binary counter
1459 40 unneback
module vl_cnt_bin_ce_rew_q_zq_l1 (
1460
 cke, rew, q, zq, level1, rst, clk);
1461 25 unneback
   parameter length = 4;
1462
   input cke;
1463
   input rew;
1464
   output [length:1] q;
1465
   output reg zq;
1466
   output reg level1;
1467
   input rst;
1468
   input clk;
1469
   parameter clear_value = 0;
1470
   parameter set_value = 1;
1471
   parameter wrap_value = 1;
1472
   parameter level1_value = 15;
1473 29 unneback
   wire clear;
1474 30 unneback
   assign clear = 1'b0;
1475 25 unneback
   reg  [length:1] qi;
1476
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1477
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1478
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1479
   assign q_next = rew ? q_next_rew : q_next_fw;
1480
   always @ (posedge clk or posedge rst)
1481
     if (rst)
1482
       qi <= {length{1'b0}};
1483
     else
1484
     if (cke)
1485
       qi <= q_next;
1486
   assign q = qi;
1487
   always @ (posedge clk or posedge rst)
1488
     if (rst)
1489
       zq <= 1'b1;
1490
     else
1491
     if (cke)
1492
       zq <= q_next == {length{1'b0}};
1493
    always @ (posedge clk or posedge rst)
1494
    if (rst)
1495
        level1 <= 1'b0;
1496
    else
1497
    if (cke)
1498 29 unneback
    if (clear)
1499
        level1 <= 1'b0;
1500
    else if (q_next == level1_value)
1501 25 unneback
        level1 <= 1'b1;
1502
    else if (qi == level1_value & rew)
1503
        level1 <= 1'b0;
1504
endmodule
1505
//////////////////////////////////////////////////////////////////////
1506
////                                                              ////
1507
////  Versatile counter                                           ////
1508
////                                                              ////
1509
////  Description                                                 ////
1510
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1511
////  counter                                                     ////
1512
////                                                              ////
1513
////  To Do:                                                      ////
1514
////   - add LFSR with more taps                                  ////
1515
////                                                              ////
1516
////  Author(s):                                                  ////
1517
////      - Michael Unneback, unneback@opencores.org              ////
1518
////        ORSoC AB                                              ////
1519
////                                                              ////
1520
//////////////////////////////////////////////////////////////////////
1521
////                                                              ////
1522
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1523
////                                                              ////
1524
//// This source file may be used and distributed without         ////
1525
//// restriction provided that this copyright statement is not    ////
1526
//// removed from the file and that any derivative work contains  ////
1527
//// the original copyright notice and the associated disclaimer. ////
1528
////                                                              ////
1529
//// This source file is free software; you can redistribute it   ////
1530
//// and/or modify it under the terms of the GNU Lesser General   ////
1531
//// Public License as published by the Free Software Foundation; ////
1532
//// either version 2.1 of the License, or (at your option) any   ////
1533
//// later version.                                               ////
1534
////                                                              ////
1535
//// This source is distributed in the hope that it will be       ////
1536
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1537
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1538
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1539
//// details.                                                     ////
1540
////                                                              ////
1541
//// You should have received a copy of the GNU Lesser General    ////
1542
//// Public License along with this source; if not, download it   ////
1543
//// from http://www.opencores.org/lgpl.shtml                     ////
1544
////                                                              ////
1545
//////////////////////////////////////////////////////////////////////
1546 75 unneback
// LFSR counter
1547 136 unneback
module vl_cnt_lfsr_zq (
1548
 zq, rst, clk);
1549
   parameter length = 4;
1550
   output reg zq;
1551
   input rst;
1552
   input clk;
1553
   parameter clear_value = 0;
1554
   parameter set_value = 1;
1555
   parameter wrap_value = 8;
1556
   parameter level1_value = 15;
1557
   reg  [length:1] qi;
1558
   reg lfsr_fb;
1559
   wire [length:1] q_next;
1560
   reg [32:1] polynom;
1561
   integer i;
1562
   always @ (qi)
1563
   begin
1564
        case (length)
1565
         2: polynom = 32'b11;                               // 0x3
1566
         3: polynom = 32'b110;                              // 0x6
1567
         4: polynom = 32'b1100;                             // 0xC
1568
         5: polynom = 32'b10100;                            // 0x14
1569
         6: polynom = 32'b110000;                           // 0x30
1570
         7: polynom = 32'b1100000;                          // 0x60
1571
         8: polynom = 32'b10111000;                         // 0xb8
1572
         9: polynom = 32'b100010000;                        // 0x110
1573
        10: polynom = 32'b1001000000;                       // 0x240
1574
        11: polynom = 32'b10100000000;                      // 0x500
1575
        12: polynom = 32'b100000101001;                     // 0x829
1576
        13: polynom = 32'b1000000001100;                    // 0x100C
1577
        14: polynom = 32'b10000000010101;                   // 0x2015
1578
        15: polynom = 32'b110000000000000;                  // 0x6000
1579
        16: polynom = 32'b1101000000001000;                 // 0xD008
1580
        17: polynom = 32'b10010000000000000;                // 0x12000
1581
        18: polynom = 32'b100000010000000000;               // 0x20400
1582
        19: polynom = 32'b1000000000000100011;              // 0x40023
1583
        20: polynom = 32'b10010000000000000000;             // 0x90000
1584
        21: polynom = 32'b101000000000000000000;            // 0x140000
1585
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1586
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1587
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1588
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1589
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1590
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1591
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1592
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1593
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1594
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1595
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1596
        default: polynom = 32'b0;
1597
        endcase
1598
        lfsr_fb = qi[length];
1599
        for (i=length-1; i>=1; i=i-1) begin
1600
            if (polynom[i])
1601
                lfsr_fb = lfsr_fb  ~^ qi[i];
1602
        end
1603
    end
1604
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1605
   always @ (posedge clk or posedge rst)
1606
     if (rst)
1607
       qi <= {length{1'b0}};
1608
     else
1609
       qi <= q_next;
1610
   always @ (posedge clk or posedge rst)
1611
     if (rst)
1612
       zq <= 1'b1;
1613
     else
1614
       zq <= q_next == {length{1'b0}};
1615
endmodule
1616
//////////////////////////////////////////////////////////////////////
1617
////                                                              ////
1618
////  Versatile counter                                           ////
1619
////                                                              ////
1620
////  Description                                                 ////
1621
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1622
////  counter                                                     ////
1623
////                                                              ////
1624
////  To Do:                                                      ////
1625
////   - add LFSR with more taps                                  ////
1626
////                                                              ////
1627
////  Author(s):                                                  ////
1628
////      - Michael Unneback, unneback@opencores.org              ////
1629
////        ORSoC AB                                              ////
1630
////                                                              ////
1631
//////////////////////////////////////////////////////////////////////
1632
////                                                              ////
1633
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1634
////                                                              ////
1635
//// This source file may be used and distributed without         ////
1636
//// restriction provided that this copyright statement is not    ////
1637
//// removed from the file and that any derivative work contains  ////
1638
//// the original copyright notice and the associated disclaimer. ////
1639
////                                                              ////
1640
//// This source file is free software; you can redistribute it   ////
1641
//// and/or modify it under the terms of the GNU Lesser General   ////
1642
//// Public License as published by the Free Software Foundation; ////
1643
//// either version 2.1 of the License, or (at your option) any   ////
1644
//// later version.                                               ////
1645
////                                                              ////
1646
//// This source is distributed in the hope that it will be       ////
1647
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1648
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1649
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1650
//// details.                                                     ////
1651
////                                                              ////
1652
//// You should have received a copy of the GNU Lesser General    ////
1653
//// Public License along with this source; if not, download it   ////
1654
//// from http://www.opencores.org/lgpl.shtml                     ////
1655
////                                                              ////
1656
//////////////////////////////////////////////////////////////////////
1657
// LFSR counter
1658 75 unneback
module vl_cnt_lfsr_ce (
1659
 cke, zq, rst, clk);
1660
   parameter length = 4;
1661
   input cke;
1662
   output reg zq;
1663
   input rst;
1664
   input clk;
1665
   parameter clear_value = 0;
1666
   parameter set_value = 1;
1667
   parameter wrap_value = 0;
1668
   parameter level1_value = 15;
1669
   reg  [length:1] qi;
1670
   reg lfsr_fb;
1671
   wire [length:1] q_next;
1672
   reg [32:1] polynom;
1673
   integer i;
1674
   always @ (qi)
1675
   begin
1676
        case (length)
1677
         2: polynom = 32'b11;                               // 0x3
1678
         3: polynom = 32'b110;                              // 0x6
1679
         4: polynom = 32'b1100;                             // 0xC
1680
         5: polynom = 32'b10100;                            // 0x14
1681
         6: polynom = 32'b110000;                           // 0x30
1682
         7: polynom = 32'b1100000;                          // 0x60
1683
         8: polynom = 32'b10111000;                         // 0xb8
1684
         9: polynom = 32'b100010000;                        // 0x110
1685
        10: polynom = 32'b1001000000;                       // 0x240
1686
        11: polynom = 32'b10100000000;                      // 0x500
1687
        12: polynom = 32'b100000101001;                     // 0x829
1688
        13: polynom = 32'b1000000001100;                    // 0x100C
1689
        14: polynom = 32'b10000000010101;                   // 0x2015
1690
        15: polynom = 32'b110000000000000;                  // 0x6000
1691
        16: polynom = 32'b1101000000001000;                 // 0xD008
1692
        17: polynom = 32'b10010000000000000;                // 0x12000
1693
        18: polynom = 32'b100000010000000000;               // 0x20400
1694
        19: polynom = 32'b1000000000000100011;              // 0x40023
1695
        20: polynom = 32'b10010000000000000000;             // 0x90000
1696
        21: polynom = 32'b101000000000000000000;            // 0x140000
1697
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1698
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1699
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1700
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1701
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1702
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1703
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1704
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1705
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1706
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1707
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1708
        default: polynom = 32'b0;
1709
        endcase
1710
        lfsr_fb = qi[length];
1711
        for (i=length-1; i>=1; i=i-1) begin
1712
            if (polynom[i])
1713
                lfsr_fb = lfsr_fb  ~^ qi[i];
1714
        end
1715
    end
1716
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1717
   always @ (posedge clk or posedge rst)
1718
     if (rst)
1719
       qi <= {length{1'b0}};
1720
     else
1721
     if (cke)
1722
       qi <= q_next;
1723
   always @ (posedge clk or posedge rst)
1724
     if (rst)
1725
       zq <= 1'b1;
1726
     else
1727
     if (cke)
1728
       zq <= q_next == {length{1'b0}};
1729
endmodule
1730
//////////////////////////////////////////////////////////////////////
1731
////                                                              ////
1732
////  Versatile counter                                           ////
1733
////                                                              ////
1734
////  Description                                                 ////
1735
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1736
////  counter                                                     ////
1737
////                                                              ////
1738
////  To Do:                                                      ////
1739
////   - add LFSR with more taps                                  ////
1740
////                                                              ////
1741
////  Author(s):                                                  ////
1742
////      - Michael Unneback, unneback@opencores.org              ////
1743
////        ORSoC AB                                              ////
1744
////                                                              ////
1745
//////////////////////////////////////////////////////////////////////
1746
////                                                              ////
1747
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1748
////                                                              ////
1749
//// This source file may be used and distributed without         ////
1750
//// restriction provided that this copyright statement is not    ////
1751
//// removed from the file and that any derivative work contains  ////
1752
//// the original copyright notice and the associated disclaimer. ////
1753
////                                                              ////
1754
//// This source file is free software; you can redistribute it   ////
1755
//// and/or modify it under the terms of the GNU Lesser General   ////
1756
//// Public License as published by the Free Software Foundation; ////
1757
//// either version 2.1 of the License, or (at your option) any   ////
1758
//// later version.                                               ////
1759
////                                                              ////
1760
//// This source is distributed in the hope that it will be       ////
1761
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1762
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1763
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1764
//// details.                                                     ////
1765
////                                                              ////
1766
//// You should have received a copy of the GNU Lesser General    ////
1767
//// Public License along with this source; if not, download it   ////
1768
//// from http://www.opencores.org/lgpl.shtml                     ////
1769
////                                                              ////
1770
//////////////////////////////////////////////////////////////////////
1771 139 unneback
// LFSR counter
1772
module vl_cnt_lfsr_ce_zq (
1773
 cke, zq, rst, clk);
1774
   parameter length = 4;
1775
   input cke;
1776
   output reg zq;
1777
   input rst;
1778
   input clk;
1779
   parameter clear_value = 0;
1780
   parameter set_value = 1;
1781
   parameter wrap_value = 8;
1782
   parameter level1_value = 15;
1783
   reg  [length:1] qi;
1784
   reg lfsr_fb;
1785
   wire [length:1] q_next;
1786
   reg [32:1] polynom;
1787
   integer i;
1788
   always @ (qi)
1789
   begin
1790
        case (length)
1791
         2: polynom = 32'b11;                               // 0x3
1792
         3: polynom = 32'b110;                              // 0x6
1793
         4: polynom = 32'b1100;                             // 0xC
1794
         5: polynom = 32'b10100;                            // 0x14
1795
         6: polynom = 32'b110000;                           // 0x30
1796
         7: polynom = 32'b1100000;                          // 0x60
1797
         8: polynom = 32'b10111000;                         // 0xb8
1798
         9: polynom = 32'b100010000;                        // 0x110
1799
        10: polynom = 32'b1001000000;                       // 0x240
1800
        11: polynom = 32'b10100000000;                      // 0x500
1801
        12: polynom = 32'b100000101001;                     // 0x829
1802
        13: polynom = 32'b1000000001100;                    // 0x100C
1803
        14: polynom = 32'b10000000010101;                   // 0x2015
1804
        15: polynom = 32'b110000000000000;                  // 0x6000
1805
        16: polynom = 32'b1101000000001000;                 // 0xD008
1806
        17: polynom = 32'b10010000000000000;                // 0x12000
1807
        18: polynom = 32'b100000010000000000;               // 0x20400
1808
        19: polynom = 32'b1000000000000100011;              // 0x40023
1809
        20: polynom = 32'b10010000000000000000;             // 0x90000
1810
        21: polynom = 32'b101000000000000000000;            // 0x140000
1811
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1812
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1813
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1814
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1815
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1816
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1817
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1818
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1819
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1820
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1821
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1822
        default: polynom = 32'b0;
1823
        endcase
1824
        lfsr_fb = qi[length];
1825
        for (i=length-1; i>=1; i=i-1) begin
1826
            if (polynom[i])
1827
                lfsr_fb = lfsr_fb  ~^ qi[i];
1828
        end
1829
    end
1830
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1831
   always @ (posedge clk or posedge rst)
1832
     if (rst)
1833
       qi <= {length{1'b0}};
1834
     else
1835
     if (cke)
1836
       qi <= q_next;
1837
   always @ (posedge clk or posedge rst)
1838
     if (rst)
1839
       zq <= 1'b1;
1840
     else
1841
     if (cke)
1842
       zq <= q_next == {length{1'b0}};
1843
endmodule
1844
//////////////////////////////////////////////////////////////////////
1845
////                                                              ////
1846
////  Versatile counter                                           ////
1847
////                                                              ////
1848
////  Description                                                 ////
1849
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1850
////  counter                                                     ////
1851
////                                                              ////
1852
////  To Do:                                                      ////
1853
////   - add LFSR with more taps                                  ////
1854
////                                                              ////
1855
////  Author(s):                                                  ////
1856
////      - Michael Unneback, unneback@opencores.org              ////
1857
////        ORSoC AB                                              ////
1858
////                                                              ////
1859
//////////////////////////////////////////////////////////////////////
1860
////                                                              ////
1861
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1862
////                                                              ////
1863
//// This source file may be used and distributed without         ////
1864
//// restriction provided that this copyright statement is not    ////
1865
//// removed from the file and that any derivative work contains  ////
1866
//// the original copyright notice and the associated disclaimer. ////
1867
////                                                              ////
1868
//// This source file is free software; you can redistribute it   ////
1869
//// and/or modify it under the terms of the GNU Lesser General   ////
1870
//// Public License as published by the Free Software Foundation; ////
1871
//// either version 2.1 of the License, or (at your option) any   ////
1872
//// later version.                                               ////
1873
////                                                              ////
1874
//// This source is distributed in the hope that it will be       ////
1875
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1876
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1877
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1878
//// details.                                                     ////
1879
////                                                              ////
1880
//// You should have received a copy of the GNU Lesser General    ////
1881
//// Public License along with this source; if not, download it   ////
1882
//// from http://www.opencores.org/lgpl.shtml                     ////
1883
////                                                              ////
1884
//////////////////////////////////////////////////////////////////////
1885
// LFSR counter
1886
module vl_cnt_lfsr_ce_q (
1887
 cke, q, rst, clk);
1888
   parameter length = 4;
1889
   input cke;
1890
   output [length:1] q;
1891
   input rst;
1892
   input clk;
1893
   parameter clear_value = 0;
1894
   parameter set_value = 1;
1895
   parameter wrap_value = 8;
1896
   parameter level1_value = 15;
1897
   reg  [length:1] qi;
1898
   reg lfsr_fb;
1899
   wire [length:1] q_next;
1900
   reg [32:1] polynom;
1901
   integer i;
1902
   always @ (qi)
1903
   begin
1904
        case (length)
1905
         2: polynom = 32'b11;                               // 0x3
1906
         3: polynom = 32'b110;                              // 0x6
1907
         4: polynom = 32'b1100;                             // 0xC
1908
         5: polynom = 32'b10100;                            // 0x14
1909
         6: polynom = 32'b110000;                           // 0x30
1910
         7: polynom = 32'b1100000;                          // 0x60
1911
         8: polynom = 32'b10111000;                         // 0xb8
1912
         9: polynom = 32'b100010000;                        // 0x110
1913
        10: polynom = 32'b1001000000;                       // 0x240
1914
        11: polynom = 32'b10100000000;                      // 0x500
1915
        12: polynom = 32'b100000101001;                     // 0x829
1916
        13: polynom = 32'b1000000001100;                    // 0x100C
1917
        14: polynom = 32'b10000000010101;                   // 0x2015
1918
        15: polynom = 32'b110000000000000;                  // 0x6000
1919
        16: polynom = 32'b1101000000001000;                 // 0xD008
1920
        17: polynom = 32'b10010000000000000;                // 0x12000
1921
        18: polynom = 32'b100000010000000000;               // 0x20400
1922
        19: polynom = 32'b1000000000000100011;              // 0x40023
1923
        20: polynom = 32'b10010000000000000000;             // 0x90000
1924
        21: polynom = 32'b101000000000000000000;            // 0x140000
1925
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1926
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1927
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1928
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1929
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1930
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1931
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1932
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1933
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1934
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1935
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1936
        default: polynom = 32'b0;
1937
        endcase
1938
        lfsr_fb = qi[length];
1939
        for (i=length-1; i>=1; i=i-1) begin
1940
            if (polynom[i])
1941
                lfsr_fb = lfsr_fb  ~^ qi[i];
1942
        end
1943
    end
1944
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1945
   always @ (posedge clk or posedge rst)
1946
     if (rst)
1947
       qi <= {length{1'b0}};
1948
     else
1949
     if (cke)
1950
       qi <= q_next;
1951
   assign q = qi;
1952
endmodule
1953
//////////////////////////////////////////////////////////////////////
1954
////                                                              ////
1955
////  Versatile counter                                           ////
1956
////                                                              ////
1957
////  Description                                                 ////
1958
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1959
////  counter                                                     ////
1960
////                                                              ////
1961
////  To Do:                                                      ////
1962
////   - add LFSR with more taps                                  ////
1963
////                                                              ////
1964
////  Author(s):                                                  ////
1965
////      - Michael Unneback, unneback@opencores.org              ////
1966
////        ORSoC AB                                              ////
1967
////                                                              ////
1968
//////////////////////////////////////////////////////////////////////
1969
////                                                              ////
1970
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1971
////                                                              ////
1972
//// This source file may be used and distributed without         ////
1973
//// restriction provided that this copyright statement is not    ////
1974
//// removed from the file and that any derivative work contains  ////
1975
//// the original copyright notice and the associated disclaimer. ////
1976
////                                                              ////
1977
//// This source file is free software; you can redistribute it   ////
1978
//// and/or modify it under the terms of the GNU Lesser General   ////
1979
//// Public License as published by the Free Software Foundation; ////
1980
//// either version 2.1 of the License, or (at your option) any   ////
1981
//// later version.                                               ////
1982
////                                                              ////
1983
//// This source is distributed in the hope that it will be       ////
1984
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1985
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1986
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1987
//// details.                                                     ////
1988
////                                                              ////
1989
//// You should have received a copy of the GNU Lesser General    ////
1990
//// Public License along with this source; if not, download it   ////
1991
//// from http://www.opencores.org/lgpl.shtml                     ////
1992
////                                                              ////
1993
//////////////////////////////////////////////////////////////////////
1994
// LFSR counter
1995
module vl_cnt_lfsr_ce_clear_q (
1996
 clear, cke, q, rst, clk);
1997
   parameter length = 4;
1998
   input clear;
1999
   input cke;
2000
   output [length:1] q;
2001
   input rst;
2002
   input clk;
2003
   parameter clear_value = 0;
2004
   parameter set_value = 1;
2005
   parameter wrap_value = 8;
2006
   parameter level1_value = 15;
2007
   reg  [length:1] qi;
2008
   reg lfsr_fb;
2009
   wire [length:1] q_next;
2010
   reg [32:1] polynom;
2011
   integer i;
2012
   always @ (qi)
2013
   begin
2014
        case (length)
2015
         2: polynom = 32'b11;                               // 0x3
2016
         3: polynom = 32'b110;                              // 0x6
2017
         4: polynom = 32'b1100;                             // 0xC
2018
         5: polynom = 32'b10100;                            // 0x14
2019
         6: polynom = 32'b110000;                           // 0x30
2020
         7: polynom = 32'b1100000;                          // 0x60
2021
         8: polynom = 32'b10111000;                         // 0xb8
2022
         9: polynom = 32'b100010000;                        // 0x110
2023
        10: polynom = 32'b1001000000;                       // 0x240
2024
        11: polynom = 32'b10100000000;                      // 0x500
2025
        12: polynom = 32'b100000101001;                     // 0x829
2026
        13: polynom = 32'b1000000001100;                    // 0x100C
2027
        14: polynom = 32'b10000000010101;                   // 0x2015
2028
        15: polynom = 32'b110000000000000;                  // 0x6000
2029
        16: polynom = 32'b1101000000001000;                 // 0xD008
2030
        17: polynom = 32'b10010000000000000;                // 0x12000
2031
        18: polynom = 32'b100000010000000000;               // 0x20400
2032
        19: polynom = 32'b1000000000000100011;              // 0x40023
2033
        20: polynom = 32'b10010000000000000000;             // 0x90000
2034
        21: polynom = 32'b101000000000000000000;            // 0x140000
2035
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2036
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2037
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2038
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2039
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2040
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2041
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2042
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2043
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2044
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2045
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2046
        default: polynom = 32'b0;
2047
        endcase
2048
        lfsr_fb = qi[length];
2049
        for (i=length-1; i>=1; i=i-1) begin
2050
            if (polynom[i])
2051
                lfsr_fb = lfsr_fb  ~^ qi[i];
2052
        end
2053
    end
2054
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2055
   always @ (posedge clk or posedge rst)
2056
     if (rst)
2057
       qi <= {length{1'b0}};
2058
     else
2059
     if (cke)
2060
       qi <= q_next;
2061
   assign q = qi;
2062
endmodule
2063
//////////////////////////////////////////////////////////////////////
2064
////                                                              ////
2065
////  Versatile counter                                           ////
2066
////                                                              ////
2067
////  Description                                                 ////
2068
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2069
////  counter                                                     ////
2070
////                                                              ////
2071
////  To Do:                                                      ////
2072
////   - add LFSR with more taps                                  ////
2073
////                                                              ////
2074
////  Author(s):                                                  ////
2075
////      - Michael Unneback, unneback@opencores.org              ////
2076
////        ORSoC AB                                              ////
2077
////                                                              ////
2078
//////////////////////////////////////////////////////////////////////
2079
////                                                              ////
2080
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2081
////                                                              ////
2082
//// This source file may be used and distributed without         ////
2083
//// restriction provided that this copyright statement is not    ////
2084
//// removed from the file and that any derivative work contains  ////
2085
//// the original copyright notice and the associated disclaimer. ////
2086
////                                                              ////
2087
//// This source file is free software; you can redistribute it   ////
2088
//// and/or modify it under the terms of the GNU Lesser General   ////
2089
//// Public License as published by the Free Software Foundation; ////
2090
//// either version 2.1 of the License, or (at your option) any   ////
2091
//// later version.                                               ////
2092
////                                                              ////
2093
//// This source is distributed in the hope that it will be       ////
2094
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2095
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2096
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2097
//// details.                                                     ////
2098
////                                                              ////
2099
//// You should have received a copy of the GNU Lesser General    ////
2100
//// Public License along with this source; if not, download it   ////
2101
//// from http://www.opencores.org/lgpl.shtml                     ////
2102
////                                                              ////
2103
//////////////////////////////////////////////////////////////////////
2104
// LFSR counter
2105
module vl_cnt_lfsr_ce_q_zq (
2106
 cke, q, zq, rst, clk);
2107
   parameter length = 4;
2108
   input cke;
2109
   output [length:1] q;
2110
   output reg zq;
2111
   input rst;
2112
   input clk;
2113
   parameter clear_value = 0;
2114
   parameter set_value = 1;
2115
   parameter wrap_value = 8;
2116
   parameter level1_value = 15;
2117
   reg  [length:1] qi;
2118
   reg lfsr_fb;
2119
   wire [length:1] q_next;
2120
   reg [32:1] polynom;
2121
   integer i;
2122
   always @ (qi)
2123
   begin
2124
        case (length)
2125
         2: polynom = 32'b11;                               // 0x3
2126
         3: polynom = 32'b110;                              // 0x6
2127
         4: polynom = 32'b1100;                             // 0xC
2128
         5: polynom = 32'b10100;                            // 0x14
2129
         6: polynom = 32'b110000;                           // 0x30
2130
         7: polynom = 32'b1100000;                          // 0x60
2131
         8: polynom = 32'b10111000;                         // 0xb8
2132
         9: polynom = 32'b100010000;                        // 0x110
2133
        10: polynom = 32'b1001000000;                       // 0x240
2134
        11: polynom = 32'b10100000000;                      // 0x500
2135
        12: polynom = 32'b100000101001;                     // 0x829
2136
        13: polynom = 32'b1000000001100;                    // 0x100C
2137
        14: polynom = 32'b10000000010101;                   // 0x2015
2138
        15: polynom = 32'b110000000000000;                  // 0x6000
2139
        16: polynom = 32'b1101000000001000;                 // 0xD008
2140
        17: polynom = 32'b10010000000000000;                // 0x12000
2141
        18: polynom = 32'b100000010000000000;               // 0x20400
2142
        19: polynom = 32'b1000000000000100011;              // 0x40023
2143
        20: polynom = 32'b10010000000000000000;             // 0x90000
2144
        21: polynom = 32'b101000000000000000000;            // 0x140000
2145
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2146
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2147
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2148
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2149
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2150
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2151
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2152
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2153
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2154
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2155
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2156
        default: polynom = 32'b0;
2157
        endcase
2158
        lfsr_fb = qi[length];
2159
        for (i=length-1; i>=1; i=i-1) begin
2160
            if (polynom[i])
2161
                lfsr_fb = lfsr_fb  ~^ qi[i];
2162
        end
2163
    end
2164
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2165
   always @ (posedge clk or posedge rst)
2166
     if (rst)
2167
       qi <= {length{1'b0}};
2168
     else
2169
     if (cke)
2170
       qi <= q_next;
2171
   assign q = qi;
2172
   always @ (posedge clk or posedge rst)
2173
     if (rst)
2174
       zq <= 1'b1;
2175
     else
2176
     if (cke)
2177
       zq <= q_next == {length{1'b0}};
2178
endmodule
2179
//////////////////////////////////////////////////////////////////////
2180
////                                                              ////
2181
////  Versatile counter                                           ////
2182
////                                                              ////
2183
////  Description                                                 ////
2184
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2185
////  counter                                                     ////
2186
////                                                              ////
2187
////  To Do:                                                      ////
2188
////   - add LFSR with more taps                                  ////
2189
////                                                              ////
2190
////  Author(s):                                                  ////
2191
////      - Michael Unneback, unneback@opencores.org              ////
2192
////        ORSoC AB                                              ////
2193
////                                                              ////
2194
//////////////////////////////////////////////////////////////////////
2195
////                                                              ////
2196
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2197
////                                                              ////
2198
//// This source file may be used and distributed without         ////
2199
//// restriction provided that this copyright statement is not    ////
2200
//// removed from the file and that any derivative work contains  ////
2201
//// the original copyright notice and the associated disclaimer. ////
2202
////                                                              ////
2203
//// This source file is free software; you can redistribute it   ////
2204
//// and/or modify it under the terms of the GNU Lesser General   ////
2205
//// Public License as published by the Free Software Foundation; ////
2206
//// either version 2.1 of the License, or (at your option) any   ////
2207
//// later version.                                               ////
2208
////                                                              ////
2209
//// This source is distributed in the hope that it will be       ////
2210
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2211
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2212
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2213
//// details.                                                     ////
2214
////                                                              ////
2215
//// You should have received a copy of the GNU Lesser General    ////
2216
//// Public License along with this source; if not, download it   ////
2217
//// from http://www.opencores.org/lgpl.shtml                     ////
2218
////                                                              ////
2219
//////////////////////////////////////////////////////////////////////
2220
// LFSR counter
2221
module vl_cnt_lfsr_ce_rew_l1 (
2222
 cke, rew, level1, rst, clk);
2223
   parameter length = 4;
2224
   input cke;
2225
   input rew;
2226
   output reg level1;
2227
   input rst;
2228
   input clk;
2229
   parameter clear_value = 0;
2230
   parameter set_value = 1;
2231
   parameter wrap_value = 8;
2232
   parameter level1_value = 15;
2233
   wire clear;
2234
   assign clear = 1'b0;
2235
   reg  [length:1] qi;
2236
   reg lfsr_fb, lfsr_fb_rew;
2237
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2238
   reg [32:1] polynom_rew;
2239
   integer j;
2240
   reg [32:1] polynom;
2241
   integer i;
2242
   always @ (qi)
2243
   begin
2244
        case (length)
2245
         2: polynom = 32'b11;                               // 0x3
2246
         3: polynom = 32'b110;                              // 0x6
2247
         4: polynom = 32'b1100;                             // 0xC
2248
         5: polynom = 32'b10100;                            // 0x14
2249
         6: polynom = 32'b110000;                           // 0x30
2250
         7: polynom = 32'b1100000;                          // 0x60
2251
         8: polynom = 32'b10111000;                         // 0xb8
2252
         9: polynom = 32'b100010000;                        // 0x110
2253
        10: polynom = 32'b1001000000;                       // 0x240
2254
        11: polynom = 32'b10100000000;                      // 0x500
2255
        12: polynom = 32'b100000101001;                     // 0x829
2256
        13: polynom = 32'b1000000001100;                    // 0x100C
2257
        14: polynom = 32'b10000000010101;                   // 0x2015
2258
        15: polynom = 32'b110000000000000;                  // 0x6000
2259
        16: polynom = 32'b1101000000001000;                 // 0xD008
2260
        17: polynom = 32'b10010000000000000;                // 0x12000
2261
        18: polynom = 32'b100000010000000000;               // 0x20400
2262
        19: polynom = 32'b1000000000000100011;              // 0x40023
2263
        20: polynom = 32'b10010000000000000000;             // 0x90000
2264
        21: polynom = 32'b101000000000000000000;            // 0x140000
2265
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2266
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2267
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2268
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2269
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2270
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2271
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2272
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2273
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2274
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2275
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2276
        default: polynom = 32'b0;
2277
        endcase
2278
        lfsr_fb = qi[length];
2279
        for (i=length-1; i>=1; i=i-1) begin
2280
            if (polynom[i])
2281
                lfsr_fb = lfsr_fb  ~^ qi[i];
2282
        end
2283
    end
2284
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2285
   always @ (qi)
2286
   begin
2287
        case (length)
2288
         2: polynom_rew = 32'b11;
2289
         3: polynom_rew = 32'b110;
2290
         4: polynom_rew = 32'b1100;
2291
         5: polynom_rew = 32'b10100;
2292
         6: polynom_rew = 32'b110000;
2293
         7: polynom_rew = 32'b1100000;
2294
         8: polynom_rew = 32'b10111000;
2295
         9: polynom_rew = 32'b100010000;
2296
        10: polynom_rew = 32'b1001000000;
2297
        11: polynom_rew = 32'b10100000000;
2298
        12: polynom_rew = 32'b100000101001;
2299
        13: polynom_rew = 32'b1000000001100;
2300
        14: polynom_rew = 32'b10000000010101;
2301
        15: polynom_rew = 32'b110000000000000;
2302
        16: polynom_rew = 32'b1101000000001000;
2303
        17: polynom_rew = 32'b10010000000000000;
2304
        18: polynom_rew = 32'b100000010000000000;
2305
        19: polynom_rew = 32'b1000000000000100011;
2306
        20: polynom_rew = 32'b10000010000000000000;
2307
        21: polynom_rew = 32'b101000000000000000000;
2308
        22: polynom_rew = 32'b1100000000000000000000;
2309
        23: polynom_rew = 32'b10000100000000000000000;
2310
        24: polynom_rew = 32'b111000010000000000000000;
2311
        25: polynom_rew = 32'b1001000000000000000000000;
2312
        26: polynom_rew = 32'b10000000000000000000100011;
2313
        27: polynom_rew = 32'b100000000000000000000010011;
2314
        28: polynom_rew = 32'b1100100000000000000000000000;
2315
        29: polynom_rew = 32'b10100000000000000000000000000;
2316
        30: polynom_rew = 32'b100000000000000000000000101001;
2317
        31: polynom_rew = 32'b1001000000000000000000000000000;
2318
        32: polynom_rew = 32'b10000000001000000000000000000011;
2319
        default: polynom_rew = 32'b0;
2320
        endcase
2321
        // rotate left
2322
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
2323
        lfsr_fb_rew = qi[length];
2324
        for (i=length-1; i>=1; i=i-1) begin
2325
            if (polynom_rew[i])
2326
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
2327
        end
2328
    end
2329
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
2330
   assign q_next = rew ? q_next_rew : q_next_fw;
2331
   always @ (posedge clk or posedge rst)
2332
     if (rst)
2333
       qi <= {length{1'b0}};
2334
     else
2335
     if (cke)
2336
       qi <= q_next;
2337
    always @ (posedge clk or posedge rst)
2338
    if (rst)
2339
        level1 <= 1'b0;
2340
    else
2341
    if (cke)
2342
    if (clear)
2343
        level1 <= 1'b0;
2344
    else if (q_next == level1_value)
2345
        level1 <= 1'b1;
2346
    else if (qi == level1_value & rew)
2347
        level1 <= 1'b0;
2348
endmodule
2349
//////////////////////////////////////////////////////////////////////
2350
////                                                              ////
2351
////  Versatile counter                                           ////
2352
////                                                              ////
2353
////  Description                                                 ////
2354
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2355
////  counter                                                     ////
2356
////                                                              ////
2357
////  To Do:                                                      ////
2358
////   - add LFSR with more taps                                  ////
2359
////                                                              ////
2360
////  Author(s):                                                  ////
2361
////      - Michael Unneback, unneback@opencores.org              ////
2362
////        ORSoC AB                                              ////
2363
////                                                              ////
2364
//////////////////////////////////////////////////////////////////////
2365
////                                                              ////
2366
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2367
////                                                              ////
2368
//// This source file may be used and distributed without         ////
2369
//// restriction provided that this copyright statement is not    ////
2370
//// removed from the file and that any derivative work contains  ////
2371
//// the original copyright notice and the associated disclaimer. ////
2372
////                                                              ////
2373
//// This source file is free software; you can redistribute it   ////
2374
//// and/or modify it under the terms of the GNU Lesser General   ////
2375
//// Public License as published by the Free Software Foundation; ////
2376
//// either version 2.1 of the License, or (at your option) any   ////
2377
//// later version.                                               ////
2378
////                                                              ////
2379
//// This source is distributed in the hope that it will be       ////
2380
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2381
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2382
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2383
//// details.                                                     ////
2384
////                                                              ////
2385
//// You should have received a copy of the GNU Lesser General    ////
2386
//// Public License along with this source; if not, download it   ////
2387
//// from http://www.opencores.org/lgpl.shtml                     ////
2388
////                                                              ////
2389
//////////////////////////////////////////////////////////////////////
2390 6 unneback
// GRAY counter
2391 139 unneback
module vl_cnt_gray (
2392
 q, rst, clk);
2393
   parameter length = 4;
2394
   output reg [length:1] q;
2395
   input rst;
2396
   input clk;
2397
   parameter clear_value = 0;
2398
   parameter set_value = 1;
2399
   parameter wrap_value = 8;
2400
   parameter level1_value = 15;
2401
   reg  [length:1] qi;
2402
   wire [length:1] q_next;
2403
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2404
   always @ (posedge clk or posedge rst)
2405
     if (rst)
2406
       qi <= {length{1'b0}};
2407
     else
2408
       qi <= q_next;
2409
   always @ (posedge clk or posedge rst)
2410
     if (rst)
2411
       q <= {length{1'b0}};
2412
     else
2413
         q <= (q_next>>1) ^ q_next;
2414
endmodule
2415
//////////////////////////////////////////////////////////////////////
2416
////                                                              ////
2417
////  Versatile counter                                           ////
2418
////                                                              ////
2419
////  Description                                                 ////
2420
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2421
////  counter                                                     ////
2422
////                                                              ////
2423
////  To Do:                                                      ////
2424
////   - add LFSR with more taps                                  ////
2425
////                                                              ////
2426
////  Author(s):                                                  ////
2427
////      - Michael Unneback, unneback@opencores.org              ////
2428
////        ORSoC AB                                              ////
2429
////                                                              ////
2430
//////////////////////////////////////////////////////////////////////
2431
////                                                              ////
2432
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2433
////                                                              ////
2434
//// This source file may be used and distributed without         ////
2435
//// restriction provided that this copyright statement is not    ////
2436
//// removed from the file and that any derivative work contains  ////
2437
//// the original copyright notice and the associated disclaimer. ////
2438
////                                                              ////
2439
//// This source file is free software; you can redistribute it   ////
2440
//// and/or modify it under the terms of the GNU Lesser General   ////
2441
//// Public License as published by the Free Software Foundation; ////
2442
//// either version 2.1 of the License, or (at your option) any   ////
2443
//// later version.                                               ////
2444
////                                                              ////
2445
//// This source is distributed in the hope that it will be       ////
2446
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2447
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2448
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2449
//// details.                                                     ////
2450
////                                                              ////
2451
//// You should have received a copy of the GNU Lesser General    ////
2452
//// Public License along with this source; if not, download it   ////
2453
//// from http://www.opencores.org/lgpl.shtml                     ////
2454
////                                                              ////
2455
//////////////////////////////////////////////////////////////////////
2456
// GRAY counter
2457
module vl_cnt_gray_ce (
2458
 cke, q, rst, clk);
2459
   parameter length = 4;
2460
   input cke;
2461
   output reg [length:1] q;
2462
   input rst;
2463
   input clk;
2464
   parameter clear_value = 0;
2465
   parameter set_value = 1;
2466
   parameter wrap_value = 8;
2467
   parameter level1_value = 15;
2468
   reg  [length:1] qi;
2469
   wire [length:1] q_next;
2470
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2471
   always @ (posedge clk or posedge rst)
2472
     if (rst)
2473
       qi <= {length{1'b0}};
2474
     else
2475
     if (cke)
2476
       qi <= q_next;
2477
   always @ (posedge clk or posedge rst)
2478
     if (rst)
2479
       q <= {length{1'b0}};
2480
     else
2481
       if (cke)
2482
         q <= (q_next>>1) ^ q_next;
2483
endmodule
2484
//////////////////////////////////////////////////////////////////////
2485
////                                                              ////
2486
////  Versatile counter                                           ////
2487
////                                                              ////
2488
////  Description                                                 ////
2489
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2490
////  counter                                                     ////
2491
////                                                              ////
2492
////  To Do:                                                      ////
2493
////   - add LFSR with more taps                                  ////
2494
////                                                              ////
2495
////  Author(s):                                                  ////
2496
////      - Michael Unneback, unneback@opencores.org              ////
2497
////        ORSoC AB                                              ////
2498
////                                                              ////
2499
//////////////////////////////////////////////////////////////////////
2500
////                                                              ////
2501
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2502
////                                                              ////
2503
//// This source file may be used and distributed without         ////
2504
//// restriction provided that this copyright statement is not    ////
2505
//// removed from the file and that any derivative work contains  ////
2506
//// the original copyright notice and the associated disclaimer. ////
2507
////                                                              ////
2508
//// This source file is free software; you can redistribute it   ////
2509
//// and/or modify it under the terms of the GNU Lesser General   ////
2510
//// Public License as published by the Free Software Foundation; ////
2511
//// either version 2.1 of the License, or (at your option) any   ////
2512
//// later version.                                               ////
2513
////                                                              ////
2514
//// This source is distributed in the hope that it will be       ////
2515
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2516
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2517
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2518
//// details.                                                     ////
2519
////                                                              ////
2520
//// You should have received a copy of the GNU Lesser General    ////
2521
//// Public License along with this source; if not, download it   ////
2522
//// from http://www.opencores.org/lgpl.shtml                     ////
2523
////                                                              ////
2524
//////////////////////////////////////////////////////////////////////
2525
// GRAY counter
2526 40 unneback
module vl_cnt_gray_ce_bin (
2527
 cke, q, q_bin, rst, clk);
2528 6 unneback
   parameter length = 4;
2529
   input cke;
2530
   output reg [length:1] q;
2531
   output [length:1] q_bin;
2532
   input rst;
2533
   input clk;
2534
   parameter clear_value = 0;
2535
   parameter set_value = 1;
2536
   parameter wrap_value = 8;
2537
   parameter level1_value = 15;
2538
   reg  [length:1] qi;
2539
   wire [length:1] q_next;
2540
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2541
   always @ (posedge clk or posedge rst)
2542
     if (rst)
2543
       qi <= {length{1'b0}};
2544
     else
2545
     if (cke)
2546
       qi <= q_next;
2547
   always @ (posedge clk or posedge rst)
2548
     if (rst)
2549
       q <= {length{1'b0}};
2550
     else
2551
       if (cke)
2552
         q <= (q_next>>1) ^ q_next;
2553
   assign q_bin = qi;
2554
endmodule
2555
//////////////////////////////////////////////////////////////////////
2556
////                                                              ////
2557
////  Versatile library, counters                                 ////
2558
////                                                              ////
2559
////  Description                                                 ////
2560
////  counters                                                    ////
2561
////                                                              ////
2562
////                                                              ////
2563
////  To Do:                                                      ////
2564
////   - add more counters                                        ////
2565
////                                                              ////
2566
////  Author(s):                                                  ////
2567
////      - Michael Unneback, unneback@opencores.org              ////
2568
////        ORSoC AB                                              ////
2569
////                                                              ////
2570
//////////////////////////////////////////////////////////////////////
2571
////                                                              ////
2572
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2573
////                                                              ////
2574
//// This source file may be used and distributed without         ////
2575
//// restriction provided that this copyright statement is not    ////
2576
//// removed from the file and that any derivative work contains  ////
2577
//// the original copyright notice and the associated disclaimer. ////
2578
////                                                              ////
2579
//// This source file is free software; you can redistribute it   ////
2580
//// and/or modify it under the terms of the GNU Lesser General   ////
2581
//// Public License as published by the Free Software Foundation; ////
2582
//// either version 2.1 of the License, or (at your option) any   ////
2583
//// later version.                                               ////
2584
////                                                              ////
2585
//// This source is distributed in the hope that it will be       ////
2586
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2587
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2588
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2589
//// details.                                                     ////
2590
////                                                              ////
2591
//// You should have received a copy of the GNU Lesser General    ////
2592
//// Public License along with this source; if not, download it   ////
2593
//// from http://www.opencores.org/lgpl.shtml                     ////
2594
////                                                              ////
2595
//////////////////////////////////////////////////////////////////////
2596 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
2597 6 unneback
   parameter length = 4;
2598
   output reg [0:length-1] q;
2599
   input rst;
2600
   input clk;
2601
    always @ (posedge clk or posedge rst)
2602
    if (rst)
2603
        q <= {1'b1,{length-1{1'b0}}};
2604
    else
2605
        q <= {q[length-1],q[0:length-2]};
2606
endmodule
2607