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1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  Versatile library, clock and reset                          ////
4
////                                                              ////
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////  Description                                                 ////
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////  Logic related to clock and reset                            ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
10
////   - add more different registers                             ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
17
////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
// Global buffer
43
// usage:
44
// use to enable global buffers for high fan out signals such as clock and reset
45
altera
46
 // ALTERA
47
 //ACTEL
48
// sync reset
49
// input active lo async reset, normally from external reset generetaor and/or switch
50
// output active high global reset sync with two DFFs 
51
`timescale 1 ns/100 ps
52
module vl_sync_rst ( rst_n_i, rst_o, clk);
53
input rst_n_i, clk;
54
output rst_o;
55
reg [0:1] tmp;
56
always @ (posedge clk or negedge rst_n_i)
57
if (!rst_n_i)
58
        tmp <= 2'b00;
59
else
60
        tmp <= {1'b1,tmp[0]};
61
vl_gbuf buf_i0( .i(tmp[1]), .o(rst_o));
62
endmodule
63
// vl_pll
64
 //altera
65
 //actel
66
//////////////////////////////////////////////////////////////////////
67
////                                                              ////
68
////  Versatile library, registers                                ////
69
////                                                              ////
70
////  Description                                                 ////
71
////  Different type of registers                                 ////
72
////                                                              ////
73
////                                                              ////
74
////  To Do:                                                      ////
75
////   - add more different registers                             ////
76
////                                                              ////
77
////  Author(s):                                                  ////
78
////      - Michael Unneback, unneback@opencores.org              ////
79
////        ORSoC AB                                              ////
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////                                                              ////
81
//////////////////////////////////////////////////////////////////////
82
////                                                              ////
83
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
84
////                                                              ////
85
//// This source file may be used and distributed without         ////
86
//// restriction provided that this copyright statement is not    ////
87
//// removed from the file and that any derivative work contains  ////
88
//// the original copyright notice and the associated disclaimer. ////
89
////                                                              ////
90
//// This source file is free software; you can redistribute it   ////
91
//// and/or modify it under the terms of the GNU Lesser General   ////
92
//// Public License as published by the Free Software Foundation; ////
93
//// either version 2.1 of the License, or (at your option) any   ////
94
//// later version.                                               ////
95
////                                                              ////
96
//// This source is distributed in the hope that it will be       ////
97
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
98
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
99
//// PURPOSE.  See the GNU Lesser General Public License for more ////
100
//// details.                                                     ////
101
////                                                              ////
102
//// You should have received a copy of the GNU Lesser General    ////
103
//// Public License along with this source; if not, download it   ////
104
//// from http://www.opencores.org/lgpl.shtml                     ////
105
////                                                              ////
106
//////////////////////////////////////////////////////////////////////
107
module dff ( d, q, clk, rst);
108
        parameter width = 1;
109
        parameter reset_value = 0;
110
        input [width-1:0] d;
111
        input clk, rst;
112
        output reg [width-1:0] q;
113
        always @ (posedge clk or posedge rst)
114
        if (rst)
115
                q <= reset_value;
116
        else
117
                q <= d;
118
endmodule
119
module dff_array ( d, q, clk, rst);
120
        parameter width = 1;
121
        parameter depth = 2;
122
        parameter reset_value = 1'b0;
123
        input [width-1:0] d;
124
        input clk, rst;
125
        output [width-1:0] q;
126
        reg  [0:depth-1] q_tmp [width-1:0];
127
        integer i;
128
        always @ (posedge clk or posedge rst)
129
        if (rst) begin
130
            for (i=0;i<depth;i=i+1)
131
                q_tmp[i] <= {width{reset_value}};
132
        end else begin
133
            q_tmp[0] <= d;
134
            for (i=1;i<depth;i=i+1)
135
                q_tmp[i] <= q_tmp[i-1];
136
        end
137
    assign q = q_tmp[depth-1];
138
endmodule
139
module dff_ce ( d, ce, q, clk, rst);
140
        parameter width = 1;
141
        parameter reset_value = 0;
142
        input [width-1:0] d;
143
        input ce, clk, rst;
144
        output reg [width-1:0] q;
145
        always @ (posedge clk or posedge rst)
146
        if (rst)
147
                q <= reset_value;
148
        else
149
                if (ce)
150
                        q <= d;
151
endmodule
152 8 unneback
module dff_ce_clear ( d, ce, clear, q, clk, rst);
153
        parameter width = 1;
154
        parameter reset_value = 0;
155
        input [width-1:0] d;
156 10 unneback
        input ce, clear, clk, rst;
157 8 unneback
        output reg [width-1:0] q;
158
        always @ (posedge clk or posedge rst)
159
        if (rst)
160
            q <= reset_value;
161
        else
162
            if (ce)
163
                if (clear)
164
                    q <= {width{1'b0}};
165
                else
166
                    q <= d;
167
endmodule
168 6 unneback
// megafunction wizard: %LPM_FF%
169
// GENERATION: STANDARD
170
// VERSION: WM1.0
171
// MODULE: lpm_ff 
172
// ============================================================
173
// File Name: dff_sr.v
174
// Megafunction Name(s):
175
//                      lpm_ff
176
//
177
// Simulation Library Files(s):
178
//                      lpm
179
// ============================================================
180
// ************************************************************
181
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
182
//
183
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
184
// ************************************************************
185
//Copyright (C) 1991-2010 Altera Corporation
186
//Your use of Altera Corporation's design tools, logic functions 
187
//and other software and tools, and its AMPP partner logic 
188
//functions, and any output files from any of the foregoing 
189
//(including device programming or simulation files), and any 
190
//associated documentation or information are expressly subject 
191
//to the terms and conditions of the Altera Program License 
192
//Subscription Agreement, Altera MegaCore Function License 
193
//Agreement, or other applicable license agreement, including, 
194
//without limitation, that your use is for the sole purpose of 
195
//programming logic devices manufactured by Altera and sold by 
196
//Altera or its authorized distributors.  Please refer to the 
197
//applicable agreement for further details.
198
// synopsys translate_off
199
`timescale 1 ps / 1 ps
200
// synopsys translate_on
201
module dff_sr (
202
        aclr,
203
        aset,
204
        clock,
205
        data,
206
        q);
207
        input     aclr;
208
        input     aset;
209
        input     clock;
210
        input     data;
211
        output    q;
212
        wire [0:0] sub_wire0;
213
        wire [0:0] sub_wire1 = sub_wire0[0:0];
214
        wire  q = sub_wire1;
215
        wire  sub_wire2 = data;
216
        wire  sub_wire3 = sub_wire2;
217
        lpm_ff  lpm_ff_component (
218
                                .aclr (aclr),
219
                                .clock (clock),
220
                                .data (sub_wire3),
221
                                .aset (aset),
222
                                .q (sub_wire0)
223
                                // synopsys translate_off
224
                                ,
225
                                .aload (),
226
                                .enable (),
227
                                .sclr (),
228
                                .sload (),
229
                                .sset ()
230
                                // synopsys translate_on
231
                                );
232
        defparam
233
                lpm_ff_component.lpm_fftype = "DFF",
234
                lpm_ff_component.lpm_type = "LPM_FF",
235
                lpm_ff_component.lpm_width = 1;
236
endmodule
237
// ============================================================
238
// CNX file retrieval info
239
// ============================================================
240
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
241
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
242
// Retrieval info: PRIVATE: ASET NUMERIC "1"
243
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
244
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
245
// Retrieval info: PRIVATE: DFF NUMERIC "1"
246
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
247
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
248
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
249
// Retrieval info: PRIVATE: SSET NUMERIC "0"
250
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
251
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
252
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
253
// Retrieval info: PRIVATE: nBit NUMERIC "1"
254
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
255
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
256
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
257
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
258
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
259
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
260
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
261
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
262
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
263
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
264
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
265
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
266
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
267
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
268
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
269
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
270
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
271
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
272
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
273
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
274
// Retrieval info: LIB_FILE: lpm
275
// LATCH
276
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
277
module latch ( d, le, q, clk);
278
input d, le;
279
output q;
280
input clk;
281
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
282
endmodule
283 15 unneback
module delay ( d, q, clk, rst);
284
parameter depth = 10;
285
input d;
286
output q;
287
input clk, rst;
288
reg [1:depth] dffs;
289
always @ (posedge clk or posedge rst)
290
if (rst)
291
    dffs <= {depth{1'b0}};
292
else
293
    dffs <= {d,dffs[1:depth-1]};
294
assign q = dffs[depth];
295
endmodule
296 6 unneback
//////////////////////////////////////////////////////////////////////
297
////                                                              ////
298
////  Versatile counter                                           ////
299
////                                                              ////
300
////  Description                                                 ////
301
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
302
////  counter                                                     ////
303
////                                                              ////
304
////  To Do:                                                      ////
305
////   - add LFSR with more taps                                  ////
306
////                                                              ////
307
////  Author(s):                                                  ////
308
////      - Michael Unneback, unneback@opencores.org              ////
309
////        ORSoC AB                                              ////
310
////                                                              ////
311
//////////////////////////////////////////////////////////////////////
312
////                                                              ////
313
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
314
////                                                              ////
315
//// This source file may be used and distributed without         ////
316
//// restriction provided that this copyright statement is not    ////
317
//// removed from the file and that any derivative work contains  ////
318
//// the original copyright notice and the associated disclaimer. ////
319
////                                                              ////
320
//// This source file is free software; you can redistribute it   ////
321
//// and/or modify it under the terms of the GNU Lesser General   ////
322
//// Public License as published by the Free Software Foundation; ////
323
//// either version 2.1 of the License, or (at your option) any   ////
324
//// later version.                                               ////
325
////                                                              ////
326
//// This source is distributed in the hope that it will be       ////
327
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
328
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
329
//// PURPOSE.  See the GNU Lesser General Public License for more ////
330
//// details.                                                     ////
331
////                                                              ////
332
//// You should have received a copy of the GNU Lesser General    ////
333
//// Public License along with this source; if not, download it   ////
334
//// from http://www.opencores.org/lgpl.shtml                     ////
335
////                                                              ////
336
//////////////////////////////////////////////////////////////////////
337
// binary counter
338
module cnt_bin_ce ( cke, q, rst, clk);
339
   parameter length = 4;
340
   input cke;
341
   output [length:1] q;
342
   input rst;
343
   input clk;
344
   parameter clear_value = 0;
345
   parameter set_value = 1;
346
   parameter wrap_value = 0;
347
   parameter level1_value = 15;
348
   reg  [length:1] qi;
349
   wire [length:1] q_next;
350
   assign q_next = qi + {{length-1{1'b0}},1'b1};
351
   always @ (posedge clk or posedge rst)
352
     if (rst)
353
       qi <= {length{1'b0}};
354
     else
355
     if (cke)
356
       qi <= q_next;
357
   assign q = qi;
358
endmodule
359
//////////////////////////////////////////////////////////////////////
360
////                                                              ////
361
////  Versatile counter                                           ////
362
////                                                              ////
363
////  Description                                                 ////
364
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
365
////  counter                                                     ////
366
////                                                              ////
367
////  To Do:                                                      ////
368
////   - add LFSR with more taps                                  ////
369
////                                                              ////
370
////  Author(s):                                                  ////
371
////      - Michael Unneback, unneback@opencores.org              ////
372
////        ORSoC AB                                              ////
373
////                                                              ////
374
//////////////////////////////////////////////////////////////////////
375
////                                                              ////
376
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
377
////                                                              ////
378
//// This source file may be used and distributed without         ////
379
//// restriction provided that this copyright statement is not    ////
380
//// removed from the file and that any derivative work contains  ////
381
//// the original copyright notice and the associated disclaimer. ////
382
////                                                              ////
383
//// This source file is free software; you can redistribute it   ////
384
//// and/or modify it under the terms of the GNU Lesser General   ////
385
//// Public License as published by the Free Software Foundation; ////
386
//// either version 2.1 of the License, or (at your option) any   ////
387
//// later version.                                               ////
388
////                                                              ////
389
//// This source is distributed in the hope that it will be       ////
390
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
391
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
392
//// PURPOSE.  See the GNU Lesser General Public License for more ////
393
//// details.                                                     ////
394
////                                                              ////
395
//// You should have received a copy of the GNU Lesser General    ////
396
//// Public License along with this source; if not, download it   ////
397
//// from http://www.opencores.org/lgpl.shtml                     ////
398
////                                                              ////
399
//////////////////////////////////////////////////////////////////////
400
// binary counter
401
module cnt_bin_ce_clear ( clear, cke, q, rst, clk);
402
   parameter length = 4;
403
   input clear;
404
   input cke;
405
   output [length:1] q;
406
   input rst;
407
   input clk;
408
   parameter clear_value = 0;
409
   parameter set_value = 1;
410
   parameter wrap_value = 0;
411
   parameter level1_value = 15;
412
   reg  [length:1] qi;
413
   wire [length:1] q_next;
414
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
415
   always @ (posedge clk or posedge rst)
416
     if (rst)
417
       qi <= {length{1'b0}};
418
     else
419
     if (cke)
420
       qi <= q_next;
421
   assign q = qi;
422
endmodule
423
//////////////////////////////////////////////////////////////////////
424
////                                                              ////
425
////  Versatile counter                                           ////
426
////                                                              ////
427
////  Description                                                 ////
428
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
429
////  counter                                                     ////
430
////                                                              ////
431
////  To Do:                                                      ////
432
////   - add LFSR with more taps                                  ////
433
////                                                              ////
434
////  Author(s):                                                  ////
435
////      - Michael Unneback, unneback@opencores.org              ////
436
////        ORSoC AB                                              ////
437
////                                                              ////
438
//////////////////////////////////////////////////////////////////////
439
////                                                              ////
440
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
441
////                                                              ////
442
//// This source file may be used and distributed without         ////
443
//// restriction provided that this copyright statement is not    ////
444
//// removed from the file and that any derivative work contains  ////
445
//// the original copyright notice and the associated disclaimer. ////
446
////                                                              ////
447
//// This source file is free software; you can redistribute it   ////
448
//// and/or modify it under the terms of the GNU Lesser General   ////
449
//// Public License as published by the Free Software Foundation; ////
450
//// either version 2.1 of the License, or (at your option) any   ////
451
//// later version.                                               ////
452
////                                                              ////
453
//// This source is distributed in the hope that it will be       ////
454
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
455
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
456
//// PURPOSE.  See the GNU Lesser General Public License for more ////
457
//// details.                                                     ////
458
////                                                              ////
459
//// You should have received a copy of the GNU Lesser General    ////
460
//// Public License along with this source; if not, download it   ////
461
//// from http://www.opencores.org/lgpl.shtml                     ////
462
////                                                              ////
463
//////////////////////////////////////////////////////////////////////
464
// binary counter
465
module cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
466
   parameter length = 4;
467
   input clear;
468
   input set;
469
   input cke;
470
   input rew;
471
   output [length:1] q;
472
   input rst;
473
   input clk;
474
   parameter clear_value = 0;
475
   parameter set_value = 1;
476
   parameter wrap_value = 0;
477
   parameter level1_value = 15;
478
   reg  [length:1] qi;
479
   wire  [length:1] q_next, q_next_fw, q_next_rew;
480
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
481
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
482
   assign q_next = rew ? q_next_rew : q_next_fw;
483
   always @ (posedge clk or posedge rst)
484
     if (rst)
485
       qi <= {length{1'b0}};
486
     else
487
     if (cke)
488
       qi <= q_next;
489
   assign q = qi;
490
endmodule
491
//////////////////////////////////////////////////////////////////////
492
////                                                              ////
493
////  Versatile counter                                           ////
494
////                                                              ////
495
////  Description                                                 ////
496
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
497
////  counter                                                     ////
498
////                                                              ////
499
////  To Do:                                                      ////
500
////   - add LFSR with more taps                                  ////
501
////                                                              ////
502
////  Author(s):                                                  ////
503
////      - Michael Unneback, unneback@opencores.org              ////
504
////        ORSoC AB                                              ////
505
////                                                              ////
506
//////////////////////////////////////////////////////////////////////
507
////                                                              ////
508
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
509
////                                                              ////
510
//// This source file may be used and distributed without         ////
511
//// restriction provided that this copyright statement is not    ////
512
//// removed from the file and that any derivative work contains  ////
513
//// the original copyright notice and the associated disclaimer. ////
514
////                                                              ////
515
//// This source file is free software; you can redistribute it   ////
516
//// and/or modify it under the terms of the GNU Lesser General   ////
517
//// Public License as published by the Free Software Foundation; ////
518
//// either version 2.1 of the License, or (at your option) any   ////
519
//// later version.                                               ////
520
////                                                              ////
521
//// This source is distributed in the hope that it will be       ////
522
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
523
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
524
//// PURPOSE.  See the GNU Lesser General Public License for more ////
525
//// details.                                                     ////
526
////                                                              ////
527
//// You should have received a copy of the GNU Lesser General    ////
528
//// Public License along with this source; if not, download it   ////
529
//// from http://www.opencores.org/lgpl.shtml                     ////
530
////                                                              ////
531
//////////////////////////////////////////////////////////////////////
532
// binary counter
533
module cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
534
   parameter length = 4;
535
   input cke;
536
   input rew;
537
   output reg level1;
538
   input rst;
539
   input clk;
540
   parameter clear_value = 0;
541
   parameter set_value = 1;
542
   parameter wrap_value = 1;
543
   parameter level1_value = 15;
544
   reg  [length:1] qi;
545
   wire  [length:1] q_next, q_next_fw, q_next_rew;
546
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
547
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
548
   assign q_next = rew ? q_next_rew : q_next_fw;
549
   always @ (posedge clk or posedge rst)
550
     if (rst)
551
       qi <= {length{1'b0}};
552
     else
553
     if (cke)
554
       qi <= q_next;
555
    always @ (posedge clk or posedge rst)
556
    if (rst)
557
        level1 <= 1'b0;
558
    else
559
    if (cke)
560
    if (q_next == level1_value)
561
        level1 <= 1'b1;
562
    else if (qi == level1_value & rew)
563
        level1 <= 1'b0;
564
endmodule
565
//////////////////////////////////////////////////////////////////////
566
////                                                              ////
567
////  Versatile counter                                           ////
568
////                                                              ////
569
////  Description                                                 ////
570
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
571
////  counter                                                     ////
572
////                                                              ////
573
////  To Do:                                                      ////
574
////   - add LFSR with more taps                                  ////
575
////                                                              ////
576
////  Author(s):                                                  ////
577
////      - Michael Unneback, unneback@opencores.org              ////
578
////        ORSoC AB                                              ////
579
////                                                              ////
580
//////////////////////////////////////////////////////////////////////
581
////                                                              ////
582
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
583
////                                                              ////
584
//// This source file may be used and distributed without         ////
585
//// restriction provided that this copyright statement is not    ////
586
//// removed from the file and that any derivative work contains  ////
587
//// the original copyright notice and the associated disclaimer. ////
588
////                                                              ////
589
//// This source file is free software; you can redistribute it   ////
590
//// and/or modify it under the terms of the GNU Lesser General   ////
591
//// Public License as published by the Free Software Foundation; ////
592
//// either version 2.1 of the License, or (at your option) any   ////
593
//// later version.                                               ////
594
////                                                              ////
595
//// This source is distributed in the hope that it will be       ////
596
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
597
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
598
//// PURPOSE.  See the GNU Lesser General Public License for more ////
599
//// details.                                                     ////
600
////                                                              ////
601
//// You should have received a copy of the GNU Lesser General    ////
602
//// Public License along with this source; if not, download it   ////
603
//// from http://www.opencores.org/lgpl.shtml                     ////
604
////                                                              ////
605
//////////////////////////////////////////////////////////////////////
606
// LFSR counter
607
module cnt_lfsr_zq ( zq, rst, clk);
608
   parameter length = 4;
609
   output reg zq;
610
   input rst;
611
   input clk;
612
   parameter clear_value = 0;
613
   parameter set_value = 1;
614
   parameter wrap_value = 8;
615
   parameter level1_value = 15;
616
   reg  [length:1] qi;
617
   reg lfsr_fb;
618
   wire [length:1] q_next;
619
   reg [32:1] polynom;
620
   integer i;
621
   always @ (qi)
622
   begin
623
        case (length)
624
         2: polynom = 32'b11;                               // 0x3
625
         3: polynom = 32'b110;                              // 0x6
626
         4: polynom = 32'b1100;                             // 0xC
627
         5: polynom = 32'b10100;                            // 0x14
628
         6: polynom = 32'b110000;                           // 0x30
629
         7: polynom = 32'b1100000;                          // 0x60
630
         8: polynom = 32'b10111000;                         // 0xb8
631
         9: polynom = 32'b100010000;                        // 0x110
632
        10: polynom = 32'b1001000000;                       // 0x240
633
        11: polynom = 32'b10100000000;                      // 0x500
634
        12: polynom = 32'b100000101001;                     // 0x829
635
        13: polynom = 32'b1000000001100;                    // 0x100C
636
        14: polynom = 32'b10000000010101;                   // 0x2015
637
        15: polynom = 32'b110000000000000;                  // 0x6000
638
        16: polynom = 32'b1101000000001000;                 // 0xD008
639
        17: polynom = 32'b10010000000000000;                // 0x12000
640
        18: polynom = 32'b100000010000000000;               // 0x20400
641
        19: polynom = 32'b1000000000000100011;              // 0x40023
642
        20: polynom = 32'b10000010000000000000;             // 0x82000
643
        21: polynom = 32'b101000000000000000000;            // 0x140000
644
        22: polynom = 32'b1100000000000000000000;           // 0x300000
645
        23: polynom = 32'b10000100000000000000000;          // 0x420000
646
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
647
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
648
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
649
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
650
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
651
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
652
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
653
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
654
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
655
        default: polynom = 32'b0;
656
        endcase
657
        lfsr_fb = qi[length];
658
        for (i=length-1; i>=1; i=i-1) begin
659
            if (polynom[i])
660
                lfsr_fb = lfsr_fb  ~^ qi[i];
661
        end
662
    end
663
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
664
   always @ (posedge clk or posedge rst)
665
     if (rst)
666
       qi <= {length{1'b0}};
667
     else
668
       qi <= q_next;
669
   always @ (posedge clk or posedge rst)
670
     if (rst)
671
       zq <= 1'b1;
672
     else
673
       zq <= q_next == {length{1'b0}};
674
endmodule
675
//////////////////////////////////////////////////////////////////////
676
////                                                              ////
677
////  Versatile counter                                           ////
678
////                                                              ////
679
////  Description                                                 ////
680
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
681
////  counter                                                     ////
682
////                                                              ////
683
////  To Do:                                                      ////
684
////   - add LFSR with more taps                                  ////
685
////                                                              ////
686
////  Author(s):                                                  ////
687
////      - Michael Unneback, unneback@opencores.org              ////
688
////        ORSoC AB                                              ////
689
////                                                              ////
690
//////////////////////////////////////////////////////////////////////
691
////                                                              ////
692
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
693
////                                                              ////
694
//// This source file may be used and distributed without         ////
695
//// restriction provided that this copyright statement is not    ////
696
//// removed from the file and that any derivative work contains  ////
697
//// the original copyright notice and the associated disclaimer. ////
698
////                                                              ////
699
//// This source file is free software; you can redistribute it   ////
700
//// and/or modify it under the terms of the GNU Lesser General   ////
701
//// Public License as published by the Free Software Foundation; ////
702
//// either version 2.1 of the License, or (at your option) any   ////
703
//// later version.                                               ////
704
////                                                              ////
705
//// This source is distributed in the hope that it will be       ////
706
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
707
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
708
//// PURPOSE.  See the GNU Lesser General Public License for more ////
709
//// details.                                                     ////
710
////                                                              ////
711
//// You should have received a copy of the GNU Lesser General    ////
712
//// Public License along with this source; if not, download it   ////
713
//// from http://www.opencores.org/lgpl.shtml                     ////
714
////                                                              ////
715
//////////////////////////////////////////////////////////////////////
716
// LFSR counter
717
module cnt_lfsr_ce_zq ( cke, zq, rst, clk);
718
   parameter length = 4;
719
   input cke;
720
   output reg zq;
721
   input rst;
722
   input clk;
723
   parameter clear_value = 0;
724
   parameter set_value = 1;
725
   parameter wrap_value = 8;
726
   parameter level1_value = 15;
727
   reg  [length:1] qi;
728
   reg lfsr_fb;
729
   wire [length:1] q_next;
730
   reg [32:1] polynom;
731
   integer i;
732
   always @ (qi)
733
   begin
734
        case (length)
735
         2: polynom = 32'b11;                               // 0x3
736
         3: polynom = 32'b110;                              // 0x6
737
         4: polynom = 32'b1100;                             // 0xC
738
         5: polynom = 32'b10100;                            // 0x14
739
         6: polynom = 32'b110000;                           // 0x30
740
         7: polynom = 32'b1100000;                          // 0x60
741
         8: polynom = 32'b10111000;                         // 0xb8
742
         9: polynom = 32'b100010000;                        // 0x110
743
        10: polynom = 32'b1001000000;                       // 0x240
744
        11: polynom = 32'b10100000000;                      // 0x500
745
        12: polynom = 32'b100000101001;                     // 0x829
746
        13: polynom = 32'b1000000001100;                    // 0x100C
747
        14: polynom = 32'b10000000010101;                   // 0x2015
748
        15: polynom = 32'b110000000000000;                  // 0x6000
749
        16: polynom = 32'b1101000000001000;                 // 0xD008
750
        17: polynom = 32'b10010000000000000;                // 0x12000
751
        18: polynom = 32'b100000010000000000;               // 0x20400
752
        19: polynom = 32'b1000000000000100011;              // 0x40023
753
        20: polynom = 32'b10000010000000000000;             // 0x82000
754
        21: polynom = 32'b101000000000000000000;            // 0x140000
755
        22: polynom = 32'b1100000000000000000000;           // 0x300000
756
        23: polynom = 32'b10000100000000000000000;          // 0x420000
757
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
758
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
759
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
760
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
761
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
762
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
763
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
764
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
765
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
766
        default: polynom = 32'b0;
767
        endcase
768
        lfsr_fb = qi[length];
769
        for (i=length-1; i>=1; i=i-1) begin
770
            if (polynom[i])
771
                lfsr_fb = lfsr_fb  ~^ qi[i];
772
        end
773
    end
774
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
775
   always @ (posedge clk or posedge rst)
776
     if (rst)
777
       qi <= {length{1'b0}};
778
     else
779
     if (cke)
780
       qi <= q_next;
781
   always @ (posedge clk or posedge rst)
782
     if (rst)
783
       zq <= 1'b1;
784
     else
785
     if (cke)
786
       zq <= q_next == {length{1'b0}};
787
endmodule
788
//////////////////////////////////////////////////////////////////////
789
////                                                              ////
790
////  Versatile counter                                           ////
791
////                                                              ////
792
////  Description                                                 ////
793
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
794
////  counter                                                     ////
795
////                                                              ////
796
////  To Do:                                                      ////
797
////   - add LFSR with more taps                                  ////
798
////                                                              ////
799
////  Author(s):                                                  ////
800
////      - Michael Unneback, unneback@opencores.org              ////
801
////        ORSoC AB                                              ////
802
////                                                              ////
803
//////////////////////////////////////////////////////////////////////
804
////                                                              ////
805
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
806
////                                                              ////
807
//// This source file may be used and distributed without         ////
808
//// restriction provided that this copyright statement is not    ////
809
//// removed from the file and that any derivative work contains  ////
810
//// the original copyright notice and the associated disclaimer. ////
811
////                                                              ////
812
//// This source file is free software; you can redistribute it   ////
813
//// and/or modify it under the terms of the GNU Lesser General   ////
814
//// Public License as published by the Free Software Foundation; ////
815
//// either version 2.1 of the License, or (at your option) any   ////
816
//// later version.                                               ////
817
////                                                              ////
818
//// This source is distributed in the hope that it will be       ////
819
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
820
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
821
//// PURPOSE.  See the GNU Lesser General Public License for more ////
822
//// details.                                                     ////
823
////                                                              ////
824
//// You should have received a copy of the GNU Lesser General    ////
825
//// Public License along with this source; if not, download it   ////
826
//// from http://www.opencores.org/lgpl.shtml                     ////
827
////                                                              ////
828
//////////////////////////////////////////////////////////////////////
829
// LFSR counter
830
module cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
831
   parameter length = 4;
832
   input cke;
833
   input rew;
834
   output reg level1;
835
   input rst;
836
   input clk;
837
   parameter clear_value = 0;
838
   parameter set_value = 1;
839
   parameter wrap_value = 8;
840
   parameter level1_value = 15;
841
   reg  [length:1] qi;
842
   reg lfsr_fb, lfsr_fb_rew;
843
   wire  [length:1] q_next, q_next_fw, q_next_rew;
844
   reg [32:1] polynom_rew;
845
   integer j;
846
   reg [32:1] polynom;
847
   integer i;
848
   always @ (qi)
849
   begin
850
        case (length)
851
         2: polynom = 32'b11;                               // 0x3
852
         3: polynom = 32'b110;                              // 0x6
853
         4: polynom = 32'b1100;                             // 0xC
854
         5: polynom = 32'b10100;                            // 0x14
855
         6: polynom = 32'b110000;                           // 0x30
856
         7: polynom = 32'b1100000;                          // 0x60
857
         8: polynom = 32'b10111000;                         // 0xb8
858
         9: polynom = 32'b100010000;                        // 0x110
859
        10: polynom = 32'b1001000000;                       // 0x240
860
        11: polynom = 32'b10100000000;                      // 0x500
861
        12: polynom = 32'b100000101001;                     // 0x829
862
        13: polynom = 32'b1000000001100;                    // 0x100C
863
        14: polynom = 32'b10000000010101;                   // 0x2015
864
        15: polynom = 32'b110000000000000;                  // 0x6000
865
        16: polynom = 32'b1101000000001000;                 // 0xD008
866
        17: polynom = 32'b10010000000000000;                // 0x12000
867
        18: polynom = 32'b100000010000000000;               // 0x20400
868
        19: polynom = 32'b1000000000000100011;              // 0x40023
869
        20: polynom = 32'b10000010000000000000;             // 0x82000
870
        21: polynom = 32'b101000000000000000000;            // 0x140000
871
        22: polynom = 32'b1100000000000000000000;           // 0x300000
872
        23: polynom = 32'b10000100000000000000000;          // 0x420000
873
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
874
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
875
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
876
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
877
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
878
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
879
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
880
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
881
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
882
        default: polynom = 32'b0;
883
        endcase
884
        lfsr_fb = qi[length];
885
        for (i=length-1; i>=1; i=i-1) begin
886
            if (polynom[i])
887
                lfsr_fb = lfsr_fb  ~^ qi[i];
888
        end
889
    end
890
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
891
   always @ (qi)
892
   begin
893
        case (length)
894
         2: polynom_rew = 32'b11;
895
         3: polynom_rew = 32'b110;
896
         4: polynom_rew = 32'b1100;
897
         5: polynom_rew = 32'b10100;
898
         6: polynom_rew = 32'b110000;
899
         7: polynom_rew = 32'b1100000;
900
         8: polynom_rew = 32'b10111000;
901
         9: polynom_rew = 32'b100010000;
902
        10: polynom_rew = 32'b1001000000;
903
        11: polynom_rew = 32'b10100000000;
904
        12: polynom_rew = 32'b100000101001;
905
        13: polynom_rew = 32'b1000000001100;
906
        14: polynom_rew = 32'b10000000010101;
907
        15: polynom_rew = 32'b110000000000000;
908
        16: polynom_rew = 32'b1101000000001000;
909
        17: polynom_rew = 32'b10010000000000000;
910
        18: polynom_rew = 32'b100000010000000000;
911
        19: polynom_rew = 32'b1000000000000100011;
912
        20: polynom_rew = 32'b10000010000000000000;
913
        21: polynom_rew = 32'b101000000000000000000;
914
        22: polynom_rew = 32'b1100000000000000000000;
915
        23: polynom_rew = 32'b10000100000000000000000;
916
        24: polynom_rew = 32'b111000010000000000000000;
917
        25: polynom_rew = 32'b1001000000000000000000000;
918
        26: polynom_rew = 32'b10000000000000000000100011;
919
        27: polynom_rew = 32'b100000000000000000000010011;
920
        28: polynom_rew = 32'b1100100000000000000000000000;
921
        29: polynom_rew = 32'b10100000000000000000000000000;
922
        30: polynom_rew = 32'b100000000000000000000000101001;
923
        31: polynom_rew = 32'b1001000000000000000000000000000;
924
        32: polynom_rew = 32'b10000000001000000000000000000011;
925
        default: polynom_rew = 32'b0;
926
        endcase
927
        // rotate left
928
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
929
        lfsr_fb_rew = qi[length];
930
        for (i=length-1; i>=1; i=i-1) begin
931
            if (polynom_rew[i])
932
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
933
        end
934
    end
935
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
936
   assign q_next = rew ? q_next_rew : q_next_fw;
937
   always @ (posedge clk or posedge rst)
938
     if (rst)
939
       qi <= {length{1'b0}};
940
     else
941
     if (cke)
942
       qi <= q_next;
943
    always @ (posedge clk or posedge rst)
944
    if (rst)
945
        level1 <= 1'b0;
946
    else
947
    if (cke)
948
    if (q_next == level1_value)
949
        level1 <= 1'b1;
950
    else if (qi == level1_value & rew)
951
        level1 <= 1'b0;
952
endmodule
953
//////////////////////////////////////////////////////////////////////
954
////                                                              ////
955
////  Versatile counter                                           ////
956
////                                                              ////
957
////  Description                                                 ////
958
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
959
////  counter                                                     ////
960
////                                                              ////
961
////  To Do:                                                      ////
962
////   - add LFSR with more taps                                  ////
963
////                                                              ////
964
////  Author(s):                                                  ////
965
////      - Michael Unneback, unneback@opencores.org              ////
966
////        ORSoC AB                                              ////
967
////                                                              ////
968
//////////////////////////////////////////////////////////////////////
969
////                                                              ////
970
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
971
////                                                              ////
972
//// This source file may be used and distributed without         ////
973
//// restriction provided that this copyright statement is not    ////
974
//// removed from the file and that any derivative work contains  ////
975
//// the original copyright notice and the associated disclaimer. ////
976
////                                                              ////
977
//// This source file is free software; you can redistribute it   ////
978
//// and/or modify it under the terms of the GNU Lesser General   ////
979
//// Public License as published by the Free Software Foundation; ////
980
//// either version 2.1 of the License, or (at your option) any   ////
981
//// later version.                                               ////
982
////                                                              ////
983
//// This source is distributed in the hope that it will be       ////
984
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
985
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
986
//// PURPOSE.  See the GNU Lesser General Public License for more ////
987
//// details.                                                     ////
988
////                                                              ////
989
//// You should have received a copy of the GNU Lesser General    ////
990
//// Public License along with this source; if not, download it   ////
991
//// from http://www.opencores.org/lgpl.shtml                     ////
992
////                                                              ////
993
//////////////////////////////////////////////////////////////////////
994
// GRAY counter
995
module cnt_gray ( q, rst, clk);
996
   parameter length = 4;
997
   output reg [length:1] q;
998
   input rst;
999
   input clk;
1000
   parameter clear_value = 0;
1001
   parameter set_value = 1;
1002
   parameter wrap_value = 8;
1003
   parameter level1_value = 15;
1004
   reg  [length:1] qi;
1005
   wire [length:1] q_next;
1006
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1007
   always @ (posedge clk or posedge rst)
1008
     if (rst)
1009
       qi <= {length{1'b0}};
1010
     else
1011
       qi <= q_next;
1012
   always @ (posedge clk or posedge rst)
1013
     if (rst)
1014
       q <= {length{1'b0}};
1015
     else
1016
         q <= (q_next>>1) ^ q_next;
1017
endmodule
1018
//////////////////////////////////////////////////////////////////////
1019
////                                                              ////
1020
////  Versatile counter                                           ////
1021
////                                                              ////
1022
////  Description                                                 ////
1023
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1024
////  counter                                                     ////
1025
////                                                              ////
1026
////  To Do:                                                      ////
1027
////   - add LFSR with more taps                                  ////
1028
////                                                              ////
1029
////  Author(s):                                                  ////
1030
////      - Michael Unneback, unneback@opencores.org              ////
1031
////        ORSoC AB                                              ////
1032
////                                                              ////
1033
//////////////////////////////////////////////////////////////////////
1034
////                                                              ////
1035
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1036
////                                                              ////
1037
//// This source file may be used and distributed without         ////
1038
//// restriction provided that this copyright statement is not    ////
1039
//// removed from the file and that any derivative work contains  ////
1040
//// the original copyright notice and the associated disclaimer. ////
1041
////                                                              ////
1042
//// This source file is free software; you can redistribute it   ////
1043
//// and/or modify it under the terms of the GNU Lesser General   ////
1044
//// Public License as published by the Free Software Foundation; ////
1045
//// either version 2.1 of the License, or (at your option) any   ////
1046
//// later version.                                               ////
1047
////                                                              ////
1048
//// This source is distributed in the hope that it will be       ////
1049
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1050
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1051
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1052
//// details.                                                     ////
1053
////                                                              ////
1054
//// You should have received a copy of the GNU Lesser General    ////
1055
//// Public License along with this source; if not, download it   ////
1056
//// from http://www.opencores.org/lgpl.shtml                     ////
1057
////                                                              ////
1058
//////////////////////////////////////////////////////////////////////
1059
// GRAY counter
1060
module cnt_gray_ce ( cke, q, rst, clk);
1061
   parameter length = 4;
1062
   input cke;
1063
   output reg [length:1] q;
1064
   input rst;
1065
   input clk;
1066
   parameter clear_value = 0;
1067
   parameter set_value = 1;
1068
   parameter wrap_value = 8;
1069
   parameter level1_value = 15;
1070
   reg  [length:1] qi;
1071
   wire [length:1] q_next;
1072
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1073
   always @ (posedge clk or posedge rst)
1074
     if (rst)
1075
       qi <= {length{1'b0}};
1076
     else
1077
     if (cke)
1078
       qi <= q_next;
1079
   always @ (posedge clk or posedge rst)
1080
     if (rst)
1081
       q <= {length{1'b0}};
1082
     else
1083
       if (cke)
1084
         q <= (q_next>>1) ^ q_next;
1085
endmodule
1086
//////////////////////////////////////////////////////////////////////
1087
////                                                              ////
1088
////  Versatile counter                                           ////
1089
////                                                              ////
1090
////  Description                                                 ////
1091
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1092
////  counter                                                     ////
1093
////                                                              ////
1094
////  To Do:                                                      ////
1095
////   - add LFSR with more taps                                  ////
1096
////                                                              ////
1097
////  Author(s):                                                  ////
1098
////      - Michael Unneback, unneback@opencores.org              ////
1099
////        ORSoC AB                                              ////
1100
////                                                              ////
1101
//////////////////////////////////////////////////////////////////////
1102
////                                                              ////
1103
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1104
////                                                              ////
1105
//// This source file may be used and distributed without         ////
1106
//// restriction provided that this copyright statement is not    ////
1107
//// removed from the file and that any derivative work contains  ////
1108
//// the original copyright notice and the associated disclaimer. ////
1109
////                                                              ////
1110
//// This source file is free software; you can redistribute it   ////
1111
//// and/or modify it under the terms of the GNU Lesser General   ////
1112
//// Public License as published by the Free Software Foundation; ////
1113
//// either version 2.1 of the License, or (at your option) any   ////
1114
//// later version.                                               ////
1115
////                                                              ////
1116
//// This source is distributed in the hope that it will be       ////
1117
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1118
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1119
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1120
//// details.                                                     ////
1121
////                                                              ////
1122
//// You should have received a copy of the GNU Lesser General    ////
1123
//// Public License along with this source; if not, download it   ////
1124
//// from http://www.opencores.org/lgpl.shtml                     ////
1125
////                                                              ////
1126
//////////////////////////////////////////////////////////////////////
1127
// GRAY counter
1128
module cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
1129
   parameter length = 4;
1130
   input cke;
1131
   output reg [length:1] q;
1132
   output [length:1] q_bin;
1133
   input rst;
1134
   input clk;
1135
   parameter clear_value = 0;
1136
   parameter set_value = 1;
1137
   parameter wrap_value = 8;
1138
   parameter level1_value = 15;
1139
   reg  [length:1] qi;
1140
   wire [length:1] q_next;
1141
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1142
   always @ (posedge clk or posedge rst)
1143
     if (rst)
1144
       qi <= {length{1'b0}};
1145
     else
1146
     if (cke)
1147
       qi <= q_next;
1148
   always @ (posedge clk or posedge rst)
1149
     if (rst)
1150
       q <= {length{1'b0}};
1151
     else
1152
       if (cke)
1153
         q <= (q_next>>1) ^ q_next;
1154
   assign q_bin = qi;
1155
endmodule
1156
//////////////////////////////////////////////////////////////////////
1157
////                                                              ////
1158
////  Versatile library, counters                                 ////
1159
////                                                              ////
1160
////  Description                                                 ////
1161
////  counters                                                    ////
1162
////                                                              ////
1163
////                                                              ////
1164
////  To Do:                                                      ////
1165
////   - add more counters                                        ////
1166
////                                                              ////
1167
////  Author(s):                                                  ////
1168
////      - Michael Unneback, unneback@opencores.org              ////
1169
////        ORSoC AB                                              ////
1170
////                                                              ////
1171
//////////////////////////////////////////////////////////////////////
1172
////                                                              ////
1173
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1174
////                                                              ////
1175
//// This source file may be used and distributed without         ////
1176
//// restriction provided that this copyright statement is not    ////
1177
//// removed from the file and that any derivative work contains  ////
1178
//// the original copyright notice and the associated disclaimer. ////
1179
////                                                              ////
1180
//// This source file is free software; you can redistribute it   ////
1181
//// and/or modify it under the terms of the GNU Lesser General   ////
1182
//// Public License as published by the Free Software Foundation; ////
1183
//// either version 2.1 of the License, or (at your option) any   ////
1184
//// later version.                                               ////
1185
////                                                              ////
1186
//// This source is distributed in the hope that it will be       ////
1187
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1188
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1189
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1190
//// details.                                                     ////
1191
////                                                              ////
1192
//// You should have received a copy of the GNU Lesser General    ////
1193
//// Public License along with this source; if not, download it   ////
1194
//// from http://www.opencores.org/lgpl.shtml                     ////
1195
////                                                              ////
1196
//////////////////////////////////////////////////////////////////////
1197
module cnt_shreg_wrap ( q, rst, clk);
1198
   parameter length = 4;
1199
   output reg [0:length-1] q;
1200
   input rst;
1201
   input clk;
1202
    always @ (posedge clk or posedge rst)
1203
    if (rst)
1204
        q <= {1'b1,{length-1{1'b0}}};
1205
    else
1206
        q <= {q[length-1],q[0:length-2]};
1207
endmodule
1208
module cnt_shreg_ce_wrap ( cke, q, rst, clk);
1209
   parameter length = 4;
1210
   input cke;
1211
   output reg [0:length-1] q;
1212
   input rst;
1213
   input clk;
1214
    always @ (posedge clk or posedge rst)
1215
    if (rst)
1216
        q <= {1'b1,{length-1{1'b0}}};
1217
    else
1218
        if (cke)
1219
            q <= {q[length-1],q[0:length-2]};
1220
endmodule
1221
module cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1222
   parameter length = 4;
1223
   input cke, clear;
1224
   output reg [0:length-1] q;
1225
   input rst;
1226
   input clk;
1227
    always @ (posedge clk or posedge rst)
1228
    if (rst)
1229
        q <= {1'b1,{length-1{1'b0}}};
1230
    else
1231
        if (cke)
1232
            if (clear)
1233
                q <= {1'b1,{length-1{1'b0}}};
1234
            else
1235
                q <= q >> 1;
1236
endmodule
1237
module cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
1238
   parameter length = 4;
1239
   input cke, clear;
1240
   output reg [0:length-1] q;
1241
   input rst;
1242
   input clk;
1243
    always @ (posedge clk or posedge rst)
1244
    if (rst)
1245
        q <= {1'b1,{length-1{1'b0}}};
1246
    else
1247
        if (cke)
1248
            if (clear)
1249
                q <= {1'b1,{length-1{1'b0}}};
1250
            else
1251
            q <= {q[length-1],q[0:length-2]};
1252
endmodule
1253
//////////////////////////////////////////////////////////////////////
1254
////                                                              ////
1255
////  Versatile library, memories                                 ////
1256
////                                                              ////
1257
////  Description                                                 ////
1258
////  memories                                                    ////
1259
////                                                              ////
1260
////                                                              ////
1261
////  To Do:                                                      ////
1262
////   - add more memory types                                    ////
1263
////                                                              ////
1264
////  Author(s):                                                  ////
1265
////      - Michael Unneback, unneback@opencores.org              ////
1266
////        ORSoC AB                                              ////
1267
////                                                              ////
1268
//////////////////////////////////////////////////////////////////////
1269
////                                                              ////
1270
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1271
////                                                              ////
1272
//// This source file may be used and distributed without         ////
1273
//// restriction provided that this copyright statement is not    ////
1274
//// removed from the file and that any derivative work contains  ////
1275
//// the original copyright notice and the associated disclaimer. ////
1276
////                                                              ////
1277
//// This source file is free software; you can redistribute it   ////
1278
//// and/or modify it under the terms of the GNU Lesser General   ////
1279
//// Public License as published by the Free Software Foundation; ////
1280
//// either version 2.1 of the License, or (at your option) any   ////
1281
//// later version.                                               ////
1282
////                                                              ////
1283
//// This source is distributed in the hope that it will be       ////
1284
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1285
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1286
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1287
//// details.                                                     ////
1288
////                                                              ////
1289
//// You should have received a copy of the GNU Lesser General    ////
1290
//// Public License along with this source; if not, download it   ////
1291
//// from http://www.opencores.org/lgpl.shtml                     ////
1292
////                                                              ////
1293
//////////////////////////////////////////////////////////////////////
1294
/// ROM
1295 7 unneback
module vl_rom_init ( adr, q, clk);
1296
   parameter data_width = 32;
1297
   parameter addr_width = 8;
1298
   input [(addr_width-1):0]       adr;
1299
   output reg [(data_width-1):0] q;
1300
   input                         clk;
1301
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
1302
   parameter memory_file = "vl_rom.vmem";
1303
   initial
1304
     begin
1305
        $readmemh(memory_file, rom);
1306
     end
1307
   always @ (posedge clk)
1308
     q <= rom[adr];
1309
endmodule
1310 14 unneback
/*
1311 7 unneback
module vl_rom ( adr, q, clk);
1312 6 unneback
parameter data_width = 32;
1313
parameter addr_width = 4;
1314
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
1315
    {32'h18000000},
1316
    {32'hA8200000},
1317
    {32'hA8200000},
1318
    {32'hA8200000},
1319
    {32'h44003000},
1320
    {32'h15000000},
1321
    {32'h15000000},
1322
    {32'h15000000},
1323
    {32'h15000000},
1324
    {32'h15000000},
1325
    {32'h15000000},
1326
    {32'h15000000},
1327
    {32'h15000000},
1328
    {32'h15000000},
1329
    {32'h15000000},
1330
    {32'h15000000}};
1331 7 unneback
input [addr_width-1:0] adr;
1332 6 unneback
output reg [data_width-1:0] q;
1333
input clk;
1334
always @ (posedge clk)
1335 7 unneback
    q <= data[adr];
1336 6 unneback
endmodule
1337 14 unneback
*/
1338 6 unneback
// Single port RAM
1339
module vl_ram ( d, adr, we, q, clk);
1340
   parameter data_width = 32;
1341
   parameter addr_width = 8;
1342
   input [(data_width-1):0]      d;
1343
   input [(addr_width-1):0]       adr;
1344
   input                         we;
1345 7 unneback
   output reg [(data_width-1):0] q;
1346 6 unneback
   input                         clk;
1347
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1348 7 unneback
   parameter init = 0;
1349
   parameter memory_file = "vl_ram.vmem";
1350
   generate if (init) begin : init_mem
1351
   initial
1352
     begin
1353
        $readmemh(memory_file, ram);
1354
     end
1355
   end
1356
   endgenerate
1357 6 unneback
   always @ (posedge clk)
1358
   begin
1359
   if (we)
1360
     ram[adr] <= d;
1361
   q <= ram[adr];
1362
   end
1363
endmodule
1364 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
1365
   parameter data_width = 32;
1366
   parameter addr_width = 8;
1367
   input [(data_width-1):0]      d;
1368
   input [(addr_width-1):0]       adr;
1369
   input [(addr_width/4)-1:0]    be;
1370
   input                         we;
1371
   output reg [(data_width-1):0] q;
1372
   input                         clk;
1373
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1374
   parameter init = 0;
1375
   parameter memory_file = "vl_ram.vmem";
1376
   generate if (init) begin : init_mem
1377
   initial
1378
     begin
1379
        $readmemh(memory_file, ram);
1380
     end
1381
   end
1382
   endgenerate
1383
   genvar i;
1384
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
1385
      always @ (posedge clk)
1386
      if (we & be[i])
1387
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
1388
   end
1389
   endgenerate
1390
   always @ (posedge clk)
1391
      q <= ram[adr];
1392
endmodule
1393 6 unneback
// Dual port RAM
1394
// ACTEL FPGA should not use logic to handle rw collision
1395 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1396 6 unneback
   parameter data_width = 32;
1397
   parameter addr_width = 8;
1398
   input [(data_width-1):0]      d_a;
1399
   input [(addr_width-1):0]       adr_a;
1400
   input [(addr_width-1):0]       adr_b;
1401
   input                         we_a;
1402
   output [(data_width-1):0]      q_b;
1403
   input                         clk_a, clk_b;
1404
   reg [(addr_width-1):0]         adr_b_reg;
1405
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
1406 7 unneback
   parameter init = 0;
1407
   parameter memory_file = "vl_ram.vmem";
1408
   generate if (init) begin : init_mem
1409
   initial
1410
     begin
1411
        $readmemh(memory_file, ram);
1412
     end
1413
   end
1414
   endgenerate
1415 6 unneback
   always @ (posedge clk_a)
1416
   if (we_a)
1417
     ram[adr_a] <= d_a;
1418
   always @ (posedge clk_b)
1419
   adr_b_reg <= adr_b;
1420
   assign q_b = ram[adr_b_reg];
1421
endmodule
1422 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1423 6 unneback
   parameter data_width = 32;
1424
   parameter addr_width = 8;
1425
   input [(data_width-1):0]      d_a;
1426
   input [(addr_width-1):0]       adr_a;
1427
   input [(addr_width-1):0]       adr_b;
1428
   input                         we_a;
1429
   output [(data_width-1):0]      q_b;
1430
   output reg [(data_width-1):0] q_a;
1431
   input                         clk_a, clk_b;
1432
   reg [(data_width-1):0]         q_b;
1433
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
1434 7 unneback
   parameter init = 0;
1435
   parameter memory_file = "vl_ram.vmem";
1436
   generate if (init) begin : init_mem
1437
   initial
1438
     begin
1439
        $readmemh(memory_file, ram);
1440
     end
1441
   end
1442
   endgenerate
1443 6 unneback
   always @ (posedge clk_a)
1444
     begin
1445
        q_a <= ram[adr_a];
1446
        if (we_a)
1447
             ram[adr_a] <= d_a;
1448
     end
1449
   always @ (posedge clk_b)
1450
          q_b <= ram[adr_b];
1451
endmodule
1452 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
1453 6 unneback
   parameter data_width = 32;
1454
   parameter addr_width = 8;
1455
   input [(data_width-1):0]      d_a;
1456
   input [(addr_width-1):0]       adr_a;
1457
   input [(addr_width-1):0]       adr_b;
1458
   input                         we_a;
1459
   output [(data_width-1):0]      q_b;
1460
   input [(data_width-1):0]       d_b;
1461
   output reg [(data_width-1):0] q_a;
1462
   input                         we_b;
1463
   input                         clk_a, clk_b;
1464
   reg [(data_width-1):0]         q_b;
1465
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
1466 7 unneback
   parameter init = 0;
1467
   parameter memory_file = "vl_ram.vmem";
1468
   generate if (init) begin : init_mem
1469
   initial
1470
     begin
1471
        $readmemh(memory_file, ram);
1472
     end
1473
   end
1474
   endgenerate
1475 6 unneback
   always @ (posedge clk_a)
1476
     begin
1477
        q_a <= ram[adr_a];
1478
        if (we_a)
1479
             ram[adr_a] <= d_a;
1480
     end
1481
   always @ (posedge clk_b)
1482
     begin
1483
        q_b <= ram[adr_b];
1484
        if (we_b)
1485
          ram[adr_b] <= d_b;
1486
     end
1487
endmodule
1488
// Content addresable memory, CAM
1489
// FIFO
1490
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
1491 11 unneback
   parameter addr_width = 4;
1492
   parameter N = addr_width-1;
1493 6 unneback
   parameter Q1 = 2'b00;
1494
   parameter Q2 = 2'b01;
1495
   parameter Q3 = 2'b11;
1496
   parameter Q4 = 2'b10;
1497
   parameter going_empty = 1'b0;
1498
   parameter going_full  = 1'b1;
1499
   input [N:0]  wptr, rptr;
1500 14 unneback
   output       fifo_empty;
1501 6 unneback
   output       fifo_full;
1502
   input        wclk, rclk, rst;
1503
   wire direction;
1504
   reg  direction_set, direction_clr;
1505
   wire async_empty, async_full;
1506
   wire fifo_full2;
1507 14 unneback
   wire fifo_empty2;
1508 6 unneback
   // direction_set
1509
   always @ (wptr[N:N-1] or rptr[N:N-1])
1510
     case ({wptr[N:N-1],rptr[N:N-1]})
1511
       {Q1,Q2} : direction_set <= 1'b1;
1512
       {Q2,Q3} : direction_set <= 1'b1;
1513
       {Q3,Q4} : direction_set <= 1'b1;
1514
       {Q4,Q1} : direction_set <= 1'b1;
1515
       default : direction_set <= 1'b0;
1516
     endcase
1517
   // direction_clear
1518
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
1519
     if (rst)
1520
       direction_clr <= 1'b1;
1521
     else
1522
       case ({wptr[N:N-1],rptr[N:N-1]})
1523
         {Q2,Q1} : direction_clr <= 1'b1;
1524
         {Q3,Q2} : direction_clr <= 1'b1;
1525
         {Q4,Q3} : direction_clr <= 1'b1;
1526
         {Q1,Q4} : direction_clr <= 1'b1;
1527
         default : direction_clr <= 1'b0;
1528
       endcase
1529
    dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
1530
   assign async_empty = (wptr == rptr) && (direction==going_empty);
1531
   assign async_full  = (wptr == rptr) && (direction==going_full);
1532
    dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
1533
    dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
1534
/*
1535
   always @ (posedge wclk or posedge rst or posedge async_full)
1536
     if (rst)
1537
       {fifo_full, fifo_full2} <= 2'b00;
1538
     else if (async_full)
1539
       {fifo_full, fifo_full2} <= 2'b11;
1540
     else
1541
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
1542
*/
1543 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
1544 6 unneback
     if (async_empty)
1545
       {fifo_empty, fifo_empty2} <= 2'b11;
1546
     else
1547 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
1548
    dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
1549
    dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
1550 6 unneback
endmodule // async_comp
1551
module vl_fifo_1r1w_async (
1552
    d, wr, fifo_full, wr_clk, wr_rst,
1553
    q, rd, fifo_empty, rd_clk, rd_rst
1554
    );
1555
parameter data_width = 18;
1556
parameter addr_width = 4;
1557
// write side
1558
input  [data_width-1:0] d;
1559
input                   wr;
1560
output                  fifo_full;
1561
input                   wr_clk;
1562
input                   wr_rst;
1563
// read side
1564
output [data_width-1:0] q;
1565
input                   rd;
1566
output                  fifo_empty;
1567
input                   rd_clk;
1568
input                   rd_rst;
1569
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
1570
vl_fifo_1r1w_async (
1571
    d, wr, fifo_full, wr_clk, wr_rst,
1572
    q, rd, fifo_empty, rd_clk, rd_rst
1573
    );
1574 7 unneback
cnt_gray_ce_bin
1575 6 unneback
    # ( .length(addr_width))
1576
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
1577 7 unneback
cnt_gray_ce_bin
1578 6 unneback
    # (.length(addr_width))
1579
    fifo_rd_adr( .cke(wr), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_rst));
1580 7 unneback
vl_dpram_1r1w
1581 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
1582
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
1583
vl_fifo_cmp_async
1584
    # (.addr_width(addr_width))
1585
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
1586
endmodule
1587 8 unneback
module vl_fifo_2r2w_async (
1588 6 unneback
    // a side
1589
    a_d, a_wr, a_fifo_full,
1590
    a_q, a_rd, a_fifo_empty,
1591
    a_clk, a_rst,
1592
    // b side
1593
    b_d, b_wr, b_fifo_full,
1594
    b_q, b_rd, b_fifo_empty,
1595
    b_clk, b_rst
1596
    );
1597
parameter data_width = 18;
1598
parameter addr_width = 4;
1599
// a side
1600
input  [data_width-1:0] a_d;
1601
input                   a_wr;
1602
output                  a_fifo_full;
1603
output [data_width-1:0] a_q;
1604
input                   a_rd;
1605
output                  a_fifo_empty;
1606
input                   a_clk;
1607
input                   a_rst;
1608
// b side
1609
input  [data_width-1:0] b_d;
1610
input                   b_wr;
1611
output                  b_fifo_full;
1612
output [data_width-1:0] b_q;
1613
input                   b_rd;
1614
output                  b_fifo_empty;
1615
input                   b_clk;
1616
input                   b_rst;
1617
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1618
vl_fifo_1r1w_async_a (
1619
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
1620
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
1621
    );
1622
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1623
vl_fifo_1r1w_async_b (
1624
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
1625
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
1626
    );
1627
endmodule
1628 8 unneback
module vl_fifo_2r2w_async_simplex (
1629 6 unneback
    // a side
1630
    a_d, a_wr, a_fifo_full,
1631
    a_q, a_rd, a_fifo_empty,
1632
    a_clk, a_rst,
1633
    // b side
1634
    b_d, b_wr, b_fifo_full,
1635
    b_q, b_rd, b_fifo_empty,
1636
    b_clk, b_rst
1637
    );
1638
parameter data_width = 18;
1639
parameter addr_width = 4;
1640
// a side
1641
input  [data_width-1:0] a_d;
1642
input                   a_wr;
1643
output                  a_fifo_full;
1644
output [data_width-1:0] a_q;
1645
input                   a_rd;
1646
output                  a_fifo_empty;
1647
input                   a_clk;
1648
input                   a_rst;
1649
// b side
1650
input  [data_width-1:0] b_d;
1651
input                   b_wr;
1652
output                  b_fifo_full;
1653
output [data_width-1:0] b_q;
1654
input                   b_rd;
1655
output                  b_fifo_empty;
1656
input                   b_clk;
1657
input                   b_rst;
1658
// adr_gen
1659
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
1660
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
1661
// dpram
1662
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1663 7 unneback
cnt_gray_ce_bin
1664 6 unneback
    # ( .length(addr_width))
1665
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
1666 7 unneback
cnt_gray_ce_bin
1667 6 unneback
    # (.length(addr_width))
1668
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
1669 7 unneback
cnt_gray_ce_bin
1670 6 unneback
    # ( .length(addr_width))
1671
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
1672 7 unneback
cnt_gray_ce_bin
1673 6 unneback
    # (.length(addr_width))
1674
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
1675
// mux read or write adr to DPRAM
1676
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
1677
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
1678 11 unneback
vl_dpram_2r2w
1679 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
1680
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1681
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1682 11 unneback
vl_fifo_cmp_async
1683 6 unneback
    # (.addr_width(addr_width))
1684
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
1685 11 unneback
vl_fifo_cmp_async
1686 6 unneback
    # (.addr_width(addr_width))
1687
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
1688
endmodule
1689 12 unneback
//////////////////////////////////////////////////////////////////////
1690
////                                                              ////
1691
////  Versatile library, wishbone stuff                           ////
1692
////                                                              ////
1693
////  Description                                                 ////
1694
////  Wishbone compliant modules                                  ////
1695
////                                                              ////
1696
////                                                              ////
1697
////  To Do:                                                      ////
1698
////   -                                                          ////
1699
////                                                              ////
1700
////  Author(s):                                                  ////
1701
////      - Michael Unneback, unneback@opencores.org              ////
1702
////        ORSoC AB                                              ////
1703
////                                                              ////
1704
//////////////////////////////////////////////////////////////////////
1705
////                                                              ////
1706
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1707
////                                                              ////
1708
//// This source file may be used and distributed without         ////
1709
//// restriction provided that this copyright statement is not    ////
1710
//// removed from the file and that any derivative work contains  ////
1711
//// the original copyright notice and the associated disclaimer. ////
1712
////                                                              ////
1713
//// This source file is free software; you can redistribute it   ////
1714
//// and/or modify it under the terms of the GNU Lesser General   ////
1715
//// Public License as published by the Free Software Foundation; ////
1716
//// either version 2.1 of the License, or (at your option) any   ////
1717
//// later version.                                               ////
1718
////                                                              ////
1719
//// This source is distributed in the hope that it will be       ////
1720
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1721
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1722
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1723
//// details.                                                     ////
1724
////                                                              ////
1725
//// You should have received a copy of the GNU Lesser General    ////
1726
//// Public License along with this source; if not, download it   ////
1727
//// from http://www.opencores.org/lgpl.shtml                     ////
1728
////                                                              ////
1729
//////////////////////////////////////////////////////////////////////
1730
// async wb3 - wb3 bridge
1731
`timescale 1ns/1ns
1732
module wb3wb3_bridge (
1733
        // wishbone slave side
1734
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
1735
        // wishbone master side
1736
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
1737
input [31:0] wbs_dat_i;
1738
input [31:2] wbs_adr_i;
1739
input [3:0]  wbs_sel_i;
1740
input [1:0]  wbs_bte_i;
1741
input [2:0]  wbs_cti_i;
1742
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
1743
output [31:0] wbs_dat_o;
1744 14 unneback
output wbs_ack_o;
1745 12 unneback
input wbs_clk, wbs_rst;
1746
output [31:0] wbm_dat_o;
1747
output reg [31:2] wbm_adr_o;
1748
output [3:0]  wbm_sel_o;
1749
output reg [1:0]  wbm_bte_o;
1750
output reg [2:0]  wbm_cti_o;
1751 14 unneback
output reg wbm_we_o;
1752
output wbm_cyc_o;
1753 12 unneback
output wbm_stb_o;
1754
input [31:0]  wbm_dat_i;
1755
input wbm_ack_i;
1756
input wbm_clk, wbm_rst;
1757
parameter addr_width = 4;
1758
// bte
1759
parameter linear       = 2'b00;
1760
parameter wrap4        = 2'b01;
1761
parameter wrap8        = 2'b10;
1762
parameter wrap16       = 2'b11;
1763
// cti
1764
parameter classic      = 3'b000;
1765
parameter incburst     = 3'b010;
1766
parameter endofburst   = 3'b111;
1767
parameter wbs_adr  = 1'b0;
1768
parameter wbs_data = 1'b1;
1769
parameter wbm_adr0 = 2'b00;
1770
parameter wbm_adr1 = 2'b01;
1771
parameter wbm_data = 2'b10;
1772
reg [1:0] wbs_bte_reg;
1773
reg wbs;
1774
wire wbs_eoc_alert, wbm_eoc_alert;
1775
reg wbs_eoc, wbm_eoc;
1776
reg [1:0] wbm;
1777 14 unneback
wire [1:16] wbs_count, wbm_count;
1778 12 unneback
wire [35:0] a_d, a_q, b_d, b_q;
1779
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
1780
reg a_rd_reg;
1781
wire b_rd_adr, b_rd_data;
1782 14 unneback
wire b_rd_data_reg;
1783
wire [35:0] temp;
1784 12 unneback
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
1785
always @ (posedge wbs_clk or posedge wbs_rst)
1786
if (wbs_rst)
1787
        wbs_eoc <= 1'b0;
1788
else
1789
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
1790
                wbs_eoc <= wbs_bte_i==linear;
1791
        else if (wbs_eoc_alert & (a_rd | a_wr))
1792
                wbs_eoc <= 1'b1;
1793
cnt_shreg_ce_clear # ( .length(16))
1794
    cnt0 (
1795
        .cke(wbs_ack_o),
1796
        .clear(wbs_eoc),
1797
        .q(wbs_count),
1798
        .rst(wbs_rst),
1799
        .clk(wbs_clk));
1800
always @ (posedge wbs_clk or posedge wbs_rst)
1801
if (wbs_rst)
1802
        wbs <= wbs_adr;
1803
else
1804
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
1805
                wbs <= wbs_data;
1806
        else if (wbs_eoc & wbs_ack_o)
1807
                wbs <= wbs_adr;
1808
// wbs FIFO
1809
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
1810
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
1811
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
1812
              1'b0;
1813
assign a_rd = !a_fifo_empty;
1814
always @ (posedge wbs_clk or posedge wbs_rst)
1815
if (wbs_rst)
1816
        a_rd_reg <= 1'b0;
1817
else
1818
        a_rd_reg <= a_rd;
1819
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
1820
assign wbs_dat_o = a_q[35:4];
1821
always @ (posedge wbs_clk or posedge wbs_rst)
1822
if (wbs_rst)
1823 13 unneback
        wbs_bte_reg <= 2'b00;
1824 12 unneback
else
1825 13 unneback
        wbs_bte_reg <= wbs_bte_i;
1826 12 unneback
// wbm FIFO
1827
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
1828
always @ (posedge wbm_clk or posedge wbm_rst)
1829
if (wbm_rst)
1830
        wbm_eoc <= 1'b0;
1831
else
1832
        if (wbm==wbm_adr0 & !b_fifo_empty)
1833
                wbm_eoc <= b_q[4:3] == linear;
1834
        else if (wbm_eoc_alert & wbm_ack_i)
1835
                wbm_eoc <= 1'b1;
1836
always @ (posedge wbm_clk or posedge wbm_rst)
1837
if (wbm_rst)
1838
        wbm <= wbm_adr0;
1839
else
1840
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
1841
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
1842
        (wbm==wbm_adr1 & !wbm_we_o) |
1843
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
1844
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
1845
assign b_d = {wbm_dat_i,4'b1111};
1846
assign b_wr = !wbm_we_o & wbm_ack_i;
1847
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
1848
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
1849
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
1850
                   1'b0;
1851
assign b_rd = b_rd_adr | b_rd_data;
1852
dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
1853
dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
1854
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
1855
cnt_shreg_ce_clear # ( .length(16))
1856
    cnt1 (
1857
        .cke(wbm_ack_i),
1858
        .clear(wbm_eoc),
1859
        .q(wbm_count),
1860
        .rst(wbm_rst),
1861
        .clk(wbm_clk));
1862
assign wbm_cyc_o = wbm==wbm_data;
1863
assign wbm_stb_o = (wbm==wbm_data & wbm_we_o) ? !b_fifo_empty :
1864
                   (wbm==wbm_data) ? 1'b1 :
1865
                   1'b0;
1866
always @ (posedge wbm_clk or posedge wbm_rst)
1867
if (wbm_rst)
1868
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
1869
else begin
1870
        if (wbm==wbm_adr0 & !b_fifo_empty)
1871
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
1872
        else if (wbm_eoc_alert & wbm_ack_i)
1873
                wbm_cti_o <= endofburst;
1874
end
1875
//async_fifo_dw_simplex_top
1876
vl_fifo_2r2w_async_simplex
1877
# ( .data_width(36), .addr_width(addr_width))
1878
fifo (
1879
    // a side
1880
    .a_d(a_d),
1881
    .a_wr(a_wr),
1882
    .a_fifo_full(a_fifo_full),
1883
    .a_q(a_q),
1884
    .a_rd(a_rd),
1885
    .a_fifo_empty(a_fifo_empty),
1886
    .a_clk(wbs_clk),
1887
    .a_rst(wbs_rst),
1888
    // b side
1889
    .b_d(b_d),
1890
    .b_wr(b_wr),
1891
    .b_fifo_full(b_fifo_full),
1892
    .b_q(b_q),
1893
    .b_rd(b_rd),
1894
    .b_fifo_empty(b_fifo_empty),
1895
    .b_clk(wbm_clk),
1896
    .b_rst(wbm_rst)
1897
    );
1898
endmodule

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