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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Blame information for rev 150

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1 60 unneback
// default SYN_KEEP definition
2 136 unneback
///////////////////////////////////////
3
// dependencies
4
///////////////////////////////////////
5 97 unneback
// size to width
6 6 unneback
//////////////////////////////////////////////////////////////////////
7
////                                                              ////
8
////  Versatile library, clock and reset                          ////
9
////                                                              ////
10
////  Description                                                 ////
11
////  Logic related to clock and reset                            ////
12
////                                                              ////
13
////                                                              ////
14
////  To Do:                                                      ////
15
////   - add more different registers                             ////
16
////                                                              ////
17
////  Author(s):                                                  ////
18
////      - Michael Unneback, unneback@opencores.org              ////
19
////        ORSoC AB                                              ////
20
////                                                              ////
21
//////////////////////////////////////////////////////////////////////
22
////                                                              ////
23
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
24
////                                                              ////
25
//// This source file may be used and distributed without         ////
26
//// restriction provided that this copyright statement is not    ////
27
//// removed from the file and that any derivative work contains  ////
28
//// the original copyright notice and the associated disclaimer. ////
29
////                                                              ////
30
//// This source file is free software; you can redistribute it   ////
31
//// and/or modify it under the terms of the GNU Lesser General   ////
32
//// Public License as published by the Free Software Foundation; ////
33
//// either version 2.1 of the License, or (at your option) any   ////
34
//// later version.                                               ////
35
////                                                              ////
36
//// This source is distributed in the hope that it will be       ////
37
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
38
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
39
//// PURPOSE.  See the GNU Lesser General Public License for more ////
40
//// details.                                                     ////
41
////                                                              ////
42
//// You should have received a copy of the GNU Lesser General    ////
43
//// Public License along with this source; if not, download it   ////
44
//// from http://www.opencores.org/lgpl.shtml                     ////
45
////                                                              ////
46
//////////////////////////////////////////////////////////////////////
47 21 unneback
//altera
48 33 unneback
module vl_gbuf ( i, o);
49
input i;
50
output o;
51
assign o = i;
52
endmodule
53 6 unneback
 // ALTERA
54
 //ACTEL
55
// sync reset
56 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
57 6 unneback
// output active high global reset sync with two DFFs 
58
`timescale 1 ns/100 ps
59
module vl_sync_rst ( rst_n_i, rst_o, clk);
60
input rst_n_i, clk;
61
output rst_o;
62 18 unneback
reg [1:0] tmp;
63 6 unneback
always @ (posedge clk or negedge rst_n_i)
64
if (!rst_n_i)
65 17 unneback
        tmp <= 2'b11;
66 6 unneback
else
67 33 unneback
        tmp <= {1'b0,tmp[1]};
68 17 unneback
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
69 6 unneback
endmodule
70
// vl_pll
71 32 unneback
///////////////////////////////////////////////////////////////////////////////
72
`timescale 1 ps/1 ps
73
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
74
parameter index = 0;
75
parameter number_of_clk = 1;
76
parameter period_time_0 = 20000;
77
parameter period_time_1 = 20000;
78
parameter period_time_2 = 20000;
79
parameter period_time_3 = 20000;
80
parameter period_time_4 = 20000;
81
parameter lock_delay = 2000000;
82
input clk_i, rst_n_i;
83
output lock;
84
output reg [0:number_of_clk-1] clk_o;
85
output [0:number_of_clk-1] rst_o;
86 33 unneback
`ifdef SIM_PLL
87 32 unneback
always
88
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
89
generate if (number_of_clk > 1)
90
always
91
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
92
endgenerate
93
generate if (number_of_clk > 2)
94
always
95
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
96
endgenerate
97 33 unneback
generate if (number_of_clk > 3)
98 32 unneback
always
99
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
100
endgenerate
101 33 unneback
generate if (number_of_clk > 4)
102 32 unneback
always
103
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
104
endgenerate
105
genvar i;
106
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
107
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
108
end
109
endgenerate
110 33 unneback
//assign #lock_delay lock = rst_n_i;
111
assign lock = rst_n_i;
112 32 unneback
endmodule
113 33 unneback
`else
114
`ifdef VL_PLL0
115
`ifdef VL_PLL0_CLK1
116
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
117
`endif
118
`ifdef VL_PLL0_CLK2
119
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
120
`endif
121
`ifdef VL_PLL0_CLK3
122
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
123
`endif
124
`ifdef VL_PLL0_CLK4
125
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
126
`endif
127
`ifdef VL_PLL0_CLK5
128
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
129
`endif
130
`endif
131
`ifdef VL_PLL1
132
`ifdef VL_PLL1_CLK1
133
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
134
`endif
135
`ifdef VL_PLL1_CLK2
136
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
137
`endif
138
`ifdef VL_PLL1_CLK3
139
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
140
`endif
141
`ifdef VL_PLL1_CLK4
142
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
143
`endif
144
`ifdef VL_PLL1_CLK5
145
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
146
`endif
147
`endif
148
`ifdef VL_PLL2
149
`ifdef VL_PLL2_CLK1
150
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
151
`endif
152
`ifdef VL_PLL2_CLK2
153
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
154
`endif
155
`ifdef VL_PLL2_CLK3
156
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
157
`endif
158
`ifdef VL_PLL2_CLK4
159
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
160
`endif
161
`ifdef VL_PLL2_CLK5
162
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
163
`endif
164
`endif
165
`ifdef VL_PLL3
166
`ifdef VL_PLL3_CLK1
167
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
168
`endif
169
`ifdef VL_PLL3_CLK2
170
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
171
`endif
172
`ifdef VL_PLL3_CLK3
173
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
174
`endif
175
`ifdef VL_PLL3_CLK4
176
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
177
`endif
178
`ifdef VL_PLL3_CLK5
179
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
180
`endif
181
`endif
182 32 unneback
genvar i;
183
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
184 40 unneback
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
185 32 unneback
end
186
endgenerate
187
endmodule
188 33 unneback
`endif
189 32 unneback
///////////////////////////////////////////////////////////////////////////////
190 6 unneback
 //altera
191
 //actel
192
//////////////////////////////////////////////////////////////////////
193
////                                                              ////
194
////  Versatile library, registers                                ////
195
////                                                              ////
196
////  Description                                                 ////
197
////  Different type of registers                                 ////
198
////                                                              ////
199
////                                                              ////
200
////  To Do:                                                      ////
201
////   - add more different registers                             ////
202
////                                                              ////
203
////  Author(s):                                                  ////
204
////      - Michael Unneback, unneback@opencores.org              ////
205
////        ORSoC AB                                              ////
206
////                                                              ////
207
//////////////////////////////////////////////////////////////////////
208
////                                                              ////
209
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
210
////                                                              ////
211
//// This source file may be used and distributed without         ////
212
//// restriction provided that this copyright statement is not    ////
213
//// removed from the file and that any derivative work contains  ////
214
//// the original copyright notice and the associated disclaimer. ////
215
////                                                              ////
216
//// This source file is free software; you can redistribute it   ////
217
//// and/or modify it under the terms of the GNU Lesser General   ////
218
//// Public License as published by the Free Software Foundation; ////
219
//// either version 2.1 of the License, or (at your option) any   ////
220
//// later version.                                               ////
221
////                                                              ////
222
//// This source is distributed in the hope that it will be       ////
223
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
224
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
225
//// PURPOSE.  See the GNU Lesser General Public License for more ////
226
//// details.                                                     ////
227
////                                                              ////
228
//// You should have received a copy of the GNU Lesser General    ////
229
//// Public License along with this source; if not, download it   ////
230
//// from http://www.opencores.org/lgpl.shtml                     ////
231
////                                                              ////
232
//////////////////////////////////////////////////////////////////////
233 18 unneback
module vl_dff ( d, q, clk, rst);
234 6 unneback
        parameter width = 1;
235 139 unneback
        parameter reset_value = {width{1'b0}};
236 6 unneback
        input [width-1:0] d;
237
        input clk, rst;
238
        output reg [width-1:0] q;
239
        always @ (posedge clk or posedge rst)
240
        if (rst)
241
                q <= reset_value;
242
        else
243
                q <= d;
244
endmodule
245 18 unneback
module vl_dff_array ( d, q, clk, rst);
246 6 unneback
        parameter width = 1;
247
        parameter depth = 2;
248
        parameter reset_value = 1'b0;
249
        input [width-1:0] d;
250
        input clk, rst;
251
        output [width-1:0] q;
252
        reg  [0:depth-1] q_tmp [width-1:0];
253
        integer i;
254
        always @ (posedge clk or posedge rst)
255
        if (rst) begin
256
            for (i=0;i<depth;i=i+1)
257
                q_tmp[i] <= {width{reset_value}};
258
        end else begin
259
            q_tmp[0] <= d;
260
            for (i=1;i<depth;i=i+1)
261
                q_tmp[i] <= q_tmp[i-1];
262
        end
263
    assign q = q_tmp[depth-1];
264
endmodule
265 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
266 6 unneback
        parameter width = 1;
267 139 unneback
        parameter reset_value = {width{1'b0}};
268 6 unneback
        input [width-1:0] d;
269
        input ce, clk, rst;
270
        output reg [width-1:0] q;
271
        always @ (posedge clk or posedge rst)
272
        if (rst)
273
                q <= reset_value;
274
        else
275
                if (ce)
276
                        q <= d;
277
endmodule
278 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
279 8 unneback
        parameter width = 1;
280 139 unneback
        parameter reset_value = {width{1'b0}};
281 8 unneback
        input [width-1:0] d;
282 10 unneback
        input ce, clear, clk, rst;
283 8 unneback
        output reg [width-1:0] q;
284
        always @ (posedge clk or posedge rst)
285
        if (rst)
286
            q <= reset_value;
287
        else
288
            if (ce)
289
                if (clear)
290
                    q <= {width{1'b0}};
291
                else
292
                    q <= d;
293
endmodule
294 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
295
        parameter width = 1;
296 139 unneback
        parameter reset_value = {width{1'b0}};
297 24 unneback
        input [width-1:0] d;
298
        input ce, set, clk, rst;
299
        output reg [width-1:0] q;
300
        always @ (posedge clk or posedge rst)
301
        if (rst)
302
            q <= reset_value;
303
        else
304
            if (ce)
305
                if (set)
306
                    q <= {width{1'b1}};
307
                else
308
                    q <= d;
309
endmodule
310 29 unneback
module vl_spr ( sp, r, q, clk, rst);
311 64 unneback
        //parameter width = 1;
312
        parameter reset_value = 1'b0;
313 29 unneback
        input sp, r;
314
        output reg q;
315
        input clk, rst;
316
        always @ (posedge clk or posedge rst)
317
        if (rst)
318
            q <= reset_value;
319
        else
320
            if (sp)
321
                q <= 1'b1;
322
            else if (r)
323
                q <= 1'b0;
324
endmodule
325
module vl_srp ( s, rp, q, clk, rst);
326
        parameter width = 1;
327
        parameter reset_value = 0;
328
        input s, rp;
329
        output reg q;
330
        input clk, rst;
331
        always @ (posedge clk or posedge rst)
332
        if (rst)
333
            q <= reset_value;
334
        else
335
            if (rp)
336
                q <= 1'b0;
337
            else if (s)
338
                q <= 1'b1;
339
endmodule
340 6 unneback
// megafunction wizard: %LPM_FF%
341
// GENERATION: STANDARD
342
// VERSION: WM1.0
343
// MODULE: lpm_ff 
344
// ============================================================
345
// File Name: dff_sr.v
346
// Megafunction Name(s):
347
//                      lpm_ff
348
//
349
// Simulation Library Files(s):
350
//                      lpm
351
// ============================================================
352
// ************************************************************
353
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
354
//
355
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
356
// ************************************************************
357
//Copyright (C) 1991-2010 Altera Corporation
358
//Your use of Altera Corporation's design tools, logic functions 
359
//and other software and tools, and its AMPP partner logic 
360
//functions, and any output files from any of the foregoing 
361
//(including device programming or simulation files), and any 
362
//associated documentation or information are expressly subject 
363
//to the terms and conditions of the Altera Program License 
364
//Subscription Agreement, Altera MegaCore Function License 
365
//Agreement, or other applicable license agreement, including, 
366
//without limitation, that your use is for the sole purpose of 
367
//programming logic devices manufactured by Altera and sold by 
368
//Altera or its authorized distributors.  Please refer to the 
369
//applicable agreement for further details.
370
// synopsys translate_off
371
`timescale 1 ps / 1 ps
372
// synopsys translate_on
373 18 unneback
module vl_dff_sr (
374 6 unneback
        aclr,
375
        aset,
376
        clock,
377
        data,
378
        q);
379
        input     aclr;
380
        input     aset;
381
        input     clock;
382
        input     data;
383
        output    q;
384
        wire [0:0] sub_wire0;
385
        wire [0:0] sub_wire1 = sub_wire0[0:0];
386
        wire  q = sub_wire1;
387
        wire  sub_wire2 = data;
388
        wire  sub_wire3 = sub_wire2;
389
        lpm_ff  lpm_ff_component (
390
                                .aclr (aclr),
391
                                .clock (clock),
392
                                .data (sub_wire3),
393
                                .aset (aset),
394
                                .q (sub_wire0)
395
                                // synopsys translate_off
396
                                ,
397
                                .aload (),
398
                                .enable (),
399
                                .sclr (),
400
                                .sload (),
401
                                .sset ()
402
                                // synopsys translate_on
403
                                );
404
        defparam
405
                lpm_ff_component.lpm_fftype = "DFF",
406
                lpm_ff_component.lpm_type = "LPM_FF",
407
                lpm_ff_component.lpm_width = 1;
408
endmodule
409
// ============================================================
410
// CNX file retrieval info
411
// ============================================================
412
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
413
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
414
// Retrieval info: PRIVATE: ASET NUMERIC "1"
415
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
416
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
417
// Retrieval info: PRIVATE: DFF NUMERIC "1"
418
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
419
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
420
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
421
// Retrieval info: PRIVATE: SSET NUMERIC "0"
422
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
423
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
424
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
425
// Retrieval info: PRIVATE: nBit NUMERIC "1"
426
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
427
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
428
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
429
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
430
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
431
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
432
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
433
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
434
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
435
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
436
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
437
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
438
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
439
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
440
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
441
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
442
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
443
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
444
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
445
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
446
// Retrieval info: LIB_FILE: lpm
447
// LATCH
448
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
449 18 unneback
module vl_latch ( d, le, q, clk);
450 6 unneback
input d, le;
451
output q;
452
input clk;
453
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
454
endmodule
455 18 unneback
module vl_shreg ( d, q, clk, rst);
456 17 unneback
parameter depth = 10;
457
input d;
458
output q;
459
input clk, rst;
460
reg [1:depth] dffs;
461
always @ (posedge clk or posedge rst)
462
if (rst)
463
    dffs <= {depth{1'b0}};
464
else
465
    dffs <= {d,dffs[1:depth-1]};
466
assign q = dffs[depth];
467
endmodule
468 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
469 17 unneback
parameter depth = 10;
470
input d, ce;
471
output q;
472
input clk, rst;
473
reg [1:depth] dffs;
474
always @ (posedge clk or posedge rst)
475
if (rst)
476
    dffs <= {depth{1'b0}};
477
else
478
    if (ce)
479
        dffs <= {d,dffs[1:depth-1]};
480
assign q = dffs[depth];
481
endmodule
482 18 unneback
module vl_delay ( d, q, clk, rst);
483 15 unneback
parameter depth = 10;
484
input d;
485
output q;
486
input clk, rst;
487
reg [1:depth] dffs;
488
always @ (posedge clk or posedge rst)
489
if (rst)
490
    dffs <= {depth{1'b0}};
491
else
492
    dffs <= {d,dffs[1:depth-1]};
493
assign q = dffs[depth];
494
endmodule
495 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
496 17 unneback
parameter depth = 10;
497
input d;
498
output q, emptyflag;
499
input clk, rst;
500
reg [1:depth] dffs;
501
always @ (posedge clk or posedge rst)
502
if (rst)
503
    dffs <= {depth{1'b0}};
504
else
505
    dffs <= {d,dffs[1:depth-1]};
506
assign q = dffs[depth];
507
assign emptyflag = !(|dffs);
508
endmodule
509 98 unneback
module vl_pulse2toggle ( pl, q, clk, rst);
510 94 unneback
input pl;
511 98 unneback
output reg q;
512 94 unneback
input clk, rst;
513
always @ (posedge clk or posedge rst)
514
if (rst)
515
    q <= 1'b0;
516
else
517
    q <= pl ^ q;
518
endmodule
519 98 unneback
module vl_toggle2pulse (d, pl, clk, rst);
520 94 unneback
input d;
521
output pl;
522
input clk, rst;
523
reg dff;
524
always @ (posedge clk or posedge rst)
525
if (rst)
526
    dff <= 1'b0;
527
else
528
    dff <= d;
529 98 unneback
assign pl = d ^ dff;
530 94 unneback
endmodule
531
module vl_synchronizer (d, q, clk, rst);
532
input d;
533
output reg q;
534 116 unneback
input clk, rst;
535 94 unneback
reg dff;
536
always @ (posedge clk or posedge rst)
537
if (rst)
538 100 unneback
    {q,dff} <= 2'b00;
539 94 unneback
else
540 100 unneback
    {q,dff} <= {dff,d};
541 94 unneback
endmodule
542 97 unneback
module vl_cdc ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst);
543 94 unneback
input start_pl;
544
output take_it_pl;
545
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
546
output got_it_pl;
547
input clk_src, rst_src;
548
input clk_dst, rst_dst;
549
wire take_it_tg, take_it_tg_sync;
550
wire got_it_tg, got_it_tg_sync;
551
// src -> dst
552
vl_pulse2toggle p2t0 (
553
    .pl(start_pl),
554
    .q(take_it_tg),
555
    .clk(clk_src),
556
    .rst(rst_src));
557
vl_synchronizer sync0 (
558
    .d(take_it_tg),
559
    .q(take_it_tg_sync),
560
    .clk(clk_dst),
561
    .rst(rst_dst));
562
vl_toggle2pulse t2p0 (
563 100 unneback
    .d(take_it_tg_sync),
564 94 unneback
    .pl(take_it_pl),
565
    .clk(clk_dst),
566
    .rst(rst_dst));
567
// dst -> src
568 98 unneback
vl_pulse2toggle p2t1 (
569 94 unneback
    .pl(take_it_grant_pl),
570
    .q(got_it_tg),
571
    .clk(clk_dst),
572
    .rst(rst_dst));
573
vl_synchronizer sync1 (
574
    .d(got_it_tg),
575
    .q(got_it_tg_sync),
576
    .clk(clk_src),
577
    .rst(rst_src));
578
vl_toggle2pulse t2p1 (
579 100 unneback
    .d(got_it_tg_sync),
580 94 unneback
    .pl(got_it_pl),
581
    .clk(clk_src),
582
    .rst(rst_src));
583
endmodule
584 6 unneback
//////////////////////////////////////////////////////////////////////
585
////                                                              ////
586 18 unneback
////  Logic functions                                             ////
587
////                                                              ////
588
////  Description                                                 ////
589
////  Logic functions such as multiplexers                        ////
590
////                                                              ////
591
////                                                              ////
592
////  To Do:                                                      ////
593
////   -                                                          ////
594
////                                                              ////
595
////  Author(s):                                                  ////
596
////      - Michael Unneback, unneback@opencores.org              ////
597
////        ORSoC AB                                              ////
598
////                                                              ////
599
//////////////////////////////////////////////////////////////////////
600
////                                                              ////
601
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
602
////                                                              ////
603
//// This source file may be used and distributed without         ////
604
//// restriction provided that this copyright statement is not    ////
605
//// removed from the file and that any derivative work contains  ////
606
//// the original copyright notice and the associated disclaimer. ////
607
////                                                              ////
608
//// This source file is free software; you can redistribute it   ////
609
//// and/or modify it under the terms of the GNU Lesser General   ////
610
//// Public License as published by the Free Software Foundation; ////
611
//// either version 2.1 of the License, or (at your option) any   ////
612
//// later version.                                               ////
613
////                                                              ////
614
//// This source is distributed in the hope that it will be       ////
615
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
616
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
617
//// PURPOSE.  See the GNU Lesser General Public License for more ////
618
//// details.                                                     ////
619
////                                                              ////
620
//// You should have received a copy of the GNU Lesser General    ////
621
//// Public License along with this source; if not, download it   ////
622
//// from http://www.opencores.org/lgpl.shtml                     ////
623
////                                                              ////
624
//////////////////////////////////////////////////////////////////////
625 36 unneback
module vl_mux_andor ( a, sel, dout);
626
parameter width = 32;
627
parameter nr_of_ports = 4;
628
input [nr_of_ports*width-1:0] a;
629
input [nr_of_ports-1:0] sel;
630
output reg [width-1:0] dout;
631 38 unneback
integer i,j;
632 36 unneback
always @ (a, sel)
633
begin
634
    dout = a[width-1:0] & {width{sel[0]}};
635 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
636
        for (j=0;j<width;j=j+1)
637
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
638 36 unneback
end
639
endmodule
640 34 unneback
module vl_mux2_andor ( a1, a0, sel, dout);
641
parameter width = 32;
642 35 unneback
localparam nr_of_ports = 2;
643 34 unneback
input [width-1:0] a1, a0;
644
input [nr_of_ports-1:0] sel;
645
output [width-1:0] dout;
646 36 unneback
vl_mux_andor
647 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
648 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
649 34 unneback
endmodule
650
module vl_mux3_andor ( a2, a1, a0, sel, dout);
651
parameter width = 32;
652 35 unneback
localparam nr_of_ports = 3;
653 34 unneback
input [width-1:0] a2, a1, a0;
654
input [nr_of_ports-1:0] sel;
655
output [width-1:0] dout;
656 36 unneback
vl_mux_andor
657 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
658 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
659 34 unneback
endmodule
660 18 unneback
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
661
parameter width = 32;
662 35 unneback
localparam nr_of_ports = 4;
663 18 unneback
input [width-1:0] a3, a2, a1, a0;
664
input [nr_of_ports-1:0] sel;
665 22 unneback
output [width-1:0] dout;
666 36 unneback
vl_mux_andor
667 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
668 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
669 18 unneback
endmodule
670
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
671
parameter width = 32;
672 35 unneback
localparam nr_of_ports = 5;
673 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
674
input [nr_of_ports-1:0] sel;
675 22 unneback
output [width-1:0] dout;
676 36 unneback
vl_mux_andor
677 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
678 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
679 18 unneback
endmodule
680
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
681
parameter width = 32;
682 35 unneback
localparam nr_of_ports = 6;
683 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
684
input [nr_of_ports-1:0] sel;
685 22 unneback
output [width-1:0] dout;
686 36 unneback
vl_mux_andor
687 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
688 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
689 18 unneback
endmodule
690 43 unneback
module vl_parity_generate (data, parity);
691
parameter word_size = 32;
692
parameter chunk_size = 8;
693
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
694
input [word_size-1:0] data;
695
output reg [word_size/chunk_size-1:0] parity;
696
integer i,j;
697
always @ (data)
698
for (i=0;i<word_size/chunk_size;i=i+1) begin
699
    parity[i] = parity_type;
700
    for (j=0;j<chunk_size;j=j+1) begin
701 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
702 43 unneback
    end
703
end
704
endmodule
705
module vl_parity_check( data, parity, parity_error);
706
parameter word_size = 32;
707
parameter chunk_size = 8;
708
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
709
input [word_size-1:0] data;
710
input [word_size/chunk_size-1:0] parity;
711
output parity_error;
712 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
713 43 unneback
integer i,j;
714
always @ (data or parity)
715
for (i=0;i<word_size/chunk_size;i=i+1) begin
716
    error_flag[i] = parity[i] ^ parity_type;
717
    for (j=0;j<chunk_size;j=j+1) begin
718 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
719 43 unneback
    end
720
end
721
assign parity_error = |error_flag;
722
endmodule
723 18 unneback
//////////////////////////////////////////////////////////////////////
724
////                                                              ////
725 44 unneback
////  IO functions                                                ////
726
////                                                              ////
727
////  Description                                                 ////
728
////  IO functions such as IOB flip-flops                         ////
729
////                                                              ////
730
////                                                              ////
731
////  To Do:                                                      ////
732
////   -                                                          ////
733
////                                                              ////
734
////  Author(s):                                                  ////
735
////      - Michael Unneback, unneback@opencores.org              ////
736
////        ORSoC AB                                              ////
737
////                                                              ////
738
//////////////////////////////////////////////////////////////////////
739
////                                                              ////
740
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
741
////                                                              ////
742
//// This source file may be used and distributed without         ////
743
//// restriction provided that this copyright statement is not    ////
744
//// removed from the file and that any derivative work contains  ////
745
//// the original copyright notice and the associated disclaimer. ////
746
////                                                              ////
747
//// This source file is free software; you can redistribute it   ////
748
//// and/or modify it under the terms of the GNU Lesser General   ////
749
//// Public License as published by the Free Software Foundation; ////
750
//// either version 2.1 of the License, or (at your option) any   ////
751
//// later version.                                               ////
752
////                                                              ////
753
//// This source is distributed in the hope that it will be       ////
754
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
755
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
756
//// PURPOSE.  See the GNU Lesser General Public License for more ////
757
//// details.                                                     ////
758
////                                                              ////
759
//// You should have received a copy of the GNU Lesser General    ////
760
//// Public License along with this source; if not, download it   ////
761
//// from http://www.opencores.org/lgpl.shtml                     ////
762
////                                                              ////
763
//////////////////////////////////////////////////////////////////////
764 45 unneback
`timescale 1ns/1ns
765 44 unneback
module vl_o_dff (d_i, o_pad, clk, rst);
766
parameter width = 1;
767 45 unneback
parameter reset_value = {width{1'b0}};
768
input  [width-1:0]  d_i;
769 44 unneback
output [width-1:0] o_pad;
770
input clk, rst;
771 60 unneback
wire [width-1:0] d_i_int /*synthesis syn_keep = 1*/;
772 45 unneback
reg  [width-1:0] o_pad_int;
773 44 unneback
assign d_i_int = d_i;
774
genvar i;
775 45 unneback
generate
776 136 unneback
for (i=0;i<width;i=i+1) begin : dffs
777 44 unneback
    always @ (posedge clk or posedge rst)
778
    if (rst)
779 45 unneback
        o_pad_int[i] <= reset_value[i];
780 44 unneback
    else
781 45 unneback
        o_pad_int[i] <= d_i_int[i];
782
    assign #1 o_pad[i] = o_pad_int[i];
783 44 unneback
end
784
endgenerate
785
endmodule
786 45 unneback
`timescale 1ns/1ns
787 44 unneback
module vl_io_dff_oe ( d_i, d_o, oe, io_pad, clk, rst);
788
parameter width = 1;
789 140 unneback
parameter reset_value = 1'b0;
790 44 unneback
input  [width-1:0] d_o;
791
output reg [width-1:0] d_i;
792
input oe;
793
inout [width-1:0] io_pad;
794
input clk, rst;
795 60 unneback
wire [width-1:0] oe_d /*synthesis syn_keep = 1*/;
796 44 unneback
reg [width-1:0] oe_q;
797
reg [width-1:0] d_o_q;
798
assign oe_d = {width{oe}};
799
genvar i;
800
generate
801 136 unneback
for (i=0;i<width;i=i+1) begin : dffs
802 44 unneback
    always @ (posedge clk or posedge rst)
803
    if (rst)
804
        oe_q[i] <= 1'b0;
805
    else
806
        oe_q[i] <= oe_d[i];
807
    always @ (posedge clk or posedge rst)
808
    if (rst)
809 140 unneback
        d_o_q[i] <= reset_value;
810 44 unneback
    else
811
        d_o_q[i] <= d_o[i];
812
    always @ (posedge clk or posedge rst)
813
    if (rst)
814 140 unneback
        d_i[i] <= reset_value;
815 44 unneback
    else
816
        d_i[i] <= io_pad[i];
817 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
818 44 unneback
end
819
endgenerate
820
endmodule
821 136 unneback
module vl_o_ddr (d_h_i, d_l_i, o_pad, clk, rst);
822
parameter width = 1;
823
input  [width-1:0] d_h_i, d_l_i;
824
output [width-1:0] o_pad;
825
input clk, rst;
826
genvar i;
827
generate
828
for (i=0;i<width;i=i+1) begin : ddr
829
    ddio_out ddio_out0( .aclr(rst), .datain_h(d_h_i[i]), .datain_l(d_l_i[i]), .outclock(clk), .dataout(o_pad[i]) );
830
end
831
endgenerate
832
endmodule
833
module vl_o_clk ( clk_o_pad, clk, rst);
834
input clk, rst;
835
output clk_o_pad;
836
vl_o_ddr o_ddr0( .d_h_i(1'b1), .d_l_i(1'b0), .o_pad(clk_o_pad), .clk(clk), .rst(rst));
837
endmodule
838 44 unneback
//////////////////////////////////////////////////////////////////////
839
////                                                              ////
840 6 unneback
////  Versatile counter                                           ////
841
////                                                              ////
842
////  Description                                                 ////
843
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
844
////  counter                                                     ////
845
////                                                              ////
846
////  To Do:                                                      ////
847
////   - add LFSR with more taps                                  ////
848
////                                                              ////
849
////  Author(s):                                                  ////
850
////      - Michael Unneback, unneback@opencores.org              ////
851
////        ORSoC AB                                              ////
852
////                                                              ////
853
//////////////////////////////////////////////////////////////////////
854
////                                                              ////
855
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
856
////                                                              ////
857
//// This source file may be used and distributed without         ////
858
//// restriction provided that this copyright statement is not    ////
859
//// removed from the file and that any derivative work contains  ////
860
//// the original copyright notice and the associated disclaimer. ////
861
////                                                              ////
862
//// This source file is free software; you can redistribute it   ////
863
//// and/or modify it under the terms of the GNU Lesser General   ////
864
//// Public License as published by the Free Software Foundation; ////
865
//// either version 2.1 of the License, or (at your option) any   ////
866
//// later version.                                               ////
867
////                                                              ////
868
//// This source is distributed in the hope that it will be       ////
869
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
870
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
871
//// PURPOSE.  See the GNU Lesser General Public License for more ////
872
//// details.                                                     ////
873
////                                                              ////
874
//// You should have received a copy of the GNU Lesser General    ////
875
//// Public License along with this source; if not, download it   ////
876
//// from http://www.opencores.org/lgpl.shtml                     ////
877
////                                                              ////
878
//////////////////////////////////////////////////////////////////////
879
// binary counter
880 139 unneback
module vl_cnt_bin (
881
 q, rst, clk);
882
   parameter length = 4;
883
   output [length:1] q;
884
   input rst;
885
   input clk;
886
   parameter clear_value = 0;
887
   parameter set_value = 1;
888
   parameter wrap_value = 0;
889
   parameter level1_value = 15;
890
   reg  [length:1] qi;
891
   wire [length:1] q_next;
892
   assign q_next = qi + {{length-1{1'b0}},1'b1};
893
   always @ (posedge clk or posedge rst)
894
     if (rst)
895
       qi <= {length{1'b0}};
896
     else
897
       qi <= q_next;
898
   assign q = qi;
899
endmodule
900
//////////////////////////////////////////////////////////////////////
901
////                                                              ////
902
////  Versatile counter                                           ////
903
////                                                              ////
904
////  Description                                                 ////
905
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
906
////  counter                                                     ////
907
////                                                              ////
908
////  To Do:                                                      ////
909
////   - add LFSR with more taps                                  ////
910
////                                                              ////
911
////  Author(s):                                                  ////
912
////      - Michael Unneback, unneback@opencores.org              ////
913
////        ORSoC AB                                              ////
914
////                                                              ////
915
//////////////////////////////////////////////////////////////////////
916
////                                                              ////
917
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
918
////                                                              ////
919
//// This source file may be used and distributed without         ////
920
//// restriction provided that this copyright statement is not    ////
921
//// removed from the file and that any derivative work contains  ////
922
//// the original copyright notice and the associated disclaimer. ////
923
////                                                              ////
924
//// This source file is free software; you can redistribute it   ////
925
//// and/or modify it under the terms of the GNU Lesser General   ////
926
//// Public License as published by the Free Software Foundation; ////
927
//// either version 2.1 of the License, or (at your option) any   ////
928
//// later version.                                               ////
929
////                                                              ////
930
//// This source is distributed in the hope that it will be       ////
931
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
932
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
933
//// PURPOSE.  See the GNU Lesser General Public License for more ////
934
//// details.                                                     ////
935
////                                                              ////
936
//// You should have received a copy of the GNU Lesser General    ////
937
//// Public License along with this source; if not, download it   ////
938
//// from http://www.opencores.org/lgpl.shtml                     ////
939
////                                                              ////
940
//////////////////////////////////////////////////////////////////////
941
// binary counter
942
module vl_cnt_bin_clear (
943
 clear, q, rst, clk);
944
   parameter length = 4;
945
   input clear;
946
   output [length:1] q;
947
   input rst;
948
   input clk;
949
   parameter clear_value = 0;
950
   parameter set_value = 1;
951
   parameter wrap_value = 0;
952
   parameter level1_value = 15;
953
   reg  [length:1] qi;
954
   wire [length:1] q_next;
955
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
956
   always @ (posedge clk or posedge rst)
957
     if (rst)
958
       qi <= {length{1'b0}};
959
     else
960
       qi <= q_next;
961
   assign q = qi;
962
endmodule
963
//////////////////////////////////////////////////////////////////////
964
////                                                              ////
965
////  Versatile counter                                           ////
966
////                                                              ////
967
////  Description                                                 ////
968
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
969
////  counter                                                     ////
970
////                                                              ////
971
////  To Do:                                                      ////
972
////   - add LFSR with more taps                                  ////
973
////                                                              ////
974
////  Author(s):                                                  ////
975
////      - Michael Unneback, unneback@opencores.org              ////
976
////        ORSoC AB                                              ////
977
////                                                              ////
978
//////////////////////////////////////////////////////////////////////
979
////                                                              ////
980
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
981
////                                                              ////
982
//// This source file may be used and distributed without         ////
983
//// restriction provided that this copyright statement is not    ////
984
//// removed from the file and that any derivative work contains  ////
985
//// the original copyright notice and the associated disclaimer. ////
986
////                                                              ////
987
//// This source file is free software; you can redistribute it   ////
988
//// and/or modify it under the terms of the GNU Lesser General   ////
989
//// Public License as published by the Free Software Foundation; ////
990
//// either version 2.1 of the License, or (at your option) any   ////
991
//// later version.                                               ////
992
////                                                              ////
993
//// This source is distributed in the hope that it will be       ////
994
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
995
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
996
//// PURPOSE.  See the GNU Lesser General Public License for more ////
997
//// details.                                                     ////
998
////                                                              ////
999
//// You should have received a copy of the GNU Lesser General    ////
1000
//// Public License along with this source; if not, download it   ////
1001
//// from http://www.opencores.org/lgpl.shtml                     ////
1002
////                                                              ////
1003
//////////////////////////////////////////////////////////////////////
1004
// binary counter
1005 40 unneback
module vl_cnt_bin_ce (
1006
 cke, q, rst, clk);
1007 22 unneback
   parameter length = 4;
1008 6 unneback
   input cke;
1009
   output [length:1] q;
1010
   input rst;
1011
   input clk;
1012
   parameter clear_value = 0;
1013
   parameter set_value = 1;
1014
   parameter wrap_value = 0;
1015
   parameter level1_value = 15;
1016
   reg  [length:1] qi;
1017
   wire [length:1] q_next;
1018
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1019
   always @ (posedge clk or posedge rst)
1020
     if (rst)
1021
       qi <= {length{1'b0}};
1022
     else
1023
     if (cke)
1024
       qi <= q_next;
1025
   assign q = qi;
1026
endmodule
1027
//////////////////////////////////////////////////////////////////////
1028
////                                                              ////
1029
////  Versatile counter                                           ////
1030
////                                                              ////
1031
////  Description                                                 ////
1032
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1033
////  counter                                                     ////
1034
////                                                              ////
1035
////  To Do:                                                      ////
1036
////   - add LFSR with more taps                                  ////
1037
////                                                              ////
1038
////  Author(s):                                                  ////
1039
////      - Michael Unneback, unneback@opencores.org              ////
1040
////        ORSoC AB                                              ////
1041
////                                                              ////
1042
//////////////////////////////////////////////////////////////////////
1043
////                                                              ////
1044
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1045
////                                                              ////
1046
//// This source file may be used and distributed without         ////
1047
//// restriction provided that this copyright statement is not    ////
1048
//// removed from the file and that any derivative work contains  ////
1049
//// the original copyright notice and the associated disclaimer. ////
1050
////                                                              ////
1051
//// This source file is free software; you can redistribute it   ////
1052
//// and/or modify it under the terms of the GNU Lesser General   ////
1053
//// Public License as published by the Free Software Foundation; ////
1054
//// either version 2.1 of the License, or (at your option) any   ////
1055
//// later version.                                               ////
1056
////                                                              ////
1057
//// This source is distributed in the hope that it will be       ////
1058
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1059
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1060
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1061
//// details.                                                     ////
1062
////                                                              ////
1063
//// You should have received a copy of the GNU Lesser General    ////
1064
//// Public License along with this source; if not, download it   ////
1065
//// from http://www.opencores.org/lgpl.shtml                     ////
1066
////                                                              ////
1067
//////////////////////////////////////////////////////////////////////
1068
// binary counter
1069 139 unneback
module vl_cnt_bin_ce_clear (
1070
 clear, cke, q, rst, clk);
1071
   parameter length = 4;
1072
   input clear;
1073
   input cke;
1074
   output [length:1] q;
1075
   input rst;
1076
   input clk;
1077
   parameter clear_value = 0;
1078
   parameter set_value = 1;
1079
   parameter wrap_value = 0;
1080
   parameter level1_value = 15;
1081
   reg  [length:1] qi;
1082
   wire [length:1] q_next;
1083
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1084
   always @ (posedge clk or posedge rst)
1085
     if (rst)
1086
       qi <= {length{1'b0}};
1087
     else
1088
     if (cke)
1089
       qi <= q_next;
1090
   assign q = qi;
1091
endmodule
1092
//////////////////////////////////////////////////////////////////////
1093
////                                                              ////
1094
////  Versatile counter                                           ////
1095
////                                                              ////
1096
////  Description                                                 ////
1097
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1098
////  counter                                                     ////
1099
////                                                              ////
1100
////  To Do:                                                      ////
1101
////   - add LFSR with more taps                                  ////
1102
////                                                              ////
1103
////  Author(s):                                                  ////
1104
////      - Michael Unneback, unneback@opencores.org              ////
1105
////        ORSoC AB                                              ////
1106
////                                                              ////
1107
//////////////////////////////////////////////////////////////////////
1108
////                                                              ////
1109
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1110
////                                                              ////
1111
//// This source file may be used and distributed without         ////
1112
//// restriction provided that this copyright statement is not    ////
1113
//// removed from the file and that any derivative work contains  ////
1114
//// the original copyright notice and the associated disclaimer. ////
1115
////                                                              ////
1116
//// This source file is free software; you can redistribute it   ////
1117
//// and/or modify it under the terms of the GNU Lesser General   ////
1118
//// Public License as published by the Free Software Foundation; ////
1119
//// either version 2.1 of the License, or (at your option) any   ////
1120
//// later version.                                               ////
1121
////                                                              ////
1122
//// This source is distributed in the hope that it will be       ////
1123
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1124
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1125
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1126
//// details.                                                     ////
1127
////                                                              ////
1128
//// You should have received a copy of the GNU Lesser General    ////
1129
//// Public License along with this source; if not, download it   ////
1130
//// from http://www.opencores.org/lgpl.shtml                     ////
1131
////                                                              ////
1132
//////////////////////////////////////////////////////////////////////
1133
// binary counter
1134
module vl_cnt_bin_ce_clear_l1_l2 (
1135
 clear, cke, q, level1, level2, rst, clk);
1136
   parameter length = 4;
1137
   input clear;
1138
   input cke;
1139
   output [length:1] q;
1140
   output reg level1;
1141
   output reg level2;
1142
   input rst;
1143
   input clk;
1144
   parameter clear_value = 0;
1145
   parameter set_value = 1;
1146
   parameter wrap_value = 15;
1147
   parameter level1_value = 8;
1148
   parameter level2_value = 15;
1149
   wire rew;
1150
   assign rew = 1'b0;
1151
   reg  [length:1] qi;
1152
   wire [length:1] q_next;
1153
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
1154
   always @ (posedge clk or posedge rst)
1155
     if (rst)
1156
       qi <= {length{1'b0}};
1157
     else
1158
     if (cke)
1159
       qi <= q_next;
1160
   assign q = qi;
1161
    always @ (posedge clk or posedge rst)
1162
    if (rst)
1163
        level1 <= 1'b0;
1164
    else
1165
    if (cke)
1166
    if (clear)
1167
        level1 <= 1'b0;
1168
    else if (q_next == level1_value)
1169
        level1 <= 1'b1;
1170
    else if (qi == level1_value & rew)
1171
        level1 <= 1'b0;
1172
    always @ (posedge clk or posedge rst)
1173
    if (rst)
1174
        level2 <= 1'b0;
1175
    else
1176
    if (cke)
1177
    if (clear)
1178
        level2 <= 1'b0;
1179
    else if (q_next == level2_value)
1180
        level2 <= 1'b1;
1181
    else if (qi == level2_value & rew)
1182
        level2 <= 1'b0;
1183
endmodule
1184
//////////////////////////////////////////////////////////////////////
1185
////                                                              ////
1186
////  Versatile counter                                           ////
1187
////                                                              ////
1188
////  Description                                                 ////
1189
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1190
////  counter                                                     ////
1191
////                                                              ////
1192
////  To Do:                                                      ////
1193
////   - add LFSR with more taps                                  ////
1194
////                                                              ////
1195
////  Author(s):                                                  ////
1196
////      - Michael Unneback, unneback@opencores.org              ////
1197
////        ORSoC AB                                              ////
1198
////                                                              ////
1199
//////////////////////////////////////////////////////////////////////
1200
////                                                              ////
1201
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1202
////                                                              ////
1203
//// This source file may be used and distributed without         ////
1204
//// restriction provided that this copyright statement is not    ////
1205
//// removed from the file and that any derivative work contains  ////
1206
//// the original copyright notice and the associated disclaimer. ////
1207
////                                                              ////
1208
//// This source file is free software; you can redistribute it   ////
1209
//// and/or modify it under the terms of the GNU Lesser General   ////
1210
//// Public License as published by the Free Software Foundation; ////
1211
//// either version 2.1 of the License, or (at your option) any   ////
1212
//// later version.                                               ////
1213
////                                                              ////
1214
//// This source is distributed in the hope that it will be       ////
1215
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1216
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1217
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1218
//// details.                                                     ////
1219
////                                                              ////
1220
//// You should have received a copy of the GNU Lesser General    ////
1221
//// Public License along with this source; if not, download it   ////
1222
//// from http://www.opencores.org/lgpl.shtml                     ////
1223
////                                                              ////
1224
//////////////////////////////////////////////////////////////////////
1225
// binary counter
1226
module vl_cnt_bin_ce_clear_set_rew (
1227
 clear, set, cke, rew, q, rst, clk);
1228
   parameter length = 4;
1229
   input clear;
1230
   input set;
1231
   input cke;
1232
   input rew;
1233
   output [length:1] q;
1234
   input rst;
1235
   input clk;
1236
   parameter clear_value = 0;
1237
   parameter set_value = 1;
1238
   parameter wrap_value = 0;
1239
   parameter level1_value = 15;
1240
   reg  [length:1] qi;
1241
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1242
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1243
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1244
   assign q_next = rew ? q_next_rew : q_next_fw;
1245
   always @ (posedge clk or posedge rst)
1246
     if (rst)
1247
       qi <= {length{1'b0}};
1248
     else
1249
     if (cke)
1250
       qi <= q_next;
1251
   assign q = qi;
1252
endmodule
1253
//////////////////////////////////////////////////////////////////////
1254
////                                                              ////
1255
////  Versatile counter                                           ////
1256
////                                                              ////
1257
////  Description                                                 ////
1258
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1259
////  counter                                                     ////
1260
////                                                              ////
1261
////  To Do:                                                      ////
1262
////   - add LFSR with more taps                                  ////
1263
////                                                              ////
1264
////  Author(s):                                                  ////
1265
////      - Michael Unneback, unneback@opencores.org              ////
1266
////        ORSoC AB                                              ////
1267
////                                                              ////
1268
//////////////////////////////////////////////////////////////////////
1269
////                                                              ////
1270
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1271
////                                                              ////
1272
//// This source file may be used and distributed without         ////
1273
//// restriction provided that this copyright statement is not    ////
1274
//// removed from the file and that any derivative work contains  ////
1275
//// the original copyright notice and the associated disclaimer. ////
1276
////                                                              ////
1277
//// This source file is free software; you can redistribute it   ////
1278
//// and/or modify it under the terms of the GNU Lesser General   ////
1279
//// Public License as published by the Free Software Foundation; ////
1280
//// either version 2.1 of the License, or (at your option) any   ////
1281
//// later version.                                               ////
1282
////                                                              ////
1283
//// This source is distributed in the hope that it will be       ////
1284
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1285
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1286
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1287
//// details.                                                     ////
1288
////                                                              ////
1289
//// You should have received a copy of the GNU Lesser General    ////
1290
//// Public License along with this source; if not, download it   ////
1291
//// from http://www.opencores.org/lgpl.shtml                     ////
1292
////                                                              ////
1293
//////////////////////////////////////////////////////////////////////
1294
// binary counter
1295
module vl_cnt_bin_ce_rew_l1 (
1296
 cke, rew, level1, rst, clk);
1297
   parameter length = 4;
1298
   input cke;
1299
   input rew;
1300
   output reg level1;
1301
   input rst;
1302
   input clk;
1303
   parameter clear_value = 0;
1304
   parameter set_value = 1;
1305
   parameter wrap_value = 1;
1306
   parameter level1_value = 15;
1307
   wire clear;
1308
   assign clear = 1'b0;
1309
   reg  [length:1] qi;
1310
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1311
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1312
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1313
   assign q_next = rew ? q_next_rew : q_next_fw;
1314
   always @ (posedge clk or posedge rst)
1315
     if (rst)
1316
       qi <= {length{1'b0}};
1317
     else
1318
     if (cke)
1319
       qi <= q_next;
1320
    always @ (posedge clk or posedge rst)
1321
    if (rst)
1322
        level1 <= 1'b0;
1323
    else
1324
    if (cke)
1325
    if (clear)
1326
        level1 <= 1'b0;
1327
    else if (q_next == level1_value)
1328
        level1 <= 1'b1;
1329
    else if (qi == level1_value & rew)
1330
        level1 <= 1'b0;
1331
endmodule
1332
//////////////////////////////////////////////////////////////////////
1333
////                                                              ////
1334
////  Versatile counter                                           ////
1335
////                                                              ////
1336
////  Description                                                 ////
1337
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1338
////  counter                                                     ////
1339
////                                                              ////
1340
////  To Do:                                                      ////
1341
////   - add LFSR with more taps                                  ////
1342
////                                                              ////
1343
////  Author(s):                                                  ////
1344
////      - Michael Unneback, unneback@opencores.org              ////
1345
////        ORSoC AB                                              ////
1346
////                                                              ////
1347
//////////////////////////////////////////////////////////////////////
1348
////                                                              ////
1349
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1350
////                                                              ////
1351
//// This source file may be used and distributed without         ////
1352
//// restriction provided that this copyright statement is not    ////
1353
//// removed from the file and that any derivative work contains  ////
1354
//// the original copyright notice and the associated disclaimer. ////
1355
////                                                              ////
1356
//// This source file is free software; you can redistribute it   ////
1357
//// and/or modify it under the terms of the GNU Lesser General   ////
1358
//// Public License as published by the Free Software Foundation; ////
1359
//// either version 2.1 of the License, or (at your option) any   ////
1360
//// later version.                                               ////
1361
////                                                              ////
1362
//// This source is distributed in the hope that it will be       ////
1363
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1364
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1365
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1366
//// details.                                                     ////
1367
////                                                              ////
1368
//// You should have received a copy of the GNU Lesser General    ////
1369
//// Public License along with this source; if not, download it   ////
1370
//// from http://www.opencores.org/lgpl.shtml                     ////
1371
////                                                              ////
1372
//////////////////////////////////////////////////////////////////////
1373
// binary counter
1374 40 unneback
module vl_cnt_bin_ce_rew_zq_l1 (
1375
 cke, rew, zq, level1, rst, clk);
1376 6 unneback
   parameter length = 4;
1377
   input cke;
1378
   input rew;
1379 25 unneback
   output reg zq;
1380
   output reg level1;
1381
   input rst;
1382
   input clk;
1383
   parameter clear_value = 0;
1384
   parameter set_value = 1;
1385
   parameter wrap_value = 1;
1386
   parameter level1_value = 15;
1387 29 unneback
   wire clear;
1388 30 unneback
   assign clear = 1'b0;
1389 25 unneback
   reg  [length:1] qi;
1390
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1391
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1392
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1393
   assign q_next = rew ? q_next_rew : q_next_fw;
1394
   always @ (posedge clk or posedge rst)
1395
     if (rst)
1396
       qi <= {length{1'b0}};
1397
     else
1398
     if (cke)
1399
       qi <= q_next;
1400
   always @ (posedge clk or posedge rst)
1401
     if (rst)
1402
       zq <= 1'b1;
1403
     else
1404
     if (cke)
1405
       zq <= q_next == {length{1'b0}};
1406
    always @ (posedge clk or posedge rst)
1407
    if (rst)
1408
        level1 <= 1'b0;
1409
    else
1410
    if (cke)
1411 29 unneback
    if (clear)
1412
        level1 <= 1'b0;
1413
    else if (q_next == level1_value)
1414 25 unneback
        level1 <= 1'b1;
1415
    else if (qi == level1_value & rew)
1416
        level1 <= 1'b0;
1417
endmodule
1418
//////////////////////////////////////////////////////////////////////
1419
////                                                              ////
1420
////  Versatile counter                                           ////
1421
////                                                              ////
1422
////  Description                                                 ////
1423
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1424
////  counter                                                     ////
1425
////                                                              ////
1426
////  To Do:                                                      ////
1427
////   - add LFSR with more taps                                  ////
1428
////                                                              ////
1429
////  Author(s):                                                  ////
1430
////      - Michael Unneback, unneback@opencores.org              ////
1431
////        ORSoC AB                                              ////
1432
////                                                              ////
1433
//////////////////////////////////////////////////////////////////////
1434
////                                                              ////
1435
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1436
////                                                              ////
1437
//// This source file may be used and distributed without         ////
1438
//// restriction provided that this copyright statement is not    ////
1439
//// removed from the file and that any derivative work contains  ////
1440
//// the original copyright notice and the associated disclaimer. ////
1441
////                                                              ////
1442
//// This source file is free software; you can redistribute it   ////
1443
//// and/or modify it under the terms of the GNU Lesser General   ////
1444
//// Public License as published by the Free Software Foundation; ////
1445
//// either version 2.1 of the License, or (at your option) any   ////
1446
//// later version.                                               ////
1447
////                                                              ////
1448
//// This source is distributed in the hope that it will be       ////
1449
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1450
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1451
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1452
//// details.                                                     ////
1453
////                                                              ////
1454
//// You should have received a copy of the GNU Lesser General    ////
1455
//// Public License along with this source; if not, download it   ////
1456
//// from http://www.opencores.org/lgpl.shtml                     ////
1457
////                                                              ////
1458
//////////////////////////////////////////////////////////////////////
1459
// binary counter
1460 40 unneback
module vl_cnt_bin_ce_rew_q_zq_l1 (
1461
 cke, rew, q, zq, level1, rst, clk);
1462 25 unneback
   parameter length = 4;
1463
   input cke;
1464
   input rew;
1465
   output [length:1] q;
1466
   output reg zq;
1467
   output reg level1;
1468
   input rst;
1469
   input clk;
1470
   parameter clear_value = 0;
1471
   parameter set_value = 1;
1472
   parameter wrap_value = 1;
1473
   parameter level1_value = 15;
1474 29 unneback
   wire clear;
1475 30 unneback
   assign clear = 1'b0;
1476 25 unneback
   reg  [length:1] qi;
1477
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1478
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1479
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1480
   assign q_next = rew ? q_next_rew : q_next_fw;
1481
   always @ (posedge clk or posedge rst)
1482
     if (rst)
1483
       qi <= {length{1'b0}};
1484
     else
1485
     if (cke)
1486
       qi <= q_next;
1487
   assign q = qi;
1488
   always @ (posedge clk or posedge rst)
1489
     if (rst)
1490
       zq <= 1'b1;
1491
     else
1492
     if (cke)
1493
       zq <= q_next == {length{1'b0}};
1494
    always @ (posedge clk or posedge rst)
1495
    if (rst)
1496
        level1 <= 1'b0;
1497
    else
1498
    if (cke)
1499 29 unneback
    if (clear)
1500
        level1 <= 1'b0;
1501
    else if (q_next == level1_value)
1502 25 unneback
        level1 <= 1'b1;
1503
    else if (qi == level1_value & rew)
1504
        level1 <= 1'b0;
1505
endmodule
1506
//////////////////////////////////////////////////////////////////////
1507
////                                                              ////
1508
////  Versatile counter                                           ////
1509
////                                                              ////
1510
////  Description                                                 ////
1511
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1512
////  counter                                                     ////
1513
////                                                              ////
1514
////  To Do:                                                      ////
1515
////   - add LFSR with more taps                                  ////
1516
////                                                              ////
1517
////  Author(s):                                                  ////
1518
////      - Michael Unneback, unneback@opencores.org              ////
1519
////        ORSoC AB                                              ////
1520
////                                                              ////
1521
//////////////////////////////////////////////////////////////////////
1522
////                                                              ////
1523
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1524
////                                                              ////
1525
//// This source file may be used and distributed without         ////
1526
//// restriction provided that this copyright statement is not    ////
1527
//// removed from the file and that any derivative work contains  ////
1528
//// the original copyright notice and the associated disclaimer. ////
1529
////                                                              ////
1530
//// This source file is free software; you can redistribute it   ////
1531
//// and/or modify it under the terms of the GNU Lesser General   ////
1532
//// Public License as published by the Free Software Foundation; ////
1533
//// either version 2.1 of the License, or (at your option) any   ////
1534
//// later version.                                               ////
1535
////                                                              ////
1536
//// This source is distributed in the hope that it will be       ////
1537
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1538
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1539
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1540
//// details.                                                     ////
1541
////                                                              ////
1542
//// You should have received a copy of the GNU Lesser General    ////
1543
//// Public License along with this source; if not, download it   ////
1544
//// from http://www.opencores.org/lgpl.shtml                     ////
1545
////                                                              ////
1546
//////////////////////////////////////////////////////////////////////
1547 75 unneback
// LFSR counter
1548 136 unneback
module vl_cnt_lfsr_zq (
1549
 zq, rst, clk);
1550
   parameter length = 4;
1551
   output reg zq;
1552
   input rst;
1553
   input clk;
1554
   parameter clear_value = 0;
1555
   parameter set_value = 1;
1556
   parameter wrap_value = 8;
1557
   parameter level1_value = 15;
1558
   reg  [length:1] qi;
1559
   reg lfsr_fb;
1560
   wire [length:1] q_next;
1561
   reg [32:1] polynom;
1562
   integer i;
1563
   always @ (qi)
1564
   begin
1565
        case (length)
1566
         2: polynom = 32'b11;                               // 0x3
1567
         3: polynom = 32'b110;                              // 0x6
1568
         4: polynom = 32'b1100;                             // 0xC
1569
         5: polynom = 32'b10100;                            // 0x14
1570
         6: polynom = 32'b110000;                           // 0x30
1571
         7: polynom = 32'b1100000;                          // 0x60
1572
         8: polynom = 32'b10111000;                         // 0xb8
1573
         9: polynom = 32'b100010000;                        // 0x110
1574
        10: polynom = 32'b1001000000;                       // 0x240
1575
        11: polynom = 32'b10100000000;                      // 0x500
1576
        12: polynom = 32'b100000101001;                     // 0x829
1577
        13: polynom = 32'b1000000001100;                    // 0x100C
1578
        14: polynom = 32'b10000000010101;                   // 0x2015
1579
        15: polynom = 32'b110000000000000;                  // 0x6000
1580
        16: polynom = 32'b1101000000001000;                 // 0xD008
1581
        17: polynom = 32'b10010000000000000;                // 0x12000
1582
        18: polynom = 32'b100000010000000000;               // 0x20400
1583
        19: polynom = 32'b1000000000000100011;              // 0x40023
1584
        20: polynom = 32'b10010000000000000000;             // 0x90000
1585
        21: polynom = 32'b101000000000000000000;            // 0x140000
1586
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1587
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1588
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1589
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1590
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1591
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1592
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1593
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1594
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1595
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1596
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1597
        default: polynom = 32'b0;
1598
        endcase
1599
        lfsr_fb = qi[length];
1600
        for (i=length-1; i>=1; i=i-1) begin
1601
            if (polynom[i])
1602
                lfsr_fb = lfsr_fb  ~^ qi[i];
1603
        end
1604
    end
1605
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1606
   always @ (posedge clk or posedge rst)
1607
     if (rst)
1608
       qi <= {length{1'b0}};
1609
     else
1610
       qi <= q_next;
1611
   always @ (posedge clk or posedge rst)
1612
     if (rst)
1613
       zq <= 1'b1;
1614
     else
1615
       zq <= q_next == {length{1'b0}};
1616
endmodule
1617
//////////////////////////////////////////////////////////////////////
1618
////                                                              ////
1619
////  Versatile counter                                           ////
1620
////                                                              ////
1621
////  Description                                                 ////
1622
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1623
////  counter                                                     ////
1624
////                                                              ////
1625
////  To Do:                                                      ////
1626
////   - add LFSR with more taps                                  ////
1627
////                                                              ////
1628
////  Author(s):                                                  ////
1629
////      - Michael Unneback, unneback@opencores.org              ////
1630
////        ORSoC AB                                              ////
1631
////                                                              ////
1632
//////////////////////////////////////////////////////////////////////
1633
////                                                              ////
1634
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1635
////                                                              ////
1636
//// This source file may be used and distributed without         ////
1637
//// restriction provided that this copyright statement is not    ////
1638
//// removed from the file and that any derivative work contains  ////
1639
//// the original copyright notice and the associated disclaimer. ////
1640
////                                                              ////
1641
//// This source file is free software; you can redistribute it   ////
1642
//// and/or modify it under the terms of the GNU Lesser General   ////
1643
//// Public License as published by the Free Software Foundation; ////
1644
//// either version 2.1 of the License, or (at your option) any   ////
1645
//// later version.                                               ////
1646
////                                                              ////
1647
//// This source is distributed in the hope that it will be       ////
1648
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1649
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1650
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1651
//// details.                                                     ////
1652
////                                                              ////
1653
//// You should have received a copy of the GNU Lesser General    ////
1654
//// Public License along with this source; if not, download it   ////
1655
//// from http://www.opencores.org/lgpl.shtml                     ////
1656
////                                                              ////
1657
//////////////////////////////////////////////////////////////////////
1658
// LFSR counter
1659 75 unneback
module vl_cnt_lfsr_ce (
1660
 cke, zq, rst, clk);
1661
   parameter length = 4;
1662
   input cke;
1663
   output reg zq;
1664
   input rst;
1665
   input clk;
1666
   parameter clear_value = 0;
1667
   parameter set_value = 1;
1668
   parameter wrap_value = 0;
1669
   parameter level1_value = 15;
1670
   reg  [length:1] qi;
1671
   reg lfsr_fb;
1672
   wire [length:1] q_next;
1673
   reg [32:1] polynom;
1674
   integer i;
1675
   always @ (qi)
1676
   begin
1677
        case (length)
1678
         2: polynom = 32'b11;                               // 0x3
1679
         3: polynom = 32'b110;                              // 0x6
1680
         4: polynom = 32'b1100;                             // 0xC
1681
         5: polynom = 32'b10100;                            // 0x14
1682
         6: polynom = 32'b110000;                           // 0x30
1683
         7: polynom = 32'b1100000;                          // 0x60
1684
         8: polynom = 32'b10111000;                         // 0xb8
1685
         9: polynom = 32'b100010000;                        // 0x110
1686
        10: polynom = 32'b1001000000;                       // 0x240
1687
        11: polynom = 32'b10100000000;                      // 0x500
1688
        12: polynom = 32'b100000101001;                     // 0x829
1689
        13: polynom = 32'b1000000001100;                    // 0x100C
1690
        14: polynom = 32'b10000000010101;                   // 0x2015
1691
        15: polynom = 32'b110000000000000;                  // 0x6000
1692
        16: polynom = 32'b1101000000001000;                 // 0xD008
1693
        17: polynom = 32'b10010000000000000;                // 0x12000
1694
        18: polynom = 32'b100000010000000000;               // 0x20400
1695
        19: polynom = 32'b1000000000000100011;              // 0x40023
1696
        20: polynom = 32'b10010000000000000000;             // 0x90000
1697
        21: polynom = 32'b101000000000000000000;            // 0x140000
1698
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1699
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1700
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1701
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1702
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1703
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1704
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1705
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1706
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1707
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1708
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1709
        default: polynom = 32'b0;
1710
        endcase
1711
        lfsr_fb = qi[length];
1712
        for (i=length-1; i>=1; i=i-1) begin
1713
            if (polynom[i])
1714
                lfsr_fb = lfsr_fb  ~^ qi[i];
1715
        end
1716
    end
1717
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1718
   always @ (posedge clk or posedge rst)
1719
     if (rst)
1720
       qi <= {length{1'b0}};
1721
     else
1722
     if (cke)
1723
       qi <= q_next;
1724
   always @ (posedge clk or posedge rst)
1725
     if (rst)
1726
       zq <= 1'b1;
1727
     else
1728
     if (cke)
1729
       zq <= q_next == {length{1'b0}};
1730
endmodule
1731
//////////////////////////////////////////////////////////////////////
1732
////                                                              ////
1733
////  Versatile counter                                           ////
1734
////                                                              ////
1735
////  Description                                                 ////
1736
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1737
////  counter                                                     ////
1738
////                                                              ////
1739
////  To Do:                                                      ////
1740
////   - add LFSR with more taps                                  ////
1741
////                                                              ////
1742
////  Author(s):                                                  ////
1743
////      - Michael Unneback, unneback@opencores.org              ////
1744
////        ORSoC AB                                              ////
1745
////                                                              ////
1746
//////////////////////////////////////////////////////////////////////
1747
////                                                              ////
1748
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1749
////                                                              ////
1750
//// This source file may be used and distributed without         ////
1751
//// restriction provided that this copyright statement is not    ////
1752
//// removed from the file and that any derivative work contains  ////
1753
//// the original copyright notice and the associated disclaimer. ////
1754
////                                                              ////
1755
//// This source file is free software; you can redistribute it   ////
1756
//// and/or modify it under the terms of the GNU Lesser General   ////
1757
//// Public License as published by the Free Software Foundation; ////
1758
//// either version 2.1 of the License, or (at your option) any   ////
1759
//// later version.                                               ////
1760
////                                                              ////
1761
//// This source is distributed in the hope that it will be       ////
1762
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1763
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1764
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1765
//// details.                                                     ////
1766
////                                                              ////
1767
//// You should have received a copy of the GNU Lesser General    ////
1768
//// Public License along with this source; if not, download it   ////
1769
//// from http://www.opencores.org/lgpl.shtml                     ////
1770
////                                                              ////
1771
//////////////////////////////////////////////////////////////////////
1772 139 unneback
// LFSR counter
1773
module vl_cnt_lfsr_ce_zq (
1774
 cke, zq, rst, clk);
1775
   parameter length = 4;
1776
   input cke;
1777
   output reg zq;
1778
   input rst;
1779
   input clk;
1780
   parameter clear_value = 0;
1781
   parameter set_value = 1;
1782
   parameter wrap_value = 8;
1783
   parameter level1_value = 15;
1784
   reg  [length:1] qi;
1785
   reg lfsr_fb;
1786
   wire [length:1] q_next;
1787
   reg [32:1] polynom;
1788
   integer i;
1789
   always @ (qi)
1790
   begin
1791
        case (length)
1792
         2: polynom = 32'b11;                               // 0x3
1793
         3: polynom = 32'b110;                              // 0x6
1794
         4: polynom = 32'b1100;                             // 0xC
1795
         5: polynom = 32'b10100;                            // 0x14
1796
         6: polynom = 32'b110000;                           // 0x30
1797
         7: polynom = 32'b1100000;                          // 0x60
1798
         8: polynom = 32'b10111000;                         // 0xb8
1799
         9: polynom = 32'b100010000;                        // 0x110
1800
        10: polynom = 32'b1001000000;                       // 0x240
1801
        11: polynom = 32'b10100000000;                      // 0x500
1802
        12: polynom = 32'b100000101001;                     // 0x829
1803
        13: polynom = 32'b1000000001100;                    // 0x100C
1804
        14: polynom = 32'b10000000010101;                   // 0x2015
1805
        15: polynom = 32'b110000000000000;                  // 0x6000
1806
        16: polynom = 32'b1101000000001000;                 // 0xD008
1807
        17: polynom = 32'b10010000000000000;                // 0x12000
1808
        18: polynom = 32'b100000010000000000;               // 0x20400
1809
        19: polynom = 32'b1000000000000100011;              // 0x40023
1810
        20: polynom = 32'b10010000000000000000;             // 0x90000
1811
        21: polynom = 32'b101000000000000000000;            // 0x140000
1812
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1813
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1814
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1815
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1816
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1817
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1818
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1819
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1820
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1821
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1822
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1823
        default: polynom = 32'b0;
1824
        endcase
1825
        lfsr_fb = qi[length];
1826
        for (i=length-1; i>=1; i=i-1) begin
1827
            if (polynom[i])
1828
                lfsr_fb = lfsr_fb  ~^ qi[i];
1829
        end
1830
    end
1831
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1832
   always @ (posedge clk or posedge rst)
1833
     if (rst)
1834
       qi <= {length{1'b0}};
1835
     else
1836
     if (cke)
1837
       qi <= q_next;
1838
   always @ (posedge clk or posedge rst)
1839
     if (rst)
1840
       zq <= 1'b1;
1841
     else
1842
     if (cke)
1843
       zq <= q_next == {length{1'b0}};
1844
endmodule
1845
//////////////////////////////////////////////////////////////////////
1846
////                                                              ////
1847
////  Versatile counter                                           ////
1848
////                                                              ////
1849
////  Description                                                 ////
1850
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1851
////  counter                                                     ////
1852
////                                                              ////
1853
////  To Do:                                                      ////
1854
////   - add LFSR with more taps                                  ////
1855
////                                                              ////
1856
////  Author(s):                                                  ////
1857
////      - Michael Unneback, unneback@opencores.org              ////
1858
////        ORSoC AB                                              ////
1859
////                                                              ////
1860
//////////////////////////////////////////////////////////////////////
1861
////                                                              ////
1862
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1863
////                                                              ////
1864
//// This source file may be used and distributed without         ////
1865
//// restriction provided that this copyright statement is not    ////
1866
//// removed from the file and that any derivative work contains  ////
1867
//// the original copyright notice and the associated disclaimer. ////
1868
////                                                              ////
1869
//// This source file is free software; you can redistribute it   ////
1870
//// and/or modify it under the terms of the GNU Lesser General   ////
1871
//// Public License as published by the Free Software Foundation; ////
1872
//// either version 2.1 of the License, or (at your option) any   ////
1873
//// later version.                                               ////
1874
////                                                              ////
1875
//// This source is distributed in the hope that it will be       ////
1876
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1877
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1878
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1879
//// details.                                                     ////
1880
////                                                              ////
1881
//// You should have received a copy of the GNU Lesser General    ////
1882
//// Public License along with this source; if not, download it   ////
1883
//// from http://www.opencores.org/lgpl.shtml                     ////
1884
////                                                              ////
1885
//////////////////////////////////////////////////////////////////////
1886
// LFSR counter
1887
module vl_cnt_lfsr_ce_q (
1888
 cke, q, rst, clk);
1889
   parameter length = 4;
1890
   input cke;
1891
   output [length:1] q;
1892
   input rst;
1893
   input clk;
1894
   parameter clear_value = 0;
1895
   parameter set_value = 1;
1896
   parameter wrap_value = 8;
1897
   parameter level1_value = 15;
1898
   reg  [length:1] qi;
1899
   reg lfsr_fb;
1900
   wire [length:1] q_next;
1901
   reg [32:1] polynom;
1902
   integer i;
1903
   always @ (qi)
1904
   begin
1905
        case (length)
1906
         2: polynom = 32'b11;                               // 0x3
1907
         3: polynom = 32'b110;                              // 0x6
1908
         4: polynom = 32'b1100;                             // 0xC
1909
         5: polynom = 32'b10100;                            // 0x14
1910
         6: polynom = 32'b110000;                           // 0x30
1911
         7: polynom = 32'b1100000;                          // 0x60
1912
         8: polynom = 32'b10111000;                         // 0xb8
1913
         9: polynom = 32'b100010000;                        // 0x110
1914
        10: polynom = 32'b1001000000;                       // 0x240
1915
        11: polynom = 32'b10100000000;                      // 0x500
1916
        12: polynom = 32'b100000101001;                     // 0x829
1917
        13: polynom = 32'b1000000001100;                    // 0x100C
1918
        14: polynom = 32'b10000000010101;                   // 0x2015
1919
        15: polynom = 32'b110000000000000;                  // 0x6000
1920
        16: polynom = 32'b1101000000001000;                 // 0xD008
1921
        17: polynom = 32'b10010000000000000;                // 0x12000
1922
        18: polynom = 32'b100000010000000000;               // 0x20400
1923
        19: polynom = 32'b1000000000000100011;              // 0x40023
1924
        20: polynom = 32'b10010000000000000000;             // 0x90000
1925
        21: polynom = 32'b101000000000000000000;            // 0x140000
1926
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1927
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1928
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1929
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1930
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1931
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1932
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1933
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1934
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1935
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1936
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1937
        default: polynom = 32'b0;
1938
        endcase
1939
        lfsr_fb = qi[length];
1940
        for (i=length-1; i>=1; i=i-1) begin
1941
            if (polynom[i])
1942
                lfsr_fb = lfsr_fb  ~^ qi[i];
1943
        end
1944
    end
1945
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1946
   always @ (posedge clk or posedge rst)
1947
     if (rst)
1948
       qi <= {length{1'b0}};
1949
     else
1950
     if (cke)
1951
       qi <= q_next;
1952
   assign q = qi;
1953
endmodule
1954
//////////////////////////////////////////////////////////////////////
1955
////                                                              ////
1956
////  Versatile counter                                           ////
1957
////                                                              ////
1958
////  Description                                                 ////
1959
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1960
////  counter                                                     ////
1961
////                                                              ////
1962
////  To Do:                                                      ////
1963
////   - add LFSR with more taps                                  ////
1964
////                                                              ////
1965
////  Author(s):                                                  ////
1966
////      - Michael Unneback, unneback@opencores.org              ////
1967
////        ORSoC AB                                              ////
1968
////                                                              ////
1969
//////////////////////////////////////////////////////////////////////
1970
////                                                              ////
1971
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1972
////                                                              ////
1973
//// This source file may be used and distributed without         ////
1974
//// restriction provided that this copyright statement is not    ////
1975
//// removed from the file and that any derivative work contains  ////
1976
//// the original copyright notice and the associated disclaimer. ////
1977
////                                                              ////
1978
//// This source file is free software; you can redistribute it   ////
1979
//// and/or modify it under the terms of the GNU Lesser General   ////
1980
//// Public License as published by the Free Software Foundation; ////
1981
//// either version 2.1 of the License, or (at your option) any   ////
1982
//// later version.                                               ////
1983
////                                                              ////
1984
//// This source is distributed in the hope that it will be       ////
1985
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1986
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1987
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1988
//// details.                                                     ////
1989
////                                                              ////
1990
//// You should have received a copy of the GNU Lesser General    ////
1991
//// Public License along with this source; if not, download it   ////
1992
//// from http://www.opencores.org/lgpl.shtml                     ////
1993
////                                                              ////
1994
//////////////////////////////////////////////////////////////////////
1995
// LFSR counter
1996
module vl_cnt_lfsr_ce_clear_q (
1997
 clear, cke, q, rst, clk);
1998
   parameter length = 4;
1999
   input clear;
2000
   input cke;
2001
   output [length:1] q;
2002
   input rst;
2003
   input clk;
2004
   parameter clear_value = 0;
2005
   parameter set_value = 1;
2006
   parameter wrap_value = 8;
2007
   parameter level1_value = 15;
2008
   reg  [length:1] qi;
2009
   reg lfsr_fb;
2010
   wire [length:1] q_next;
2011
   reg [32:1] polynom;
2012
   integer i;
2013
   always @ (qi)
2014
   begin
2015
        case (length)
2016
         2: polynom = 32'b11;                               // 0x3
2017
         3: polynom = 32'b110;                              // 0x6
2018
         4: polynom = 32'b1100;                             // 0xC
2019
         5: polynom = 32'b10100;                            // 0x14
2020
         6: polynom = 32'b110000;                           // 0x30
2021
         7: polynom = 32'b1100000;                          // 0x60
2022
         8: polynom = 32'b10111000;                         // 0xb8
2023
         9: polynom = 32'b100010000;                        // 0x110
2024
        10: polynom = 32'b1001000000;                       // 0x240
2025
        11: polynom = 32'b10100000000;                      // 0x500
2026
        12: polynom = 32'b100000101001;                     // 0x829
2027
        13: polynom = 32'b1000000001100;                    // 0x100C
2028
        14: polynom = 32'b10000000010101;                   // 0x2015
2029
        15: polynom = 32'b110000000000000;                  // 0x6000
2030
        16: polynom = 32'b1101000000001000;                 // 0xD008
2031
        17: polynom = 32'b10010000000000000;                // 0x12000
2032
        18: polynom = 32'b100000010000000000;               // 0x20400
2033
        19: polynom = 32'b1000000000000100011;              // 0x40023
2034
        20: polynom = 32'b10010000000000000000;             // 0x90000
2035
        21: polynom = 32'b101000000000000000000;            // 0x140000
2036
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2037
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2038
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2039
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2040
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2041
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2042
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2043
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2044
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2045
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2046
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2047
        default: polynom = 32'b0;
2048
        endcase
2049
        lfsr_fb = qi[length];
2050
        for (i=length-1; i>=1; i=i-1) begin
2051
            if (polynom[i])
2052
                lfsr_fb = lfsr_fb  ~^ qi[i];
2053
        end
2054
    end
2055
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2056
   always @ (posedge clk or posedge rst)
2057
     if (rst)
2058
       qi <= {length{1'b0}};
2059
     else
2060
     if (cke)
2061
       qi <= q_next;
2062
   assign q = qi;
2063
endmodule
2064
//////////////////////////////////////////////////////////////////////
2065
////                                                              ////
2066
////  Versatile counter                                           ////
2067
////                                                              ////
2068
////  Description                                                 ////
2069
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2070
////  counter                                                     ////
2071
////                                                              ////
2072
////  To Do:                                                      ////
2073
////   - add LFSR with more taps                                  ////
2074
////                                                              ////
2075
////  Author(s):                                                  ////
2076
////      - Michael Unneback, unneback@opencores.org              ////
2077
////        ORSoC AB                                              ////
2078
////                                                              ////
2079
//////////////////////////////////////////////////////////////////////
2080
////                                                              ////
2081
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2082
////                                                              ////
2083
//// This source file may be used and distributed without         ////
2084
//// restriction provided that this copyright statement is not    ////
2085
//// removed from the file and that any derivative work contains  ////
2086
//// the original copyright notice and the associated disclaimer. ////
2087
////                                                              ////
2088
//// This source file is free software; you can redistribute it   ////
2089
//// and/or modify it under the terms of the GNU Lesser General   ////
2090
//// Public License as published by the Free Software Foundation; ////
2091
//// either version 2.1 of the License, or (at your option) any   ////
2092
//// later version.                                               ////
2093
////                                                              ////
2094
//// This source is distributed in the hope that it will be       ////
2095
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2096
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2097
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2098
//// details.                                                     ////
2099
////                                                              ////
2100
//// You should have received a copy of the GNU Lesser General    ////
2101
//// Public License along with this source; if not, download it   ////
2102
//// from http://www.opencores.org/lgpl.shtml                     ////
2103
////                                                              ////
2104
//////////////////////////////////////////////////////////////////////
2105
// LFSR counter
2106
module vl_cnt_lfsr_ce_q_zq (
2107
 cke, q, zq, rst, clk);
2108
   parameter length = 4;
2109
   input cke;
2110
   output [length:1] q;
2111
   output reg zq;
2112
   input rst;
2113
   input clk;
2114
   parameter clear_value = 0;
2115
   parameter set_value = 1;
2116
   parameter wrap_value = 8;
2117
   parameter level1_value = 15;
2118
   reg  [length:1] qi;
2119
   reg lfsr_fb;
2120
   wire [length:1] q_next;
2121
   reg [32:1] polynom;
2122
   integer i;
2123
   always @ (qi)
2124
   begin
2125
        case (length)
2126
         2: polynom = 32'b11;                               // 0x3
2127
         3: polynom = 32'b110;                              // 0x6
2128
         4: polynom = 32'b1100;                             // 0xC
2129
         5: polynom = 32'b10100;                            // 0x14
2130
         6: polynom = 32'b110000;                           // 0x30
2131
         7: polynom = 32'b1100000;                          // 0x60
2132
         8: polynom = 32'b10111000;                         // 0xb8
2133
         9: polynom = 32'b100010000;                        // 0x110
2134
        10: polynom = 32'b1001000000;                       // 0x240
2135
        11: polynom = 32'b10100000000;                      // 0x500
2136
        12: polynom = 32'b100000101001;                     // 0x829
2137
        13: polynom = 32'b1000000001100;                    // 0x100C
2138
        14: polynom = 32'b10000000010101;                   // 0x2015
2139
        15: polynom = 32'b110000000000000;                  // 0x6000
2140
        16: polynom = 32'b1101000000001000;                 // 0xD008
2141
        17: polynom = 32'b10010000000000000;                // 0x12000
2142
        18: polynom = 32'b100000010000000000;               // 0x20400
2143
        19: polynom = 32'b1000000000000100011;              // 0x40023
2144
        20: polynom = 32'b10010000000000000000;             // 0x90000
2145
        21: polynom = 32'b101000000000000000000;            // 0x140000
2146
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2147
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2148
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2149
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2150
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2151
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2152
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2153
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2154
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2155
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2156
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2157
        default: polynom = 32'b0;
2158
        endcase
2159
        lfsr_fb = qi[length];
2160
        for (i=length-1; i>=1; i=i-1) begin
2161
            if (polynom[i])
2162
                lfsr_fb = lfsr_fb  ~^ qi[i];
2163
        end
2164
    end
2165
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2166
   always @ (posedge clk or posedge rst)
2167
     if (rst)
2168
       qi <= {length{1'b0}};
2169
     else
2170
     if (cke)
2171
       qi <= q_next;
2172
   assign q = qi;
2173
   always @ (posedge clk or posedge rst)
2174
     if (rst)
2175
       zq <= 1'b1;
2176
     else
2177
     if (cke)
2178
       zq <= q_next == {length{1'b0}};
2179
endmodule
2180
//////////////////////////////////////////////////////////////////////
2181
////                                                              ////
2182
////  Versatile counter                                           ////
2183
////                                                              ////
2184
////  Description                                                 ////
2185
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2186
////  counter                                                     ////
2187
////                                                              ////
2188
////  To Do:                                                      ////
2189
////   - add LFSR with more taps                                  ////
2190
////                                                              ////
2191
////  Author(s):                                                  ////
2192
////      - Michael Unneback, unneback@opencores.org              ////
2193
////        ORSoC AB                                              ////
2194
////                                                              ////
2195
//////////////////////////////////////////////////////////////////////
2196
////                                                              ////
2197
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2198
////                                                              ////
2199
//// This source file may be used and distributed without         ////
2200
//// restriction provided that this copyright statement is not    ////
2201
//// removed from the file and that any derivative work contains  ////
2202
//// the original copyright notice and the associated disclaimer. ////
2203
////                                                              ////
2204
//// This source file is free software; you can redistribute it   ////
2205
//// and/or modify it under the terms of the GNU Lesser General   ////
2206
//// Public License as published by the Free Software Foundation; ////
2207
//// either version 2.1 of the License, or (at your option) any   ////
2208
//// later version.                                               ////
2209
////                                                              ////
2210
//// This source is distributed in the hope that it will be       ////
2211
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2212
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2213
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2214
//// details.                                                     ////
2215
////                                                              ////
2216
//// You should have received a copy of the GNU Lesser General    ////
2217
//// Public License along with this source; if not, download it   ////
2218
//// from http://www.opencores.org/lgpl.shtml                     ////
2219
////                                                              ////
2220
//////////////////////////////////////////////////////////////////////
2221
// LFSR counter
2222
module vl_cnt_lfsr_ce_rew_l1 (
2223
 cke, rew, level1, rst, clk);
2224
   parameter length = 4;
2225
   input cke;
2226
   input rew;
2227
   output reg level1;
2228
   input rst;
2229
   input clk;
2230
   parameter clear_value = 0;
2231
   parameter set_value = 1;
2232
   parameter wrap_value = 8;
2233
   parameter level1_value = 15;
2234
   wire clear;
2235
   assign clear = 1'b0;
2236
   reg  [length:1] qi;
2237
   reg lfsr_fb, lfsr_fb_rew;
2238
   wire  [length:1] q_next, q_next_fw, q_next_rew;
2239
   reg [32:1] polynom_rew;
2240
   integer j;
2241
   reg [32:1] polynom;
2242
   integer i;
2243
   always @ (qi)
2244
   begin
2245
        case (length)
2246
         2: polynom = 32'b11;                               // 0x3
2247
         3: polynom = 32'b110;                              // 0x6
2248
         4: polynom = 32'b1100;                             // 0xC
2249
         5: polynom = 32'b10100;                            // 0x14
2250
         6: polynom = 32'b110000;                           // 0x30
2251
         7: polynom = 32'b1100000;                          // 0x60
2252
         8: polynom = 32'b10111000;                         // 0xb8
2253
         9: polynom = 32'b100010000;                        // 0x110
2254
        10: polynom = 32'b1001000000;                       // 0x240
2255
        11: polynom = 32'b10100000000;                      // 0x500
2256
        12: polynom = 32'b100000101001;                     // 0x829
2257
        13: polynom = 32'b1000000001100;                    // 0x100C
2258
        14: polynom = 32'b10000000010101;                   // 0x2015
2259
        15: polynom = 32'b110000000000000;                  // 0x6000
2260
        16: polynom = 32'b1101000000001000;                 // 0xD008
2261
        17: polynom = 32'b10010000000000000;                // 0x12000
2262
        18: polynom = 32'b100000010000000000;               // 0x20400
2263
        19: polynom = 32'b1000000000000100011;              // 0x40023
2264
        20: polynom = 32'b10010000000000000000;             // 0x90000
2265
        21: polynom = 32'b101000000000000000000;            // 0x140000
2266
        22: polynom = 32'b1100000000000000000000;           // 0x300000
2267
        23: polynom = 32'b10000100000000000000000;          // 0x420000
2268
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
2269
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
2270
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
2271
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
2272
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
2273
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
2274
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
2275
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
2276
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
2277
        default: polynom = 32'b0;
2278
        endcase
2279
        lfsr_fb = qi[length];
2280
        for (i=length-1; i>=1; i=i-1) begin
2281
            if (polynom[i])
2282
                lfsr_fb = lfsr_fb  ~^ qi[i];
2283
        end
2284
    end
2285
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
2286
   always @ (qi)
2287
   begin
2288
        case (length)
2289
         2: polynom_rew = 32'b11;
2290
         3: polynom_rew = 32'b110;
2291
         4: polynom_rew = 32'b1100;
2292
         5: polynom_rew = 32'b10100;
2293
         6: polynom_rew = 32'b110000;
2294
         7: polynom_rew = 32'b1100000;
2295
         8: polynom_rew = 32'b10111000;
2296
         9: polynom_rew = 32'b100010000;
2297
        10: polynom_rew = 32'b1001000000;
2298
        11: polynom_rew = 32'b10100000000;
2299
        12: polynom_rew = 32'b100000101001;
2300
        13: polynom_rew = 32'b1000000001100;
2301
        14: polynom_rew = 32'b10000000010101;
2302
        15: polynom_rew = 32'b110000000000000;
2303
        16: polynom_rew = 32'b1101000000001000;
2304
        17: polynom_rew = 32'b10010000000000000;
2305
        18: polynom_rew = 32'b100000010000000000;
2306
        19: polynom_rew = 32'b1000000000000100011;
2307
        20: polynom_rew = 32'b10000010000000000000;
2308
        21: polynom_rew = 32'b101000000000000000000;
2309
        22: polynom_rew = 32'b1100000000000000000000;
2310
        23: polynom_rew = 32'b10000100000000000000000;
2311
        24: polynom_rew = 32'b111000010000000000000000;
2312
        25: polynom_rew = 32'b1001000000000000000000000;
2313
        26: polynom_rew = 32'b10000000000000000000100011;
2314
        27: polynom_rew = 32'b100000000000000000000010011;
2315
        28: polynom_rew = 32'b1100100000000000000000000000;
2316
        29: polynom_rew = 32'b10100000000000000000000000000;
2317
        30: polynom_rew = 32'b100000000000000000000000101001;
2318
        31: polynom_rew = 32'b1001000000000000000000000000000;
2319
        32: polynom_rew = 32'b10000000001000000000000000000011;
2320
        default: polynom_rew = 32'b0;
2321
        endcase
2322
        // rotate left
2323
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
2324
        lfsr_fb_rew = qi[length];
2325
        for (i=length-1; i>=1; i=i-1) begin
2326
            if (polynom_rew[i])
2327
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
2328
        end
2329
    end
2330
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
2331
   assign q_next = rew ? q_next_rew : q_next_fw;
2332
   always @ (posedge clk or posedge rst)
2333
     if (rst)
2334
       qi <= {length{1'b0}};
2335
     else
2336
     if (cke)
2337
       qi <= q_next;
2338
    always @ (posedge clk or posedge rst)
2339
    if (rst)
2340
        level1 <= 1'b0;
2341
    else
2342
    if (cke)
2343
    if (clear)
2344
        level1 <= 1'b0;
2345
    else if (q_next == level1_value)
2346
        level1 <= 1'b1;
2347
    else if (qi == level1_value & rew)
2348
        level1 <= 1'b0;
2349
endmodule
2350
//////////////////////////////////////////////////////////////////////
2351
////                                                              ////
2352
////  Versatile counter                                           ////
2353
////                                                              ////
2354
////  Description                                                 ////
2355
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2356
////  counter                                                     ////
2357
////                                                              ////
2358
////  To Do:                                                      ////
2359
////   - add LFSR with more taps                                  ////
2360
////                                                              ////
2361
////  Author(s):                                                  ////
2362
////      - Michael Unneback, unneback@opencores.org              ////
2363
////        ORSoC AB                                              ////
2364
////                                                              ////
2365
//////////////////////////////////////////////////////////////////////
2366
////                                                              ////
2367
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2368
////                                                              ////
2369
//// This source file may be used and distributed without         ////
2370
//// restriction provided that this copyright statement is not    ////
2371
//// removed from the file and that any derivative work contains  ////
2372
//// the original copyright notice and the associated disclaimer. ////
2373
////                                                              ////
2374
//// This source file is free software; you can redistribute it   ////
2375
//// and/or modify it under the terms of the GNU Lesser General   ////
2376
//// Public License as published by the Free Software Foundation; ////
2377
//// either version 2.1 of the License, or (at your option) any   ////
2378
//// later version.                                               ////
2379
////                                                              ////
2380
//// This source is distributed in the hope that it will be       ////
2381
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2382
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2383
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2384
//// details.                                                     ////
2385
////                                                              ////
2386
//// You should have received a copy of the GNU Lesser General    ////
2387
//// Public License along with this source; if not, download it   ////
2388
//// from http://www.opencores.org/lgpl.shtml                     ////
2389
////                                                              ////
2390
//////////////////////////////////////////////////////////////////////
2391 6 unneback
// GRAY counter
2392 139 unneback
module vl_cnt_gray (
2393
 q, rst, clk);
2394
   parameter length = 4;
2395
   output reg [length:1] q;
2396
   input rst;
2397
   input clk;
2398
   parameter clear_value = 0;
2399
   parameter set_value = 1;
2400
   parameter wrap_value = 8;
2401
   parameter level1_value = 15;
2402
   reg  [length:1] qi;
2403
   wire [length:1] q_next;
2404
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2405
   always @ (posedge clk or posedge rst)
2406
     if (rst)
2407
       qi <= {length{1'b0}};
2408
     else
2409
       qi <= q_next;
2410
   always @ (posedge clk or posedge rst)
2411
     if (rst)
2412
       q <= {length{1'b0}};
2413
     else
2414
         q <= (q_next>>1) ^ q_next;
2415
endmodule
2416
//////////////////////////////////////////////////////////////////////
2417
////                                                              ////
2418
////  Versatile counter                                           ////
2419
////                                                              ////
2420
////  Description                                                 ////
2421
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2422
////  counter                                                     ////
2423
////                                                              ////
2424
////  To Do:                                                      ////
2425
////   - add LFSR with more taps                                  ////
2426
////                                                              ////
2427
////  Author(s):                                                  ////
2428
////      - Michael Unneback, unneback@opencores.org              ////
2429
////        ORSoC AB                                              ////
2430
////                                                              ////
2431
//////////////////////////////////////////////////////////////////////
2432
////                                                              ////
2433
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2434
////                                                              ////
2435
//// This source file may be used and distributed without         ////
2436
//// restriction provided that this copyright statement is not    ////
2437
//// removed from the file and that any derivative work contains  ////
2438
//// the original copyright notice and the associated disclaimer. ////
2439
////                                                              ////
2440
//// This source file is free software; you can redistribute it   ////
2441
//// and/or modify it under the terms of the GNU Lesser General   ////
2442
//// Public License as published by the Free Software Foundation; ////
2443
//// either version 2.1 of the License, or (at your option) any   ////
2444
//// later version.                                               ////
2445
////                                                              ////
2446
//// This source is distributed in the hope that it will be       ////
2447
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2448
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2449
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2450
//// details.                                                     ////
2451
////                                                              ////
2452
//// You should have received a copy of the GNU Lesser General    ////
2453
//// Public License along with this source; if not, download it   ////
2454
//// from http://www.opencores.org/lgpl.shtml                     ////
2455
////                                                              ////
2456
//////////////////////////////////////////////////////////////////////
2457
// GRAY counter
2458
module vl_cnt_gray_ce (
2459
 cke, q, rst, clk);
2460
   parameter length = 4;
2461
   input cke;
2462
   output reg [length:1] q;
2463
   input rst;
2464
   input clk;
2465
   parameter clear_value = 0;
2466
   parameter set_value = 1;
2467
   parameter wrap_value = 8;
2468
   parameter level1_value = 15;
2469
   reg  [length:1] qi;
2470
   wire [length:1] q_next;
2471
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2472
   always @ (posedge clk or posedge rst)
2473
     if (rst)
2474
       qi <= {length{1'b0}};
2475
     else
2476
     if (cke)
2477
       qi <= q_next;
2478
   always @ (posedge clk or posedge rst)
2479
     if (rst)
2480
       q <= {length{1'b0}};
2481
     else
2482
       if (cke)
2483
         q <= (q_next>>1) ^ q_next;
2484
endmodule
2485
//////////////////////////////////////////////////////////////////////
2486
////                                                              ////
2487
////  Versatile counter                                           ////
2488
////                                                              ////
2489
////  Description                                                 ////
2490
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2491
////  counter                                                     ////
2492
////                                                              ////
2493
////  To Do:                                                      ////
2494
////   - add LFSR with more taps                                  ////
2495
////                                                              ////
2496
////  Author(s):                                                  ////
2497
////      - Michael Unneback, unneback@opencores.org              ////
2498
////        ORSoC AB                                              ////
2499
////                                                              ////
2500
//////////////////////////////////////////////////////////////////////
2501
////                                                              ////
2502
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2503
////                                                              ////
2504
//// This source file may be used and distributed without         ////
2505
//// restriction provided that this copyright statement is not    ////
2506
//// removed from the file and that any derivative work contains  ////
2507
//// the original copyright notice and the associated disclaimer. ////
2508
////                                                              ////
2509
//// This source file is free software; you can redistribute it   ////
2510
//// and/or modify it under the terms of the GNU Lesser General   ////
2511
//// Public License as published by the Free Software Foundation; ////
2512
//// either version 2.1 of the License, or (at your option) any   ////
2513
//// later version.                                               ////
2514
////                                                              ////
2515
//// This source is distributed in the hope that it will be       ////
2516
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2517
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2518
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2519
//// details.                                                     ////
2520
////                                                              ////
2521
//// You should have received a copy of the GNU Lesser General    ////
2522
//// Public License along with this source; if not, download it   ////
2523
//// from http://www.opencores.org/lgpl.shtml                     ////
2524
////                                                              ////
2525
//////////////////////////////////////////////////////////////////////
2526
// GRAY counter
2527 40 unneback
module vl_cnt_gray_ce_bin (
2528
 cke, q, q_bin, rst, clk);
2529 6 unneback
   parameter length = 4;
2530
   input cke;
2531
   output reg [length:1] q;
2532
   output [length:1] q_bin;
2533
   input rst;
2534
   input clk;
2535
   parameter clear_value = 0;
2536
   parameter set_value = 1;
2537
   parameter wrap_value = 8;
2538
   parameter level1_value = 15;
2539
   reg  [length:1] qi;
2540
   wire [length:1] q_next;
2541
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2542
   always @ (posedge clk or posedge rst)
2543
     if (rst)
2544
       qi <= {length{1'b0}};
2545
     else
2546
     if (cke)
2547
       qi <= q_next;
2548
   always @ (posedge clk or posedge rst)
2549
     if (rst)
2550
       q <= {length{1'b0}};
2551
     else
2552
       if (cke)
2553
         q <= (q_next>>1) ^ q_next;
2554
   assign q_bin = qi;
2555
endmodule
2556
//////////////////////////////////////////////////////////////////////
2557
////                                                              ////
2558
////  Versatile library, counters                                 ////
2559
////                                                              ////
2560
////  Description                                                 ////
2561
////  counters                                                    ////
2562
////                                                              ////
2563
////                                                              ////
2564
////  To Do:                                                      ////
2565
////   - add more counters                                        ////
2566
////                                                              ////
2567
////  Author(s):                                                  ////
2568
////      - Michael Unneback, unneback@opencores.org              ////
2569
////        ORSoC AB                                              ////
2570
////                                                              ////
2571
//////////////////////////////////////////////////////////////////////
2572
////                                                              ////
2573
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2574
////                                                              ////
2575
//// This source file may be used and distributed without         ////
2576
//// restriction provided that this copyright statement is not    ////
2577
//// removed from the file and that any derivative work contains  ////
2578
//// the original copyright notice and the associated disclaimer. ////
2579
////                                                              ////
2580
//// This source file is free software; you can redistribute it   ////
2581
//// and/or modify it under the terms of the GNU Lesser General   ////
2582
//// Public License as published by the Free Software Foundation; ////
2583
//// either version 2.1 of the License, or (at your option) any   ////
2584
//// later version.                                               ////
2585
////                                                              ////
2586
//// This source is distributed in the hope that it will be       ////
2587
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2588
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2589
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2590
//// details.                                                     ////
2591
////                                                              ////
2592
//// You should have received a copy of the GNU Lesser General    ////
2593
//// Public License along with this source; if not, download it   ////
2594
//// from http://www.opencores.org/lgpl.shtml                     ////
2595
////                                                              ////
2596
//////////////////////////////////////////////////////////////////////
2597 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
2598 6 unneback
   parameter length = 4;
2599
   output reg [0:length-1] q;
2600
   input rst;
2601
   input clk;
2602
    always @ (posedge clk or posedge rst)
2603
    if (rst)
2604
        q <= {1'b1,{length-1{1'b0}}};
2605
    else
2606
        q <= {q[length-1],q[0:length-2]};
2607
endmodule
2608 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
2609 6 unneback
   parameter length = 4;
2610
   input cke;
2611
   output reg [0:length-1] q;
2612
   input rst;
2613
   input clk;
2614
    always @ (posedge clk or posedge rst)
2615
    if (rst)
2616
        q <= {1'b1,{length-1{1'b0}}};
2617
    else
2618
        if (cke)
2619
            q <= {q[length-1],q[0:length-2]};
2620
endmodule
2621 105 unneback
module vl_cnt_shreg_clear ( clear, q, rst, clk);
2622
   parameter length = 4;
2623
   input clear;
2624
   output reg [0:length-1] q;
2625
   input rst;
2626
   input clk;
2627
    always @ (posedge clk or posedge rst)
2628
    if (rst)
2629
        q <= {1'b1,{length-1{1'b0}}};
2630
    else
2631
        if (clear)
2632
            q <= {1'b1,{length-1{1'b0}}};
2633
        else
2634
            q <= q >> 1;
2635
endmodule
2636 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
2637 6 unneback
   parameter length = 4;
2638
   input cke, clear;
2639
   output reg [0:length-1] q;
2640
   input rst;
2641
   input clk;
2642
    always @ (posedge clk or posedge rst)
2643
    if (rst)
2644
        q <= {1'b1,{length-1{1'b0}}};
2645
    else
2646
        if (cke)
2647
            if (clear)
2648
                q <= {1'b1,{length-1{1'b0}}};
2649
            else
2650
                q <= q >> 1;
2651
endmodule
2652 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
2653 6 unneback
   parameter length = 4;
2654
   input cke, clear;
2655
   output reg [0:length-1] q;
2656
   input rst;
2657
   input clk;
2658
    always @ (posedge clk or posedge rst)
2659
    if (rst)
2660
        q <= {1'b1,{length-1{1'b0}}};
2661
    else
2662
        if (cke)
2663
            if (clear)
2664
                q <= {1'b1,{length-1{1'b0}}};
2665
            else
2666
            q <= {q[length-1],q[0:length-2]};
2667
endmodule
2668
//////////////////////////////////////////////////////////////////////
2669
////                                                              ////
2670
////  Versatile library, memories                                 ////
2671
////                                                              ////
2672
////  Description                                                 ////
2673
////  memories                                                    ////
2674
////                                                              ////
2675
////                                                              ////
2676
////  To Do:                                                      ////
2677
////   - add more memory types                                    ////
2678
////                                                              ////
2679
////  Author(s):                                                  ////
2680
////      - Michael Unneback, unneback@opencores.org              ////
2681
////        ORSoC AB                                              ////
2682
////                                                              ////
2683
//////////////////////////////////////////////////////////////////////
2684
////                                                              ////
2685
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2686
////                                                              ////
2687
//// This source file may be used and distributed without         ////
2688
//// restriction provided that this copyright statement is not    ////
2689
//// removed from the file and that any derivative work contains  ////
2690
//// the original copyright notice and the associated disclaimer. ////
2691
////                                                              ////
2692
//// This source file is free software; you can redistribute it   ////
2693
//// and/or modify it under the terms of the GNU Lesser General   ////
2694
//// Public License as published by the Free Software Foundation; ////
2695
//// either version 2.1 of the License, or (at your option) any   ////
2696
//// later version.                                               ////
2697
////                                                              ////
2698
//// This source is distributed in the hope that it will be       ////
2699
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2700
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2701
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2702
//// details.                                                     ////
2703
////                                                              ////
2704
//// You should have received a copy of the GNU Lesser General    ////
2705
//// Public License along with this source; if not, download it   ////
2706
//// from http://www.opencores.org/lgpl.shtml                     ////
2707
////                                                              ////
2708
//////////////////////////////////////////////////////////////////////
2709
/// ROM
2710 7 unneback
module vl_rom_init ( adr, q, clk);
2711
   parameter data_width = 32;
2712
   parameter addr_width = 8;
2713 75 unneback
   parameter mem_size = 1<<addr_width;
2714 7 unneback
   input [(addr_width-1):0]       adr;
2715
   output reg [(data_width-1):0] q;
2716
   input                         clk;
2717 75 unneback
   reg [data_width-1:0] rom [mem_size-1:0];
2718 7 unneback
   parameter memory_file = "vl_rom.vmem";
2719
   initial
2720
     begin
2721
        $readmemh(memory_file, rom);
2722
     end
2723
   always @ (posedge clk)
2724
     q <= rom[adr];
2725
endmodule
2726 6 unneback
// Single port RAM
2727
module vl_ram ( d, adr, we, q, clk);
2728
   parameter data_width = 32;
2729
   parameter addr_width = 8;
2730 75 unneback
   parameter mem_size = 1<<addr_width;
2731 100 unneback
   parameter debug = 0;
2732 6 unneback
   input [(data_width-1):0]      d;
2733
   input [(addr_width-1):0]       adr;
2734
   input                         we;
2735 7 unneback
   output reg [(data_width-1):0] q;
2736 6 unneback
   input                         clk;
2737 98 unneback
   reg [data_width-1:0] ram [mem_size-1:0];
2738 100 unneback
    parameter memory_init = 0;
2739
    parameter memory_file = "vl_ram.vmem";
2740
    generate
2741
    if (memory_init == 1) begin : init_mem
2742
        initial
2743
            $readmemh(memory_file, ram);
2744
   end else if (memory_init == 2) begin : init_zero
2745
        integer k;
2746
        initial
2747
            for (k = 0; k < mem_size; k = k + 1)
2748
                ram[k] = 0;
2749 7 unneback
   end
2750
   endgenerate
2751 100 unneback
    generate
2752
    if (debug==1) begin : debug_we
2753
        always @ (posedge clk)
2754
        if (we)
2755
            $display ("Value %h written at address %h : time %t", d, adr, $time);
2756
    end
2757
    endgenerate
2758 6 unneback
   always @ (posedge clk)
2759
   begin
2760
   if (we)
2761
     ram[adr] <= d;
2762
   q <= ram[adr];
2763
   end
2764
endmodule
2765 91 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
2766 7 unneback
   parameter data_width = 32;
2767 72 unneback
   parameter addr_width = 6;
2768 75 unneback
   parameter mem_size = 1<<addr_width;
2769 7 unneback
   input [(data_width-1):0]      d;
2770
   input [(addr_width-1):0]       adr;
2771 73 unneback
   input [(data_width/8)-1:0]    be;
2772 7 unneback
   input                         we;
2773
   output reg [(data_width-1):0] q;
2774
   input                         clk;
2775 65 unneback
`ifdef SYSTEMVERILOG
2776 95 unneback
    // use a multi-dimensional packed array
2777
    //t o model individual bytes within the word
2778
    logic [data_width/8-1:0][7:0] ram [0:mem_size-1];// # words = 1 << address width
2779 65 unneback
`else
2780 85 unneback
    reg [data_width-1:0] ram [mem_size-1:0];
2781
    wire [data_width/8-1:0] cke;
2782 65 unneback
`endif
2783 100 unneback
    parameter memory_init = 0;
2784
    parameter memory_file = "vl_ram.vmem";
2785
    generate
2786
    if (memory_init == 1) begin : init_mem
2787
        initial
2788
            $readmemh(memory_file, ram);
2789
    end else if (memory_init == 2) begin : init_zero
2790
        integer k;
2791
        initial
2792
            for (k = 0; k < mem_size; k = k + 1)
2793
                ram[k] = 0;
2794
    end
2795 7 unneback
   endgenerate
2796 60 unneback
`ifdef SYSTEMVERILOG
2797
always_ff@(posedge clk)
2798
begin
2799 95 unneback
    if(we) begin
2800 86 unneback
        if(be[3]) ram[adr][3] <= d[31:24];
2801
        if(be[2]) ram[adr][2] <= d[23:16];
2802
        if(be[1]) ram[adr][1] <= d[15:8];
2803
        if(be[0]) ram[adr][0] <= d[7:0];
2804 60 unneback
    end
2805 90 unneback
        q <= ram[adr];
2806 60 unneback
end
2807
`else
2808 85 unneback
assign cke = {data_width/8{we}} & be;
2809 7 unneback
   genvar i;
2810 85 unneback
   generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
2811 7 unneback
      always @ (posedge clk)
2812 85 unneback
      if (cke[i])
2813 7 unneback
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
2814
   end
2815
   endgenerate
2816
   always @ (posedge clk)
2817
      q <= ram[adr];
2818 60 unneback
`endif
2819 93 unneback
`ifdef verilator
2820 85 unneback
   // Function to access RAM (for use by Verilator).
2821
   function [31:0] get_mem;
2822
      // verilator public
2823 90 unneback
      input [addr_width-1:0]             addr;
2824 85 unneback
      get_mem = ram[addr];
2825
   endfunction // get_mem
2826
   // Function to write RAM (for use by Verilator).
2827
   function set_mem;
2828
      // verilator public
2829 90 unneback
      input [addr_width-1:0]             addr;
2830
      input [data_width-1:0]             data;
2831 85 unneback
      ram[addr] = data;
2832
   endfunction // set_mem
2833 93 unneback
`endif
2834 7 unneback
endmodule
2835
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
2836 6 unneback
   parameter data_width = 32;
2837
   parameter addr_width = 8;
2838 75 unneback
   parameter mem_size = 1<<addr_width;
2839 6 unneback
   input [(data_width-1):0]      d_a;
2840
   input [(addr_width-1):0]       adr_a;
2841
   input [(addr_width-1):0]       adr_b;
2842
   input                         we_a;
2843 118 unneback
   output reg [(data_width-1):0]          q_b;
2844 6 unneback
   input                         clk_a, clk_b;
2845 119 unneback
   reg [data_width-1:0] ram [0:mem_size-1] ;
2846 100 unneback
    parameter memory_init = 0;
2847
    parameter memory_file = "vl_ram.vmem";
2848
    parameter debug = 0;
2849
    generate
2850
    if (memory_init == 1) begin : init_mem
2851
        initial
2852
            $readmemh(memory_file, ram);
2853
    end else if (memory_init == 2) begin : init_zero
2854
        integer k;
2855
        initial
2856
            for (k = 0; k < mem_size; k = k + 1)
2857
                ram[k] = 0;
2858
    end
2859 7 unneback
   endgenerate
2860 100 unneback
    generate
2861
    if (debug==1) begin : debug_we
2862
        always @ (posedge clk_a)
2863
        if (we_a)
2864
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
2865
    end
2866
    endgenerate
2867 6 unneback
   always @ (posedge clk_a)
2868
   if (we_a)
2869
     ram[adr_a] <= d_a;
2870
   always @ (posedge clk_b)
2871 118 unneback
      q_b = ram[adr_b];
2872 6 unneback
endmodule
2873 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
2874 6 unneback
   parameter data_width = 32;
2875
   parameter addr_width = 8;
2876 75 unneback
   parameter mem_size = 1<<addr_width;
2877 6 unneback
   input [(data_width-1):0]      d_a;
2878
   input [(addr_width-1):0]       adr_a;
2879
   input [(addr_width-1):0]       adr_b;
2880
   input                         we_a;
2881
   output [(data_width-1):0]      q_b;
2882
   output reg [(data_width-1):0] q_a;
2883
   input                         clk_a, clk_b;
2884
   reg [(data_width-1):0]         q_b;
2885 119 unneback
   reg [data_width-1:0] ram [0:mem_size-1] ;
2886 100 unneback
    parameter memory_init = 0;
2887
    parameter memory_file = "vl_ram.vmem";
2888
    parameter debug = 0;
2889
    generate
2890
    if (memory_init == 1) begin : init_mem
2891
        initial
2892
            $readmemh(memory_file, ram);
2893
    end else if (memory_init == 2) begin : init_zero
2894
        integer k;
2895
        initial
2896
            for (k = 0; k < mem_size; k = k + 1)
2897
                ram[k] = 0;
2898
    end
2899 7 unneback
   endgenerate
2900 100 unneback
    generate
2901
    if (debug==1) begin : debug_we
2902
        always @ (posedge clk_a)
2903
        if (we_a)
2904
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
2905
    end
2906
    endgenerate
2907 6 unneback
   always @ (posedge clk_a)
2908
     begin
2909
        q_a <= ram[adr_a];
2910
        if (we_a)
2911
             ram[adr_a] <= d_a;
2912
     end
2913
   always @ (posedge clk_b)
2914
          q_b <= ram[adr_b];
2915
endmodule
2916 100 unneback
module vl_dpram_1r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, adr_b, we_b, clk_b );
2917
   parameter data_width = 32;
2918
   parameter addr_width = 8;
2919
   parameter mem_size = 1<<addr_width;
2920
   input [(data_width-1):0]      d_a;
2921
   input [(addr_width-1):0]       adr_a;
2922
   input [(addr_width-1):0]       adr_b;
2923
   input                         we_a;
2924
   input [(data_width-1):0]       d_b;
2925
   output reg [(data_width-1):0] q_a;
2926
   input                         we_b;
2927
   input                         clk_a, clk_b;
2928
   reg [(data_width-1):0]         q_b;
2929 119 unneback
   reg [data_width-1:0] ram [0:mem_size-1] ;
2930 100 unneback
    parameter memory_init = 0;
2931
    parameter memory_file = "vl_ram.vmem";
2932
    parameter debug = 0;
2933
    generate
2934
    if (memory_init == 1) begin : init_mem
2935
        initial
2936
            $readmemh(memory_file, ram);
2937
    end else if (memory_init == 2) begin : init_zero
2938
        integer k;
2939
        initial
2940
            for (k = 0; k < mem_size; k = k + 1)
2941
                ram[k] = 0;
2942
    end
2943
   endgenerate
2944
    generate
2945
    if (debug==1) begin : debug_we
2946
        always @ (posedge clk_a)
2947
        if (we_a)
2948
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
2949
        always @ (posedge clk_b)
2950
        if (we_b)
2951
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
2952
    end
2953
    endgenerate
2954
   always @ (posedge clk_a)
2955
     begin
2956
        q_a <= ram[adr_a];
2957
        if (we_a)
2958
             ram[adr_a] <= d_a;
2959
     end
2960
   always @ (posedge clk_b)
2961
     begin
2962
        if (we_b)
2963
          ram[adr_b] <= d_b;
2964
     end
2965
endmodule
2966 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
2967 6 unneback
   parameter data_width = 32;
2968
   parameter addr_width = 8;
2969 75 unneback
   parameter mem_size = 1<<addr_width;
2970 6 unneback
   input [(data_width-1):0]      d_a;
2971
   input [(addr_width-1):0]       adr_a;
2972
   input [(addr_width-1):0]       adr_b;
2973
   input                         we_a;
2974
   output [(data_width-1):0]      q_b;
2975
   input [(data_width-1):0]       d_b;
2976
   output reg [(data_width-1):0] q_a;
2977
   input                         we_b;
2978
   input                         clk_a, clk_b;
2979
   reg [(data_width-1):0]         q_b;
2980 119 unneback
   reg [data_width-1:0] ram [0:mem_size-1] ;
2981 100 unneback
    parameter memory_init = 0;
2982
    parameter memory_file = "vl_ram.vmem";
2983
    parameter debug = 0;
2984
    generate
2985
    if (memory_init) begin : init_mem
2986
        initial
2987
            $readmemh(memory_file, ram);
2988
    end else if (memory_init == 2) begin : init_zero
2989
        integer k;
2990
        initial
2991
            for (k = 0; k < mem_size; k = k + 1)
2992
                ram[k] = 0;
2993
    end
2994 7 unneback
   endgenerate
2995 100 unneback
    generate
2996
    if (debug==1) begin : debug_we
2997
        always @ (posedge clk_a)
2998
        if (we_a)
2999
            $display ("Debug: Value %h written at address %h : time %t", d_a, adr_a, $time);
3000
        always @ (posedge clk_b)
3001
        if (we_b)
3002
            $display ("Debug: Value %h written at address %h : time %t", d_b, adr_b, $time);
3003
    end
3004
    endgenerate
3005 6 unneback
   always @ (posedge clk_a)
3006
     begin
3007
        q_a <= ram[adr_a];
3008
        if (we_a)
3009
             ram[adr_a] <= d_a;
3010
     end
3011
   always @ (posedge clk_b)
3012
     begin
3013
        q_b <= ram[adr_b];
3014
        if (we_b)
3015
          ram[adr_b] <= d_b;
3016
     end
3017
endmodule
3018 92 unneback
module vl_dpram_be_2r2w ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
3019 75 unneback
   parameter a_data_width = 32;
3020
   parameter a_addr_width = 8;
3021 95 unneback
   parameter b_data_width = 64; //a_data_width;
3022 124 unneback
   //localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
3023
   localparam b_addr_width =
3024 125 unneback
        (a_data_width==b_data_width) ? a_addr_width :
3025
        (a_data_width==b_data_width*2) ? a_addr_width+1 :
3026
        (a_data_width==b_data_width*4) ? a_addr_width+2 :
3027
        (a_data_width==b_data_width*8) ? a_addr_width+3 :
3028
        (a_data_width==b_data_width*16) ? a_addr_width+4 :
3029
        (a_data_width==b_data_width*32) ? a_addr_width+5 :
3030
        (a_data_width==b_data_width/2) ? a_addr_width-1 :
3031
        (a_data_width==b_data_width/4) ? a_addr_width-2 :
3032
        (a_data_width==b_data_width/8) ? a_addr_width-3 :
3033
        (a_data_width==b_data_width/16) ? a_addr_width-4 :
3034
        (a_data_width==b_data_width/32) ? a_addr_width-5 : 0;
3035 95 unneback
   localparam ratio = (a_addr_width>b_addr_width) ? (a_addr_width/b_addr_width) : (b_addr_width/a_addr_width);
3036
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<b_addr_width) : (1<<a_addr_width);
3037 100 unneback
   parameter memory_init = 0;
3038 95 unneback
   parameter memory_file = "vl_ram.vmem";
3039 100 unneback
   parameter debug = 0;
3040 75 unneback
   input [(a_data_width-1):0]      d_a;
3041 91 unneback
   input [(a_addr_width-1):0]       adr_a;
3042
   input [(a_data_width/8-1):0]    be_a;
3043
   input                           we_a;
3044 75 unneback
   output reg [(a_data_width-1):0] q_a;
3045 91 unneback
   input [(b_data_width-1):0]       d_b;
3046
   input [(b_addr_width-1):0]       adr_b;
3047 92 unneback
   input [(b_data_width/8-1):0]    be_b;
3048
   input                           we_b;
3049
   output reg [(b_data_width-1):0]          q_b;
3050 91 unneback
   input                           clk_a, clk_b;
3051 100 unneback
    generate
3052
    if (debug==1) begin : debug_we
3053
        always @ (posedge clk_a)
3054
        if (we_a)
3055 141 unneback
            $display ("Debug: Value %h written on port A at address %h : time %t", d_a, adr_a, $time);
3056 100 unneback
        always @ (posedge clk_b)
3057
        if (we_b)
3058 141 unneback
            $display ("Debug: Value %h written on port B at address %h : time %t", d_b, adr_b, $time);
3059 100 unneback
    end
3060
    endgenerate
3061 91 unneback
`ifdef SYSTEMVERILOG
3062
// use a multi-dimensional packed array
3063
//to model individual bytes within the word
3064 75 unneback
generate
3065 91 unneback
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
3066 98 unneback
    logic [0:3][7:0] ram [0:mem_size-1] ;
3067 95 unneback
    initial
3068 100 unneback
        if (memory_init==1)
3069 95 unneback
            $readmemh(memory_file, ram);
3070 100 unneback
    integer k;
3071
    initial
3072
        if (memory_init==2)
3073
            for (k = 0; k < mem_size; k = k + 1)
3074
                ram[k] = 0;
3075 91 unneback
    always_ff@(posedge clk_a)
3076
    begin
3077
        if(we_a) begin
3078 100 unneback
            if(be_a[3]) ram[adr_a][0] <= d_a[31:24];
3079
            if(be_a[2]) ram[adr_a][1] <= d_a[23:16];
3080
            if(be_a[1]) ram[adr_a][2] <= d_a[15:8];
3081
            if(be_a[0]) ram[adr_a][3] <= d_a[7:0];
3082 91 unneback
        end
3083
    end
3084 92 unneback
    always@(posedge clk_a)
3085
        q_a = ram[adr_a];
3086 91 unneback
    always_ff@(posedge clk_b)
3087 92 unneback
    begin
3088
        if(we_b) begin
3089 100 unneback
            if(be_b[3]) ram[adr_b][0] <= d_b[31:24];
3090
            if(be_b[2]) ram[adr_b][1] <= d_b[23:16];
3091
            if(be_b[1]) ram[adr_b][2] <= d_b[15:8];
3092
            if(be_b[0]) ram[adr_b][3] <= d_b[7:0];
3093 92 unneback
        end
3094
    end
3095
    always@(posedge clk_b)
3096
        q_b = ram[adr_b];
3097 75 unneback
end
3098
endgenerate
3099 95 unneback
generate
3100
if (a_data_width==64 & b_data_width==64) begin : dpram_6464
3101 98 unneback
    logic [0:7][7:0] ram [0:mem_size-1] ;
3102 95 unneback
    initial
3103 100 unneback
        if (memory_init==1)
3104 95 unneback
            $readmemh(memory_file, ram);
3105 100 unneback
    integer k;
3106
    initial
3107
        if (memory_init==2)
3108
            for (k = 0; k < mem_size; k = k + 1)
3109
                ram[k] = 0;
3110 95 unneback
    always_ff@(posedge clk_a)
3111
    begin
3112
        if(we_a) begin
3113
            if(be_a[7]) ram[adr_a][7] <= d_a[63:56];
3114
            if(be_a[6]) ram[adr_a][6] <= d_a[55:48];
3115
            if(be_a[5]) ram[adr_a][5] <= d_a[47:40];
3116
            if(be_a[4]) ram[adr_a][4] <= d_a[39:32];
3117
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
3118
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
3119
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
3120
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
3121
        end
3122
    end
3123
    always@(posedge clk_a)
3124
        q_a = ram[adr_a];
3125
    always_ff@(posedge clk_b)
3126
    begin
3127
        if(we_b) begin
3128
            if(be_b[7]) ram[adr_b][7] <= d_b[63:56];
3129
            if(be_b[6]) ram[adr_b][6] <= d_b[55:48];
3130
            if(be_b[5]) ram[adr_b][5] <= d_b[47:40];
3131
            if(be_b[4]) ram[adr_b][4] <= d_b[39:32];
3132
            if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
3133
            if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
3134
            if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
3135
            if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
3136
        end
3137
    end
3138
    always@(posedge clk_b)
3139
        q_b = ram[adr_b];
3140
end
3141
endgenerate
3142
generate
3143
if (a_data_width==32 & b_data_width==16) begin : dpram_3216
3144
logic [31:0] temp;
3145 128 unneback
vl_dpram_be_2r2w # (.a_data_width(32), .b_data_width(32), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
3146
dpram3232 (
3147 95 unneback
    .d_a(d_a),
3148
    .q_a(q_a),
3149
    .adr_a(adr_a),
3150
    .be_a(be_a),
3151
    .we_a(we_a),
3152
    .clk_a(clk_a),
3153
    .d_b({d_b,d_b}),
3154
    .q_b(temp),
3155 128 unneback
    .adr_b(adr_b[b_addr_width-1:1]),
3156 137 unneback
    .be_b({be_b,be_b} & {{2{!adr_b[0]}},{2{adr_b[0]}}}),
3157 95 unneback
    .we_b(we_b),
3158
    .clk_b(clk_b)
3159
);
3160 100 unneback
always @ (adr_b[0] or temp)
3161 95 unneback
    if (adr_b[0])
3162
        q_b = temp[31:16];
3163
    else
3164
        q_b = temp[15:0];
3165
end
3166
endgenerate
3167
generate
3168
if (a_data_width==32 & b_data_width==64) begin : dpram_3264
3169
logic [63:0] temp;
3170 128 unneback
vl_dpram_be_2r2w # (.a_data_width(32), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .memory_init(memory_init), .memory_file(memory_file))
3171 95 unneback
dpram6464 (
3172
    .d_a({d_a,d_a}),
3173
    .q_a(temp),
3174
    .adr_a(adr_a[a_addr_width-1:1]),
3175
    .be_a({be_a,be_a} & {{4{adr_a[0]}},{4{!adr_a[0]}}}),
3176
    .we_a(we_a),
3177
    .clk_a(clk_a),
3178
    .d_b(d_b),
3179
    .q_b(q_b),
3180
    .adr_b(adr_b),
3181
    .be_b(be_b),
3182
    .we_b(we_b),
3183
    .clk_b(clk_b)
3184
);
3185 100 unneback
always @ (adr_a[0] or temp)
3186 95 unneback
    if (adr_a[0])
3187
        q_a = temp[63:32];
3188
    else
3189
        q_a = temp[31:0];
3190
end
3191
endgenerate
3192 91 unneback
`else
3193 92 unneback
    // This modules requires SystemVerilog
3194 98 unneback
    // at this point anyway
3195 91 unneback
`endif
3196 75 unneback
endmodule
3197 6 unneback
// FIFO
3198 25 unneback
module vl_fifo_1r1w_fill_level_sync (
3199
    d, wr, fifo_full,
3200
    q, rd, fifo_empty,
3201
    fill_level,
3202
    clk, rst
3203
    );
3204
parameter data_width = 18;
3205
parameter addr_width = 4;
3206
// write side
3207
input  [data_width-1:0] d;
3208
input                   wr;
3209
output                  fifo_full;
3210
// read side
3211
output [data_width-1:0] q;
3212
input                   rd;
3213
output                  fifo_empty;
3214
// common
3215
output [addr_width:0]   fill_level;
3216
input rst, clk;
3217
wire [addr_width:1] wadr, radr;
3218
vl_cnt_bin_ce
3219
    # ( .length(addr_width))
3220
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
3221
vl_cnt_bin_ce
3222
    # (.length(addr_width))
3223
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
3224
vl_dpram_1r1w
3225
    # (.data_width(data_width), .addr_width(addr_width))
3226
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
3227 31 unneback
vl_cnt_bin_ce_rew_q_zq_l1
3228 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
3229 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
3230
endmodule
3231 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
3232
// RAM is supposed to be larger than the two FIFOs
3233
// LFSR counters used adr pointers
3234
module vl_fifo_2r2w_sync_simplex (
3235
    // a side
3236
    a_d, a_wr, a_fifo_full,
3237
    a_q, a_rd, a_fifo_empty,
3238
    a_fill_level,
3239
    // b side
3240
    b_d, b_wr, b_fifo_full,
3241
    b_q, b_rd, b_fifo_empty,
3242
    b_fill_level,
3243
    // common
3244
    clk, rst
3245
    );
3246
parameter data_width = 8;
3247
parameter addr_width = 5;
3248
parameter fifo_full_level = (1<<addr_width)-1;
3249
// a side
3250
input  [data_width-1:0] a_d;
3251
input                   a_wr;
3252
output                  a_fifo_full;
3253
output [data_width-1:0] a_q;
3254
input                   a_rd;
3255
output                  a_fifo_empty;
3256
output [addr_width-1:0] a_fill_level;
3257
// b side
3258
input  [data_width-1:0] b_d;
3259
input                   b_wr;
3260
output                  b_fifo_full;
3261
output [data_width-1:0] b_q;
3262
input                   b_rd;
3263
output                  b_fifo_empty;
3264
output [addr_width-1:0] b_fill_level;
3265
input                   clk;
3266
input                   rst;
3267
// adr_gen
3268
wire [addr_width:1] a_wadr, a_radr;
3269
wire [addr_width:1] b_wadr, b_radr;
3270
// dpram
3271
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
3272
vl_cnt_lfsr_ce
3273
    # ( .length(addr_width))
3274
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
3275
vl_cnt_lfsr_ce
3276
    # (.length(addr_width))
3277
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
3278
vl_cnt_lfsr_ce
3279
    # ( .length(addr_width))
3280
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
3281
vl_cnt_lfsr_ce
3282
    # (.length(addr_width))
3283
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
3284
// mux read or write adr to DPRAM
3285
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
3286
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
3287
vl_dpram_2r2w
3288
    # (.data_width(data_width), .addr_width(addr_width+1))
3289
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
3290
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
3291
vl_cnt_bin_ce_rew_zq_l1
3292 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
3293 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
3294
vl_cnt_bin_ce_rew_zq_l1
3295 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
3296 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
3297
endmodule
3298 6 unneback
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
3299 11 unneback
   parameter addr_width = 4;
3300
   parameter N = addr_width-1;
3301 6 unneback
   parameter Q1 = 2'b00;
3302
   parameter Q2 = 2'b01;
3303
   parameter Q3 = 2'b11;
3304
   parameter Q4 = 2'b10;
3305
   parameter going_empty = 1'b0;
3306
   parameter going_full  = 1'b1;
3307
   input [N:0]  wptr, rptr;
3308 14 unneback
   output       fifo_empty;
3309 6 unneback
   output       fifo_full;
3310
   input        wclk, rclk, rst;
3311
   wire direction;
3312
   reg  direction_set, direction_clr;
3313
   wire async_empty, async_full;
3314
   wire fifo_full2;
3315 14 unneback
   wire fifo_empty2;
3316 6 unneback
   // direction_set
3317
   always @ (wptr[N:N-1] or rptr[N:N-1])
3318
     case ({wptr[N:N-1],rptr[N:N-1]})
3319
       {Q1,Q2} : direction_set <= 1'b1;
3320
       {Q2,Q3} : direction_set <= 1'b1;
3321
       {Q3,Q4} : direction_set <= 1'b1;
3322
       {Q4,Q1} : direction_set <= 1'b1;
3323
       default : direction_set <= 1'b0;
3324
     endcase
3325
   // direction_clear
3326
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
3327
     if (rst)
3328
       direction_clr <= 1'b1;
3329
     else
3330
       case ({wptr[N:N-1],rptr[N:N-1]})
3331
         {Q2,Q1} : direction_clr <= 1'b1;
3332
         {Q3,Q2} : direction_clr <= 1'b1;
3333
         {Q4,Q3} : direction_clr <= 1'b1;
3334
         {Q1,Q4} : direction_clr <= 1'b1;
3335
         default : direction_clr <= 1'b0;
3336
       endcase
3337 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
3338 6 unneback
   assign async_empty = (wptr == rptr) && (direction==going_empty);
3339
   assign async_full  = (wptr == rptr) && (direction==going_full);
3340 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
3341
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
3342 6 unneback
/*
3343
   always @ (posedge wclk or posedge rst or posedge async_full)
3344
     if (rst)
3345
       {fifo_full, fifo_full2} <= 2'b00;
3346
     else if (async_full)
3347
       {fifo_full, fifo_full2} <= 2'b11;
3348
     else
3349
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
3350
*/
3351 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
3352 6 unneback
     if (async_empty)
3353
       {fifo_empty, fifo_empty2} <= 2'b11;
3354
     else
3355 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
3356 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
3357
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
3358 27 unneback
endmodule // async_compb
3359 6 unneback
module vl_fifo_1r1w_async (
3360
    d, wr, fifo_full, wr_clk, wr_rst,
3361
    q, rd, fifo_empty, rd_clk, rd_rst
3362
    );
3363
parameter data_width = 18;
3364
parameter addr_width = 4;
3365
// write side
3366
input  [data_width-1:0] d;
3367
input                   wr;
3368
output                  fifo_full;
3369
input                   wr_clk;
3370
input                   wr_rst;
3371
// read side
3372
output [data_width-1:0] q;
3373
input                   rd;
3374
output                  fifo_empty;
3375
input                   rd_clk;
3376
input                   rd_rst;
3377
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
3378 18 unneback
vl_cnt_gray_ce_bin
3379 6 unneback
    # ( .length(addr_width))
3380
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
3381 18 unneback
vl_cnt_gray_ce_bin
3382 6 unneback
    # (.length(addr_width))
3383 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
3384 7 unneback
vl_dpram_1r1w
3385 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
3386
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
3387
vl_fifo_cmp_async
3388
    # (.addr_width(addr_width))
3389
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
3390
endmodule
3391 8 unneback
module vl_fifo_2r2w_async (
3392 6 unneback
    // a side
3393
    a_d, a_wr, a_fifo_full,
3394
    a_q, a_rd, a_fifo_empty,
3395
    a_clk, a_rst,
3396
    // b side
3397
    b_d, b_wr, b_fifo_full,
3398
    b_q, b_rd, b_fifo_empty,
3399
    b_clk, b_rst
3400
    );
3401
parameter data_width = 18;
3402
parameter addr_width = 4;
3403
// a side
3404
input  [data_width-1:0] a_d;
3405
input                   a_wr;
3406
output                  a_fifo_full;
3407
output [data_width-1:0] a_q;
3408
input                   a_rd;
3409
output                  a_fifo_empty;
3410
input                   a_clk;
3411
input                   a_rst;
3412
// b side
3413
input  [data_width-1:0] b_d;
3414
input                   b_wr;
3415
output                  b_fifo_full;
3416
output [data_width-1:0] b_q;
3417
input                   b_rd;
3418
output                  b_fifo_empty;
3419
input                   b_clk;
3420
input                   b_rst;
3421
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
3422
vl_fifo_1r1w_async_a (
3423
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
3424
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
3425
    );
3426
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
3427
vl_fifo_1r1w_async_b (
3428
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
3429
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
3430
    );
3431
endmodule
3432 8 unneback
module vl_fifo_2r2w_async_simplex (
3433 6 unneback
    // a side
3434
    a_d, a_wr, a_fifo_full,
3435
    a_q, a_rd, a_fifo_empty,
3436
    a_clk, a_rst,
3437
    // b side
3438
    b_d, b_wr, b_fifo_full,
3439
    b_q, b_rd, b_fifo_empty,
3440
    b_clk, b_rst
3441
    );
3442
parameter data_width = 18;
3443
parameter addr_width = 4;
3444
// a side
3445
input  [data_width-1:0] a_d;
3446
input                   a_wr;
3447
output                  a_fifo_full;
3448
output [data_width-1:0] a_q;
3449
input                   a_rd;
3450
output                  a_fifo_empty;
3451
input                   a_clk;
3452
input                   a_rst;
3453
// b side
3454
input  [data_width-1:0] b_d;
3455
input                   b_wr;
3456
output                  b_fifo_full;
3457
output [data_width-1:0] b_q;
3458
input                   b_rd;
3459
output                  b_fifo_empty;
3460
input                   b_clk;
3461
input                   b_rst;
3462
// adr_gen
3463
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
3464
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
3465
// dpram
3466
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
3467 18 unneback
vl_cnt_gray_ce_bin
3468 6 unneback
    # ( .length(addr_width))
3469
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
3470 18 unneback
vl_cnt_gray_ce_bin
3471 6 unneback
    # (.length(addr_width))
3472
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
3473 18 unneback
vl_cnt_gray_ce_bin
3474 6 unneback
    # ( .length(addr_width))
3475
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
3476 18 unneback
vl_cnt_gray_ce_bin
3477 6 unneback
    # (.length(addr_width))
3478
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
3479
// mux read or write adr to DPRAM
3480
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
3481
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
3482 11 unneback
vl_dpram_2r2w
3483 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
3484
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
3485
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
3486 11 unneback
vl_fifo_cmp_async
3487 6 unneback
    # (.addr_width(addr_width))
3488
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
3489 11 unneback
vl_fifo_cmp_async
3490 6 unneback
    # (.addr_width(addr_width))
3491
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
3492
endmodule
3493 48 unneback
module vl_reg_file (
3494 146 unneback
    a1, a2, a3, wd3, we3, rd1, rd2, clk, rst );
3495
parameter dw = 32;
3496
parameter aw = 5;
3497 143 unneback
parameter debug = 0;
3498 146 unneback
input [aw-1:0] a1, a2, a3;
3499
input [dw-1:0] wd3;
3500 48 unneback
input we3;
3501 146 unneback
output [dw-1:0] rd1, rd2;
3502 147 unneback
input clk, rst;
3503 146 unneback
wire [dw-1:0] rd1mem, rd2mem;
3504
reg [dw-1:0] wreg;
3505
reg sel1, sel2;
3506 143 unneback
generate
3507
if (debug==1) begin : debug_we
3508
    always @ (posedge clk)
3509 144 unneback
        if (we3)
3510 145 unneback
            $display ("Value %h written at register %h : time %t", wd3, a3, $time);
3511 143 unneback
end
3512
endgenerate
3513 48 unneback
vl_dpram_1r1w
3514 146 unneback
    # ( .data_width(dw), .addr_width(aw))
3515 48 unneback
    ram1 (
3516
        .d_a(wd3),
3517
        .adr_a(a3),
3518
        .we_a(we3),
3519
        .clk_a(clk),
3520 146 unneback
        .q_b(rd1mem),
3521 48 unneback
        .adr_b(a1),
3522
        .clk_b(clk) );
3523
vl_dpram_1r1w
3524 146 unneback
    # ( .data_width(dw), .addr_width(aw))
3525 48 unneback
    ram2 (
3526
        .d_a(wd3),
3527
        .adr_a(a3),
3528
        .we_a(we3),
3529
        .clk_a(clk),
3530 146 unneback
        .q_b(rd2mem),
3531 48 unneback
        .adr_b(a2),
3532
        .clk_b(clk) );
3533 146 unneback
always @ (posedge clk or posedge rst)
3534
if (rst)
3535 148 unneback
    {sel1, sel2, wreg} <= {1'b0,1'b0,{dw{1'b0}}};
3536 146 unneback
else
3537
    {sel1,sel2,wreg} <= {we3 & a1==a3, we3 & a2==a3,wd3};
3538
assign rd1 = (sel1) ? wreg : rd1mem;
3539
assign rd2 = (sel2) ? wreg : rd2mem;
3540 48 unneback
endmodule
3541 12 unneback
//////////////////////////////////////////////////////////////////////
3542
////                                                              ////
3543
////  Versatile library, wishbone stuff                           ////
3544
////                                                              ////
3545
////  Description                                                 ////
3546
////  Wishbone compliant modules                                  ////
3547
////                                                              ////
3548
////                                                              ////
3549
////  To Do:                                                      ////
3550
////   -                                                          ////
3551
////                                                              ////
3552
////  Author(s):                                                  ////
3553
////      - Michael Unneback, unneback@opencores.org              ////
3554
////        ORSoC AB                                              ////
3555
////                                                              ////
3556
//////////////////////////////////////////////////////////////////////
3557
////                                                              ////
3558
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
3559
////                                                              ////
3560
//// This source file may be used and distributed without         ////
3561
//// restriction provided that this copyright statement is not    ////
3562
//// removed from the file and that any derivative work contains  ////
3563
//// the original copyright notice and the associated disclaimer. ////
3564
////                                                              ////
3565
//// This source file is free software; you can redistribute it   ////
3566
//// and/or modify it under the terms of the GNU Lesser General   ////
3567
//// Public License as published by the Free Software Foundation; ////
3568
//// either version 2.1 of the License, or (at your option) any   ////
3569
//// later version.                                               ////
3570
////                                                              ////
3571
//// This source is distributed in the hope that it will be       ////
3572
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
3573
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
3574
//// PURPOSE.  See the GNU Lesser General Public License for more ////
3575
//// details.                                                     ////
3576
////                                                              ////
3577
//// You should have received a copy of the GNU Lesser General    ////
3578
//// Public License along with this source; if not, download it   ////
3579
//// from http://www.opencores.org/lgpl.shtml                     ////
3580
////                                                              ////
3581
//////////////////////////////////////////////////////////////////////
3582
`timescale 1ns/1ns
3583 85 unneback
module vl_wb_adr_inc ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
3584 83 unneback
parameter adr_width = 10;
3585
parameter max_burst_width = 4;
3586 85 unneback
input cyc_i, stb_i, we_i;
3587 83 unneback
input [2:0] cti_i;
3588
input [1:0] bte_i;
3589
input [adr_width-1:0] adr_i;
3590
output [adr_width-1:0] adr_o;
3591
output ack_o;
3592
input clk, rst;
3593
reg [adr_width-1:0] adr;
3594 90 unneback
wire [max_burst_width-1:0] to_adr;
3595 91 unneback
reg [max_burst_width-1:0] last_adr;
3596 92 unneback
reg last_cycle;
3597
localparam idle_or_eoc = 1'b0;
3598
localparam cyc_or_ws   = 1'b1;
3599 91 unneback
always @ (posedge clk or posedge rst)
3600
if (rst)
3601
    last_adr <= {max_burst_width{1'b0}};
3602
else
3603
    if (stb_i)
3604 92 unneback
        last_adr <=adr_o[max_burst_width-1:0];
3605 83 unneback
generate
3606
if (max_burst_width==0) begin : inst_0
3607 97 unneback
        reg ack_o;
3608
        assign adr_o = adr_i;
3609
        always @ (posedge clk or posedge rst)
3610
        if (rst)
3611
            ack_o <= 1'b0;
3612
        else
3613
            ack_o <= cyc_i & stb_i & !ack_o;
3614 83 unneback
end else begin
3615
    always @ (posedge clk or posedge rst)
3616
    if (rst)
3617 92 unneback
        last_cycle <= idle_or_eoc;
3618 83 unneback
    else
3619 92 unneback
        last_cycle <= (!cyc_i) ? idle_or_eoc : //idle
3620
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? idle_or_eoc : // eoc
3621
                      (cyc_i & !stb_i) ? cyc_or_ws : //ws
3622
                      cyc_or_ws; // cyc
3623
    assign to_adr = (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
3624 85 unneback
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
3625 91 unneback
                                        (!stb_i) ? last_adr :
3626 92 unneback
                                        (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] :
3627 85 unneback
                                        adr[max_burst_width-1:0];
3628 92 unneback
    assign ack_o = (last_cycle==cyc_or_ws) & stb_i;
3629 83 unneback
end
3630
endgenerate
3631
generate
3632
if (max_burst_width==2) begin : inst_2
3633
    always @ (posedge clk or posedge rst)
3634
    if (rst)
3635
        adr <= 2'h0;
3636
    else
3637
        if (cyc_i & stb_i)
3638
            adr[1:0] <= to_adr[1:0] + 2'd1;
3639
        else
3640
            adr <= to_adr[1:0];
3641
end
3642
endgenerate
3643
generate
3644
if (max_burst_width==3) begin : inst_3
3645
    always @ (posedge clk or posedge rst)
3646
    if (rst)
3647
        adr <= 3'h0;
3648
    else
3649
        if (cyc_i & stb_i)
3650
            case (bte_i)
3651
            2'b01: adr[2:0] <= {to_adr[2],to_adr[1:0] + 2'd1};
3652
            default: adr[3:0] <= to_adr[2:0] + 3'd1;
3653
            endcase
3654
        else
3655
            adr <= to_adr[2:0];
3656
end
3657
endgenerate
3658
generate
3659
if (max_burst_width==4) begin : inst_4
3660
    always @ (posedge clk or posedge rst)
3661
    if (rst)
3662
        adr <= 4'h0;
3663
    else
3664 91 unneback
        if (stb_i) // | (!stb_i & last_cycle!=ws)) // for !stb_i restart with adr_i +1, only inc once
3665 83 unneback
            case (bte_i)
3666
            2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
3667
            2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
3668
            default: adr[3:0] <= to_adr + 4'd1;
3669
            endcase
3670
        else
3671
            adr <= to_adr[3:0];
3672
end
3673
endgenerate
3674
generate
3675
if (adr_width > max_burst_width) begin : pass_through
3676
    assign adr_o[adr_width-1:max_burst_width] = adr_i[adr_width-1:max_burst_width];
3677
end
3678
endgenerate
3679
endmodule
3680
// async wb3 - wb3 bridge
3681
`timescale 1ns/1ns
3682 18 unneback
module vl_wb3wb3_bridge (
3683 12 unneback
        // wishbone slave side
3684
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
3685
        // wishbone master side
3686
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
3687 95 unneback
parameter style = "FIFO"; // valid: simple, FIFO
3688
parameter addr_width = 4;
3689 12 unneback
input [31:0] wbs_dat_i;
3690
input [31:2] wbs_adr_i;
3691
input [3:0]  wbs_sel_i;
3692
input [1:0]  wbs_bte_i;
3693
input [2:0]  wbs_cti_i;
3694
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
3695
output [31:0] wbs_dat_o;
3696 14 unneback
output wbs_ack_o;
3697 12 unneback
input wbs_clk, wbs_rst;
3698
output [31:0] wbm_dat_o;
3699
output reg [31:2] wbm_adr_o;
3700
output [3:0]  wbm_sel_o;
3701
output reg [1:0]  wbm_bte_o;
3702
output reg [2:0]  wbm_cti_o;
3703 14 unneback
output reg wbm_we_o;
3704
output wbm_cyc_o;
3705 12 unneback
output wbm_stb_o;
3706
input [31:0]  wbm_dat_i;
3707
input wbm_ack_i;
3708
input wbm_clk, wbm_rst;
3709
// bte
3710
parameter linear       = 2'b00;
3711
parameter wrap4        = 2'b01;
3712
parameter wrap8        = 2'b10;
3713
parameter wrap16       = 2'b11;
3714
// cti
3715
parameter classic      = 3'b000;
3716
parameter incburst     = 3'b010;
3717
parameter endofburst   = 3'b111;
3718 95 unneback
localparam wbs_adr  = 1'b0;
3719
localparam wbs_data = 1'b1;
3720
localparam wbm_adr0      = 2'b00;
3721
localparam wbm_adr1      = 2'b01;
3722
localparam wbm_data      = 2'b10;
3723
localparam wbm_data_wait = 2'b11;
3724 12 unneback
reg [1:0] wbs_bte_reg;
3725
reg wbs;
3726
wire wbs_eoc_alert, wbm_eoc_alert;
3727
reg wbs_eoc, wbm_eoc;
3728
reg [1:0] wbm;
3729 14 unneback
wire [1:16] wbs_count, wbm_count;
3730 12 unneback
wire [35:0] a_d, a_q, b_d, b_q;
3731
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
3732
reg a_rd_reg;
3733
wire b_rd_adr, b_rd_data;
3734 14 unneback
wire b_rd_data_reg;
3735
wire [35:0] temp;
3736 12 unneback
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
3737
always @ (posedge wbs_clk or posedge wbs_rst)
3738
if (wbs_rst)
3739
        wbs_eoc <= 1'b0;
3740
else
3741
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
3742 78 unneback
                wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111);
3743 12 unneback
        else if (wbs_eoc_alert & (a_rd | a_wr))
3744
                wbs_eoc <= 1'b1;
3745 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
3746 12 unneback
    cnt0 (
3747
        .cke(wbs_ack_o),
3748
        .clear(wbs_eoc),
3749
        .q(wbs_count),
3750
        .rst(wbs_rst),
3751
        .clk(wbs_clk));
3752
always @ (posedge wbs_clk or posedge wbs_rst)
3753
if (wbs_rst)
3754
        wbs <= wbs_adr;
3755
else
3756 75 unneback
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)
3757 12 unneback
                wbs <= wbs_data;
3758
        else if (wbs_eoc & wbs_ack_o)
3759
                wbs <= wbs_adr;
3760
// wbs FIFO
3761 75 unneback
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};
3762
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :
3763 12 unneback
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
3764
              1'b0;
3765
assign a_rd = !a_fifo_empty;
3766
always @ (posedge wbs_clk or posedge wbs_rst)
3767
if (wbs_rst)
3768
        a_rd_reg <= 1'b0;
3769
else
3770
        a_rd_reg <= a_rd;
3771
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
3772
assign wbs_dat_o = a_q[35:4];
3773
always @ (posedge wbs_clk or posedge wbs_rst)
3774
if (wbs_rst)
3775 13 unneback
        wbs_bte_reg <= 2'b00;
3776 12 unneback
else
3777 13 unneback
        wbs_bte_reg <= wbs_bte_i;
3778 12 unneback
// wbm FIFO
3779
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
3780
always @ (posedge wbm_clk or posedge wbm_rst)
3781
if (wbm_rst)
3782
        wbm_eoc <= 1'b0;
3783
else
3784
        if (wbm==wbm_adr0 & !b_fifo_empty)
3785
                wbm_eoc <= b_q[4:3] == linear;
3786
        else if (wbm_eoc_alert & wbm_ack_i)
3787
                wbm_eoc <= 1'b1;
3788
always @ (posedge wbm_clk or posedge wbm_rst)
3789
if (wbm_rst)
3790
        wbm <= wbm_adr0;
3791
else
3792 33 unneback
/*
3793 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
3794
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
3795
        (wbm==wbm_adr1 & !wbm_we_o) |
3796
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
3797
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
3798 33 unneback
*/
3799
    case (wbm)
3800
    wbm_adr0:
3801
        if (!b_fifo_empty)
3802
            wbm <= wbm_adr1;
3803
    wbm_adr1:
3804
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
3805
            wbm <= wbm_data;
3806
    wbm_data:
3807
        if (wbm_ack_i & wbm_eoc)
3808
            wbm <= wbm_adr0;
3809
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
3810
            wbm <= wbm_data_wait;
3811
    wbm_data_wait:
3812
        if (!b_fifo_empty)
3813
            wbm <= wbm_data;
3814
    endcase
3815 12 unneback
assign b_d = {wbm_dat_i,4'b1111};
3816
assign b_wr = !wbm_we_o & wbm_ack_i;
3817
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
3818
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
3819
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
3820 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
3821 12 unneback
                   1'b0;
3822
assign b_rd = b_rd_adr | b_rd_data;
3823 18 unneback
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
3824
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
3825 12 unneback
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
3826 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
3827 12 unneback
    cnt1 (
3828
        .cke(wbm_ack_i),
3829
        .clear(wbm_eoc),
3830
        .q(wbm_count),
3831
        .rst(wbm_rst),
3832
        .clk(wbm_clk));
3833 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
3834
assign wbm_stb_o = (wbm==wbm_data);
3835 12 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
3836
if (wbm_rst)
3837
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
3838
else begin
3839
        if (wbm==wbm_adr0 & !b_fifo_empty)
3840
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
3841
        else if (wbm_eoc_alert & wbm_ack_i)
3842
                wbm_cti_o <= endofburst;
3843
end
3844
//async_fifo_dw_simplex_top
3845
vl_fifo_2r2w_async_simplex
3846
# ( .data_width(36), .addr_width(addr_width))
3847
fifo (
3848
    // a side
3849
    .a_d(a_d),
3850
    .a_wr(a_wr),
3851
    .a_fifo_full(a_fifo_full),
3852
    .a_q(a_q),
3853
    .a_rd(a_rd),
3854
    .a_fifo_empty(a_fifo_empty),
3855
    .a_clk(wbs_clk),
3856
    .a_rst(wbs_rst),
3857
    // b side
3858
    .b_d(b_d),
3859
    .b_wr(b_wr),
3860
    .b_fifo_full(b_fifo_full),
3861
    .b_q(b_q),
3862
    .b_rd(b_rd),
3863
    .b_fifo_empty(b_fifo_empty),
3864
    .b_clk(wbm_clk),
3865
    .b_rst(wbm_rst)
3866
    );
3867
endmodule
3868 75 unneback
module vl_wb3avalon_bridge (
3869
        // wishbone slave side
3870
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
3871 77 unneback
        // avalon master side
3872 75 unneback
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
3873 85 unneback
parameter linewrapburst = 1'b0;
3874 75 unneback
input [31:0] wbs_dat_i;
3875
input [31:2] wbs_adr_i;
3876
input [3:0]  wbs_sel_i;
3877
input [1:0]  wbs_bte_i;
3878
input [2:0]  wbs_cti_i;
3879 83 unneback
input wbs_we_i;
3880
input wbs_cyc_i;
3881
input wbs_stb_i;
3882 75 unneback
output [31:0] wbs_dat_o;
3883
output wbs_ack_o;
3884
input wbs_clk, wbs_rst;
3885
input [31:0] readdata;
3886
output [31:0] writedata;
3887
output [31:2] address;
3888
output [3:0]  be;
3889
output write;
3890 81 unneback
output read;
3891 75 unneback
output beginbursttransfer;
3892
output [3:0] burstcount;
3893
input readdatavalid;
3894
input waitrequest;
3895
input clk;
3896
input rst;
3897
wire [1:0] wbm_bte_o;
3898
wire [2:0] wbm_cti_o;
3899
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
3900
reg last_cyc;
3901 79 unneback
reg [3:0] counter;
3902 82 unneback
reg read_busy;
3903 75 unneback
always @ (posedge clk or posedge rst)
3904
if (rst)
3905
    last_cyc <= 1'b0;
3906
else
3907
    last_cyc <= wbm_cyc_o;
3908 79 unneback
always @ (posedge clk or posedge rst)
3909
if (rst)
3910 82 unneback
    read_busy <= 1'b0;
3911 79 unneback
else
3912 82 unneback
    if (read & !waitrequest)
3913
        read_busy <= 1'b1;
3914
    else if (wbm_ack_i & wbm_cti_o!=3'b010)
3915
        read_busy <= 1'b0;
3916
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;
3917 75 unneback
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
3918
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
3919
                    (wbm_bte_o==2'b10) ? 4'd8 :
3920 78 unneback
                    (wbm_bte_o==2'b11) ? 4'd16:
3921
                    4'd1;
3922 82 unneback
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);
3923 79 unneback
always @ (posedge clk or posedge rst)
3924
if (rst) begin
3925
    counter <= 4'd0;
3926
end else
3927 80 unneback
    if (wbm_we_o) begin
3928
        if (!waitrequest & !last_cyc & wbm_cyc_o) begin
3929 85 unneback
            counter <= burstcount -4'd1;
3930 80 unneback
        end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
3931
            counter <= burstcount;
3932
        end else if (!waitrequest & wbm_stb_o) begin
3933
            counter <= counter - 4'd1;
3934
        end
3935 82 unneback
    end
3936 81 unneback
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
3937 77 unneback
vl_wb3wb3_bridge wbwb3inst (
3938 75 unneback
    // wishbone slave side
3939
    .wbs_dat_i(wbs_dat_i),
3940
    .wbs_adr_i(wbs_adr_i),
3941
    .wbs_sel_i(wbs_sel_i),
3942
    .wbs_bte_i(wbs_bte_i),
3943
    .wbs_cti_i(wbs_cti_i),
3944
    .wbs_we_i(wbs_we_i),
3945
    .wbs_cyc_i(wbs_cyc_i),
3946
    .wbs_stb_i(wbs_stb_i),
3947
    .wbs_dat_o(wbs_dat_o),
3948
    .wbs_ack_o(wbs_ack_o),
3949
    .wbs_clk(wbs_clk),
3950
    .wbs_rst(wbs_rst),
3951
    // wishbone master side
3952
    .wbm_dat_o(writedata),
3953 78 unneback
    .wbm_adr_o(address),
3954 75 unneback
    .wbm_sel_o(be),
3955
    .wbm_bte_o(wbm_bte_o),
3956
    .wbm_cti_o(wbm_cti_o),
3957
    .wbm_we_o(wbm_we_o),
3958
    .wbm_cyc_o(wbm_cyc_o),
3959
    .wbm_stb_o(wbm_stb_o),
3960
    .wbm_dat_i(readdata),
3961
    .wbm_ack_i(wbm_ack_i),
3962
    .wbm_clk(clk),
3963
    .wbm_rst(rst));
3964
endmodule
3965 49 unneback
// WB RAM with byte enable
3966 101 unneback
module vl_wb_ram (
3967 69 unneback
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
3968 101 unneback
    wbs_dat_o, wbs_ack_o, wbs_stall_o, wb_clk, wb_rst);
3969
parameter adr_width = 16;
3970
parameter mem_size = 1<<adr_width;
3971
parameter dat_width = 32;
3972
parameter max_burst_width = 4; // only used for B3
3973
parameter mode = "B3"; // valid options: B3, B4
3974 60 unneback
parameter memory_init = 1;
3975
parameter memory_file = "vl_ram.vmem";
3976 101 unneback
input [dat_width-1:0] wbs_dat_i;
3977
input [adr_width-1:0] wbs_adr_i;
3978
input [2:0] wbs_cti_i;
3979
input [1:0] wbs_bte_i;
3980
input [dat_width/8-1:0] wbs_sel_i;
3981 70 unneback
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
3982 101 unneback
output [dat_width-1:0] wbs_dat_o;
3983 70 unneback
output wbs_ack_o;
3984 101 unneback
output wbs_stall_o;
3985 71 unneback
input wb_clk, wb_rst;
3986 101 unneback
wire [adr_width-1:0] adr;
3987
wire we;
3988
generate
3989
if (mode=="B3") begin : B3_inst
3990
vl_wb_adr_inc # ( .adr_width(adr_width), .max_burst_width(max_burst_width)) adr_inc0 (
3991 83 unneback
    .cyc_i(wbs_cyc_i),
3992
    .stb_i(wbs_stb_i),
3993
    .cti_i(wbs_cti_i),
3994
    .bte_i(wbs_bte_i),
3995
    .adr_i(wbs_adr_i),
3996 85 unneback
    .we_i(wbs_we_i),
3997 83 unneback
    .ack_o(wbs_ack_o),
3998
    .adr_o(adr),
3999
    .clk(wb_clk),
4000
    .rst(wb_rst));
4001 101 unneback
assign we = wbs_we_i & wbs_ack_o;
4002
end else if (mode=="B4") begin : B4_inst
4003
reg wbs_ack_o_reg;
4004
always @ (posedge wb_clk or posedge wb_rst)
4005
    if (wb_rst)
4006
        wbs_ack_o_reg <= 1'b0;
4007
    else
4008
        wbs_ack_o_reg <= wbs_stb_i & wbs_cyc_i;
4009
assign wbs_ack_o = wbs_ack_o_reg;
4010
assign wbs_stall_o = 1'b0;
4011
assign adr = wbs_adr_i;
4012
assign we = wbs_we_i & wbs_cyc_i & wbs_stb_i;
4013
end
4014
endgenerate
4015 100 unneback
vl_ram_be # (
4016
    .data_width(dat_width),
4017
    .addr_width(adr_width),
4018
    .mem_size(mem_size),
4019
    .memory_init(memory_init),
4020
    .memory_file(memory_file))
4021
ram0(
4022 101 unneback
    .d(wbs_dat_i),
4023
    .adr(adr),
4024
    .be(wbs_sel_i),
4025
    .we(we),
4026
    .q(wbs_dat_o),
4027 100 unneback
    .clk(wb_clk)
4028
);
4029 49 unneback
endmodule
4030 103 unneback
// A wishbone compliant RAM module that can be placed in front of other memory controllers
4031
module vl_wb_shadow_ram (
4032
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
4033
    wbs_dat_o, wbs_ack_o, wbs_stall_o,
4034
    wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
4035
    wbm_dat_i, wbm_ack_i, wbm_stall_i,
4036
    wb_clk, wb_rst);
4037
parameter dat_width = 32;
4038
parameter mode = "B4";
4039
parameter max_burst_width = 4; // only used for B3
4040
parameter shadow_mem_adr_width = 10;
4041
parameter shadow_mem_size = 1024;
4042
parameter shadow_mem_init = 2;
4043
parameter shadow_mem_file = "vl_ram.v";
4044
parameter main_mem_adr_width = 24;
4045
input [dat_width-1:0] wbs_dat_i;
4046
input [main_mem_adr_width-1:0] wbs_adr_i;
4047
input [2:0] wbs_cti_i;
4048
input [1:0] wbs_bte_i;
4049
input [dat_width/8-1:0] wbs_sel_i;
4050
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
4051
output [dat_width-1:0] wbs_dat_o;
4052
output wbs_ack_o;
4053
output wbs_stall_o;
4054
output [dat_width-1:0] wbm_dat_o;
4055
output [main_mem_adr_width-1:0] wbm_adr_o;
4056
output [2:0] wbm_cti_o;
4057
output [1:0] wbm_bte_o;
4058
output [dat_width/8-1:0] wbm_sel_o;
4059
output wbm_we_o, wbm_stb_o, wbm_cyc_o;
4060
input [dat_width-1:0] wbm_dat_i;
4061
input wbm_ack_i, wbm_stall_i;
4062
input wb_clk, wb_rst;
4063
generate
4064
if (shadow_mem_size>0) begin : shadow_ram_inst
4065
wire cyc;
4066
wire [dat_width-1:0] dat;
4067
wire stall, ack;
4068
assign cyc = wbs_cyc_i & (wbs_adr_i<=shadow_mem_size);
4069
vl_wb_ram # (
4070
    .dat_width(dat_width),
4071
    .adr_width(shadow_mem_adr_width),
4072
    .mem_size(shadow_mem_size),
4073
    .memory_init(shadow_mem_init),
4074 117 unneback
    .memory_file(shadow_mem_file),
4075 103 unneback
    .mode(mode))
4076
shadow_mem0 (
4077
    .wbs_dat_i(wbs_dat_i),
4078
    .wbs_adr_i(wbs_adr_i[shadow_mem_adr_width-1:0]),
4079
    .wbs_sel_i(wbs_sel_i),
4080
    .wbs_we_i (wbs_we_i),
4081
    .wbs_bte_i(wbs_bte_i),
4082
    .wbs_cti_i(wbs_cti_i),
4083
    .wbs_stb_i(wbs_stb_i),
4084
    .wbs_cyc_i(cyc),
4085
    .wbs_dat_o(dat),
4086
    .wbs_stall_o(stall),
4087
    .wbs_ack_o(ack),
4088
    .wb_clk(wb_clk),
4089
    .wb_rst(wb_rst));
4090
assign {wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o} =
4091
       {wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i};
4092
assign wbm_cyc_o = wbs_cyc_i & (wbs_adr_i>shadow_mem_size);
4093
assign wbs_dat_o = (dat & {dat_width{cyc}}) | (wbm_dat_i & {dat_width{wbm_cyc_o}});
4094
assign wbs_ack_o = (ack & cyc) | (wbm_ack_i & wbm_cyc_o);
4095
assign wbs_stall_o = (stall & cyc) | (wbm_stall_i & wbm_cyc_o);
4096
end else begin : no_shadow_ram_inst
4097
assign {wbm_dat_o, wbm_adr_o, wbm_cti_o, wbm_bte_o, wbm_sel_o, wbm_we_o, wbm_stb_o, wbm_cyc_o} =
4098
       {wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i};
4099
assign {wbs_dat_o, wbs_ack_o, wbs_stall_o} = {wbm_dat_i, wbm_ack_i, wbm_stall_i};
4100
end
4101
endgenerate
4102
endmodule
4103 17 unneback
// WB ROM
4104 48 unneback
module vl_wb_b4_rom (
4105
    wb_adr_i, wb_stb_i, wb_cyc_i,
4106
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
4107
    parameter dat_width = 32;
4108
    parameter dat_default = 32'h15000000;
4109
    parameter adr_width = 32;
4110
/*
4111
`ifndef ROM
4112
`define ROM "rom.v"
4113
`endif
4114
*/
4115
    input [adr_width-1:2]   wb_adr_i;
4116
    input                   wb_stb_i;
4117
    input                   wb_cyc_i;
4118
    output [dat_width-1:0]  wb_dat_o;
4119
    reg [dat_width-1:0]     wb_dat_o;
4120
    output                  wb_ack_o;
4121
    reg                     wb_ack_o;
4122
    output                  stall_o;
4123
    input                   wb_clk;
4124
    input                   wb_rst;
4125
always @ (posedge wb_clk or posedge wb_rst)
4126
    if (wb_rst)
4127
        wb_dat_o <= {dat_width{1'b0}};
4128
    else
4129
         case (wb_adr_i[adr_width-1:2])
4130
`ifdef ROM
4131
`include `ROM
4132
`endif
4133
           default:
4134
             wb_dat_o <= dat_default;
4135
         endcase // case (wb_adr_i)
4136
always @ (posedge wb_clk or posedge wb_rst)
4137
    if (wb_rst)
4138
        wb_ack_o <= 1'b0;
4139
    else
4140
        wb_ack_o <= wb_stb_i & wb_cyc_i;
4141
assign stall_o = 1'b0;
4142
endmodule
4143
// WB ROM
4144 18 unneback
module vl_wb_boot_rom (
4145 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
4146 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
4147
    parameter adr_hi = 31;
4148
    parameter adr_lo = 28;
4149
    parameter adr_sel = 4'hf;
4150
    parameter addr_width = 5;
4151 33 unneback
/*
4152
`ifndef BOOT_ROM
4153
`define BOOT_ROM "boot_rom.v"
4154
`endif
4155
*/
4156 18 unneback
    input [adr_hi:2]    wb_adr_i;
4157
    input               wb_stb_i;
4158
    input               wb_cyc_i;
4159
    output [31:0]        wb_dat_o;
4160
    output              wb_ack_o;
4161
    output              hit_o;
4162
    input               wb_clk;
4163
    input               wb_rst;
4164
    wire hit;
4165
    reg [31:0] wb_dat;
4166
    reg wb_ack;
4167
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
4168 17 unneback
always @ (posedge wb_clk or posedge wb_rst)
4169
    if (wb_rst)
4170 18 unneback
        wb_dat <= 32'h15000000;
4171 17 unneback
    else
4172 18 unneback
         case (wb_adr_i[addr_width-1:2])
4173 33 unneback
`ifdef BOOT_ROM
4174
`include `BOOT_ROM
4175
`endif
4176 17 unneback
           /*
4177
            // Zero r0 and jump to 0x00000100
4178 18 unneback
 
4179
            1 : wb_dat <= 32'hA8200000;
4180
            2 : wb_dat <= 32'hA8C00100;
4181
            3 : wb_dat <= 32'h44003000;
4182
            4 : wb_dat <= 32'h15000000;
4183 17 unneback
            */
4184
           default:
4185 18 unneback
             wb_dat <= 32'h00000000;
4186 17 unneback
         endcase // case (wb_adr_i)
4187
always @ (posedge wb_clk or posedge wb_rst)
4188
    if (wb_rst)
4189 18 unneback
        wb_ack <= 1'b0;
4190 17 unneback
    else
4191 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
4192
assign hit_o = hit;
4193
assign wb_dat_o = wb_dat & {32{wb_ack}};
4194
assign wb_ack_o = wb_ack;
4195 17 unneback
endmodule
4196 106 unneback
module vl_wb_dpram (
4197
        // wishbone slave side a
4198
        wbsa_dat_i, wbsa_adr_i, wbsa_sel_i, wbsa_cti_i, wbsa_bte_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o, wbsa_stall_o,
4199
        wbsa_clk, wbsa_rst,
4200
        // wishbone slave side b
4201
        wbsb_dat_i, wbsb_adr_i, wbsb_sel_i, wbsb_cti_i, wbsb_bte_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o, wbsb_stall_o,
4202
        wbsb_clk, wbsb_rst);
4203
parameter data_width_a = 32;
4204
parameter data_width_b = data_width_a;
4205
parameter addr_width_a = 8;
4206
localparam addr_width_b = data_width_a * addr_width_a / data_width_b;
4207
parameter mem_size = (addr_width_a>addr_width_b) ? (1<<addr_width_a) : (1<<addr_width_b);
4208
parameter max_burst_width_a = 4;
4209
parameter max_burst_width_b = max_burst_width_a;
4210
parameter mode = "B3";
4211 109 unneback
parameter memory_init = 0;
4212
parameter memory_file = "vl_ram.v";
4213 142 unneback
parameter debug = 0;
4214 106 unneback
input [data_width_a-1:0] wbsa_dat_i;
4215
input [addr_width_a-1:0] wbsa_adr_i;
4216
input [data_width_a/8-1:0] wbsa_sel_i;
4217
input [2:0] wbsa_cti_i;
4218
input [1:0] wbsa_bte_i;
4219
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
4220
output [data_width_a-1:0] wbsa_dat_o;
4221 109 unneback
output wbsa_ack_o;
4222 106 unneback
output wbsa_stall_o;
4223
input wbsa_clk, wbsa_rst;
4224
input [data_width_b-1:0] wbsb_dat_i;
4225
input [addr_width_b-1:0] wbsb_adr_i;
4226
input [data_width_b/8-1:0] wbsb_sel_i;
4227
input [2:0] wbsb_cti_i;
4228
input [1:0] wbsb_bte_i;
4229
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
4230
output [data_width_b-1:0] wbsb_dat_o;
4231 109 unneback
output wbsb_ack_o;
4232 106 unneback
output wbsb_stall_o;
4233
input wbsb_clk, wbsb_rst;
4234
wire [addr_width_a-1:0] adr_a;
4235
wire [addr_width_b-1:0] adr_b;
4236
wire we_a, we_b;
4237
generate
4238
if (mode=="B3") begin : b3_inst
4239
vl_wb_adr_inc # ( .adr_width(addr_width_a), .max_burst_width(max_burst_width_a)) adr_inc0 (
4240
    .cyc_i(wbsa_cyc_i),
4241
    .stb_i(wbsa_stb_i),
4242
    .cti_i(wbsa_cti_i),
4243
    .bte_i(wbsa_bte_i),
4244
    .adr_i(wbsa_adr_i),
4245
    .we_i(wbsa_we_i),
4246
    .ack_o(wbsa_ack_o),
4247
    .adr_o(adr_a),
4248
    .clk(wbsa_clk),
4249
    .rst(wbsa_rst));
4250
assign we_a = wbsa_we_i & wbsa_ack_o;
4251
vl_wb_adr_inc # ( .adr_width(addr_width_b), .max_burst_width(max_burst_width_b)) adr_inc1 (
4252
    .cyc_i(wbsb_cyc_i),
4253
    .stb_i(wbsb_stb_i),
4254
    .cti_i(wbsb_cti_i),
4255
    .bte_i(wbsb_bte_i),
4256
    .adr_i(wbsb_adr_i),
4257
    .we_i(wbsb_we_i),
4258
    .ack_o(wbsb_ack_o),
4259
    .adr_o(adr_b),
4260
    .clk(wbsb_clk),
4261
    .rst(wbsb_rst));
4262
assign we_b = wbsb_we_i & wbsb_ack_o;
4263
end else if (mode=="B4") begin : b4_inst
4264 142 unneback
assign adr_a = wbsa_adr_i;
4265 109 unneback
vl_dff dffacka ( .d(wbsa_stb_i & wbsa_cyc_i), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
4266 106 unneback
assign wbsa_stall_o = 1'b0;
4267
assign we_a = wbsa_we_i & wbsa_cyc_i & wbsa_stb_i;
4268 142 unneback
assign adr_b = wbsb_adr_i;
4269 109 unneback
vl_dff dffackb ( .d(wbsb_stb_i & wbsb_cyc_i), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
4270 106 unneback
assign wbsb_stall_o = 1'b0;
4271
assign we_b = wbsb_we_i & wbsb_cyc_i & wbsb_stb_i;
4272
end
4273
endgenerate
4274 109 unneback
vl_dpram_be_2r2w # ( .a_data_width(data_width_a), .a_addr_width(addr_width_a), .mem_size(mem_size),
4275 110 unneback
                 .b_data_width(data_width_b),
4276 142 unneback
                 .memory_init(memory_init), .memory_file(memory_file),
4277
                 .debug(debug))
4278 106 unneback
ram_i (
4279
    .d_a(wbsa_dat_i),
4280
    .q_a(wbsa_dat_o),
4281
    .adr_a(adr_a),
4282
    .be_a(wbsa_sel_i),
4283
    .we_a(we_a),
4284
    .clk_a(wbsa_clk),
4285
    .d_b(wbsb_dat_i),
4286
    .q_b(wbsb_dat_o),
4287
    .adr_b(adr_b),
4288
    .be_b(wbsb_sel_i),
4289
    .we_b(we_b),
4290
    .clk_b(wbsb_clk) );
4291
endmodule
4292 101 unneback
module vl_wb_cache (
4293 103 unneback
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_stall_o, wbs_clk, wbs_rst,
4294 98 unneback
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o, wbm_dat_i, wbm_ack_i, wbm_stall_i, wbm_clk, wbm_rst
4295 97 unneback
);
4296
parameter dw_s = 32;
4297
parameter aw_s = 24;
4298
parameter dw_m = dw_s;
4299 124 unneback
//localparam aw_m = dw_s * aw_s / dw_m;
4300
localparam aw_m =
4301 126 unneback
        (dw_s==dw_m) ? aw_s :
4302
        (dw_s==dw_m*2) ? aw_s+1 :
4303
        (dw_s==dw_m*4) ? aw_s+2 :
4304
        (dw_s==dw_m*8) ? aw_s+3 :
4305
        (dw_s==dw_m*16) ? aw_s+4 :
4306
        (dw_s==dw_m*32) ? aw_s+5 :
4307
        (dw_s==dw_m/2) ? aw_s-1 :
4308 127 unneback
        (dw_s==dw_m/4) ? aw_s-2 :
4309 126 unneback
        (dw_s==dw_m/8) ? aw_s-3 :
4310
        (dw_s==dw_m/16) ? aw_s-4 :
4311
        (dw_s==dw_m/32) ? aw_s-5 : 0;
4312 100 unneback
parameter wbs_max_burst_width = 4;
4313 103 unneback
parameter wbs_mode = "B3";
4314 97 unneback
parameter async = 1; // wbs_clk != wbm_clk
4315
parameter nr_of_ways = 1;
4316
parameter aw_offset = 4; // 4 => 16 words per cache line
4317
parameter aw_slot = 10;
4318 100 unneback
parameter valid_mem = 0;
4319
parameter debug = 0;
4320
localparam aw_b_offset = aw_offset * dw_s / dw_m;
4321 98 unneback
localparam aw_tag = aw_s - aw_slot - aw_offset;
4322 97 unneback
parameter wbm_burst_size = 4; // valid options 4,8,16
4323 98 unneback
localparam bte = (wbm_burst_size==4) ? 2'b01 : (wbm_burst_size==8) ? 2'b10 : 2'b11;
4324 100 unneback
localparam wbm_burst_width = (wbm_burst_size==1) ? 0 : (wbm_burst_size==2) ? 1 : (wbm_burst_size==4) ? 2 : (wbm_burst_size==8) ? 3 : (wbm_burst_size==16) ? 4 : (wbm_burst_size==32) ? 5 : (wbm_burst_size==64) ? 6 : (wbm_burst_size==128) ? 7 : 8;
4325 97 unneback
localparam nr_of_wbm_burst = ((1<<aw_offset)/wbm_burst_size) * dw_s / dw_m;
4326 100 unneback
localparam nr_of_wbm_burst_width = (nr_of_wbm_burst==1) ? 0 : (nr_of_wbm_burst==2) ? 1 : (nr_of_wbm_burst==4) ? 2 : (nr_of_wbm_burst==8) ? 3 : (nr_of_wbm_burst==16) ? 4 : (nr_of_wbm_burst==32) ? 5 : (nr_of_wbm_burst==64) ? 6 : (nr_of_wbm_burst==128) ? 7 : 8;
4327 97 unneback
input [dw_s-1:0] wbs_dat_i;
4328
input [aw_s-1:0] wbs_adr_i; // dont include a1,a0
4329 98 unneback
input [dw_s/8-1:0] wbs_sel_i;
4330 97 unneback
input [2:0] wbs_cti_i;
4331
input [1:0] wbs_bte_i;
4332 98 unneback
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
4333 97 unneback
output [dw_s-1:0] wbs_dat_o;
4334
output wbs_ack_o;
4335 103 unneback
output wbs_stall_o;
4336 97 unneback
input wbs_clk, wbs_rst;
4337
output [dw_m-1:0] wbm_dat_o;
4338
output [aw_m-1:0] wbm_adr_o;
4339
output [dw_m/8-1:0] wbm_sel_o;
4340
output [2:0] wbm_cti_o;
4341
output [1:0] wbm_bte_o;
4342 98 unneback
output wbm_stb_o, wbm_cyc_o, wbm_we_o;
4343 97 unneback
input [dw_m-1:0] wbm_dat_i;
4344
input wbm_ack_i;
4345
input wbm_stall_i;
4346
input wbm_clk, wbm_rst;
4347 100 unneback
wire valid, dirty, hit;
4348 97 unneback
wire [aw_tag-1:0] tag;
4349
wire tag_mem_we;
4350
wire [aw_tag-1:0] wbs_adr_tag;
4351
wire [aw_slot-1:0] wbs_adr_slot;
4352 98 unneback
wire [aw_offset-1:0] wbs_adr_word;
4353
wire [aw_s-1:0] wbs_adr;
4354 97 unneback
reg [1:0] state;
4355
localparam idle = 2'h0;
4356
localparam rdwr = 2'h1;
4357
localparam push = 2'h2;
4358
localparam pull = 2'h3;
4359
wire eoc;
4360 103 unneback
wire we;
4361 97 unneback
// cdc
4362
wire done, mem_alert, mem_done;
4363 98 unneback
// wbm side
4364
reg [aw_m-1:0] wbm_radr;
4365
reg [aw_m-1:0] wbm_wadr;
4366 137 unneback
//wire [aw_slot-1:0] wbm_adr;
4367
wire [aw_m-1:0] wbm_adr;
4368 98 unneback
wire wbm_radr_cke, wbm_wadr_cke;
4369 100 unneback
reg [2:0] phase;
4370
// phase = {we,stb,cyc}
4371
localparam wbm_wait     = 3'b000;
4372
localparam wbm_wr       = 3'b111;
4373
localparam wbm_wr_drain = 3'b101;
4374
localparam wbm_rd       = 3'b011;
4375
localparam wbm_rd_drain = 3'b001;
4376 97 unneback
assign {wbs_adr_tag, wbs_adr_slot, wbs_adr_word} = wbs_adr_i;
4377 100 unneback
generate
4378
if (valid_mem==0) begin : no_valid_mem
4379
assign valid = 1'b1;
4380
end else begin : valid_mem_inst
4381
vl_dpram_1r1w
4382
    # ( .data_width(1), .addr_width(aw_slot), .memory_init(2), .debug(debug))
4383
    valid_mem ( .d_a(1'b1), .adr_a(wbs_adr_slot), .we_a(mem_done), .clk_a(wbm_clk),
4384
                .q_b(valid), .adr_b(wbs_adr_slot), .clk_b(wbs_clk));
4385
end
4386
endgenerate
4387
vl_dpram_1r1w
4388
    # ( .data_width(aw_tag), .addr_width(aw_slot), .memory_init(2), .debug(debug))
4389
    tag_mem ( .d_a(wbs_adr_tag), .adr_a(wbs_adr_slot), .we_a(mem_done), .clk_a(wbm_clk),
4390
              .q_b(tag), .adr_b(wbs_adr_slot), .clk_b(wbs_clk));
4391
assign hit = wbs_adr_tag == tag;
4392
vl_dpram_1r2w
4393
    # ( .data_width(1), .addr_width(aw_slot), .memory_init(2), .debug(debug))
4394
    dirty_mem (
4395
        .d_a(1'b1), .q_a(dirty), .adr_a(wbs_adr_slot), .we_a(wbs_cyc_i & wbs_we_i & wbs_ack_o), .clk_a(wbs_clk),
4396
        .d_b(1'b0), .adr_b(wbs_adr_slot), .we_b(mem_done), .clk_b(wbm_clk));
4397 103 unneback
generate
4398
if (wbs_mode=="B3") begin : inst_b3
4399 100 unneback
vl_wb_adr_inc # ( .adr_width(aw_s), .max_burst_width(wbs_max_burst_width)) adr_inc0 (
4400
    .cyc_i(wbs_cyc_i & (state==rdwr) & hit & valid),
4401
    .stb_i(wbs_stb_i & (state==rdwr) & hit & valid), // throttle depending on valid
4402 97 unneback
    .cti_i(wbs_cti_i),
4403
    .bte_i(wbs_bte_i),
4404
    .adr_i(wbs_adr_i),
4405
    .we_i (wbs_we_i),
4406
    .ack_o(wbs_ack_o),
4407
    .adr_o(wbs_adr),
4408 100 unneback
    .clk(wbs_clk),
4409
    .rst(wbs_rst));
4410 103 unneback
assign eoc = (wbs_cti_i==3'b000 | wbs_cti_i==3'b111) & wbs_ack_o;
4411
assign we = wbs_cyc_i &  wbs_we_i & wbs_ack_o;
4412
end else if (wbs_mode=="B4") begin : inst_b4
4413
end
4414
endgenerate
4415 131 unneback
localparam cache_mem_b_aw =
4416
    (dw_s==dw_m) ? aw_slot+aw_offset :
4417 133 unneback
    (dw_s==dw_m/2) ? aw_slot+aw_offset-1 :
4418
    (dw_s==dw_m/4) ? aw_slot+aw_offset-2 :
4419
    (dw_s==dw_m/8) ? aw_slot+aw_offset-3 :
4420
    (dw_s==dw_m/16) ? aw_slot+aw_offset-4 :
4421
    (dw_s==dw_m*2) ? aw_slot+aw_offset+1 :
4422
    (dw_s==dw_m*4) ? aw_slot+aw_offset+2 :
4423
    (dw_s==dw_m*8) ? aw_slot+aw_offset+3 :
4424
    (dw_s==dw_m*16) ? aw_slot+aw_offset+4 : 0;
4425 97 unneback
vl_dpram_be_2r2w
4426 100 unneback
    # ( .a_data_width(dw_s), .a_addr_width(aw_slot+aw_offset), .b_data_width(dw_m), .debug(debug))
4427 103 unneback
    cache_mem ( .d_a(wbs_dat_i), .adr_a(wbs_adr[aw_slot+aw_offset-1:0]),   .be_a(wbs_sel_i), .we_a(we), .q_a(wbs_dat_o), .clk_a(wbs_clk),
4428 136 unneback
                .d_b(wbm_dat_i), .adr_b(wbm_adr[cache_mem_b_aw-1:0]), .be_b(wbm_sel_o), .we_b(wbm_cyc_o & !wbm_we_o & wbm_ack_i), .q_b(wbm_dat_o), .clk_b(wbm_clk));
4429 97 unneback
always @ (posedge wbs_clk or posedge wbs_rst)
4430
if (wbs_rst)
4431 98 unneback
    state <= idle;
4432 97 unneback
else
4433
    case (state)
4434
    idle:
4435
        if (wbs_cyc_i)
4436
            state <= rdwr;
4437
    rdwr:
4438 100 unneback
        casex ({valid, hit, dirty, eoc})
4439
        4'b0xxx: state <= pull;
4440
        4'b11x1: state <= idle;
4441
        4'b101x: state <= push;
4442
        4'b100x: state <= pull;
4443
        endcase
4444 97 unneback
    push:
4445
        if (done)
4446
            state <= rdwr;
4447
    pull:
4448
        if (done)
4449
            state <= rdwr;
4450
    default: state <= idle;
4451
    endcase
4452
// cdc
4453
generate
4454
if (async==1) begin : cdc0
4455 100 unneback
vl_cdc cdc0 ( .start_pl(state==rdwr & (!valid | !hit)), .take_it_pl(mem_alert), .take_it_grant_pl(mem_done), .got_it_pl(done), .clk_src(wbs_clk), .rst_src(wbs_rst), .clk_dst(wbm_clk), .rst_dst(wbm_rst));
4456 97 unneback
end
4457
else begin : nocdc
4458 100 unneback
    assign mem_alert = state==rdwr & (!valid | !hit);
4459 97 unneback
    assign done = mem_done;
4460
end
4461
endgenerate
4462 136 unneback
// FSM generating a number of bursts 4 cycles
4463 97 unneback
// actual number depends on data width ratio
4464
// nr_of_wbm_burst
4465 101 unneback
reg [nr_of_wbm_burst_width+wbm_burst_width-1:0]       cnt_rw, cnt_ack;
4466 97 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
4467
if (wbm_rst)
4468 100 unneback
    cnt_rw <= {wbm_burst_width{1'b0}};
4469 97 unneback
else
4470 100 unneback
    if (wbm_cyc_o & wbm_stb_o & !wbm_stall_i)
4471
        cnt_rw <= cnt_rw + 1;
4472 98 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
4473
if (wbm_rst)
4474 100 unneback
    cnt_ack <= {wbm_burst_width{1'b0}};
4475 98 unneback
else
4476 100 unneback
    if (wbm_ack_i)
4477
        cnt_ack <= cnt_ack + 1;
4478
generate
4479 101 unneback
if (nr_of_wbm_burst==1) begin : one_burst
4480 98 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
4481
if (wbm_rst)
4482
    phase <= wbm_wait;
4483
else
4484
    case (phase)
4485
    wbm_wait:
4486
        if (mem_alert)
4487 100 unneback
            if (state==push)
4488
                phase <= wbm_wr;
4489
            else
4490
                phase <= wbm_rd;
4491 98 unneback
    wbm_wr:
4492 100 unneback
        if (&cnt_rw)
4493
            phase <= wbm_wr_drain;
4494
    wbm_wr_drain:
4495
        if (&cnt_ack)
4496 98 unneback
            phase <= wbm_rd;
4497
    wbm_rd:
4498 100 unneback
        if (&cnt_rw)
4499
            phase <= wbm_rd_drain;
4500
    wbm_rd_drain:
4501
        if (&cnt_ack)
4502
            phase <= wbm_wait;
4503 98 unneback
    default: phase <= wbm_wait;
4504
    endcase
4505 100 unneback
end else begin : multiple_burst
4506 101 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
4507
if (wbm_rst)
4508
    phase <= wbm_wait;
4509
else
4510
    case (phase)
4511
    wbm_wait:
4512
        if (mem_alert)
4513
            if (state==push)
4514
                phase <= wbm_wr;
4515
            else
4516
                phase <= wbm_rd;
4517
    wbm_wr:
4518
        if (&cnt_rw[wbm_burst_width-1:0])
4519
            phase <= wbm_wr_drain;
4520
    wbm_wr_drain:
4521
        if (&cnt_ack)
4522
            phase <= wbm_rd;
4523
        else if (&cnt_ack[wbm_burst_width-1:0])
4524
            phase <= wbm_wr;
4525
    wbm_rd:
4526
        if (&cnt_rw[wbm_burst_width-1:0])
4527
            phase <= wbm_rd_drain;
4528
    wbm_rd_drain:
4529
        if (&cnt_ack)
4530
            phase <= wbm_wait;
4531
        else if (&cnt_ack[wbm_burst_width-1:0])
4532
            phase <= wbm_rd;
4533
    default: phase <= wbm_wait;
4534
    endcase
4535 100 unneback
end
4536
endgenerate
4537 101 unneback
assign mem_done = phase==wbm_rd_drain & (&cnt_ack) & wbm_ack_i;
4538 100 unneback
assign wbm_adr_o = (phase[2]) ? {tag, wbs_adr_slot, cnt_rw} : {wbs_adr_tag, wbs_adr_slot, cnt_rw};
4539 137 unneback
assign wbm_adr   = (phase[2]) ? {wbs_adr_slot, cnt_rw} : {wbs_adr_slot, cnt_ack};
4540 100 unneback
assign wbm_sel_o = {dw_m/8{1'b1}};
4541
assign wbm_cti_o = (&cnt_rw | !wbm_stb_o) ? 3'b111 : 3'b010;
4542 98 unneback
assign wbm_bte_o = bte;
4543 100 unneback
assign {wbm_we_o, wbm_stb_o, wbm_cyc_o}  = phase;
4544 97 unneback
endmodule
4545 103 unneback
// Wishbone to avalon bridge supporting one type of burst transfer only
4546
// intended use is together with cache above
4547
// WB B4 -> pipelined avalon
4548
module vl_wb_avalon_bridge (
4549
        // wishbone slave side
4550
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_stall_o,
4551
        // avalon master side
4552
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer,
4553 136 unneback
        init_done,
4554 103 unneback
        // common
4555
        clk, rst);
4556
parameter adr_width = 30;
4557
parameter dat_width = 32;
4558
parameter burst_size = 4;
4559
input [dat_width-1:0] wbs_dat_i;
4560
input [adr_width-1:0] wbs_adr_i;
4561
input [dat_width/8-1:0]  wbs_sel_i;
4562
input [1:0]  wbs_bte_i;
4563
input [2:0]  wbs_cti_i;
4564
input wbs_we_i;
4565
input wbs_cyc_i;
4566
input wbs_stb_i;
4567 130 unneback
output [dat_width-1:0] wbs_dat_o;
4568 103 unneback
output wbs_ack_o;
4569
output wbs_stall_o;
4570
input [dat_width-1:0] readdata;
4571
input readdatavalid;
4572
output [dat_width-1:0] writedata;
4573
output [adr_width-1:0] address;
4574
output [dat_width/8-1:0]  be;
4575
output write;
4576
output read;
4577
output beginbursttransfer;
4578
output [3:0] burstcount;
4579
input waitrequest;
4580 136 unneback
input init_done;
4581 103 unneback
input clk, rst;
4582 136 unneback
// cnt1 - initiated read or writes
4583
// cnt2 - # of read or writes in pipeline
4584
reg [3:0] cnt1;
4585
reg [3:0] cnt2;
4586
reg next_state, state;
4587
localparam s0 = 1'b0;
4588
localparam s1 = 1'b1;
4589
wire eoc;
4590
always @ *
4591
begin
4592
    case (state)
4593
    s0: if (init_done & wbs_cyc_i) next_state <= s1;
4594
    s1:
4595
    default: next_state <= state;
4596
    end
4597
end
4598 103 unneback
always @ (posedge clk or posedge rst)
4599
if (rst)
4600 136 unneback
    state <= s0;
4601 103 unneback
else
4602 136 unneback
    state <= next_state;
4603
assign eoc = state==s1 & !(read | write) & (& !waitrequest & cnt2=;
4604
always @ (posedge clk or posedge rst)
4605
if (rst)
4606
    cnt1 <= 4'h0;
4607
else
4608
    if (read & !waitrequest & init_done)
4609
        cnt1 <= burst_size - 1;
4610
    else if (write & !waitrequest & init_done)
4611
        cnt1 <= cnt1 + 4'h1;
4612
    else if (next_state==idle)
4613
        cnt1 <= 4'h0;
4614
always @ (posedge clk or posedge rst)
4615
if (rst)
4616
    cnt2 <= 4'h0;
4617
else
4618
    if (read & !waitrequest & init_done)
4619
        cnt2 <= burst_size - 1;
4620
    else if (write & !waitrequest & init_done & )
4621
        cnt2 <= cnt1 + 4'h1;
4622
    else if (next_state==idle)
4623
        cnt2 <= 4'h0;
4624 103 unneback
reg wr_ack;
4625
always @ (posedge clk or posedge rst)
4626
if (rst)
4627
    wr_ack <= 1'b0;
4628
else
4629
    wr_ack <=  (wbs_we_i & wbs_cyc_i & wbs_stb_i & !wbs_stall_o);
4630
// to avalon
4631
assign writedata = wbs_dat_i;
4632
assign address = wbs_adr_i;
4633
assign be = wbs_sel_i;
4634 136 unneback
assign write = cnt!=4'h0 & wbs_cyc_i &  wbs_we_i;
4635
assign read  = cnt!=4'h0 & wbs_cyc_i & !wbs_we_i;
4636
assign beginbursttransfer = state==s0 & next_state==s1;
4637 103 unneback
assign burstcount = burst_size;
4638
// to wishbone
4639
assign wbs_dat_o = readdata;
4640
assign wbs_ack_o = wr_ack | readdatavalid;
4641
assign wbs_stall_o = waitrequest;
4642
endmodule
4643
module vl_wb_avalon_mem_cache (
4644
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i, wbs_dat_o, wbs_ack_o, wbs_stall_o, wbs_clk, wbs_rst,
4645
    readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst
4646
);
4647
// wishbone
4648
parameter wb_dat_width = 32;
4649
parameter wb_adr_width = 22;
4650
parameter wb_max_burst_width = 4;
4651
parameter wb_mode = "B4";
4652
// avalon
4653
parameter avalon_dat_width = 32;
4654 121 unneback
//localparam avalon_adr_width = wb_dat_width * wb_adr_width / avalon_dat_width;
4655 122 unneback
localparam avalon_adr_width =
4656
        (wb_dat_width==avalon_dat_width) ? wb_adr_width :
4657
        (wb_dat_width==avalon_dat_width*2) ? wb_adr_width+1 :
4658
        (wb_dat_width==avalon_dat_width*4) ? wb_adr_width+2 :
4659
        (wb_dat_width==avalon_dat_width*8) ? wb_adr_width+3 :
4660
        (wb_dat_width==avalon_dat_width*16) ? wb_adr_width+4 :
4661
        (wb_dat_width==avalon_dat_width*32) ? wb_adr_width+5 :
4662
        (wb_dat_width==avalon_dat_width/2) ? wb_adr_width-1 :
4663
        (wb_dat_width==avalon_dat_width/4) ? wb_adr_width-2 :
4664
        (wb_dat_width==avalon_dat_width/8) ? wb_adr_width-3 :
4665
        (wb_dat_width==avalon_dat_width/16) ? wb_adr_width-4 :
4666 123 unneback
        (wb_dat_width==avalon_dat_width/32) ? wb_adr_width-5 : 0;
4667 103 unneback
parameter avalon_burst_size = 4;
4668
// cache
4669
parameter async = 1;
4670
parameter nr_of_ways = 1;
4671
parameter aw_offset = 4;
4672
parameter aw_slot = 10;
4673
parameter valid_mem = 1;
4674
// shadow RAM
4675
parameter shadow_ram = 0;
4676
parameter shadow_ram_adr_width = 10;
4677
parameter shadow_ram_size = 1024;
4678
parameter shadow_ram_init = 2; // 0: no init, 1: from file, 2: with zero
4679
parameter shadow_ram_file = "vl_ram.v";
4680
input [wb_dat_width-1:0] wbs_dat_i;
4681
input [wb_adr_width-1:0] wbs_adr_i; // dont include a1,a0
4682
input [wb_dat_width/8-1:0] wbs_sel_i;
4683
input [2:0] wbs_cti_i;
4684
input [1:0] wbs_bte_i;
4685
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
4686
output [wb_dat_width-1:0] wbs_dat_o;
4687
output wbs_ack_o;
4688
output wbs_stall_o;
4689
input wbs_clk, wbs_rst;
4690
input [avalon_dat_width-1:0] readdata;
4691
input readdatavalid;
4692
output [avalon_dat_width-1:0] writedata;
4693
output [avalon_adr_width-1:0] address;
4694
output [avalon_dat_width/8-1:0]  be;
4695
output write;
4696
output read;
4697
output beginbursttransfer;
4698
output [3:0] burstcount;
4699
input waitrequest;
4700
input clk, rst;
4701
wire [wb_dat_width-1:0] wb1_dat_o;
4702
wire [wb_adr_width-1:0] wb1_adr_o;
4703
wire [wb_dat_width/8-1:0] wb1_sel_o;
4704
wire [2:0] wb1_cti_o;
4705
wire [1:0] wb1_bte_o;
4706
wire wb1_we_o;
4707
wire wb1_stb_o;
4708
wire wb1_cyc_o;
4709
wire wb1_stall_i;
4710
wire [wb_dat_width-1:0] wb1_dat_i;
4711
wire wb1_ack_i;
4712 129 unneback
wire [avalon_dat_width-1:0] wb2_dat_o;
4713
wire [avalon_adr_width-1:0] wb2_adr_o;
4714
wire [avalon_dat_width/8-1:0] wb2_sel_o;
4715 103 unneback
wire [2:0] wb2_cti_o;
4716
wire [1:0] wb2_bte_o;
4717
wire wb2_we_o;
4718
wire wb2_stb_o;
4719
wire wb2_cyc_o;
4720
wire wb2_stall_i;
4721 129 unneback
wire [avalon_dat_width-1:0] wb2_dat_i;
4722 103 unneback
wire wb2_ack_i;
4723
vl_wb_shadow_ram # ( .dat_width(wb_dat_width), .mode(wb_mode), .max_burst_width(wb_max_burst_width),
4724 120 unneback
                 .shadow_mem_adr_width(shadow_ram_adr_width), .shadow_mem_size(shadow_ram_size), .shadow_mem_init(shadow_ram_init), .shadow_mem_file(shadow_ram_file),
4725 103 unneback
                 .main_mem_adr_width(wb_adr_width))
4726
shadow_ram0 (
4727
    .wbs_dat_i(wbs_dat_i), .wbs_adr_i(wbs_adr_i), .wbs_cti_i(wbs_cti_i), .wbs_bte_i(wbs_bte_i), .wbs_sel_i(wbs_sel_i), .wbs_we_i(wbs_we_i), .wbs_stb_i(wbs_stb_i), .wbs_cyc_i(wbs_cyc_i),
4728
    .wbs_dat_o(wbs_dat_o), .wbs_ack_o(wbs_ack_o), .wbs_stall_o(wbs_stall_o),
4729
    .wbm_dat_o(wb1_dat_o), .wbm_adr_o(wb1_adr_o), .wbm_cti_o(wb1_cti_o), .wbm_bte_o(wb1_bte_o), .wbm_sel_o(wb1_sel_o), .wbm_we_o(wb1_we_o), .wbm_stb_o(wb1_stb_o), .wbm_cyc_o(wb1_cyc_o),
4730
    .wbm_dat_i(wb1_dat_i), .wbm_ack_i(wb1_ack_i), .wbm_stall_i(wb1_stall_i),
4731
    .wb_clk(wbs_clk), .wb_rst(wbs_rst));
4732
vl_wb_cache
4733
# ( .dw_s(wb_dat_width), .aw_s(wb_adr_width), .dw_m(avalon_dat_width), .wbs_mode(wb_mode), .wbs_max_burst_width(wb_max_burst_width), .async(async), .nr_of_ways(nr_of_ways), .aw_offset(aw_offset), .aw_slot(aw_slot), .valid_mem(valid_mem))
4734
cache0 (
4735
    .wbs_dat_i(wb1_dat_o), .wbs_adr_i(wb1_adr_o), .wbs_sel_i(wb1_sel_o), .wbs_cti_i(wb1_cti_o), .wbs_bte_i(wb1_bte_o), .wbs_we_i(wb1_we_o), .wbs_stb_i(wb1_stb_o), .wbs_cyc_i(wb1_cyc_o),
4736
    .wbs_dat_o(wb1_dat_i), .wbs_ack_o(wb1_ack_i), .wbs_stall_o(wb1_stall_i), .wbs_clk(wbs_clk), .wbs_rst(wbs_rst),
4737
    .wbm_dat_o(wb2_dat_o), .wbm_adr_o(wb2_adr_o), .wbm_sel_o(wb2_sel_o), .wbm_cti_o(wb2_cti_o), .wbm_bte_o(wb2_bte_o), .wbm_we_o(wb2_we_o), .wbm_stb_o(wb2_stb_o), .wbm_cyc_o(wb2_cyc_o),
4738
    .wbm_dat_i(wb2_dat_i), .wbm_ack_i(wb2_ack_i), .wbm_stall_i(wb2_stall_i), .wbm_clk(clk), .wbm_rst(rst));
4739
vl_wb_avalon_bridge # ( .adr_width(avalon_adr_width), .dat_width(avalon_dat_width), .burst_size(avalon_burst_size))
4740
bridge0 (
4741
        // wishbone slave side
4742
        .wbs_dat_i(wb2_dat_o), .wbs_adr_i(wb2_adr_o), .wbs_sel_i(wb2_sel_o), .wbs_bte_i(wb2_bte_o), .wbs_cti_i(wb2_cti_o), .wbs_we_i(wb2_we_o), .wbs_cyc_i(wb2_cyc_o), .wbs_stb_i(wb2_stb_o),
4743
        .wbs_dat_o(wb2_dat_i), .wbs_ack_o(wb2_ack_i), .wbs_stall_o(wb2_stall_i),
4744
        // avalon master side
4745
        .readdata(readdata), .readdatavalid(readdatavalid), .address(address), .read(read), .be(be), .write(write), .burstcount(burstcount), .writedata(writedata), .waitrequest(waitrequest), .beginbursttransfer(beginbursttransfer),
4746
        // common
4747
        .clk(clk), .rst(rst));
4748
endmodule
4749 136 unneback
module vl_wb_sdr_sdram (
4750
    // wisbone i/f
4751
    dat_i, adr_i, sel_i, we_i, cyc_i, stb_i, dat_o, ack_o, stall_o,
4752
    // SDR SDRAM
4753
    ba, a, cmd, cke, cs_n, dqm, dq_i, dq_o, dq_oe,
4754
    // system
4755
    clk, rst);
4756
    // external data bus size
4757
    parameter dat_size = 16;
4758
    // memory geometry parameters
4759
    parameter ba_size  = 2;
4760
    parameter row_size = 13;
4761
    parameter col_size = 9;
4762
    parameter cl = 2;
4763
    // memory timing parameters
4764
    parameter tRFC = 9;
4765
    parameter tRP  = 2;
4766
    parameter tRCD = 2;
4767
    parameter tMRD = 2;
4768
    // LMR
4769
    // [12:10] reserved
4770
    // [9]     WB, write burst; 0 - programmed burst length, 1 - single location
4771
    // [8:7]   OP Mode, 2'b00
4772
    // [6:4]   CAS Latency; 3'b010 - 2, 3'b011 - 3
4773
    // [3]     BT, Burst Type; 1'b0 - sequential, 1'b1 - interleaved
4774
    // [2:0]   Burst length; 3'b000 - 1, 3'b001 - 2, 3'b010 - 4, 3'b011 - 8, 3'b111 - full page
4775
    localparam init_wb = 1'b1;
4776
    localparam init_cl = (cl==2) ? 3'b010 : 3'b011;
4777
    localparam init_bt = 1'b0;
4778
    localparam init_bl = 3'b000;
4779
    input [dat_size-1:0] dat_i;
4780
    input [ba_size+col_size+row_size-1:0] adr_i;
4781
    input [dat_size/8-1:0] sel_i;
4782
    input we_i, cyc_i, stb_i;
4783
    output [dat_size-1:0] dat_o;
4784
    output ack_o;
4785
    output reg stall_o;
4786
    output [ba_size-1:0]    ba;
4787
    output reg [12:0]   a;
4788
    output reg [2:0]    cmd; // {ras,cas,we}
4789
    output cke, cs_n;
4790
    output reg [dat_size/8-1:0]    dqm;
4791
    output [dat_size-1:0]       dq_o;
4792
    output reg          dq_oe;
4793
    input  [dat_size-1:0]       dq_i;
4794
    input clk, rst;
4795
    wire [ba_size-1:0]   bank;
4796
    wire [row_size-1:0] row;
4797
    wire [col_size-1:0] col;
4798
    wire [0:31]  shreg;
4799
    wire                ref_cnt_zero;
4800
    reg                 refresh_req;
4801
    wire ack_rd, rd_ack_emptyflag;
4802
    wire ack_wr;
4803
    // to keep track of open rows per bank
4804
    reg [row_size-1:0]   open_row[0:3];
4805
    reg [0:3]            open_ba;
4806
    reg                 current_bank_closed, current_row_open;
4807
    parameter rfr_length = 10;
4808
    parameter rfr_wrap_value = 1010;
4809
    parameter [2:0] cmd_nop = 3'b111,
4810
                    cmd_act = 3'b011,
4811
                    cmd_rd  = 3'b101,
4812
                    cmd_wr  = 3'b100,
4813
                    cmd_pch = 3'b010,
4814
                    cmd_rfr = 3'b001,
4815
                    cmd_lmr = 3'b000;
4816
// ctrl FSM
4817
    assign cke = 1'b1;
4818
    assign cs_n = 1'b0;
4819
    reg [2:0] state, next;
4820
    function [12:0] a10_fix;
4821
        input [col_size-1:0] a;
4822
        integer i;
4823
    begin
4824
        for (i=0;i<13;i=i+1) begin
4825
            if (i<10)
4826
              if (i<col_size)
4827
                a10_fix[i] = a[i];
4828
              else
4829
                a10_fix[i] = 1'b0;
4830
            else if (i==10)
4831
              a10_fix[i] = 1'b0;
4832
            else
4833
              if (i<col_size)
4834
                a10_fix[i] = a[i-1];
4835
              else
4836
                a10_fix[i] = 1'b0;
4837
        end
4838
    end
4839
    endfunction
4840
    assign {bank,row,col} = adr_i;
4841
    always @ (posedge clk or posedge rst)
4842
    if (rst)
4843
       state <= 3'b000;
4844
    else
4845
       state <= next;
4846
    always @*
4847
    begin
4848
        next = state;
4849
        case (state)
4850
        3'b000:
4851
            if (shreg[3+tRP+tRFC+tRFC+tMRD]) next = 3'b001;
4852
        3'b001:
4853
            if (refresh_req) next = 3'b010;
4854
            else if (cyc_i & stb_i & rd_ack_emptyflag) next = 3'b011;
4855
        3'b010:
4856
            if (shreg[tRP+tRFC-2]) next = 3'b001; // take away two cycles because no cmd will be issued in idle and adr
4857
        3'b011:
4858
            if (current_bank_closed) next = 3'b101;
4859
            else if (current_row_open) next = 3'b111;
4860
            else next = 3'b100;
4861
        3'b100:
4862
            if (shreg[tRP]) next = 3'b101;
4863
        3'b101:
4864
            if (shreg[tRCD]) next = 3'b111;
4865
        3'b111:
4866
            if (!stb_i) next = 3'b001;
4867
        endcase
4868
    end
4869
    // counter
4870
    vl_cnt_shreg_clear # ( .length(32))
4871
        cnt0 (
4872
            .clear(state!=next),
4873
            .q(shreg),
4874
            .rst(rst),
4875
            .clk(clk));
4876
    // ba, a, cmd
4877
    // outputs dependent on state vector
4878
    always @ (*)
4879
        begin
4880
            {a,cmd} = {13'd0,cmd_nop};
4881
            dqm = 2'b11;
4882
            dq_oe = 1'b0;
4883
            stall_o = 1'b1;
4884
            case (state)
4885
            3'b000:
4886
                if (shreg[3]) begin
4887
                    {a,cmd} = {13'b0010000000000, cmd_pch};
4888
                end else if (shreg[3+tRP] | shreg[3+tRP+tRFC])
4889
                    {a,cmd} = {13'd0, cmd_rfr};
4890
                else if (shreg[3+tRP+tRFC+tRFC])
4891
                    {a,cmd} = {3'b000,init_wb,2'b00,init_cl,init_bt,init_bl,cmd_lmr};
4892
            3'b010:
4893
                if (shreg[0])
4894
                    {a,cmd} = {13'b0010000000000, cmd_pch};
4895
                else if (shreg[tRP])
4896
                    {a,cmd} = {13'd0, cmd_rfr};
4897
            3'b100:
4898
                if (shreg[0])
4899
                    {a,cmd} = {13'd0,cmd_pch};
4900
            3'b101:
4901
                if (shreg[0])
4902
                    {a[row_size-1:0],cmd} = {row,cmd_act};
4903
            3'b111:
4904
                begin
4905
                    if (we_i)
4906
                        cmd = cmd_wr;
4907
                    else
4908
                        cmd = cmd_rd;
4909
                    if (we_i)
4910
                        dqm = ~sel_i;
4911
                    else
4912
                        dqm = 2'b00;
4913
                    if (we_i)
4914
                        dq_oe = 1'b1;
4915
                    a = a10_fix(col);
4916
                    stall_o = 1'b0;
4917
                end
4918
            endcase
4919
        end
4920
    assign ba = bank;
4921
    // precharge individual bank A10=0
4922
    // precharge all bank A10=1
4923
    genvar i;
4924
    generate
4925
    for (i=0;i<2<<ba_size-1;i=i+1) begin : open_ba_logic
4926
        always @ (posedge clk or posedge rst)
4927
        if (rst)
4928
            {open_ba[i],open_row[i]} <= {1'b0,{row_size{1'b0}}};
4929
        else
4930
            if (cmd==cmd_pch & (a[10] | bank==i))
4931
                open_ba[i] <= 1'b0;
4932
            else if (cmd==cmd_act & bank==i)
4933
                {open_ba[i],open_row[i]} <= {1'b1,row};
4934
    end
4935
    endgenerate
4936
    // bank and row open ?
4937
    always @ (posedge clk or posedge rst)
4938
    if (rst)
4939
       {current_bank_closed, current_row_open} <= {1'b1, 1'b0};
4940
    else
4941
       {current_bank_closed, current_row_open} <= {!(open_ba[bank]), open_row[bank]==row};
4942
    // refresh counter
4943
    vl_cnt_lfsr_zq # ( .length(rfr_length), .wrap_value (rfr_wrap_value)) ref_counter0( .zq(ref_cnt_zero), .rst(rst), .clk(clk));
4944
    always @ (posedge clk or posedge rst)
4945
    if (rst)
4946
        refresh_req <= 1'b0;
4947
    else
4948
        if (ref_cnt_zero)
4949
            refresh_req <= 1'b1;
4950
        else if (state==3'b010)
4951
            refresh_req <= 1'b0;
4952
    assign dat_o = dq_i;
4953
    assign ack_wr = (state==3'b111 & we_i);
4954
    vl_delay_emptyflag # ( .depth(cl+2)) delay0 ( .d(state==3'b111 & stb_i & !we_i), .q(ack_rd), .emptyflag(rd_ack_emptyflag), .clk(clk), .rst(rst));
4955
    assign ack_o = ack_rd | ack_wr;
4956
    assign dq_o = dat_i;
4957
endmodule
4958
module vl_wb_sdr_sdram_ctrl (
4959
    // WB i/f
4960
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
4961
    wbs_dat_o, wbs_ack_o, wbs_stall_o,
4962
    // SDR SDRAM
4963
    mem_ba, mem_a, mem_cmd, mem_cke, mem_cs_n, mem_dqm, mem_dq_i, mem_dq_o, mem_dq_oe,
4964
    // system
4965
    wb_clk, wb_rst, mem_clk, mem_rst);
4966
    // WB slave
4967
    parameter wbs_dat_width = 32;
4968
    parameter wbs_adr_width = 24;
4969
    parameter wbs_mode = "B3";
4970
    parameter wbs_max_burst_width = 4;
4971
    // Shadow RAM
4972
    parameter shadow_mem_adr_width = 10;
4973
    parameter shadow_mem_size = 1024;
4974
    parameter shadow_mem_init = 2;
4975
    parameter shadow_mem_file = "vl_ram.v";
4976
    // Cache
4977
    parameter cache_async = 1; // wbs_clk != wbm_clk
4978
    parameter cache_nr_of_ways = 1;
4979
    parameter cache_aw_offset = 4; // 4 => 16 words per cache line
4980
    parameter cache_aw_slot = 10;
4981
    parameter cache_valid_mem = 0;
4982
    parameter cache_debug = 0;
4983
    // SDRAM parameters
4984
    parameter mem_dat_size = 16;
4985
    parameter mem_ba_size  = 2;
4986
    parameter mem_row_size = 13;
4987
    parameter mem_col_size = 9;
4988
    parameter mem_cl = 2;
4989
    parameter mem_tRFC = 9;
4990
    parameter mem_tRP  = 2;
4991
    parameter mem_tRCD = 2;
4992
    parameter mem_tMRD = 2;
4993
    parameter mem_rfr_length = 10;
4994
    parameter mem_rfr_wrap_value = 1010;
4995
    input [wbs_dat_width-1:0] wbs_dat_i;
4996
    input [wbs_adr_width-1:0] wbs_adr_i;
4997
    input [2:0] wbs_cti_i;
4998
    input [1:0] wbs_bte_i;
4999
    input [wbs_dat_width/8-1:0] wbs_sel_i;
5000
    input wbs_we_i, wbs_stb_i, wbs_cyc_i;
5001
    output [wbs_dat_width-1:0] wbs_dat_o;
5002
    output wbs_ack_o;
5003
    output wbs_stall_o;
5004
    output [mem_ba_size-1:0]    mem_ba;
5005
    output reg [12:0]           mem_a;
5006
    output reg [2:0]            mem_cmd; // {ras,cas,we}
5007
    output                      mem_cke, mem_cs_n;
5008
    output reg [mem_dat_size/8-1:0] mem_dqm;
5009
    output [mem_dat_size-1:0]       mem_dq_o;
5010
    output reg                  mem_dq_oe;
5011
    input  [mem_dat_size-1:0]       mem_dq_i;
5012
    input wb_clk, wb_rst, mem_clk, mem_rst;
5013
    // wbm1
5014
    wire [wbs_dat_width-1:0] wbm1_dat_o;
5015
    wire [wbs_adr_width-1:0] wbm1_adr_o;
5016
    wire [2:0] wbm1_cti_o;
5017
    wire [1:0] wbm1_bte_o;
5018
    wire [wbs_dat_width/8-1:0] wbm1_sel_o;
5019
    wire wbm1_we_o, wbm1_stb_o, wbm1_cyc_o;
5020
    wire [wbs_dat_width-1:0] wbm1_dat_i;
5021
    wire wbm1_ack_i, wbm1_stall_i;
5022
    // wbm2
5023
    wire [mem_dat_size-1:0] wbm2_dat_o;
5024
    wire [mem_ba_size+mem_row_size+mem_col_size-1:0] wbm2_adr_o;
5025
    wire [2:0] wbm2_cti_o;
5026
    wire [1:0] wbm2_bte_o;
5027
    wire [mem_dat_size/8-1:0] wbm2_sel_o;
5028
    wire wbm2_we_o, wbm2_stb_o, wbm2_cyc_o;
5029
    wire [mem_dat_size-1:0] wbm2_dat_i;
5030
    wire wbm2_ack_i, wbm2_stall_i;
5031
vl_wb_shadow_ram # (
5032
    .shadow_mem_adr_width(shadow_mem_adr_width), .shadow_mem_size(shadow_mem_size), .shadow_mem_init(shadow_mem_init), .shadow_mem_file(shadow_mem_file), .main_mem_adr_width(wbs_adr_width), .dat_width(wbs_dat_width), .mode(wbs_mode), .max_burst_width(wbs_max_burst_width) )
5033
shadow_ram0 (
5034
    .wbs_dat_i(wbs_dat_i),
5035
    .wbs_adr_i(wbs_adr_i),
5036
    .wbs_cti_i(wbs_cti_i),
5037
    .wbs_bte_i(wbs_bte_i),
5038
    .wbs_sel_i(wbs_sel_i),
5039
    .wbs_we_i (wbs_we_i),
5040
    .wbs_stb_i(wbs_stb_i),
5041
    .wbs_cyc_i(wbs_cyc_i),
5042
    .wbs_dat_o(wbs_dat_o),
5043
    .wbs_ack_o(wbs_ack_o),
5044
    .wbs_stall_o(wbs_stall_o),
5045
    .wbm_dat_o(wbm1_dat_o),
5046
    .wbm_adr_o(wbm1_adr_o),
5047
    .wbm_cti_o(wbm1_cti_o),
5048
    .wbm_bte_o(wbm1_bte_o),
5049
    .wbm_sel_o(wbm1_sel_o),
5050
    .wbm_we_o(wbm1_we_o),
5051
    .wbm_stb_o(wbm1_stb_o),
5052
    .wbm_cyc_o(wbm1_cyc_o),
5053
    .wbm_dat_i(wbm1_dat_i),
5054
    .wbm_ack_i(wbm1_ack_i),
5055
    .wbm_stall_i(wbm1_stall_i),
5056
    .wb_clk(wb_clk),
5057
    .wb_rst(wb_rst) );
5058
vl_wb_cache # (
5059
    .dw_s(wbs_dat_width), .aw_s(wbs_adr_width), .dw_m(mem_dat_size), .wbs_max_burst_width(cache_aw_offset), .wbs_mode(wbs_mode), .async(cache_async), .nr_of_ways(cache_nr_of_ways), .aw_offset(cache_aw_offset), .aw_slot(cache_aw_slot), .valid_mem(cache_valid_mem) )
5060
cache0 (
5061
    .wbs_dat_i(wbm1_dat_o),
5062
    .wbs_adr_i(wbm1_adr_o),
5063
    .wbs_sel_i(wbm1_sel_o),
5064
    .wbs_cti_i(wbm1_cti_o),
5065
    .wbs_bte_i(wbm1_bte_o),
5066
    .wbs_we_i (wbm1_we_o),
5067
    .wbs_stb_i(wbm1_stb_o),
5068
    .wbs_cyc_i(wbm1_cyc_o),
5069
    .wbs_dat_o(wbm1_dat_i),
5070
    .wbs_ack_o(wbm1_ack_i),
5071
    .wbs_stall_o(wbm1_stall_i),
5072
    .wbs_clk(wb_clk),
5073
    .wbs_rst(wb_rst),
5074
    .wbm_dat_o(wbm2_dat_o),
5075
    .wbm_adr_o(wbm2_adr_o),
5076
    .wbm_sel_o(wbm2_sel_o),
5077
    .wbm_cti_o(wbm2_cti_o),
5078
    .wbm_bte_o(wbm2_bte_o),
5079
    .wbm_we_o (wbm2_we_o),
5080
    .wbm_stb_o(wbm2_stb_o),
5081
    .wbm_cyc_o(wbm2_cyc_o),
5082
    .wbm_dat_i(wbm2_dat_i),
5083
    .wbm_ack_i(wbm2_ack_i),
5084
    .wbm_stall_i(wbm2_stall_i),
5085
    .wbm_clk(mem_clk),
5086
    .wbm_rst(mem_rst) );
5087
vl_wb_sdr_sdram # (
5088
    .dat_size(mem_dat_size), .ba_size(mem_ba_size), .row_size(mem_row_size), .col_size(mem_col_size), .cl(mem_cl), .tRFC(mem_tRFC), .tRP(mem_tRP), .tRCD(mem_tRCD), .tMRD(mem_tMRD), .rfr_length(mem_rfr_length), .rfr_wrap_value(mem_rfr_wrap_value) )
5089
ctrl0(
5090
    // wisbone i/f
5091
    .dat_i(wbm2_dat_o),
5092
    .adr_i(wbm2_adr_o),
5093
    .sel_i(wbm2_sel_o),
5094
    .we_i (wbm2_we_o),
5095
    .cyc_i(wbm2_cyc_o),
5096
    .stb_i(wbm2_stb_o),
5097
    .dat_o(wbm2_dat_i),
5098
    .ack_o(wbm2_ack_i),
5099
    .stall_o(wbm2_stall_i),
5100
    // SDR SDRAM
5101
    .ba(mem_ba),
5102
    .a(mem_a),
5103
    .cmd(mem_cmd),
5104
    .cke(mem_cke),
5105
    .cs_n(mem_cs_n),
5106
    .dqm(mem_dqm),
5107
    .dq_i(mem_dq_i),
5108
    .dq_o(mem_dq_o),
5109
    .dq_oe(mem_dq_oe),
5110
    // system
5111
    .clk(mem_clk),
5112
    .rst(mem_rst) );
5113
endmodule
5114 18 unneback
//////////////////////////////////////////////////////////////////////
5115
////                                                              ////
5116
////  Arithmetic functions                                        ////
5117
////                                                              ////
5118
////  Description                                                 ////
5119
////  Arithmetic functions for ALU and DSP                        ////
5120
////                                                              ////
5121
////                                                              ////
5122
////  To Do:                                                      ////
5123
////   -                                                          ////
5124
////                                                              ////
5125
////  Author(s):                                                  ////
5126
////      - Michael Unneback, unneback@opencores.org              ////
5127
////        ORSoC AB                                              ////
5128
////                                                              ////
5129
//////////////////////////////////////////////////////////////////////
5130
////                                                              ////
5131
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
5132
////                                                              ////
5133
//// This source file may be used and distributed without         ////
5134
//// restriction provided that this copyright statement is not    ////
5135
//// removed from the file and that any derivative work contains  ////
5136
//// the original copyright notice and the associated disclaimer. ////
5137
////                                                              ////
5138
//// This source file is free software; you can redistribute it   ////
5139
//// and/or modify it under the terms of the GNU Lesser General   ////
5140
//// Public License as published by the Free Software Foundation; ////
5141
//// either version 2.1 of the License, or (at your option) any   ////
5142
//// later version.                                               ////
5143
////                                                              ////
5144
//// This source is distributed in the hope that it will be       ////
5145
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
5146
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
5147
//// PURPOSE.  See the GNU Lesser General Public License for more ////
5148
//// details.                                                     ////
5149
////                                                              ////
5150
//// You should have received a copy of the GNU Lesser General    ////
5151
//// Public License along with this source; if not, download it   ////
5152
//// from http://www.opencores.org/lgpl.shtml                     ////
5153
////                                                              ////
5154
//////////////////////////////////////////////////////////////////////
5155
// signed multiplication
5156
module vl_mults (a,b,p);
5157
parameter operand_a_width = 18;
5158
parameter operand_b_width = 18;
5159
parameter result_hi = 35;
5160
parameter result_lo = 0;
5161
input [operand_a_width-1:0] a;
5162
input [operand_b_width-1:0] b;
5163
output [result_hi:result_lo] p;
5164
wire signed [operand_a_width-1:0] ai;
5165
wire signed [operand_b_width-1:0] bi;
5166
wire signed [operand_a_width+operand_b_width-1:0] result;
5167
    assign ai = a;
5168
    assign bi = b;
5169
    assign result = ai * bi;
5170
    assign p = result[result_hi:result_lo];
5171
endmodule
5172
module vl_mults18x18 (a,b,p);
5173
input [17:0] a,b;
5174
output [35:0] p;
5175
vl_mult
5176
    # (.operand_a_width(18), .operand_b_width(18))
5177
    mult0 (.a(a), .b(b), .p(p));
5178
endmodule
5179
// unsigned multiplication
5180
module vl_mult (a,b,p);
5181
parameter operand_a_width = 18;
5182
parameter operand_b_width = 18;
5183
parameter result_hi = 35;
5184
parameter result_lo = 0;
5185
input [operand_a_width-1:0] a;
5186
input [operand_b_width-1:0] b;
5187
output [result_hi:result_hi] p;
5188
wire [operand_a_width+operand_b_width-1:0] result;
5189
    assign result = a * b;
5190
    assign p = result[result_hi:result_lo];
5191
endmodule
5192
// shift unit
5193
// supporting the following shift functions
5194
//   SLL
5195
//   SRL
5196
//   SRA
5197
module vl_shift_unit_32( din, s, dout, opcode);
5198
input [31:0] din; // data in operand
5199
input [4:0] s; // shift operand
5200
input [1:0] opcode;
5201
output [31:0] dout;
5202
parameter opcode_sll = 2'b00;
5203 149 unneback
parameter opcode_srl = 2'b01;
5204 18 unneback
parameter opcode_sra = 2'b10;
5205 149 unneback
parameter opcode_ror = 2'b11;
5206
parameter mult=0; // if set to 1 implemented based on multipliers which saves LUT
5207
generate
5208
if (mult==1) begin : impl_mult
5209 18 unneback
wire sll, sra;
5210
assign sll = opcode == opcode_sll;
5211
assign sra = opcode == opcode_sra;
5212
wire [15:1] s1;
5213
wire [3:0] sign;
5214
wire [7:0] tmp [0:3];
5215
// first stage is multiplier based
5216
// shift operand as fractional 8.7
5217
assign s1[15] = sll & s[2:0]==3'd7;
5218
assign s1[14] = sll & s[2:0]==3'd6;
5219
assign s1[13] = sll & s[2:0]==3'd5;
5220
assign s1[12] = sll & s[2:0]==3'd4;
5221
assign s1[11] = sll & s[2:0]==3'd3;
5222
assign s1[10] = sll & s[2:0]==3'd2;
5223
assign s1[ 9] = sll & s[2:0]==3'd1;
5224
assign s1[ 8] = s[2:0]==3'd0;
5225
assign s1[ 7] = !sll & s[2:0]==3'd1;
5226
assign s1[ 6] = !sll & s[2:0]==3'd2;
5227
assign s1[ 5] = !sll & s[2:0]==3'd3;
5228
assign s1[ 4] = !sll & s[2:0]==3'd4;
5229
assign s1[ 3] = !sll & s[2:0]==3'd5;
5230
assign s1[ 2] = !sll & s[2:0]==3'd6;
5231
assign s1[ 1] = !sll & s[2:0]==3'd7;
5232
assign sign[3] = din[31] & sra;
5233
assign sign[2] = sign[3] & (&din[31:24]);
5234
assign sign[1] = sign[2] & (&din[23:16]);
5235
assign sign[0] = sign[1] & (&din[15:8]);
5236
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
5237
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
5238
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
5239
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
5240
// second stage is multiplexer based
5241
// shift on byte level
5242
// mux byte 3
5243
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
5244
                     (sll & s[4:3]==2'b01) ? tmp[2] :
5245
                     (sll & s[4:3]==2'b10) ? tmp[1] :
5246
                     (sll & s[4:3]==2'b11) ? tmp[0] :
5247
                     {8{sign[3]}};
5248
// mux byte 2
5249
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
5250
                     (sll & s[4:3]==2'b01) ? tmp[1] :
5251
                     (sll & s[4:3]==2'b10) ? tmp[0] :
5252
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
5253
                     (s[4:3]==2'b01) ? tmp[3] :
5254
                     {8{sign[3]}};
5255
// mux byte 1
5256
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
5257
                     (sll & s[4:3]==2'b01) ? tmp[0] :
5258
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
5259
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
5260
                     (s[4:3]==2'b01) ? tmp[2] :
5261
                     (s[4:3]==2'b10) ? tmp[3] :
5262
                     {8{sign[3]}};
5263
// mux byte 0
5264
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
5265
                     (sll) ?  {8{1'b0}}:
5266
                     (s[4:3]==2'b01) ? tmp[1] :
5267
                     (s[4:3]==2'b10) ? tmp[2] :
5268
                     tmp[3];
5269 149 unneback
end else begin : impl_classic
5270
reg [31:0] dout;
5271
`ifdef SYSTEMVERILOG
5272
always_comb
5273
`else
5274
always @ (din or s or opcode)
5275
`endif
5276
    case (opcode)
5277
    opcode_sll: dout = din << s;
5278
    opcode_srl: dout = din >> s;
5279 150 unneback
    opcode_sra: dout = (din >> s) | ({32,din[31]}} << (6'd32-{1'b0,s}));
5280 149 unneback
    //opcode_ror: dout = not yet implemented
5281
    default: dout = din << s;
5282
    endcase
5283
end
5284
engenerate
5285 18 unneback
endmodule
5286
// logic unit
5287
// supporting the following logic functions
5288
//    a and b
5289
//    a or  b
5290
//    a xor b
5291
//    not b
5292
module vl_logic_unit( a, b, result, opcode);
5293
parameter width = 32;
5294
parameter opcode_and = 2'b00;
5295
parameter opcode_or  = 2'b01;
5296
parameter opcode_xor = 2'b10;
5297
input [width-1:0] a,b;
5298
output [width-1:0] result;
5299
input [1:0] opcode;
5300
assign result = (opcode==opcode_and) ? a & b :
5301
                (opcode==opcode_or)  ? a | b :
5302
                (opcode==opcode_xor) ? a ^ b :
5303
                b;
5304
endmodule
5305 140 unneback
module vl_arith_unit ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
5306
parameter width = 32;
5307
parameter opcode_add = 1'b0;
5308
parameter opcode_sub = 1'b1;
5309
input [width-1:0] a,b;
5310
input c_in, add_sub, sign;
5311
output [width-1:0] result;
5312
output c_out, z, ovfl;
5313
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
5314
assign z = (result=={width{1'b0}});
5315
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
5316
               (~a[width-1] & ~b[width-1] &  result[width-1]);
5317
endmodule
5318
module vl_count_unit (din, dout, opcode);
5319
parameter width = 32;
5320
input [width-1:0] din;
5321
output [width-1:0] dout;
5322
input opcode;
5323
integer i;
5324
wire [width/32+4:0] ff1, fl1;
5325
/*
5326
always @(din) begin
5327
    ff1 = 0; i = 0;
5328
    while (din[i] == 0 && i < width) begin // complex condition
5329
        ff1 = ff1 + 1;
5330
        i = i + 1;
5331
    end
5332
end
5333
always @(din) begin
5334
    fl1 = width; i = width-1;
5335
    while (din[i] == 0 && i >= width) begin // complex condition
5336
        fl1 = fl1 - 1;
5337
        i = i - 1;
5338
    end
5339
end
5340
*/
5341
generate
5342
if (width==32) begin
5343
    assign ff1 = din[0] ? 6'd1 :
5344
                 din[1] ? 6'd2 :
5345
                 din[2] ? 6'd3 :
5346
                 din[3] ? 6'd4 :
5347
                 din[4] ? 6'd5 :
5348
                 din[5] ? 6'd6 :
5349
                 din[6] ? 6'd7 :
5350
                 din[7] ? 6'd8 :
5351
                 din[8] ? 6'd9 :
5352
                 din[9] ? 6'd10 :
5353
                 din[10] ? 6'd11 :
5354
                 din[11] ? 6'd12 :
5355
                 din[12] ? 6'd13 :
5356
                 din[13] ? 6'd14 :
5357
                 din[14] ? 6'd15 :
5358
                 din[15] ? 6'd16 :
5359
                 din[16] ? 6'd17 :
5360
                 din[17] ? 6'd18 :
5361
                 din[18] ? 6'd19 :
5362
                 din[19] ? 6'd20 :
5363
                 din[20] ? 6'd21 :
5364
                 din[21] ? 6'd22 :
5365
                 din[22] ? 6'd23 :
5366
                 din[23] ? 6'd24 :
5367
                 din[24] ? 6'd25 :
5368
                 din[25] ? 6'd26 :
5369
                 din[26] ? 6'd27 :
5370
                 din[27] ? 6'd28 :
5371
                 din[28] ? 6'd29 :
5372
                 din[29] ? 6'd30 :
5373
                 din[30] ? 6'd31 :
5374
                 din[31] ? 6'd32 :
5375
                 6'd0;
5376
    assign fl1 = din[31] ? 6'd32 :
5377
                 din[30] ? 6'd31 :
5378
                 din[29] ? 6'd30 :
5379
                 din[28] ? 6'd29 :
5380
                 din[27] ? 6'd28 :
5381
                 din[26] ? 6'd27 :
5382
                 din[25] ? 6'd26 :
5383
                 din[24] ? 6'd25 :
5384
                 din[23] ? 6'd24 :
5385
                 din[22] ? 6'd23 :
5386
                 din[21] ? 6'd22 :
5387
                 din[20] ? 6'd21 :
5388
                 din[19] ? 6'd20 :
5389
                 din[18] ? 6'd19 :
5390
                 din[17] ? 6'd18 :
5391
                 din[16] ? 6'd17 :
5392
                 din[15] ? 6'd16 :
5393
                 din[14] ? 6'd15 :
5394
                 din[13] ? 6'd14 :
5395
                 din[12] ? 6'd13 :
5396
                 din[11] ? 6'd12 :
5397
                 din[10] ? 6'd11 :
5398
                 din[9] ? 6'd10 :
5399
                 din[8] ? 6'd9 :
5400
                 din[7] ? 6'd8 :
5401
                 din[6] ? 6'd7 :
5402
                 din[5] ? 6'd6 :
5403
                 din[4] ? 6'd5 :
5404
                 din[3] ? 6'd4 :
5405
                 din[2] ? 6'd3 :
5406
                 din[1] ? 6'd2 :
5407
                 din[0] ? 6'd1 :
5408
                 6'd0;
5409
    assign dout = (!opcode) ? {{26{1'b0}}, ff1} : {{26{1'b0}}, fl1};
5410
end
5411
endgenerate
5412
generate
5413
if (width==64) begin
5414
    assign ff1 = 7'd0;
5415
    assign fl1 = 7'd0;
5416
    assign dout = (!opcode) ? {{57{1'b0}}, ff1} : {{57{1'b0}}, fl1};
5417
end
5418
endgenerate
5419
endmodule
5420
module vl_ext_unit ( a, b, F, result, opcode);
5421
parameter width = 32;
5422
input [width-1:0] a, b;
5423
input F;
5424
output reg [width-1:0] result;
5425
input [2:0] opcode;
5426
generate
5427
if (width==32) begin
5428
always @ (a or b or F or opcode)
5429
begin
5430
    case (opcode)
5431
    3'b000: result = {{24{1'b0}},a[7:0]};
5432
    3'b001: result = {{24{a[7]}},a[7:0]};
5433
    3'b010: result = {{16{1'b0}},a[7:0]};
5434
    3'b011: result = {{16{a[15]}},a[15:0]};
5435
    3'b110: result = (F) ? a : b;
5436
    default: result = {b[15:0],16'h0000};
5437
    endcase
5438
end
5439
end
5440
endgenerate
5441
generate
5442
if (width==64) begin
5443
always @ (a or b or F or opcode)
5444
begin
5445
    case (opcode)
5446
    3'b000: result = {{56{1'b0}},a[7:0]};
5447
    3'b001: result = {{56{a[7]}},a[7:0]};
5448
    3'b010: result = {{48{1'b0}},a[7:0]};
5449
    3'b011: result = {{48{a[15]}},a[15:0]};
5450
    3'b110: result = (F) ? a : b;
5451
    default: result = {32'h00000000,b[15:0],16'h0000};
5452
    endcase
5453
end
5454
end
5455
endgenerate
5456
endmodule

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