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1 6 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
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////  Versatile library, clock and reset                          ////
4
////                                                              ////
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////  Description                                                 ////
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////  Logic related to clock and reset                            ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - add more different registers                             ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
17
////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
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//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
// Global buffer
43
// usage:
44
// use to enable global buffers for high fan out signals such as clock and reset
45 21 unneback
//altera
46 6 unneback
 // ALTERA
47
 //ACTEL
48
// sync reset
49 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
50 6 unneback
// output active high global reset sync with two DFFs 
51
`timescale 1 ns/100 ps
52
module vl_sync_rst ( rst_n_i, rst_o, clk);
53
input rst_n_i, clk;
54
output rst_o;
55 18 unneback
reg [1:0] tmp;
56 6 unneback
always @ (posedge clk or negedge rst_n_i)
57
if (!rst_n_i)
58 17 unneback
        tmp <= 2'b11;
59 6 unneback
else
60 17 unneback
        tmp <= {1'b0,tmp[0]};
61
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
62 6 unneback
endmodule
63
// vl_pll
64
 //altera
65
 //actel
66
//////////////////////////////////////////////////////////////////////
67
////                                                              ////
68
////  Versatile library, registers                                ////
69
////                                                              ////
70
////  Description                                                 ////
71
////  Different type of registers                                 ////
72
////                                                              ////
73
////                                                              ////
74
////  To Do:                                                      ////
75
////   - add more different registers                             ////
76
////                                                              ////
77
////  Author(s):                                                  ////
78
////      - Michael Unneback, unneback@opencores.org              ////
79
////        ORSoC AB                                              ////
80
////                                                              ////
81
//////////////////////////////////////////////////////////////////////
82
////                                                              ////
83
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
84
////                                                              ////
85
//// This source file may be used and distributed without         ////
86
//// restriction provided that this copyright statement is not    ////
87
//// removed from the file and that any derivative work contains  ////
88
//// the original copyright notice and the associated disclaimer. ////
89
////                                                              ////
90
//// This source file is free software; you can redistribute it   ////
91
//// and/or modify it under the terms of the GNU Lesser General   ////
92
//// Public License as published by the Free Software Foundation; ////
93
//// either version 2.1 of the License, or (at your option) any   ////
94
//// later version.                                               ////
95
////                                                              ////
96
//// This source is distributed in the hope that it will be       ////
97
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
98
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
99
//// PURPOSE.  See the GNU Lesser General Public License for more ////
100
//// details.                                                     ////
101
////                                                              ////
102
//// You should have received a copy of the GNU Lesser General    ////
103
//// Public License along with this source; if not, download it   ////
104
//// from http://www.opencores.org/lgpl.shtml                     ////
105
////                                                              ////
106
//////////////////////////////////////////////////////////////////////
107 18 unneback
module vl_dff ( d, q, clk, rst);
108 6 unneback
        parameter width = 1;
109
        parameter reset_value = 0;
110
        input [width-1:0] d;
111
        input clk, rst;
112
        output reg [width-1:0] q;
113
        always @ (posedge clk or posedge rst)
114
        if (rst)
115
                q <= reset_value;
116
        else
117
                q <= d;
118
endmodule
119 18 unneback
module vl_dff_array ( d, q, clk, rst);
120 6 unneback
        parameter width = 1;
121
        parameter depth = 2;
122
        parameter reset_value = 1'b0;
123
        input [width-1:0] d;
124
        input clk, rst;
125
        output [width-1:0] q;
126
        reg  [0:depth-1] q_tmp [width-1:0];
127
        integer i;
128
        always @ (posedge clk or posedge rst)
129
        if (rst) begin
130
            for (i=0;i<depth;i=i+1)
131
                q_tmp[i] <= {width{reset_value}};
132
        end else begin
133
            q_tmp[0] <= d;
134
            for (i=1;i<depth;i=i+1)
135
                q_tmp[i] <= q_tmp[i-1];
136
        end
137
    assign q = q_tmp[depth-1];
138
endmodule
139 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
140 6 unneback
        parameter width = 1;
141
        parameter reset_value = 0;
142
        input [width-1:0] d;
143
        input ce, clk, rst;
144
        output reg [width-1:0] q;
145
        always @ (posedge clk or posedge rst)
146
        if (rst)
147
                q <= reset_value;
148
        else
149
                if (ce)
150
                        q <= d;
151
endmodule
152 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
153 8 unneback
        parameter width = 1;
154
        parameter reset_value = 0;
155
        input [width-1:0] d;
156 10 unneback
        input ce, clear, clk, rst;
157 8 unneback
        output reg [width-1:0] q;
158
        always @ (posedge clk or posedge rst)
159
        if (rst)
160
            q <= reset_value;
161
        else
162
            if (ce)
163
                if (clear)
164
                    q <= {width{1'b0}};
165
                else
166
                    q <= d;
167
endmodule
168 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
169
        parameter width = 1;
170
        parameter reset_value = 0;
171
        input [width-1:0] d;
172
        input ce, set, clk, rst;
173
        output reg [width-1:0] q;
174
        always @ (posedge clk or posedge rst)
175
        if (rst)
176
            q <= reset_value;
177
        else
178
            if (ce)
179
                if (set)
180
                    q <= {width{1'b1}};
181
                else
182
                    q <= d;
183
endmodule
184 6 unneback
// megafunction wizard: %LPM_FF%
185
// GENERATION: STANDARD
186
// VERSION: WM1.0
187
// MODULE: lpm_ff 
188
// ============================================================
189
// File Name: dff_sr.v
190
// Megafunction Name(s):
191
//                      lpm_ff
192
//
193
// Simulation Library Files(s):
194
//                      lpm
195
// ============================================================
196
// ************************************************************
197
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
198
//
199
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
200
// ************************************************************
201
//Copyright (C) 1991-2010 Altera Corporation
202
//Your use of Altera Corporation's design tools, logic functions 
203
//and other software and tools, and its AMPP partner logic 
204
//functions, and any output files from any of the foregoing 
205
//(including device programming or simulation files), and any 
206
//associated documentation or information are expressly subject 
207
//to the terms and conditions of the Altera Program License 
208
//Subscription Agreement, Altera MegaCore Function License 
209
//Agreement, or other applicable license agreement, including, 
210
//without limitation, that your use is for the sole purpose of 
211
//programming logic devices manufactured by Altera and sold by 
212
//Altera or its authorized distributors.  Please refer to the 
213
//applicable agreement for further details.
214
// synopsys translate_off
215
`timescale 1 ps / 1 ps
216
// synopsys translate_on
217 18 unneback
module vl_dff_sr (
218 6 unneback
        aclr,
219
        aset,
220
        clock,
221
        data,
222
        q);
223
        input     aclr;
224
        input     aset;
225
        input     clock;
226
        input     data;
227
        output    q;
228
        wire [0:0] sub_wire0;
229
        wire [0:0] sub_wire1 = sub_wire0[0:0];
230
        wire  q = sub_wire1;
231
        wire  sub_wire2 = data;
232
        wire  sub_wire3 = sub_wire2;
233
        lpm_ff  lpm_ff_component (
234
                                .aclr (aclr),
235
                                .clock (clock),
236
                                .data (sub_wire3),
237
                                .aset (aset),
238
                                .q (sub_wire0)
239
                                // synopsys translate_off
240
                                ,
241
                                .aload (),
242
                                .enable (),
243
                                .sclr (),
244
                                .sload (),
245
                                .sset ()
246
                                // synopsys translate_on
247
                                );
248
        defparam
249
                lpm_ff_component.lpm_fftype = "DFF",
250
                lpm_ff_component.lpm_type = "LPM_FF",
251
                lpm_ff_component.lpm_width = 1;
252
endmodule
253
// ============================================================
254
// CNX file retrieval info
255
// ============================================================
256
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
257
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
258
// Retrieval info: PRIVATE: ASET NUMERIC "1"
259
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
260
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
261
// Retrieval info: PRIVATE: DFF NUMERIC "1"
262
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
263
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
264
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
265
// Retrieval info: PRIVATE: SSET NUMERIC "0"
266
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
267
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
268
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
269
// Retrieval info: PRIVATE: nBit NUMERIC "1"
270
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
271
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
272
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
273
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
274
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
275
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
276
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
277
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
278
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
279
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
280
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
281
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
282
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
283
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
284
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
285
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
286
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
287
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
288
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
289
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
290
// Retrieval info: LIB_FILE: lpm
291
// LATCH
292
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
293 18 unneback
module vl_latch ( d, le, q, clk);
294 6 unneback
input d, le;
295
output q;
296
input clk;
297
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
298
endmodule
299 18 unneback
module vl_shreg ( d, q, clk, rst);
300 17 unneback
parameter depth = 10;
301
input d;
302
output q;
303
input clk, rst;
304
reg [1:depth] dffs;
305
always @ (posedge clk or posedge rst)
306
if (rst)
307
    dffs <= {depth{1'b0}};
308
else
309
    dffs <= {d,dffs[1:depth-1]};
310
assign q = dffs[depth];
311
endmodule
312 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
313 17 unneback
parameter depth = 10;
314
input d, ce;
315
output q;
316
input clk, rst;
317
reg [1:depth] dffs;
318
always @ (posedge clk or posedge rst)
319
if (rst)
320
    dffs <= {depth{1'b0}};
321
else
322
    if (ce)
323
        dffs <= {d,dffs[1:depth-1]};
324
assign q = dffs[depth];
325
endmodule
326 18 unneback
module vl_delay ( d, q, clk, rst);
327 15 unneback
parameter depth = 10;
328
input d;
329
output q;
330
input clk, rst;
331
reg [1:depth] dffs;
332
always @ (posedge clk or posedge rst)
333
if (rst)
334
    dffs <= {depth{1'b0}};
335
else
336
    dffs <= {d,dffs[1:depth-1]};
337
assign q = dffs[depth];
338
endmodule
339 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
340 17 unneback
parameter depth = 10;
341
input d;
342
output q, emptyflag;
343
input clk, rst;
344
reg [1:depth] dffs;
345
always @ (posedge clk or posedge rst)
346
if (rst)
347
    dffs <= {depth{1'b0}};
348
else
349
    dffs <= {d,dffs[1:depth-1]};
350
assign q = dffs[depth];
351
assign emptyflag = !(|dffs);
352
endmodule
353 6 unneback
//////////////////////////////////////////////////////////////////////
354
////                                                              ////
355 18 unneback
////  Logic functions                                             ////
356
////                                                              ////
357
////  Description                                                 ////
358
////  Logic functions such as multiplexers                        ////
359
////                                                              ////
360
////                                                              ////
361
////  To Do:                                                      ////
362
////   -                                                          ////
363
////                                                              ////
364
////  Author(s):                                                  ////
365
////      - Michael Unneback, unneback@opencores.org              ////
366
////        ORSoC AB                                              ////
367
////                                                              ////
368
//////////////////////////////////////////////////////////////////////
369
////                                                              ////
370
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
371
////                                                              ////
372
//// This source file may be used and distributed without         ////
373
//// restriction provided that this copyright statement is not    ////
374
//// removed from the file and that any derivative work contains  ////
375
//// the original copyright notice and the associated disclaimer. ////
376
////                                                              ////
377
//// This source file is free software; you can redistribute it   ////
378
//// and/or modify it under the terms of the GNU Lesser General   ////
379
//// Public License as published by the Free Software Foundation; ////
380
//// either version 2.1 of the License, or (at your option) any   ////
381
//// later version.                                               ////
382
////                                                              ////
383
//// This source is distributed in the hope that it will be       ////
384
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
385
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
386
//// PURPOSE.  See the GNU Lesser General Public License for more ////
387
//// details.                                                     ////
388
////                                                              ////
389
//// You should have received a copy of the GNU Lesser General    ////
390
//// Public License along with this source; if not, download it   ////
391
//// from http://www.opencores.org/lgpl.shtml                     ////
392
////                                                              ////
393
//////////////////////////////////////////////////////////////////////
394
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
395
parameter width = 32;
396
parameter nr_of_ports = 4;
397
input [width-1:0] a3, a2, a1, a0;
398
input [nr_of_ports-1:0] sel;
399 22 unneback
output [width-1:0] dout;
400 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
401 18 unneback
integer i;
402
// and
403
assign tmp[0] = {width{sel[0]}} & a0;
404
assign tmp[1] = {width{sel[1]}} & a1;
405
assign tmp[2] = {width{sel[2]}} & a2;
406
assign tmp[3] = {width{sel[3]}} & a3;
407
// or
408
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
409
endmodule
410
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
411
parameter width = 32;
412
parameter nr_of_ports = 5;
413
input [width-1:0] a4, a3, a2, a1, a0;
414
input [nr_of_ports-1:0] sel;
415 22 unneback
output [width-1:0] dout;
416 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
417 18 unneback
integer i;
418
// and
419
assign tmp[0] = {width{sel[0]}} & a0;
420
assign tmp[1] = {width{sel[1]}} & a1;
421
assign tmp[2] = {width{sel[2]}} & a2;
422
assign tmp[3] = {width{sel[3]}} & a3;
423
assign tmp[4] = {width{sel[4]}} & a4;
424
// or
425
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
426
endmodule
427
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
428
parameter width = 32;
429
parameter nr_of_ports = 6;
430
input [width-1:0] a5, a4, a3, a2, a1, a0;
431
input [nr_of_ports-1:0] sel;
432 22 unneback
output [width-1:0] dout;
433 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
434 18 unneback
integer i;
435
// and
436
assign tmp[0] = {width{sel[0]}} & a0;
437
assign tmp[1] = {width{sel[1]}} & a1;
438
assign tmp[2] = {width{sel[2]}} & a2;
439
assign tmp[3] = {width{sel[3]}} & a3;
440
assign tmp[4] = {width{sel[4]}} & a4;
441
assign tmp[5] = {width{sel[5]}} & a5;
442
// or
443
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
444
endmodule
445
//////////////////////////////////////////////////////////////////////
446
////                                                              ////
447 6 unneback
////  Versatile counter                                           ////
448
////                                                              ////
449
////  Description                                                 ////
450
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
451
////  counter                                                     ////
452
////                                                              ////
453
////  To Do:                                                      ////
454
////   - add LFSR with more taps                                  ////
455
////                                                              ////
456
////  Author(s):                                                  ////
457
////      - Michael Unneback, unneback@opencores.org              ////
458
////        ORSoC AB                                              ////
459
////                                                              ////
460
//////////////////////////////////////////////////////////////////////
461
////                                                              ////
462
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
463
////                                                              ////
464
//// This source file may be used and distributed without         ////
465
//// restriction provided that this copyright statement is not    ////
466
//// removed from the file and that any derivative work contains  ////
467
//// the original copyright notice and the associated disclaimer. ////
468
////                                                              ////
469
//// This source file is free software; you can redistribute it   ////
470
//// and/or modify it under the terms of the GNU Lesser General   ////
471
//// Public License as published by the Free Software Foundation; ////
472
//// either version 2.1 of the License, or (at your option) any   ////
473
//// later version.                                               ////
474
////                                                              ////
475
//// This source is distributed in the hope that it will be       ////
476
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
477
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
478
//// PURPOSE.  See the GNU Lesser General Public License for more ////
479
//// details.                                                     ////
480
////                                                              ////
481
//// You should have received a copy of the GNU Lesser General    ////
482
//// Public License along with this source; if not, download it   ////
483
//// from http://www.opencores.org/lgpl.shtml                     ////
484
////                                                              ////
485
//////////////////////////////////////////////////////////////////////
486
// binary counter
487 22 unneback
module vl_cnt_bin ( q, rst, clk);
488
   parameter length = 4;
489
   output [length:1] q;
490
   input rst;
491
   input clk;
492
   parameter clear_value = 0;
493
   parameter set_value = 1;
494
   parameter wrap_value = 0;
495
   parameter level1_value = 15;
496
   reg  [length:1] qi;
497
   wire [length:1] q_next;
498
   assign q_next = qi + {{length-1{1'b0}},1'b1};
499
   always @ (posedge clk or posedge rst)
500
     if (rst)
501
       qi <= {length{1'b0}};
502
     else
503
       qi <= q_next;
504
   assign q = qi;
505
endmodule
506
//////////////////////////////////////////////////////////////////////
507
////                                                              ////
508
////  Versatile counter                                           ////
509
////                                                              ////
510
////  Description                                                 ////
511
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
512
////  counter                                                     ////
513
////                                                              ////
514
////  To Do:                                                      ////
515
////   - add LFSR with more taps                                  ////
516
////                                                              ////
517
////  Author(s):                                                  ////
518
////      - Michael Unneback, unneback@opencores.org              ////
519
////        ORSoC AB                                              ////
520
////                                                              ////
521
//////////////////////////////////////////////////////////////////////
522
////                                                              ////
523
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
524
////                                                              ////
525
//// This source file may be used and distributed without         ////
526
//// restriction provided that this copyright statement is not    ////
527
//// removed from the file and that any derivative work contains  ////
528
//// the original copyright notice and the associated disclaimer. ////
529
////                                                              ////
530
//// This source file is free software; you can redistribute it   ////
531
//// and/or modify it under the terms of the GNU Lesser General   ////
532
//// Public License as published by the Free Software Foundation; ////
533
//// either version 2.1 of the License, or (at your option) any   ////
534
//// later version.                                               ////
535
////                                                              ////
536
//// This source is distributed in the hope that it will be       ////
537
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
538
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
539
//// PURPOSE.  See the GNU Lesser General Public License for more ////
540
//// details.                                                     ////
541
////                                                              ////
542
//// You should have received a copy of the GNU Lesser General    ////
543
//// Public License along with this source; if not, download it   ////
544
//// from http://www.opencores.org/lgpl.shtml                     ////
545
////                                                              ////
546
//////////////////////////////////////////////////////////////////////
547
// binary counter
548
module vl_cnt_bin_clear ( clear, q, rst, clk);
549
   parameter length = 4;
550
   input clear;
551
   output [length:1] q;
552
   input rst;
553
   input clk;
554
   parameter clear_value = 0;
555
   parameter set_value = 1;
556
   parameter wrap_value = 0;
557
   parameter level1_value = 15;
558
   reg  [length:1] qi;
559
   wire [length:1] q_next;
560
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
561
   always @ (posedge clk or posedge rst)
562
     if (rst)
563
       qi <= {length{1'b0}};
564
     else
565
       qi <= q_next;
566
   assign q = qi;
567
endmodule
568
//////////////////////////////////////////////////////////////////////
569
////                                                              ////
570
////  Versatile counter                                           ////
571
////                                                              ////
572
////  Description                                                 ////
573
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
574
////  counter                                                     ////
575
////                                                              ////
576
////  To Do:                                                      ////
577
////   - add LFSR with more taps                                  ////
578
////                                                              ////
579
////  Author(s):                                                  ////
580
////      - Michael Unneback, unneback@opencores.org              ////
581
////        ORSoC AB                                              ////
582
////                                                              ////
583
//////////////////////////////////////////////////////////////////////
584
////                                                              ////
585
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
586
////                                                              ////
587
//// This source file may be used and distributed without         ////
588
//// restriction provided that this copyright statement is not    ////
589
//// removed from the file and that any derivative work contains  ////
590
//// the original copyright notice and the associated disclaimer. ////
591
////                                                              ////
592
//// This source file is free software; you can redistribute it   ////
593
//// and/or modify it under the terms of the GNU Lesser General   ////
594
//// Public License as published by the Free Software Foundation; ////
595
//// either version 2.1 of the License, or (at your option) any   ////
596
//// later version.                                               ////
597
////                                                              ////
598
//// This source is distributed in the hope that it will be       ////
599
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
600
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
601
//// PURPOSE.  See the GNU Lesser General Public License for more ////
602
//// details.                                                     ////
603
////                                                              ////
604
//// You should have received a copy of the GNU Lesser General    ////
605
//// Public License along with this source; if not, download it   ////
606
//// from http://www.opencores.org/lgpl.shtml                     ////
607
////                                                              ////
608
//////////////////////////////////////////////////////////////////////
609
// binary counter
610 18 unneback
module vl_cnt_bin_ce ( cke, q, rst, clk);
611 6 unneback
   parameter length = 4;
612
   input cke;
613
   output [length:1] q;
614
   input rst;
615
   input clk;
616
   parameter clear_value = 0;
617
   parameter set_value = 1;
618
   parameter wrap_value = 0;
619
   parameter level1_value = 15;
620
   reg  [length:1] qi;
621
   wire [length:1] q_next;
622
   assign q_next = qi + {{length-1{1'b0}},1'b1};
623
   always @ (posedge clk or posedge rst)
624
     if (rst)
625
       qi <= {length{1'b0}};
626
     else
627
     if (cke)
628
       qi <= q_next;
629
   assign q = qi;
630
endmodule
631
//////////////////////////////////////////////////////////////////////
632
////                                                              ////
633
////  Versatile counter                                           ////
634
////                                                              ////
635
////  Description                                                 ////
636
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
637
////  counter                                                     ////
638
////                                                              ////
639
////  To Do:                                                      ////
640
////   - add LFSR with more taps                                  ////
641
////                                                              ////
642
////  Author(s):                                                  ////
643
////      - Michael Unneback, unneback@opencores.org              ////
644
////        ORSoC AB                                              ////
645
////                                                              ////
646
//////////////////////////////////////////////////////////////////////
647
////                                                              ////
648
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
649
////                                                              ////
650
//// This source file may be used and distributed without         ////
651
//// restriction provided that this copyright statement is not    ////
652
//// removed from the file and that any derivative work contains  ////
653
//// the original copyright notice and the associated disclaimer. ////
654
////                                                              ////
655
//// This source file is free software; you can redistribute it   ////
656
//// and/or modify it under the terms of the GNU Lesser General   ////
657
//// Public License as published by the Free Software Foundation; ////
658
//// either version 2.1 of the License, or (at your option) any   ////
659
//// later version.                                               ////
660
////                                                              ////
661
//// This source is distributed in the hope that it will be       ////
662
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
663
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
664
//// PURPOSE.  See the GNU Lesser General Public License for more ////
665
//// details.                                                     ////
666
////                                                              ////
667
//// You should have received a copy of the GNU Lesser General    ////
668
//// Public License along with this source; if not, download it   ////
669
//// from http://www.opencores.org/lgpl.shtml                     ////
670
////                                                              ////
671
//////////////////////////////////////////////////////////////////////
672
// binary counter
673 18 unneback
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
674 6 unneback
   parameter length = 4;
675
   input clear;
676
   input cke;
677
   output [length:1] q;
678
   input rst;
679
   input clk;
680
   parameter clear_value = 0;
681
   parameter set_value = 1;
682
   parameter wrap_value = 0;
683
   parameter level1_value = 15;
684
   reg  [length:1] qi;
685
   wire [length:1] q_next;
686
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
687
   always @ (posedge clk or posedge rst)
688
     if (rst)
689
       qi <= {length{1'b0}};
690
     else
691
     if (cke)
692
       qi <= q_next;
693
   assign q = qi;
694
endmodule
695
//////////////////////////////////////////////////////////////////////
696
////                                                              ////
697
////  Versatile counter                                           ////
698
////                                                              ////
699
////  Description                                                 ////
700
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
701
////  counter                                                     ////
702
////                                                              ////
703
////  To Do:                                                      ////
704
////   - add LFSR with more taps                                  ////
705
////                                                              ////
706
////  Author(s):                                                  ////
707
////      - Michael Unneback, unneback@opencores.org              ////
708
////        ORSoC AB                                              ////
709
////                                                              ////
710
//////////////////////////////////////////////////////////////////////
711
////                                                              ////
712
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
713
////                                                              ////
714
//// This source file may be used and distributed without         ////
715
//// restriction provided that this copyright statement is not    ////
716
//// removed from the file and that any derivative work contains  ////
717
//// the original copyright notice and the associated disclaimer. ////
718
////                                                              ////
719
//// This source file is free software; you can redistribute it   ////
720
//// and/or modify it under the terms of the GNU Lesser General   ////
721
//// Public License as published by the Free Software Foundation; ////
722
//// either version 2.1 of the License, or (at your option) any   ////
723
//// later version.                                               ////
724
////                                                              ////
725
//// This source is distributed in the hope that it will be       ////
726
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
727
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
728
//// PURPOSE.  See the GNU Lesser General Public License for more ////
729
//// details.                                                     ////
730
////                                                              ////
731
//// You should have received a copy of the GNU Lesser General    ////
732
//// Public License along with this source; if not, download it   ////
733
//// from http://www.opencores.org/lgpl.shtml                     ////
734
////                                                              ////
735
//////////////////////////////////////////////////////////////////////
736
// binary counter
737 18 unneback
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
738 6 unneback
   parameter length = 4;
739
   input clear;
740
   input set;
741
   input cke;
742
   input rew;
743
   output [length:1] q;
744
   input rst;
745
   input clk;
746
   parameter clear_value = 0;
747
   parameter set_value = 1;
748
   parameter wrap_value = 0;
749
   parameter level1_value = 15;
750
   reg  [length:1] qi;
751
   wire  [length:1] q_next, q_next_fw, q_next_rew;
752
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
753
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
754
   assign q_next = rew ? q_next_rew : q_next_fw;
755
   always @ (posedge clk or posedge rst)
756
     if (rst)
757
       qi <= {length{1'b0}};
758
     else
759
     if (cke)
760
       qi <= q_next;
761
   assign q = qi;
762
endmodule
763
//////////////////////////////////////////////////////////////////////
764
////                                                              ////
765
////  Versatile counter                                           ////
766
////                                                              ////
767
////  Description                                                 ////
768
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
769
////  counter                                                     ////
770
////                                                              ////
771
////  To Do:                                                      ////
772
////   - add LFSR with more taps                                  ////
773
////                                                              ////
774
////  Author(s):                                                  ////
775
////      - Michael Unneback, unneback@opencores.org              ////
776
////        ORSoC AB                                              ////
777
////                                                              ////
778
//////////////////////////////////////////////////////////////////////
779
////                                                              ////
780
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
781
////                                                              ////
782
//// This source file may be used and distributed without         ////
783
//// restriction provided that this copyright statement is not    ////
784
//// removed from the file and that any derivative work contains  ////
785
//// the original copyright notice and the associated disclaimer. ////
786
////                                                              ////
787
//// This source file is free software; you can redistribute it   ////
788
//// and/or modify it under the terms of the GNU Lesser General   ////
789
//// Public License as published by the Free Software Foundation; ////
790
//// either version 2.1 of the License, or (at your option) any   ////
791
//// later version.                                               ////
792
////                                                              ////
793
//// This source is distributed in the hope that it will be       ////
794
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
795
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
796
//// PURPOSE.  See the GNU Lesser General Public License for more ////
797
//// details.                                                     ////
798
////                                                              ////
799
//// You should have received a copy of the GNU Lesser General    ////
800
//// Public License along with this source; if not, download it   ////
801
//// from http://www.opencores.org/lgpl.shtml                     ////
802
////                                                              ////
803
//////////////////////////////////////////////////////////////////////
804
// binary counter
805 18 unneback
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
806 6 unneback
   parameter length = 4;
807
   input cke;
808
   input rew;
809
   output reg level1;
810
   input rst;
811
   input clk;
812
   parameter clear_value = 0;
813
   parameter set_value = 1;
814
   parameter wrap_value = 1;
815
   parameter level1_value = 15;
816
   reg  [length:1] qi;
817
   wire  [length:1] q_next, q_next_fw, q_next_rew;
818
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
819
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
820
   assign q_next = rew ? q_next_rew : q_next_fw;
821
   always @ (posedge clk or posedge rst)
822
     if (rst)
823
       qi <= {length{1'b0}};
824
     else
825
     if (cke)
826
       qi <= q_next;
827
    always @ (posedge clk or posedge rst)
828
    if (rst)
829
        level1 <= 1'b0;
830
    else
831
    if (cke)
832
    if (q_next == level1_value)
833
        level1 <= 1'b1;
834
    else if (qi == level1_value & rew)
835
        level1 <= 1'b0;
836
endmodule
837
//////////////////////////////////////////////////////////////////////
838
////                                                              ////
839
////  Versatile counter                                           ////
840
////                                                              ////
841
////  Description                                                 ////
842
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
843
////  counter                                                     ////
844
////                                                              ////
845
////  To Do:                                                      ////
846
////   - add LFSR with more taps                                  ////
847
////                                                              ////
848
////  Author(s):                                                  ////
849
////      - Michael Unneback, unneback@opencores.org              ////
850
////        ORSoC AB                                              ////
851
////                                                              ////
852
//////////////////////////////////////////////////////////////////////
853
////                                                              ////
854
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
855
////                                                              ////
856
//// This source file may be used and distributed without         ////
857
//// restriction provided that this copyright statement is not    ////
858
//// removed from the file and that any derivative work contains  ////
859
//// the original copyright notice and the associated disclaimer. ////
860
////                                                              ////
861
//// This source file is free software; you can redistribute it   ////
862
//// and/or modify it under the terms of the GNU Lesser General   ////
863
//// Public License as published by the Free Software Foundation; ////
864
//// either version 2.1 of the License, or (at your option) any   ////
865
//// later version.                                               ////
866
////                                                              ////
867
//// This source is distributed in the hope that it will be       ////
868
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
869
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
870
//// PURPOSE.  See the GNU Lesser General Public License for more ////
871
//// details.                                                     ////
872
////                                                              ////
873
//// You should have received a copy of the GNU Lesser General    ////
874
//// Public License along with this source; if not, download it   ////
875
//// from http://www.opencores.org/lgpl.shtml                     ////
876
////                                                              ////
877
//////////////////////////////////////////////////////////////////////
878
// LFSR counter
879 18 unneback
module vl_cnt_lfsr_zq ( zq, rst, clk);
880 6 unneback
   parameter length = 4;
881
   output reg zq;
882
   input rst;
883
   input clk;
884
   parameter clear_value = 0;
885
   parameter set_value = 1;
886
   parameter wrap_value = 8;
887
   parameter level1_value = 15;
888
   reg  [length:1] qi;
889
   reg lfsr_fb;
890
   wire [length:1] q_next;
891
   reg [32:1] polynom;
892
   integer i;
893
   always @ (qi)
894
   begin
895
        case (length)
896
         2: polynom = 32'b11;                               // 0x3
897
         3: polynom = 32'b110;                              // 0x6
898
         4: polynom = 32'b1100;                             // 0xC
899
         5: polynom = 32'b10100;                            // 0x14
900
         6: polynom = 32'b110000;                           // 0x30
901
         7: polynom = 32'b1100000;                          // 0x60
902
         8: polynom = 32'b10111000;                         // 0xb8
903
         9: polynom = 32'b100010000;                        // 0x110
904
        10: polynom = 32'b1001000000;                       // 0x240
905
        11: polynom = 32'b10100000000;                      // 0x500
906
        12: polynom = 32'b100000101001;                     // 0x829
907
        13: polynom = 32'b1000000001100;                    // 0x100C
908
        14: polynom = 32'b10000000010101;                   // 0x2015
909
        15: polynom = 32'b110000000000000;                  // 0x6000
910
        16: polynom = 32'b1101000000001000;                 // 0xD008
911
        17: polynom = 32'b10010000000000000;                // 0x12000
912
        18: polynom = 32'b100000010000000000;               // 0x20400
913
        19: polynom = 32'b1000000000000100011;              // 0x40023
914
        20: polynom = 32'b10000010000000000000;             // 0x82000
915
        21: polynom = 32'b101000000000000000000;            // 0x140000
916
        22: polynom = 32'b1100000000000000000000;           // 0x300000
917
        23: polynom = 32'b10000100000000000000000;          // 0x420000
918
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
919
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
920
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
921
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
922
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
923
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
924
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
925
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
926
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
927
        default: polynom = 32'b0;
928
        endcase
929
        lfsr_fb = qi[length];
930
        for (i=length-1; i>=1; i=i-1) begin
931
            if (polynom[i])
932
                lfsr_fb = lfsr_fb  ~^ qi[i];
933
        end
934
    end
935
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
936
   always @ (posedge clk or posedge rst)
937
     if (rst)
938
       qi <= {length{1'b0}};
939
     else
940
       qi <= q_next;
941
   always @ (posedge clk or posedge rst)
942
     if (rst)
943
       zq <= 1'b1;
944
     else
945
       zq <= q_next == {length{1'b0}};
946
endmodule
947
//////////////////////////////////////////////////////////////////////
948
////                                                              ////
949
////  Versatile counter                                           ////
950
////                                                              ////
951
////  Description                                                 ////
952
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
953
////  counter                                                     ////
954
////                                                              ////
955
////  To Do:                                                      ////
956
////   - add LFSR with more taps                                  ////
957
////                                                              ////
958
////  Author(s):                                                  ////
959
////      - Michael Unneback, unneback@opencores.org              ////
960
////        ORSoC AB                                              ////
961
////                                                              ////
962
//////////////////////////////////////////////////////////////////////
963
////                                                              ////
964
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
965
////                                                              ////
966
//// This source file may be used and distributed without         ////
967
//// restriction provided that this copyright statement is not    ////
968
//// removed from the file and that any derivative work contains  ////
969
//// the original copyright notice and the associated disclaimer. ////
970
////                                                              ////
971
//// This source file is free software; you can redistribute it   ////
972
//// and/or modify it under the terms of the GNU Lesser General   ////
973
//// Public License as published by the Free Software Foundation; ////
974
//// either version 2.1 of the License, or (at your option) any   ////
975
//// later version.                                               ////
976
////                                                              ////
977
//// This source is distributed in the hope that it will be       ////
978
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
979
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
980
//// PURPOSE.  See the GNU Lesser General Public License for more ////
981
//// details.                                                     ////
982
////                                                              ////
983
//// You should have received a copy of the GNU Lesser General    ////
984
//// Public License along with this source; if not, download it   ////
985
//// from http://www.opencores.org/lgpl.shtml                     ////
986
////                                                              ////
987
//////////////////////////////////////////////////////////////////////
988
// LFSR counter
989 18 unneback
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
990 6 unneback
   parameter length = 4;
991
   input cke;
992
   output reg zq;
993
   input rst;
994
   input clk;
995
   parameter clear_value = 0;
996
   parameter set_value = 1;
997
   parameter wrap_value = 8;
998
   parameter level1_value = 15;
999
   reg  [length:1] qi;
1000
   reg lfsr_fb;
1001
   wire [length:1] q_next;
1002
   reg [32:1] polynom;
1003
   integer i;
1004
   always @ (qi)
1005
   begin
1006
        case (length)
1007
         2: polynom = 32'b11;                               // 0x3
1008
         3: polynom = 32'b110;                              // 0x6
1009
         4: polynom = 32'b1100;                             // 0xC
1010
         5: polynom = 32'b10100;                            // 0x14
1011
         6: polynom = 32'b110000;                           // 0x30
1012
         7: polynom = 32'b1100000;                          // 0x60
1013
         8: polynom = 32'b10111000;                         // 0xb8
1014
         9: polynom = 32'b100010000;                        // 0x110
1015
        10: polynom = 32'b1001000000;                       // 0x240
1016
        11: polynom = 32'b10100000000;                      // 0x500
1017
        12: polynom = 32'b100000101001;                     // 0x829
1018
        13: polynom = 32'b1000000001100;                    // 0x100C
1019
        14: polynom = 32'b10000000010101;                   // 0x2015
1020
        15: polynom = 32'b110000000000000;                  // 0x6000
1021
        16: polynom = 32'b1101000000001000;                 // 0xD008
1022
        17: polynom = 32'b10010000000000000;                // 0x12000
1023
        18: polynom = 32'b100000010000000000;               // 0x20400
1024
        19: polynom = 32'b1000000000000100011;              // 0x40023
1025
        20: polynom = 32'b10000010000000000000;             // 0x82000
1026
        21: polynom = 32'b101000000000000000000;            // 0x140000
1027
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1028
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1029
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1030
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1031
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1032
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1033
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1034
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1035
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1036
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1037
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1038
        default: polynom = 32'b0;
1039
        endcase
1040
        lfsr_fb = qi[length];
1041
        for (i=length-1; i>=1; i=i-1) begin
1042
            if (polynom[i])
1043
                lfsr_fb = lfsr_fb  ~^ qi[i];
1044
        end
1045
    end
1046
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1047
   always @ (posedge clk or posedge rst)
1048
     if (rst)
1049
       qi <= {length{1'b0}};
1050
     else
1051
     if (cke)
1052
       qi <= q_next;
1053
   always @ (posedge clk or posedge rst)
1054
     if (rst)
1055
       zq <= 1'b1;
1056
     else
1057
     if (cke)
1058
       zq <= q_next == {length{1'b0}};
1059
endmodule
1060
//////////////////////////////////////////////////////////////////////
1061
////                                                              ////
1062
////  Versatile counter                                           ////
1063
////                                                              ////
1064
////  Description                                                 ////
1065
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1066
////  counter                                                     ////
1067
////                                                              ////
1068
////  To Do:                                                      ////
1069
////   - add LFSR with more taps                                  ////
1070
////                                                              ////
1071
////  Author(s):                                                  ////
1072
////      - Michael Unneback, unneback@opencores.org              ////
1073
////        ORSoC AB                                              ////
1074
////                                                              ////
1075
//////////////////////////////////////////////////////////////////////
1076
////                                                              ////
1077
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1078
////                                                              ////
1079
//// This source file may be used and distributed without         ////
1080
//// restriction provided that this copyright statement is not    ////
1081
//// removed from the file and that any derivative work contains  ////
1082
//// the original copyright notice and the associated disclaimer. ////
1083
////                                                              ////
1084
//// This source file is free software; you can redistribute it   ////
1085
//// and/or modify it under the terms of the GNU Lesser General   ////
1086
//// Public License as published by the Free Software Foundation; ////
1087
//// either version 2.1 of the License, or (at your option) any   ////
1088
//// later version.                                               ////
1089
////                                                              ////
1090
//// This source is distributed in the hope that it will be       ////
1091
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1092
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1093
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1094
//// details.                                                     ////
1095
////                                                              ////
1096
//// You should have received a copy of the GNU Lesser General    ////
1097
//// Public License along with this source; if not, download it   ////
1098
//// from http://www.opencores.org/lgpl.shtml                     ////
1099
////                                                              ////
1100
//////////////////////////////////////////////////////////////////////
1101
// LFSR counter
1102 22 unneback
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk);
1103
   parameter length = 4;
1104
   input cke;
1105
   output [length:1] q;
1106
   output reg zq;
1107
   input rst;
1108
   input clk;
1109
   parameter clear_value = 0;
1110
   parameter set_value = 1;
1111
   parameter wrap_value = 8;
1112
   parameter level1_value = 15;
1113
   reg  [length:1] qi;
1114
   reg lfsr_fb;
1115
   wire [length:1] q_next;
1116
   reg [32:1] polynom;
1117
   integer i;
1118
   always @ (qi)
1119
   begin
1120
        case (length)
1121
         2: polynom = 32'b11;                               // 0x3
1122
         3: polynom = 32'b110;                              // 0x6
1123
         4: polynom = 32'b1100;                             // 0xC
1124
         5: polynom = 32'b10100;                            // 0x14
1125
         6: polynom = 32'b110000;                           // 0x30
1126
         7: polynom = 32'b1100000;                          // 0x60
1127
         8: polynom = 32'b10111000;                         // 0xb8
1128
         9: polynom = 32'b100010000;                        // 0x110
1129
        10: polynom = 32'b1001000000;                       // 0x240
1130
        11: polynom = 32'b10100000000;                      // 0x500
1131
        12: polynom = 32'b100000101001;                     // 0x829
1132
        13: polynom = 32'b1000000001100;                    // 0x100C
1133
        14: polynom = 32'b10000000010101;                   // 0x2015
1134
        15: polynom = 32'b110000000000000;                  // 0x6000
1135
        16: polynom = 32'b1101000000001000;                 // 0xD008
1136
        17: polynom = 32'b10010000000000000;                // 0x12000
1137
        18: polynom = 32'b100000010000000000;               // 0x20400
1138
        19: polynom = 32'b1000000000000100011;              // 0x40023
1139
        20: polynom = 32'b10000010000000000000;             // 0x82000
1140
        21: polynom = 32'b101000000000000000000;            // 0x140000
1141
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1142
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1143
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1144
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1145
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1146
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1147
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1148
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1149
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1150
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1151
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1152
        default: polynom = 32'b0;
1153
        endcase
1154
        lfsr_fb = qi[length];
1155
        for (i=length-1; i>=1; i=i-1) begin
1156
            if (polynom[i])
1157
                lfsr_fb = lfsr_fb  ~^ qi[i];
1158
        end
1159
    end
1160
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1161
   always @ (posedge clk or posedge rst)
1162
     if (rst)
1163
       qi <= {length{1'b0}};
1164
     else
1165
     if (cke)
1166
       qi <= q_next;
1167
   assign q = qi;
1168
   always @ (posedge clk or posedge rst)
1169
     if (rst)
1170
       zq <= 1'b1;
1171
     else
1172
     if (cke)
1173
       zq <= q_next == {length{1'b0}};
1174
endmodule
1175
//////////////////////////////////////////////////////////////////////
1176
////                                                              ////
1177
////  Versatile counter                                           ////
1178
////                                                              ////
1179
////  Description                                                 ////
1180
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1181
////  counter                                                     ////
1182
////                                                              ////
1183
////  To Do:                                                      ////
1184
////   - add LFSR with more taps                                  ////
1185
////                                                              ////
1186
////  Author(s):                                                  ////
1187
////      - Michael Unneback, unneback@opencores.org              ////
1188
////        ORSoC AB                                              ////
1189
////                                                              ////
1190
//////////////////////////////////////////////////////////////////////
1191
////                                                              ////
1192
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1193
////                                                              ////
1194
//// This source file may be used and distributed without         ////
1195
//// restriction provided that this copyright statement is not    ////
1196
//// removed from the file and that any derivative work contains  ////
1197
//// the original copyright notice and the associated disclaimer. ////
1198
////                                                              ////
1199
//// This source file is free software; you can redistribute it   ////
1200
//// and/or modify it under the terms of the GNU Lesser General   ////
1201
//// Public License as published by the Free Software Foundation; ////
1202
//// either version 2.1 of the License, or (at your option) any   ////
1203
//// later version.                                               ////
1204
////                                                              ////
1205
//// This source is distributed in the hope that it will be       ////
1206
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1207
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1208
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1209
//// details.                                                     ////
1210
////                                                              ////
1211
//// You should have received a copy of the GNU Lesser General    ////
1212
//// Public License along with this source; if not, download it   ////
1213
//// from http://www.opencores.org/lgpl.shtml                     ////
1214
////                                                              ////
1215
//////////////////////////////////////////////////////////////////////
1216
// LFSR counter
1217 18 unneback
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
1218 6 unneback
   parameter length = 4;
1219
   input cke;
1220
   input rew;
1221
   output reg level1;
1222
   input rst;
1223
   input clk;
1224
   parameter clear_value = 0;
1225
   parameter set_value = 1;
1226
   parameter wrap_value = 8;
1227
   parameter level1_value = 15;
1228
   reg  [length:1] qi;
1229
   reg lfsr_fb, lfsr_fb_rew;
1230
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1231
   reg [32:1] polynom_rew;
1232
   integer j;
1233
   reg [32:1] polynom;
1234
   integer i;
1235
   always @ (qi)
1236
   begin
1237
        case (length)
1238
         2: polynom = 32'b11;                               // 0x3
1239
         3: polynom = 32'b110;                              // 0x6
1240
         4: polynom = 32'b1100;                             // 0xC
1241
         5: polynom = 32'b10100;                            // 0x14
1242
         6: polynom = 32'b110000;                           // 0x30
1243
         7: polynom = 32'b1100000;                          // 0x60
1244
         8: polynom = 32'b10111000;                         // 0xb8
1245
         9: polynom = 32'b100010000;                        // 0x110
1246
        10: polynom = 32'b1001000000;                       // 0x240
1247
        11: polynom = 32'b10100000000;                      // 0x500
1248
        12: polynom = 32'b100000101001;                     // 0x829
1249
        13: polynom = 32'b1000000001100;                    // 0x100C
1250
        14: polynom = 32'b10000000010101;                   // 0x2015
1251
        15: polynom = 32'b110000000000000;                  // 0x6000
1252
        16: polynom = 32'b1101000000001000;                 // 0xD008
1253
        17: polynom = 32'b10010000000000000;                // 0x12000
1254
        18: polynom = 32'b100000010000000000;               // 0x20400
1255
        19: polynom = 32'b1000000000000100011;              // 0x40023
1256
        20: polynom = 32'b10000010000000000000;             // 0x82000
1257
        21: polynom = 32'b101000000000000000000;            // 0x140000
1258
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1259
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1260
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1261
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1262
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1263
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1264
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1265
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1266
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1267
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1268
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1269
        default: polynom = 32'b0;
1270
        endcase
1271
        lfsr_fb = qi[length];
1272
        for (i=length-1; i>=1; i=i-1) begin
1273
            if (polynom[i])
1274
                lfsr_fb = lfsr_fb  ~^ qi[i];
1275
        end
1276
    end
1277
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1278
   always @ (qi)
1279
   begin
1280
        case (length)
1281
         2: polynom_rew = 32'b11;
1282
         3: polynom_rew = 32'b110;
1283
         4: polynom_rew = 32'b1100;
1284
         5: polynom_rew = 32'b10100;
1285
         6: polynom_rew = 32'b110000;
1286
         7: polynom_rew = 32'b1100000;
1287
         8: polynom_rew = 32'b10111000;
1288
         9: polynom_rew = 32'b100010000;
1289
        10: polynom_rew = 32'b1001000000;
1290
        11: polynom_rew = 32'b10100000000;
1291
        12: polynom_rew = 32'b100000101001;
1292
        13: polynom_rew = 32'b1000000001100;
1293
        14: polynom_rew = 32'b10000000010101;
1294
        15: polynom_rew = 32'b110000000000000;
1295
        16: polynom_rew = 32'b1101000000001000;
1296
        17: polynom_rew = 32'b10010000000000000;
1297
        18: polynom_rew = 32'b100000010000000000;
1298
        19: polynom_rew = 32'b1000000000000100011;
1299
        20: polynom_rew = 32'b10000010000000000000;
1300
        21: polynom_rew = 32'b101000000000000000000;
1301
        22: polynom_rew = 32'b1100000000000000000000;
1302
        23: polynom_rew = 32'b10000100000000000000000;
1303
        24: polynom_rew = 32'b111000010000000000000000;
1304
        25: polynom_rew = 32'b1001000000000000000000000;
1305
        26: polynom_rew = 32'b10000000000000000000100011;
1306
        27: polynom_rew = 32'b100000000000000000000010011;
1307
        28: polynom_rew = 32'b1100100000000000000000000000;
1308
        29: polynom_rew = 32'b10100000000000000000000000000;
1309
        30: polynom_rew = 32'b100000000000000000000000101001;
1310
        31: polynom_rew = 32'b1001000000000000000000000000000;
1311
        32: polynom_rew = 32'b10000000001000000000000000000011;
1312
        default: polynom_rew = 32'b0;
1313
        endcase
1314
        // rotate left
1315
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
1316
        lfsr_fb_rew = qi[length];
1317
        for (i=length-1; i>=1; i=i-1) begin
1318
            if (polynom_rew[i])
1319
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
1320
        end
1321
    end
1322
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
1323
   assign q_next = rew ? q_next_rew : q_next_fw;
1324
   always @ (posedge clk or posedge rst)
1325
     if (rst)
1326
       qi <= {length{1'b0}};
1327
     else
1328
     if (cke)
1329
       qi <= q_next;
1330
    always @ (posedge clk or posedge rst)
1331
    if (rst)
1332
        level1 <= 1'b0;
1333
    else
1334
    if (cke)
1335
    if (q_next == level1_value)
1336
        level1 <= 1'b1;
1337
    else if (qi == level1_value & rew)
1338
        level1 <= 1'b0;
1339
endmodule
1340
//////////////////////////////////////////////////////////////////////
1341
////                                                              ////
1342
////  Versatile counter                                           ////
1343
////                                                              ////
1344
////  Description                                                 ////
1345
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1346
////  counter                                                     ////
1347
////                                                              ////
1348
////  To Do:                                                      ////
1349
////   - add LFSR with more taps                                  ////
1350
////                                                              ////
1351
////  Author(s):                                                  ////
1352
////      - Michael Unneback, unneback@opencores.org              ////
1353
////        ORSoC AB                                              ////
1354
////                                                              ////
1355
//////////////////////////////////////////////////////////////////////
1356
////                                                              ////
1357
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1358
////                                                              ////
1359
//// This source file may be used and distributed without         ////
1360
//// restriction provided that this copyright statement is not    ////
1361
//// removed from the file and that any derivative work contains  ////
1362
//// the original copyright notice and the associated disclaimer. ////
1363
////                                                              ////
1364
//// This source file is free software; you can redistribute it   ////
1365
//// and/or modify it under the terms of the GNU Lesser General   ////
1366
//// Public License as published by the Free Software Foundation; ////
1367
//// either version 2.1 of the License, or (at your option) any   ////
1368
//// later version.                                               ////
1369
////                                                              ////
1370
//// This source is distributed in the hope that it will be       ////
1371
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1372
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1373
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1374
//// details.                                                     ////
1375
////                                                              ////
1376
//// You should have received a copy of the GNU Lesser General    ////
1377
//// Public License along with this source; if not, download it   ////
1378
//// from http://www.opencores.org/lgpl.shtml                     ////
1379
////                                                              ////
1380
//////////////////////////////////////////////////////////////////////
1381
// GRAY counter
1382 18 unneback
module vl_cnt_gray ( q, rst, clk);
1383 6 unneback
   parameter length = 4;
1384
   output reg [length:1] q;
1385
   input rst;
1386
   input clk;
1387
   parameter clear_value = 0;
1388
   parameter set_value = 1;
1389
   parameter wrap_value = 8;
1390
   parameter level1_value = 15;
1391
   reg  [length:1] qi;
1392
   wire [length:1] q_next;
1393
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1394
   always @ (posedge clk or posedge rst)
1395
     if (rst)
1396
       qi <= {length{1'b0}};
1397
     else
1398
       qi <= q_next;
1399
   always @ (posedge clk or posedge rst)
1400
     if (rst)
1401
       q <= {length{1'b0}};
1402
     else
1403
         q <= (q_next>>1) ^ q_next;
1404
endmodule
1405
//////////////////////////////////////////////////////////////////////
1406
////                                                              ////
1407
////  Versatile counter                                           ////
1408
////                                                              ////
1409
////  Description                                                 ////
1410
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1411
////  counter                                                     ////
1412
////                                                              ////
1413
////  To Do:                                                      ////
1414
////   - add LFSR with more taps                                  ////
1415
////                                                              ////
1416
////  Author(s):                                                  ////
1417
////      - Michael Unneback, unneback@opencores.org              ////
1418
////        ORSoC AB                                              ////
1419
////                                                              ////
1420
//////////////////////////////////////////////////////////////////////
1421
////                                                              ////
1422
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1423
////                                                              ////
1424
//// This source file may be used and distributed without         ////
1425
//// restriction provided that this copyright statement is not    ////
1426
//// removed from the file and that any derivative work contains  ////
1427
//// the original copyright notice and the associated disclaimer. ////
1428
////                                                              ////
1429
//// This source file is free software; you can redistribute it   ////
1430
//// and/or modify it under the terms of the GNU Lesser General   ////
1431
//// Public License as published by the Free Software Foundation; ////
1432
//// either version 2.1 of the License, or (at your option) any   ////
1433
//// later version.                                               ////
1434
////                                                              ////
1435
//// This source is distributed in the hope that it will be       ////
1436
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1437
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1438
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1439
//// details.                                                     ////
1440
////                                                              ////
1441
//// You should have received a copy of the GNU Lesser General    ////
1442
//// Public License along with this source; if not, download it   ////
1443
//// from http://www.opencores.org/lgpl.shtml                     ////
1444
////                                                              ////
1445
//////////////////////////////////////////////////////////////////////
1446
// GRAY counter
1447 18 unneback
module vl_cnt_gray_ce ( cke, q, rst, clk);
1448 6 unneback
   parameter length = 4;
1449
   input cke;
1450
   output reg [length:1] q;
1451
   input rst;
1452
   input clk;
1453
   parameter clear_value = 0;
1454
   parameter set_value = 1;
1455
   parameter wrap_value = 8;
1456
   parameter level1_value = 15;
1457
   reg  [length:1] qi;
1458
   wire [length:1] q_next;
1459
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1460
   always @ (posedge clk or posedge rst)
1461
     if (rst)
1462
       qi <= {length{1'b0}};
1463
     else
1464
     if (cke)
1465
       qi <= q_next;
1466
   always @ (posedge clk or posedge rst)
1467
     if (rst)
1468
       q <= {length{1'b0}};
1469
     else
1470
       if (cke)
1471
         q <= (q_next>>1) ^ q_next;
1472
endmodule
1473
//////////////////////////////////////////////////////////////////////
1474
////                                                              ////
1475
////  Versatile counter                                           ////
1476
////                                                              ////
1477
////  Description                                                 ////
1478
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1479
////  counter                                                     ////
1480
////                                                              ////
1481
////  To Do:                                                      ////
1482
////   - add LFSR with more taps                                  ////
1483
////                                                              ////
1484
////  Author(s):                                                  ////
1485
////      - Michael Unneback, unneback@opencores.org              ////
1486
////        ORSoC AB                                              ////
1487
////                                                              ////
1488
//////////////////////////////////////////////////////////////////////
1489
////                                                              ////
1490
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1491
////                                                              ////
1492
//// This source file may be used and distributed without         ////
1493
//// restriction provided that this copyright statement is not    ////
1494
//// removed from the file and that any derivative work contains  ////
1495
//// the original copyright notice and the associated disclaimer. ////
1496
////                                                              ////
1497
//// This source file is free software; you can redistribute it   ////
1498
//// and/or modify it under the terms of the GNU Lesser General   ////
1499
//// Public License as published by the Free Software Foundation; ////
1500
//// either version 2.1 of the License, or (at your option) any   ////
1501
//// later version.                                               ////
1502
////                                                              ////
1503
//// This source is distributed in the hope that it will be       ////
1504
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1505
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1506
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1507
//// details.                                                     ////
1508
////                                                              ////
1509
//// You should have received a copy of the GNU Lesser General    ////
1510
//// Public License along with this source; if not, download it   ////
1511
//// from http://www.opencores.org/lgpl.shtml                     ////
1512
////                                                              ////
1513
//////////////////////////////////////////////////////////////////////
1514
// GRAY counter
1515 18 unneback
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
1516 6 unneback
   parameter length = 4;
1517
   input cke;
1518
   output reg [length:1] q;
1519
   output [length:1] q_bin;
1520
   input rst;
1521
   input clk;
1522
   parameter clear_value = 0;
1523
   parameter set_value = 1;
1524
   parameter wrap_value = 8;
1525
   parameter level1_value = 15;
1526
   reg  [length:1] qi;
1527
   wire [length:1] q_next;
1528
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1529
   always @ (posedge clk or posedge rst)
1530
     if (rst)
1531
       qi <= {length{1'b0}};
1532
     else
1533
     if (cke)
1534
       qi <= q_next;
1535
   always @ (posedge clk or posedge rst)
1536
     if (rst)
1537
       q <= {length{1'b0}};
1538
     else
1539
       if (cke)
1540
         q <= (q_next>>1) ^ q_next;
1541
   assign q_bin = qi;
1542
endmodule
1543
//////////////////////////////////////////////////////////////////////
1544
////                                                              ////
1545
////  Versatile library, counters                                 ////
1546
////                                                              ////
1547
////  Description                                                 ////
1548
////  counters                                                    ////
1549
////                                                              ////
1550
////                                                              ////
1551
////  To Do:                                                      ////
1552
////   - add more counters                                        ////
1553
////                                                              ////
1554
////  Author(s):                                                  ////
1555
////      - Michael Unneback, unneback@opencores.org              ////
1556
////        ORSoC AB                                              ////
1557
////                                                              ////
1558
//////////////////////////////////////////////////////////////////////
1559
////                                                              ////
1560
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1561
////                                                              ////
1562
//// This source file may be used and distributed without         ////
1563
//// restriction provided that this copyright statement is not    ////
1564
//// removed from the file and that any derivative work contains  ////
1565
//// the original copyright notice and the associated disclaimer. ////
1566
////                                                              ////
1567
//// This source file is free software; you can redistribute it   ////
1568
//// and/or modify it under the terms of the GNU Lesser General   ////
1569
//// Public License as published by the Free Software Foundation; ////
1570
//// either version 2.1 of the License, or (at your option) any   ////
1571
//// later version.                                               ////
1572
////                                                              ////
1573
//// This source is distributed in the hope that it will be       ////
1574
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1575
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1576
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1577
//// details.                                                     ////
1578
////                                                              ////
1579
//// You should have received a copy of the GNU Lesser General    ////
1580
//// Public License along with this source; if not, download it   ////
1581
//// from http://www.opencores.org/lgpl.shtml                     ////
1582
////                                                              ////
1583
//////////////////////////////////////////////////////////////////////
1584 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
1585 6 unneback
   parameter length = 4;
1586
   output reg [0:length-1] q;
1587
   input rst;
1588
   input clk;
1589
    always @ (posedge clk or posedge rst)
1590
    if (rst)
1591
        q <= {1'b1,{length-1{1'b0}}};
1592
    else
1593
        q <= {q[length-1],q[0:length-2]};
1594
endmodule
1595 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
1596 6 unneback
   parameter length = 4;
1597
   input cke;
1598
   output reg [0:length-1] q;
1599
   input rst;
1600
   input clk;
1601
    always @ (posedge clk or posedge rst)
1602
    if (rst)
1603
        q <= {1'b1,{length-1{1'b0}}};
1604
    else
1605
        if (cke)
1606
            q <= {q[length-1],q[0:length-2]};
1607
endmodule
1608 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1609 6 unneback
   parameter length = 4;
1610
   input cke, clear;
1611
   output reg [0:length-1] q;
1612
   input rst;
1613
   input clk;
1614
    always @ (posedge clk or posedge rst)
1615
    if (rst)
1616
        q <= {1'b1,{length-1{1'b0}}};
1617
    else
1618
        if (cke)
1619
            if (clear)
1620
                q <= {1'b1,{length-1{1'b0}}};
1621
            else
1622
                q <= q >> 1;
1623
endmodule
1624 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
1625 6 unneback
   parameter length = 4;
1626
   input cke, clear;
1627
   output reg [0:length-1] q;
1628
   input rst;
1629
   input clk;
1630
    always @ (posedge clk or posedge rst)
1631
    if (rst)
1632
        q <= {1'b1,{length-1{1'b0}}};
1633
    else
1634
        if (cke)
1635
            if (clear)
1636
                q <= {1'b1,{length-1{1'b0}}};
1637
            else
1638
            q <= {q[length-1],q[0:length-2]};
1639
endmodule
1640
//////////////////////////////////////////////////////////////////////
1641
////                                                              ////
1642
////  Versatile library, memories                                 ////
1643
////                                                              ////
1644
////  Description                                                 ////
1645
////  memories                                                    ////
1646
////                                                              ////
1647
////                                                              ////
1648
////  To Do:                                                      ////
1649
////   - add more memory types                                    ////
1650
////                                                              ////
1651
////  Author(s):                                                  ////
1652
////      - Michael Unneback, unneback@opencores.org              ////
1653
////        ORSoC AB                                              ////
1654
////                                                              ////
1655
//////////////////////////////////////////////////////////////////////
1656
////                                                              ////
1657
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1658
////                                                              ////
1659
//// This source file may be used and distributed without         ////
1660
//// restriction provided that this copyright statement is not    ////
1661
//// removed from the file and that any derivative work contains  ////
1662
//// the original copyright notice and the associated disclaimer. ////
1663
////                                                              ////
1664
//// This source file is free software; you can redistribute it   ////
1665
//// and/or modify it under the terms of the GNU Lesser General   ////
1666
//// Public License as published by the Free Software Foundation; ////
1667
//// either version 2.1 of the License, or (at your option) any   ////
1668
//// later version.                                               ////
1669
////                                                              ////
1670
//// This source is distributed in the hope that it will be       ////
1671
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1672
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1673
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1674
//// details.                                                     ////
1675
////                                                              ////
1676
//// You should have received a copy of the GNU Lesser General    ////
1677
//// Public License along with this source; if not, download it   ////
1678
//// from http://www.opencores.org/lgpl.shtml                     ////
1679
////                                                              ////
1680
//////////////////////////////////////////////////////////////////////
1681
/// ROM
1682 7 unneback
module vl_rom_init ( adr, q, clk);
1683
   parameter data_width = 32;
1684
   parameter addr_width = 8;
1685
   input [(addr_width-1):0]       adr;
1686
   output reg [(data_width-1):0] q;
1687
   input                         clk;
1688
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
1689
   parameter memory_file = "vl_rom.vmem";
1690
   initial
1691
     begin
1692
        $readmemh(memory_file, rom);
1693
     end
1694
   always @ (posedge clk)
1695
     q <= rom[adr];
1696
endmodule
1697 14 unneback
/*
1698 7 unneback
module vl_rom ( adr, q, clk);
1699 6 unneback
parameter data_width = 32;
1700
parameter addr_width = 4;
1701
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
1702
    {32'h18000000},
1703
    {32'hA8200000},
1704
    {32'hA8200000},
1705
    {32'hA8200000},
1706
    {32'h44003000},
1707
    {32'h15000000},
1708
    {32'h15000000},
1709
    {32'h15000000},
1710
    {32'h15000000},
1711
    {32'h15000000},
1712
    {32'h15000000},
1713
    {32'h15000000},
1714
    {32'h15000000},
1715
    {32'h15000000},
1716
    {32'h15000000},
1717
    {32'h15000000}};
1718 7 unneback
input [addr_width-1:0] adr;
1719 6 unneback
output reg [data_width-1:0] q;
1720
input clk;
1721
always @ (posedge clk)
1722 7 unneback
    q <= data[adr];
1723 6 unneback
endmodule
1724 14 unneback
*/
1725 6 unneback
// Single port RAM
1726
module vl_ram ( d, adr, we, q, clk);
1727
   parameter data_width = 32;
1728
   parameter addr_width = 8;
1729
   input [(data_width-1):0]      d;
1730
   input [(addr_width-1):0]       adr;
1731
   input                         we;
1732 7 unneback
   output reg [(data_width-1):0] q;
1733 6 unneback
   input                         clk;
1734
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1735 7 unneback
   parameter init = 0;
1736
   parameter memory_file = "vl_ram.vmem";
1737
   generate if (init) begin : init_mem
1738
   initial
1739
     begin
1740
        $readmemh(memory_file, ram);
1741
     end
1742
   end
1743
   endgenerate
1744 6 unneback
   always @ (posedge clk)
1745
   begin
1746
   if (we)
1747
     ram[adr] <= d;
1748
   q <= ram[adr];
1749
   end
1750
endmodule
1751 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
1752
   parameter data_width = 32;
1753
   parameter addr_width = 8;
1754
   input [(data_width-1):0]      d;
1755
   input [(addr_width-1):0]       adr;
1756
   input [(addr_width/4)-1:0]    be;
1757
   input                         we;
1758
   output reg [(data_width-1):0] q;
1759
   input                         clk;
1760
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1761
   parameter init = 0;
1762
   parameter memory_file = "vl_ram.vmem";
1763
   generate if (init) begin : init_mem
1764
   initial
1765
     begin
1766
        $readmemh(memory_file, ram);
1767
     end
1768
   end
1769
   endgenerate
1770
   genvar i;
1771
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
1772
      always @ (posedge clk)
1773
      if (we & be[i])
1774
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
1775
   end
1776
   endgenerate
1777
   always @ (posedge clk)
1778
      q <= ram[adr];
1779
endmodule
1780 6 unneback
// Dual port RAM
1781
// ACTEL FPGA should not use logic to handle rw collision
1782 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1783 6 unneback
   parameter data_width = 32;
1784
   parameter addr_width = 8;
1785
   input [(data_width-1):0]      d_a;
1786
   input [(addr_width-1):0]       adr_a;
1787
   input [(addr_width-1):0]       adr_b;
1788
   input                         we_a;
1789
   output [(data_width-1):0]      q_b;
1790
   input                         clk_a, clk_b;
1791
   reg [(addr_width-1):0]         adr_b_reg;
1792
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
1793 7 unneback
   parameter init = 0;
1794
   parameter memory_file = "vl_ram.vmem";
1795
   generate if (init) begin : init_mem
1796
   initial
1797
     begin
1798
        $readmemh(memory_file, ram);
1799
     end
1800
   end
1801
   endgenerate
1802 6 unneback
   always @ (posedge clk_a)
1803
   if (we_a)
1804
     ram[adr_a] <= d_a;
1805
   always @ (posedge clk_b)
1806
   adr_b_reg <= adr_b;
1807
   assign q_b = ram[adr_b_reg];
1808
endmodule
1809 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1810 6 unneback
   parameter data_width = 32;
1811
   parameter addr_width = 8;
1812
   input [(data_width-1):0]      d_a;
1813
   input [(addr_width-1):0]       adr_a;
1814
   input [(addr_width-1):0]       adr_b;
1815
   input                         we_a;
1816
   output [(data_width-1):0]      q_b;
1817
   output reg [(data_width-1):0] q_a;
1818
   input                         clk_a, clk_b;
1819
   reg [(data_width-1):0]         q_b;
1820
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
1821 7 unneback
   parameter init = 0;
1822
   parameter memory_file = "vl_ram.vmem";
1823
   generate if (init) begin : init_mem
1824
   initial
1825
     begin
1826
        $readmemh(memory_file, ram);
1827
     end
1828
   end
1829
   endgenerate
1830 6 unneback
   always @ (posedge clk_a)
1831
     begin
1832
        q_a <= ram[adr_a];
1833
        if (we_a)
1834
             ram[adr_a] <= d_a;
1835
     end
1836
   always @ (posedge clk_b)
1837
          q_b <= ram[adr_b];
1838
endmodule
1839 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
1840 6 unneback
   parameter data_width = 32;
1841
   parameter addr_width = 8;
1842
   input [(data_width-1):0]      d_a;
1843
   input [(addr_width-1):0]       adr_a;
1844
   input [(addr_width-1):0]       adr_b;
1845
   input                         we_a;
1846
   output [(data_width-1):0]      q_b;
1847
   input [(data_width-1):0]       d_b;
1848
   output reg [(data_width-1):0] q_a;
1849
   input                         we_b;
1850
   input                         clk_a, clk_b;
1851
   reg [(data_width-1):0]         q_b;
1852
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
1853 7 unneback
   parameter init = 0;
1854
   parameter memory_file = "vl_ram.vmem";
1855
   generate if (init) begin : init_mem
1856
   initial
1857
     begin
1858
        $readmemh(memory_file, ram);
1859
     end
1860
   end
1861
   endgenerate
1862 6 unneback
   always @ (posedge clk_a)
1863
     begin
1864
        q_a <= ram[adr_a];
1865
        if (we_a)
1866
             ram[adr_a] <= d_a;
1867
     end
1868
   always @ (posedge clk_b)
1869
     begin
1870
        q_b <= ram[adr_b];
1871
        if (we_b)
1872
          ram[adr_b] <= d_b;
1873
     end
1874
endmodule
1875
// Content addresable memory, CAM
1876
// FIFO
1877
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
1878 11 unneback
   parameter addr_width = 4;
1879
   parameter N = addr_width-1;
1880 6 unneback
   parameter Q1 = 2'b00;
1881
   parameter Q2 = 2'b01;
1882
   parameter Q3 = 2'b11;
1883
   parameter Q4 = 2'b10;
1884
   parameter going_empty = 1'b0;
1885
   parameter going_full  = 1'b1;
1886
   input [N:0]  wptr, rptr;
1887 14 unneback
   output       fifo_empty;
1888 6 unneback
   output       fifo_full;
1889
   input        wclk, rclk, rst;
1890
   wire direction;
1891
   reg  direction_set, direction_clr;
1892
   wire async_empty, async_full;
1893
   wire fifo_full2;
1894 14 unneback
   wire fifo_empty2;
1895 6 unneback
   // direction_set
1896
   always @ (wptr[N:N-1] or rptr[N:N-1])
1897
     case ({wptr[N:N-1],rptr[N:N-1]})
1898
       {Q1,Q2} : direction_set <= 1'b1;
1899
       {Q2,Q3} : direction_set <= 1'b1;
1900
       {Q3,Q4} : direction_set <= 1'b1;
1901
       {Q4,Q1} : direction_set <= 1'b1;
1902
       default : direction_set <= 1'b0;
1903
     endcase
1904
   // direction_clear
1905
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
1906
     if (rst)
1907
       direction_clr <= 1'b1;
1908
     else
1909
       case ({wptr[N:N-1],rptr[N:N-1]})
1910
         {Q2,Q1} : direction_clr <= 1'b1;
1911
         {Q3,Q2} : direction_clr <= 1'b1;
1912
         {Q4,Q3} : direction_clr <= 1'b1;
1913
         {Q1,Q4} : direction_clr <= 1'b1;
1914
         default : direction_clr <= 1'b0;
1915
       endcase
1916 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
1917 6 unneback
   assign async_empty = (wptr == rptr) && (direction==going_empty);
1918
   assign async_full  = (wptr == rptr) && (direction==going_full);
1919 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
1920
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
1921 6 unneback
/*
1922
   always @ (posedge wclk or posedge rst or posedge async_full)
1923
     if (rst)
1924
       {fifo_full, fifo_full2} <= 2'b00;
1925
     else if (async_full)
1926
       {fifo_full, fifo_full2} <= 2'b11;
1927
     else
1928
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
1929
*/
1930 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
1931 6 unneback
     if (async_empty)
1932
       {fifo_empty, fifo_empty2} <= 2'b11;
1933
     else
1934 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
1935 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
1936
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
1937 6 unneback
endmodule // async_comp
1938
module vl_fifo_1r1w_async (
1939
    d, wr, fifo_full, wr_clk, wr_rst,
1940
    q, rd, fifo_empty, rd_clk, rd_rst
1941
    );
1942
parameter data_width = 18;
1943
parameter addr_width = 4;
1944
// write side
1945
input  [data_width-1:0] d;
1946
input                   wr;
1947
output                  fifo_full;
1948
input                   wr_clk;
1949
input                   wr_rst;
1950
// read side
1951
output [data_width-1:0] q;
1952
input                   rd;
1953
output                  fifo_empty;
1954
input                   rd_clk;
1955
input                   rd_rst;
1956
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
1957 18 unneback
vl_cnt_gray_ce_bin
1958 6 unneback
    # ( .length(addr_width))
1959
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
1960 18 unneback
vl_cnt_gray_ce_bin
1961 6 unneback
    # (.length(addr_width))
1962 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
1963 7 unneback
vl_dpram_1r1w
1964 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
1965
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
1966
vl_fifo_cmp_async
1967
    # (.addr_width(addr_width))
1968
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
1969
endmodule
1970 8 unneback
module vl_fifo_2r2w_async (
1971 6 unneback
    // a side
1972
    a_d, a_wr, a_fifo_full,
1973
    a_q, a_rd, a_fifo_empty,
1974
    a_clk, a_rst,
1975
    // b side
1976
    b_d, b_wr, b_fifo_full,
1977
    b_q, b_rd, b_fifo_empty,
1978
    b_clk, b_rst
1979
    );
1980
parameter data_width = 18;
1981
parameter addr_width = 4;
1982
// a side
1983
input  [data_width-1:0] a_d;
1984
input                   a_wr;
1985
output                  a_fifo_full;
1986
output [data_width-1:0] a_q;
1987
input                   a_rd;
1988
output                  a_fifo_empty;
1989
input                   a_clk;
1990
input                   a_rst;
1991
// b side
1992
input  [data_width-1:0] b_d;
1993
input                   b_wr;
1994
output                  b_fifo_full;
1995
output [data_width-1:0] b_q;
1996
input                   b_rd;
1997
output                  b_fifo_empty;
1998
input                   b_clk;
1999
input                   b_rst;
2000
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
2001
vl_fifo_1r1w_async_a (
2002
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
2003
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
2004
    );
2005
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
2006
vl_fifo_1r1w_async_b (
2007
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
2008
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
2009
    );
2010
endmodule
2011 8 unneback
module vl_fifo_2r2w_async_simplex (
2012 6 unneback
    // a side
2013
    a_d, a_wr, a_fifo_full,
2014
    a_q, a_rd, a_fifo_empty,
2015
    a_clk, a_rst,
2016
    // b side
2017
    b_d, b_wr, b_fifo_full,
2018
    b_q, b_rd, b_fifo_empty,
2019
    b_clk, b_rst
2020
    );
2021
parameter data_width = 18;
2022
parameter addr_width = 4;
2023
// a side
2024
input  [data_width-1:0] a_d;
2025
input                   a_wr;
2026
output                  a_fifo_full;
2027
output [data_width-1:0] a_q;
2028
input                   a_rd;
2029
output                  a_fifo_empty;
2030
input                   a_clk;
2031
input                   a_rst;
2032
// b side
2033
input  [data_width-1:0] b_d;
2034
input                   b_wr;
2035
output                  b_fifo_full;
2036
output [data_width-1:0] b_q;
2037
input                   b_rd;
2038
output                  b_fifo_empty;
2039
input                   b_clk;
2040
input                   b_rst;
2041
// adr_gen
2042
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
2043
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
2044
// dpram
2045
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
2046 18 unneback
vl_cnt_gray_ce_bin
2047 6 unneback
    # ( .length(addr_width))
2048
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
2049 18 unneback
vl_cnt_gray_ce_bin
2050 6 unneback
    # (.length(addr_width))
2051
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
2052 18 unneback
vl_cnt_gray_ce_bin
2053 6 unneback
    # ( .length(addr_width))
2054
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
2055 18 unneback
vl_cnt_gray_ce_bin
2056 6 unneback
    # (.length(addr_width))
2057
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
2058
// mux read or write adr to DPRAM
2059
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
2060
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
2061 11 unneback
vl_dpram_2r2w
2062 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
2063
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
2064
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
2065 11 unneback
vl_fifo_cmp_async
2066 6 unneback
    # (.addr_width(addr_width))
2067
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
2068 11 unneback
vl_fifo_cmp_async
2069 6 unneback
    # (.addr_width(addr_width))
2070
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
2071
endmodule
2072 12 unneback
//////////////////////////////////////////////////////////////////////
2073
////                                                              ////
2074
////  Versatile library, wishbone stuff                           ////
2075
////                                                              ////
2076
////  Description                                                 ////
2077
////  Wishbone compliant modules                                  ////
2078
////                                                              ////
2079
////                                                              ////
2080
////  To Do:                                                      ////
2081
////   -                                                          ////
2082
////                                                              ////
2083
////  Author(s):                                                  ////
2084
////      - Michael Unneback, unneback@opencores.org              ////
2085
////        ORSoC AB                                              ////
2086
////                                                              ////
2087
//////////////////////////////////////////////////////////////////////
2088
////                                                              ////
2089
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2090
////                                                              ////
2091
//// This source file may be used and distributed without         ////
2092
//// restriction provided that this copyright statement is not    ////
2093
//// removed from the file and that any derivative work contains  ////
2094
//// the original copyright notice and the associated disclaimer. ////
2095
////                                                              ////
2096
//// This source file is free software; you can redistribute it   ////
2097
//// and/or modify it under the terms of the GNU Lesser General   ////
2098
//// Public License as published by the Free Software Foundation; ////
2099
//// either version 2.1 of the License, or (at your option) any   ////
2100
//// later version.                                               ////
2101
////                                                              ////
2102
//// This source is distributed in the hope that it will be       ////
2103
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2104
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2105
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2106
//// details.                                                     ////
2107
////                                                              ////
2108
//// You should have received a copy of the GNU Lesser General    ////
2109
//// Public License along with this source; if not, download it   ////
2110
//// from http://www.opencores.org/lgpl.shtml                     ////
2111
////                                                              ////
2112
//////////////////////////////////////////////////////////////////////
2113
// async wb3 - wb3 bridge
2114
`timescale 1ns/1ns
2115 18 unneback
module vl_wb3wb3_bridge (
2116 12 unneback
        // wishbone slave side
2117
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
2118
        // wishbone master side
2119
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
2120
input [31:0] wbs_dat_i;
2121
input [31:2] wbs_adr_i;
2122
input [3:0]  wbs_sel_i;
2123
input [1:0]  wbs_bte_i;
2124
input [2:0]  wbs_cti_i;
2125
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
2126
output [31:0] wbs_dat_o;
2127 14 unneback
output wbs_ack_o;
2128 12 unneback
input wbs_clk, wbs_rst;
2129
output [31:0] wbm_dat_o;
2130
output reg [31:2] wbm_adr_o;
2131
output [3:0]  wbm_sel_o;
2132
output reg [1:0]  wbm_bte_o;
2133
output reg [2:0]  wbm_cti_o;
2134 14 unneback
output reg wbm_we_o;
2135
output wbm_cyc_o;
2136 12 unneback
output wbm_stb_o;
2137
input [31:0]  wbm_dat_i;
2138
input wbm_ack_i;
2139
input wbm_clk, wbm_rst;
2140
parameter addr_width = 4;
2141
// bte
2142
parameter linear       = 2'b00;
2143
parameter wrap4        = 2'b01;
2144
parameter wrap8        = 2'b10;
2145
parameter wrap16       = 2'b11;
2146
// cti
2147
parameter classic      = 3'b000;
2148
parameter incburst     = 3'b010;
2149
parameter endofburst   = 3'b111;
2150
parameter wbs_adr  = 1'b0;
2151
parameter wbs_data = 1'b1;
2152
parameter wbm_adr0 = 2'b00;
2153
parameter wbm_adr1 = 2'b01;
2154
parameter wbm_data = 2'b10;
2155
reg [1:0] wbs_bte_reg;
2156
reg wbs;
2157
wire wbs_eoc_alert, wbm_eoc_alert;
2158
reg wbs_eoc, wbm_eoc;
2159
reg [1:0] wbm;
2160 14 unneback
wire [1:16] wbs_count, wbm_count;
2161 12 unneback
wire [35:0] a_d, a_q, b_d, b_q;
2162
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
2163
reg a_rd_reg;
2164
wire b_rd_adr, b_rd_data;
2165 14 unneback
wire b_rd_data_reg;
2166
wire [35:0] temp;
2167 12 unneback
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
2168
always @ (posedge wbs_clk or posedge wbs_rst)
2169
if (wbs_rst)
2170
        wbs_eoc <= 1'b0;
2171
else
2172
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
2173
                wbs_eoc <= wbs_bte_i==linear;
2174
        else if (wbs_eoc_alert & (a_rd | a_wr))
2175
                wbs_eoc <= 1'b1;
2176 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
2177 12 unneback
    cnt0 (
2178
        .cke(wbs_ack_o),
2179
        .clear(wbs_eoc),
2180
        .q(wbs_count),
2181
        .rst(wbs_rst),
2182
        .clk(wbs_clk));
2183
always @ (posedge wbs_clk or posedge wbs_rst)
2184
if (wbs_rst)
2185
        wbs <= wbs_adr;
2186
else
2187
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
2188
                wbs <= wbs_data;
2189
        else if (wbs_eoc & wbs_ack_o)
2190
                wbs <= wbs_adr;
2191
// wbs FIFO
2192
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
2193
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
2194
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
2195
              1'b0;
2196
assign a_rd = !a_fifo_empty;
2197
always @ (posedge wbs_clk or posedge wbs_rst)
2198
if (wbs_rst)
2199
        a_rd_reg <= 1'b0;
2200
else
2201
        a_rd_reg <= a_rd;
2202
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
2203
assign wbs_dat_o = a_q[35:4];
2204
always @ (posedge wbs_clk or posedge wbs_rst)
2205
if (wbs_rst)
2206 13 unneback
        wbs_bte_reg <= 2'b00;
2207 12 unneback
else
2208 13 unneback
        wbs_bte_reg <= wbs_bte_i;
2209 12 unneback
// wbm FIFO
2210
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
2211
always @ (posedge wbm_clk or posedge wbm_rst)
2212
if (wbm_rst)
2213
        wbm_eoc <= 1'b0;
2214
else
2215
        if (wbm==wbm_adr0 & !b_fifo_empty)
2216
                wbm_eoc <= b_q[4:3] == linear;
2217
        else if (wbm_eoc_alert & wbm_ack_i)
2218
                wbm_eoc <= 1'b1;
2219
always @ (posedge wbm_clk or posedge wbm_rst)
2220
if (wbm_rst)
2221
        wbm <= wbm_adr0;
2222
else
2223
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
2224
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
2225
        (wbm==wbm_adr1 & !wbm_we_o) |
2226
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
2227
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
2228
assign b_d = {wbm_dat_i,4'b1111};
2229
assign b_wr = !wbm_we_o & wbm_ack_i;
2230
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
2231
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
2232
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
2233
                   1'b0;
2234
assign b_rd = b_rd_adr | b_rd_data;
2235 18 unneback
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
2236
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
2237 12 unneback
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
2238 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
2239 12 unneback
    cnt1 (
2240
        .cke(wbm_ack_i),
2241
        .clear(wbm_eoc),
2242
        .q(wbm_count),
2243
        .rst(wbm_rst),
2244
        .clk(wbm_clk));
2245
assign wbm_cyc_o = wbm==wbm_data;
2246
assign wbm_stb_o = (wbm==wbm_data & wbm_we_o) ? !b_fifo_empty :
2247
                   (wbm==wbm_data) ? 1'b1 :
2248
                   1'b0;
2249
always @ (posedge wbm_clk or posedge wbm_rst)
2250
if (wbm_rst)
2251
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
2252
else begin
2253
        if (wbm==wbm_adr0 & !b_fifo_empty)
2254
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
2255
        else if (wbm_eoc_alert & wbm_ack_i)
2256
                wbm_cti_o <= endofburst;
2257
end
2258
//async_fifo_dw_simplex_top
2259
vl_fifo_2r2w_async_simplex
2260
# ( .data_width(36), .addr_width(addr_width))
2261
fifo (
2262
    // a side
2263
    .a_d(a_d),
2264
    .a_wr(a_wr),
2265
    .a_fifo_full(a_fifo_full),
2266
    .a_q(a_q),
2267
    .a_rd(a_rd),
2268
    .a_fifo_empty(a_fifo_empty),
2269
    .a_clk(wbs_clk),
2270
    .a_rst(wbs_rst),
2271
    // b side
2272
    .b_d(b_d),
2273
    .b_wr(b_wr),
2274
    .b_fifo_full(b_fifo_full),
2275
    .b_q(b_q),
2276
    .b_rd(b_rd),
2277
    .b_fifo_empty(b_fifo_empty),
2278
    .b_clk(wbm_clk),
2279
    .b_rst(wbm_rst)
2280
    );
2281
endmodule
2282 17 unneback
// WB ROM
2283 18 unneback
module vl_wb_boot_rom (
2284 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
2285 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
2286
    parameter adr_hi = 31;
2287
    parameter adr_lo = 28;
2288
    parameter adr_sel = 4'hf;
2289
    parameter addr_width = 5;
2290 17 unneback
//E2_ifndef BOOT_ROM
2291
//E2_define BOOT_ROM "boot_rom.v"
2292
//E2_endif
2293 18 unneback
    input [adr_hi:2]    wb_adr_i;
2294
    input               wb_stb_i;
2295
    input               wb_cyc_i;
2296
    output [31:0]        wb_dat_o;
2297
    output              wb_ack_o;
2298
    output              hit_o;
2299
    input               wb_clk;
2300
    input               wb_rst;
2301
    wire hit;
2302
    reg [31:0] wb_dat;
2303
    reg wb_ack;
2304
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
2305 17 unneback
always @ (posedge wb_clk or posedge wb_rst)
2306
    if (wb_rst)
2307 18 unneback
        wb_dat <= 32'h15000000;
2308 17 unneback
    else
2309 18 unneback
         case (wb_adr_i[addr_width-1:2])
2310 17 unneback
//E2_include `BOOT_ROM
2311
           /*
2312
            // Zero r0 and jump to 0x00000100
2313 18 unneback
 
2314
            1 : wb_dat <= 32'hA8200000;
2315
            2 : wb_dat <= 32'hA8C00100;
2316
            3 : wb_dat <= 32'h44003000;
2317
            4 : wb_dat <= 32'h15000000;
2318 17 unneback
            */
2319
           default:
2320 18 unneback
             wb_dat <= 32'h00000000;
2321 17 unneback
         endcase // case (wb_adr_i)
2322
always @ (posedge wb_clk or posedge wb_rst)
2323
    if (wb_rst)
2324 18 unneback
        wb_ack <= 1'b0;
2325 17 unneback
    else
2326 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
2327
assign hit_o = hit;
2328
assign wb_dat_o = wb_dat & {32{wb_ack}};
2329
assign wb_ack_o = wb_ack;
2330 17 unneback
endmodule
2331 18 unneback
//////////////////////////////////////////////////////////////////////
2332
////                                                              ////
2333
////  Arithmetic functions                                        ////
2334
////                                                              ////
2335
////  Description                                                 ////
2336
////  Arithmetic functions for ALU and DSP                        ////
2337
////                                                              ////
2338
////                                                              ////
2339
////  To Do:                                                      ////
2340
////   -                                                          ////
2341
////                                                              ////
2342
////  Author(s):                                                  ////
2343
////      - Michael Unneback, unneback@opencores.org              ////
2344
////        ORSoC AB                                              ////
2345
////                                                              ////
2346
//////////////////////////////////////////////////////////////////////
2347
////                                                              ////
2348
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2349
////                                                              ////
2350
//// This source file may be used and distributed without         ////
2351
//// restriction provided that this copyright statement is not    ////
2352
//// removed from the file and that any derivative work contains  ////
2353
//// the original copyright notice and the associated disclaimer. ////
2354
////                                                              ////
2355
//// This source file is free software; you can redistribute it   ////
2356
//// and/or modify it under the terms of the GNU Lesser General   ////
2357
//// Public License as published by the Free Software Foundation; ////
2358
//// either version 2.1 of the License, or (at your option) any   ////
2359
//// later version.                                               ////
2360
////                                                              ////
2361
//// This source is distributed in the hope that it will be       ////
2362
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2363
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2364
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2365
//// details.                                                     ////
2366
////                                                              ////
2367
//// You should have received a copy of the GNU Lesser General    ////
2368
//// Public License along with this source; if not, download it   ////
2369
//// from http://www.opencores.org/lgpl.shtml                     ////
2370
////                                                              ////
2371
//////////////////////////////////////////////////////////////////////
2372
// signed multiplication
2373
module vl_mults (a,b,p);
2374
parameter operand_a_width = 18;
2375
parameter operand_b_width = 18;
2376
parameter result_hi = 35;
2377
parameter result_lo = 0;
2378
input [operand_a_width-1:0] a;
2379
input [operand_b_width-1:0] b;
2380
output [result_hi:result_lo] p;
2381
wire signed [operand_a_width-1:0] ai;
2382
wire signed [operand_b_width-1:0] bi;
2383
wire signed [operand_a_width+operand_b_width-1:0] result;
2384
    assign ai = a;
2385
    assign bi = b;
2386
    assign result = ai * bi;
2387
    assign p = result[result_hi:result_lo];
2388
endmodule
2389
module vl_mults18x18 (a,b,p);
2390
input [17:0] a,b;
2391
output [35:0] p;
2392
vl_mult
2393
    # (.operand_a_width(18), .operand_b_width(18))
2394
    mult0 (.a(a), .b(b), .p(p));
2395
endmodule
2396
// unsigned multiplication
2397
module vl_mult (a,b,p);
2398
parameter operand_a_width = 18;
2399
parameter operand_b_width = 18;
2400
parameter result_hi = 35;
2401
parameter result_lo = 0;
2402
input [operand_a_width-1:0] a;
2403
input [operand_b_width-1:0] b;
2404
output [result_hi:result_hi] p;
2405
wire [operand_a_width+operand_b_width-1:0] result;
2406
    assign result = a * b;
2407
    assign p = result[result_hi:result_lo];
2408
endmodule
2409
// shift unit
2410
// supporting the following shift functions
2411
//   SLL
2412
//   SRL
2413
//   SRA
2414
module vl_shift_unit_32( din, s, dout, opcode);
2415
input [31:0] din; // data in operand
2416
input [4:0] s; // shift operand
2417
input [1:0] opcode;
2418
output [31:0] dout;
2419
parameter opcode_sll = 2'b00;
2420
//parameter opcode_srl = 2'b01;
2421
parameter opcode_sra = 2'b10;
2422
//parameter opcode_ror = 2'b11;
2423
wire sll, sra;
2424
assign sll = opcode == opcode_sll;
2425
assign sra = opcode == opcode_sra;
2426
wire [15:1] s1;
2427
wire [3:0] sign;
2428
wire [7:0] tmp [0:3];
2429
// first stage is multiplier based
2430
// shift operand as fractional 8.7
2431
assign s1[15] = sll & s[2:0]==3'd7;
2432
assign s1[14] = sll & s[2:0]==3'd6;
2433
assign s1[13] = sll & s[2:0]==3'd5;
2434
assign s1[12] = sll & s[2:0]==3'd4;
2435
assign s1[11] = sll & s[2:0]==3'd3;
2436
assign s1[10] = sll & s[2:0]==3'd2;
2437
assign s1[ 9] = sll & s[2:0]==3'd1;
2438
assign s1[ 8] = s[2:0]==3'd0;
2439
assign s1[ 7] = !sll & s[2:0]==3'd1;
2440
assign s1[ 6] = !sll & s[2:0]==3'd2;
2441
assign s1[ 5] = !sll & s[2:0]==3'd3;
2442
assign s1[ 4] = !sll & s[2:0]==3'd4;
2443
assign s1[ 3] = !sll & s[2:0]==3'd5;
2444
assign s1[ 2] = !sll & s[2:0]==3'd6;
2445
assign s1[ 1] = !sll & s[2:0]==3'd7;
2446
assign sign[3] = din[31] & sra;
2447
assign sign[2] = sign[3] & (&din[31:24]);
2448
assign sign[1] = sign[2] & (&din[23:16]);
2449
assign sign[0] = sign[1] & (&din[15:8]);
2450
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
2451
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
2452
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
2453
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
2454
// second stage is multiplexer based
2455
// shift on byte level
2456
// mux byte 3
2457
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
2458
                     (sll & s[4:3]==2'b01) ? tmp[2] :
2459
                     (sll & s[4:3]==2'b10) ? tmp[1] :
2460
                     (sll & s[4:3]==2'b11) ? tmp[0] :
2461
                     {8{sign[3]}};
2462
// mux byte 2
2463
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
2464
                     (sll & s[4:3]==2'b01) ? tmp[1] :
2465
                     (sll & s[4:3]==2'b10) ? tmp[0] :
2466
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
2467
                     (s[4:3]==2'b01) ? tmp[3] :
2468
                     {8{sign[3]}};
2469
// mux byte 1
2470
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
2471
                     (sll & s[4:3]==2'b01) ? tmp[0] :
2472
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
2473
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
2474
                     (s[4:3]==2'b01) ? tmp[2] :
2475
                     (s[4:3]==2'b10) ? tmp[3] :
2476
                     {8{sign[3]}};
2477
// mux byte 0
2478
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
2479
                     (sll) ?  {8{1'b0}}:
2480
                     (s[4:3]==2'b01) ? tmp[1] :
2481
                     (s[4:3]==2'b10) ? tmp[2] :
2482
                     tmp[3];
2483
endmodule
2484
// logic unit
2485
// supporting the following logic functions
2486
//    a and b
2487
//    a or  b
2488
//    a xor b
2489
//    not b
2490
module vl_logic_unit( a, b, result, opcode);
2491
parameter width = 32;
2492
parameter opcode_and = 2'b00;
2493
parameter opcode_or  = 2'b01;
2494
parameter opcode_xor = 2'b10;
2495
input [width-1:0] a,b;
2496
output [width-1:0] result;
2497
input [1:0] opcode;
2498
assign result = (opcode==opcode_and) ? a & b :
2499
                (opcode==opcode_or)  ? a | b :
2500
                (opcode==opcode_xor) ? a ^ b :
2501
                b;
2502
endmodule
2503
module vl_arith_unit ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
2504
parameter width = 32;
2505
parameter opcode_add = 1'b0;
2506
parameter opcode_sub = 1'b1;
2507
input [width-1:0] a,b;
2508
input c_in, add_sub, sign;
2509
output [width-1:0] result;
2510
output c_out, z, ovfl;
2511
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
2512
assign z = (result=={width{1'b0}});
2513
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
2514
               (~a[width-1] & ~b[width-1] &  result[width-1]);
2515
endmodule