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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Blame information for rev 37

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1 6 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Versatile library, clock and reset                          ////
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////                                                              ////
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////  Description                                                 ////
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////  Logic related to clock and reset                            ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - add more different registers                             ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42
// Global buffer
43
// usage:
44
// use to enable global buffers for high fan out signals such as clock and reset
45 21 unneback
//altera
46 33 unneback
module vl_gbuf ( i, o);
47
input i;
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output o;
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assign o = i;
50
endmodule
51 6 unneback
 // ALTERA
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 //ACTEL
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// sync reset
54 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
55 6 unneback
// output active high global reset sync with two DFFs 
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`timescale 1 ns/100 ps
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module vl_sync_rst ( rst_n_i, rst_o, clk);
58
input rst_n_i, clk;
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output rst_o;
60 18 unneback
reg [1:0] tmp;
61 6 unneback
always @ (posedge clk or negedge rst_n_i)
62
if (!rst_n_i)
63 17 unneback
        tmp <= 2'b11;
64 6 unneback
else
65 33 unneback
        tmp <= {1'b0,tmp[1]};
66 17 unneback
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
67 6 unneback
endmodule
68
// vl_pll
69 32 unneback
///////////////////////////////////////////////////////////////////////////////
70
`timescale 1 ps/1 ps
71
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
72
parameter index = 0;
73
parameter number_of_clk = 1;
74
parameter period_time_0 = 20000;
75
parameter period_time_1 = 20000;
76
parameter period_time_2 = 20000;
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parameter period_time_3 = 20000;
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parameter period_time_4 = 20000;
79
parameter lock_delay = 2000000;
80
input clk_i, rst_n_i;
81
output lock;
82
output reg [0:number_of_clk-1] clk_o;
83
output [0:number_of_clk-1] rst_o;
84 33 unneback
`ifdef SIM_PLL
85 32 unneback
always
86
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
87
generate if (number_of_clk > 1)
88
always
89
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
90
endgenerate
91
generate if (number_of_clk > 2)
92
always
93
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
94
endgenerate
95 33 unneback
generate if (number_of_clk > 3)
96 32 unneback
always
97
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
98
endgenerate
99 33 unneback
generate if (number_of_clk > 4)
100 32 unneback
always
101
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
102
endgenerate
103
genvar i;
104
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
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     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
106
end
107
endgenerate
108 33 unneback
//assign #lock_delay lock = rst_n_i;
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assign lock = rst_n_i;
110 32 unneback
endmodule
111 33 unneback
`else
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`ifdef VL_PLL0
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`ifdef VL_PLL0_CLK1
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    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
115
`endif
116
`ifdef VL_PLL0_CLK2
117
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
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`endif
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`ifdef VL_PLL0_CLK3
120
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
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`endif
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`ifdef VL_PLL0_CLK4
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    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
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`endif
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`ifdef VL_PLL0_CLK5
126
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
127
`endif
128
`endif
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`ifdef VL_PLL1
130
`ifdef VL_PLL1_CLK1
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    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
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`endif
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`ifdef VL_PLL1_CLK2
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    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
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`endif
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`ifdef VL_PLL1_CLK3
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    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
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`endif
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`ifdef VL_PLL1_CLK4
140
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
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`endif
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`ifdef VL_PLL1_CLK5
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    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
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`endif
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`endif
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`ifdef VL_PLL2
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`ifdef VL_PLL2_CLK1
148
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
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`endif
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`ifdef VL_PLL2_CLK2
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    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
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`endif
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`ifdef VL_PLL2_CLK3
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    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
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`endif
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`ifdef VL_PLL2_CLK4
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    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
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`endif
159
`ifdef VL_PLL2_CLK5
160
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
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`endif
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`endif
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`ifdef VL_PLL3
164
`ifdef VL_PLL3_CLK1
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    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
166
`endif
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`ifdef VL_PLL3_CLK2
168
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
169
`endif
170
`ifdef VL_PLL3_CLK3
171
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
172
`endif
173
`ifdef VL_PLL3_CLK4
174
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
175
`endif
176
`ifdef VL_PLL3_CLK5
177
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
178
`endif
179
`endif
180 32 unneback
genvar i;
181
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
182 33 unneback
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
183 32 unneback
end
184
endgenerate
185
endmodule
186 33 unneback
`endif
187 32 unneback
///////////////////////////////////////////////////////////////////////////////
188 6 unneback
 //altera
189
 //actel
190
//////////////////////////////////////////////////////////////////////
191
////                                                              ////
192
////  Versatile library, registers                                ////
193
////                                                              ////
194
////  Description                                                 ////
195
////  Different type of registers                                 ////
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////                                                              ////
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////                                                              ////
198
////  To Do:                                                      ////
199
////   - add more different registers                             ////
200
////                                                              ////
201
////  Author(s):                                                  ////
202
////      - Michael Unneback, unneback@opencores.org              ////
203
////        ORSoC AB                                              ////
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////                                                              ////
205
//////////////////////////////////////////////////////////////////////
206
////                                                              ////
207
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
208
////                                                              ////
209
//// This source file may be used and distributed without         ////
210
//// restriction provided that this copyright statement is not    ////
211
//// removed from the file and that any derivative work contains  ////
212
//// the original copyright notice and the associated disclaimer. ////
213
////                                                              ////
214
//// This source file is free software; you can redistribute it   ////
215
//// and/or modify it under the terms of the GNU Lesser General   ////
216
//// Public License as published by the Free Software Foundation; ////
217
//// either version 2.1 of the License, or (at your option) any   ////
218
//// later version.                                               ////
219
////                                                              ////
220
//// This source is distributed in the hope that it will be       ////
221
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
222
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
223
//// PURPOSE.  See the GNU Lesser General Public License for more ////
224
//// details.                                                     ////
225
////                                                              ////
226
//// You should have received a copy of the GNU Lesser General    ////
227
//// Public License along with this source; if not, download it   ////
228
//// from http://www.opencores.org/lgpl.shtml                     ////
229
////                                                              ////
230
//////////////////////////////////////////////////////////////////////
231 18 unneback
module vl_dff ( d, q, clk, rst);
232 6 unneback
        parameter width = 1;
233
        parameter reset_value = 0;
234
        input [width-1:0] d;
235
        input clk, rst;
236
        output reg [width-1:0] q;
237
        always @ (posedge clk or posedge rst)
238
        if (rst)
239
                q <= reset_value;
240
        else
241
                q <= d;
242
endmodule
243 18 unneback
module vl_dff_array ( d, q, clk, rst);
244 6 unneback
        parameter width = 1;
245
        parameter depth = 2;
246
        parameter reset_value = 1'b0;
247
        input [width-1:0] d;
248
        input clk, rst;
249
        output [width-1:0] q;
250
        reg  [0:depth-1] q_tmp [width-1:0];
251
        integer i;
252
        always @ (posedge clk or posedge rst)
253
        if (rst) begin
254
            for (i=0;i<depth;i=i+1)
255
                q_tmp[i] <= {width{reset_value}};
256
        end else begin
257
            q_tmp[0] <= d;
258
            for (i=1;i<depth;i=i+1)
259
                q_tmp[i] <= q_tmp[i-1];
260
        end
261
    assign q = q_tmp[depth-1];
262
endmodule
263 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
264 6 unneback
        parameter width = 1;
265
        parameter reset_value = 0;
266
        input [width-1:0] d;
267
        input ce, clk, rst;
268
        output reg [width-1:0] q;
269
        always @ (posedge clk or posedge rst)
270
        if (rst)
271
                q <= reset_value;
272
        else
273
                if (ce)
274
                        q <= d;
275
endmodule
276 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
277 8 unneback
        parameter width = 1;
278
        parameter reset_value = 0;
279
        input [width-1:0] d;
280 10 unneback
        input ce, clear, clk, rst;
281 8 unneback
        output reg [width-1:0] q;
282
        always @ (posedge clk or posedge rst)
283
        if (rst)
284
            q <= reset_value;
285
        else
286
            if (ce)
287
                if (clear)
288
                    q <= {width{1'b0}};
289
                else
290
                    q <= d;
291
endmodule
292 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
293
        parameter width = 1;
294
        parameter reset_value = 0;
295
        input [width-1:0] d;
296
        input ce, set, clk, rst;
297
        output reg [width-1:0] q;
298
        always @ (posedge clk or posedge rst)
299
        if (rst)
300
            q <= reset_value;
301
        else
302
            if (ce)
303
                if (set)
304
                    q <= {width{1'b1}};
305
                else
306
                    q <= d;
307
endmodule
308 29 unneback
module vl_spr ( sp, r, q, clk, rst);
309
        parameter width = 1;
310
        parameter reset_value = 0;
311
        input sp, r;
312
        output reg q;
313
        input clk, rst;
314
        always @ (posedge clk or posedge rst)
315
        if (rst)
316
            q <= reset_value;
317
        else
318
            if (sp)
319
                q <= 1'b1;
320
            else if (r)
321
                q <= 1'b0;
322
endmodule
323
module vl_srp ( s, rp, q, clk, rst);
324
        parameter width = 1;
325
        parameter reset_value = 0;
326
        input s, rp;
327
        output reg q;
328
        input clk, rst;
329
        always @ (posedge clk or posedge rst)
330
        if (rst)
331
            q <= reset_value;
332
        else
333
            if (rp)
334
                q <= 1'b0;
335
            else if (s)
336
                q <= 1'b1;
337
endmodule
338 6 unneback
// megafunction wizard: %LPM_FF%
339
// GENERATION: STANDARD
340
// VERSION: WM1.0
341
// MODULE: lpm_ff 
342
// ============================================================
343
// File Name: dff_sr.v
344
// Megafunction Name(s):
345
//                      lpm_ff
346
//
347
// Simulation Library Files(s):
348
//                      lpm
349
// ============================================================
350
// ************************************************************
351
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
352
//
353
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
354
// ************************************************************
355
//Copyright (C) 1991-2010 Altera Corporation
356
//Your use of Altera Corporation's design tools, logic functions 
357
//and other software and tools, and its AMPP partner logic 
358
//functions, and any output files from any of the foregoing 
359
//(including device programming or simulation files), and any 
360
//associated documentation or information are expressly subject 
361
//to the terms and conditions of the Altera Program License 
362
//Subscription Agreement, Altera MegaCore Function License 
363
//Agreement, or other applicable license agreement, including, 
364
//without limitation, that your use is for the sole purpose of 
365
//programming logic devices manufactured by Altera and sold by 
366
//Altera or its authorized distributors.  Please refer to the 
367
//applicable agreement for further details.
368
// synopsys translate_off
369
`timescale 1 ps / 1 ps
370
// synopsys translate_on
371 18 unneback
module vl_dff_sr (
372 6 unneback
        aclr,
373
        aset,
374
        clock,
375
        data,
376
        q);
377
        input     aclr;
378
        input     aset;
379
        input     clock;
380
        input     data;
381
        output    q;
382
        wire [0:0] sub_wire0;
383
        wire [0:0] sub_wire1 = sub_wire0[0:0];
384
        wire  q = sub_wire1;
385
        wire  sub_wire2 = data;
386
        wire  sub_wire3 = sub_wire2;
387
        lpm_ff  lpm_ff_component (
388
                                .aclr (aclr),
389
                                .clock (clock),
390
                                .data (sub_wire3),
391
                                .aset (aset),
392
                                .q (sub_wire0)
393
                                // synopsys translate_off
394
                                ,
395
                                .aload (),
396
                                .enable (),
397
                                .sclr (),
398
                                .sload (),
399
                                .sset ()
400
                                // synopsys translate_on
401
                                );
402
        defparam
403
                lpm_ff_component.lpm_fftype = "DFF",
404
                lpm_ff_component.lpm_type = "LPM_FF",
405
                lpm_ff_component.lpm_width = 1;
406
endmodule
407
// ============================================================
408
// CNX file retrieval info
409
// ============================================================
410
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
411
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
412
// Retrieval info: PRIVATE: ASET NUMERIC "1"
413
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
414
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
415
// Retrieval info: PRIVATE: DFF NUMERIC "1"
416
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
417
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
418
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
419
// Retrieval info: PRIVATE: SSET NUMERIC "0"
420
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
421
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
422
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
423
// Retrieval info: PRIVATE: nBit NUMERIC "1"
424
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
425
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
426
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
427
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
428
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
429
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
430
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
431
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
432
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
433
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
434
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
435
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
436
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
437
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
438
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
439
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
440
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
441
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
442
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
443
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
444
// Retrieval info: LIB_FILE: lpm
445
// LATCH
446
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
447 18 unneback
module vl_latch ( d, le, q, clk);
448 6 unneback
input d, le;
449
output q;
450
input clk;
451
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
452
endmodule
453 18 unneback
module vl_shreg ( d, q, clk, rst);
454 17 unneback
parameter depth = 10;
455
input d;
456
output q;
457
input clk, rst;
458
reg [1:depth] dffs;
459
always @ (posedge clk or posedge rst)
460
if (rst)
461
    dffs <= {depth{1'b0}};
462
else
463
    dffs <= {d,dffs[1:depth-1]};
464
assign q = dffs[depth];
465
endmodule
466 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
467 17 unneback
parameter depth = 10;
468
input d, ce;
469
output q;
470
input clk, rst;
471
reg [1:depth] dffs;
472
always @ (posedge clk or posedge rst)
473
if (rst)
474
    dffs <= {depth{1'b0}};
475
else
476
    if (ce)
477
        dffs <= {d,dffs[1:depth-1]};
478
assign q = dffs[depth];
479
endmodule
480 18 unneback
module vl_delay ( d, q, clk, rst);
481 15 unneback
parameter depth = 10;
482
input d;
483
output q;
484
input clk, rst;
485
reg [1:depth] dffs;
486
always @ (posedge clk or posedge rst)
487
if (rst)
488
    dffs <= {depth{1'b0}};
489
else
490
    dffs <= {d,dffs[1:depth-1]};
491
assign q = dffs[depth];
492
endmodule
493 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
494 17 unneback
parameter depth = 10;
495
input d;
496
output q, emptyflag;
497
input clk, rst;
498
reg [1:depth] dffs;
499
always @ (posedge clk or posedge rst)
500
if (rst)
501
    dffs <= {depth{1'b0}};
502
else
503
    dffs <= {d,dffs[1:depth-1]};
504
assign q = dffs[depth];
505
assign emptyflag = !(|dffs);
506
endmodule
507 6 unneback
//////////////////////////////////////////////////////////////////////
508
////                                                              ////
509 18 unneback
////  Logic functions                                             ////
510
////                                                              ////
511
////  Description                                                 ////
512
////  Logic functions such as multiplexers                        ////
513
////                                                              ////
514
////                                                              ////
515
////  To Do:                                                      ////
516
////   -                                                          ////
517
////                                                              ////
518
////  Author(s):                                                  ////
519
////      - Michael Unneback, unneback@opencores.org              ////
520
////        ORSoC AB                                              ////
521
////                                                              ////
522
//////////////////////////////////////////////////////////////////////
523
////                                                              ////
524
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
525
////                                                              ////
526
//// This source file may be used and distributed without         ////
527
//// restriction provided that this copyright statement is not    ////
528
//// removed from the file and that any derivative work contains  ////
529
//// the original copyright notice and the associated disclaimer. ////
530
////                                                              ////
531
//// This source file is free software; you can redistribute it   ////
532
//// and/or modify it under the terms of the GNU Lesser General   ////
533
//// Public License as published by the Free Software Foundation; ////
534
//// either version 2.1 of the License, or (at your option) any   ////
535
//// later version.                                               ////
536
////                                                              ////
537
//// This source is distributed in the hope that it will be       ////
538
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
539
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
540
//// PURPOSE.  See the GNU Lesser General Public License for more ////
541
//// details.                                                     ////
542
////                                                              ////
543
//// You should have received a copy of the GNU Lesser General    ////
544
//// Public License along with this source; if not, download it   ////
545
//// from http://www.opencores.org/lgpl.shtml                     ////
546
////                                                              ////
547
//////////////////////////////////////////////////////////////////////
548 36 unneback
module vl_mux_andor ( a, sel, dout);
549
parameter width = 32;
550
parameter nr_of_ports = 4;
551
input [nr_of_ports*width-1:0] a;
552
input [nr_of_ports-1:0] sel;
553
output reg [width-1:0] dout;
554
always @ (a, sel)
555
begin
556
    dout = a[width-1:0] & {width{sel[0]}};
557
    for (i=nr_of_ports-2;i<nr_of_ports;i=i+1)
558
        dout = (a[i*width-1:(i-1)*width] & {width{sel[i]}}) | dout;
559
end
560
endmodule
561 34 unneback
module vl_mux2_andor ( a1, a0, sel, dout);
562
parameter width = 32;
563 35 unneback
localparam nr_of_ports = 2;
564 34 unneback
input [width-1:0] a1, a0;
565
input [nr_of_ports-1:0] sel;
566
output [width-1:0] dout;
567 36 unneback
vl_mux_andor
568
    # ( .width(width), .nr_of_ports(nr_of_ports)
569
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
570
/*
571 34 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
572
integer i;
573
// and
574
assign tmp[0] = {width{sel[0]}} & a0;
575
assign tmp[1] = {width{sel[1]}} & a1;
576
// or
577
assign dout = tmp[1] | tmp[0];
578 36 unneback
*/
579 34 unneback
endmodule
580
module vl_mux3_andor ( a2, a1, a0, sel, dout);
581
parameter width = 32;
582 35 unneback
localparam nr_of_ports = 3;
583 34 unneback
input [width-1:0] a2, a1, a0;
584
input [nr_of_ports-1:0] sel;
585
output [width-1:0] dout;
586 36 unneback
vl_mux_andor
587
    # ( .width(width), .nr_of_ports(nr_of_ports)
588
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
589
/*
590 34 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
591
integer i;
592
// and
593
assign tmp[0] = {width{sel[0]}} & a0;
594
assign tmp[1] = {width{sel[1]}} & a1;
595
assign tmp[2] = {width{sel[2]}} & a2;
596
// or
597
assign dout = tmp[2] | tmp[1] | tmp[0];
598 36 unneback
*/
599 34 unneback
endmodule
600 18 unneback
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
601
parameter width = 32;
602 35 unneback
localparam nr_of_ports = 4;
603 18 unneback
input [width-1:0] a3, a2, a1, a0;
604
input [nr_of_ports-1:0] sel;
605 22 unneback
output [width-1:0] dout;
606 36 unneback
vl_mux_andor
607
    # ( .width(width), .nr_of_ports(nr_of_ports)
608
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
609
/*
610 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
611 18 unneback
integer i;
612
// and
613
assign tmp[0] = {width{sel[0]}} & a0;
614
assign tmp[1] = {width{sel[1]}} & a1;
615
assign tmp[2] = {width{sel[2]}} & a2;
616
assign tmp[3] = {width{sel[3]}} & a3;
617
// or
618
assign dout = tmp[3] | tmp[2] | tmp[1] | tmp[0];
619 36 unneback
*/
620 18 unneback
endmodule
621
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
622
parameter width = 32;
623 35 unneback
localparam nr_of_ports = 5;
624 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
625
input [nr_of_ports-1:0] sel;
626 22 unneback
output [width-1:0] dout;
627 36 unneback
vl_mux_andor
628
    # ( .width(width), .nr_of_ports(nr_of_ports)
629
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
630
/*
631 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
632 18 unneback
integer i;
633
// and
634
assign tmp[0] = {width{sel[0]}} & a0;
635
assign tmp[1] = {width{sel[1]}} & a1;
636
assign tmp[2] = {width{sel[2]}} & a2;
637
assign tmp[3] = {width{sel[3]}} & a3;
638
assign tmp[4] = {width{sel[4]}} & a4;
639
// or
640
assign dout = tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
641 36 unneback
*/
642 18 unneback
endmodule
643
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
644
parameter width = 32;
645 35 unneback
localparam nr_of_ports = 6;
646 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
647
input [nr_of_ports-1:0] sel;
648 22 unneback
output [width-1:0] dout;
649 36 unneback
vl_mux_andor
650
    # ( .width(width), .nr_of_ports(nr_of_ports)
651
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
652
/*
653 21 unneback
wire [width-1:0] tmp [nr_of_ports-1:0];
654 18 unneback
integer i;
655
// and
656
assign tmp[0] = {width{sel[0]}} & a0;
657
assign tmp[1] = {width{sel[1]}} & a1;
658
assign tmp[2] = {width{sel[2]}} & a2;
659
assign tmp[3] = {width{sel[3]}} & a3;
660
assign tmp[4] = {width{sel[4]}} & a4;
661
assign tmp[5] = {width{sel[5]}} & a5;
662
// or
663
assign dout = tmp[5] | tmp[4] | tmp[3] | tmp[2] | tmp[1] | tmp[0];
664 36 unneback
*/
665 18 unneback
endmodule
666
//////////////////////////////////////////////////////////////////////
667
////                                                              ////
668 6 unneback
////  Versatile counter                                           ////
669
////                                                              ////
670
////  Description                                                 ////
671
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
672
////  counter                                                     ////
673
////                                                              ////
674
////  To Do:                                                      ////
675
////   - add LFSR with more taps                                  ////
676
////                                                              ////
677
////  Author(s):                                                  ////
678
////      - Michael Unneback, unneback@opencores.org              ////
679
////        ORSoC AB                                              ////
680
////                                                              ////
681
//////////////////////////////////////////////////////////////////////
682
////                                                              ////
683
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
684
////                                                              ////
685
//// This source file may be used and distributed without         ////
686
//// restriction provided that this copyright statement is not    ////
687
//// removed from the file and that any derivative work contains  ////
688
//// the original copyright notice and the associated disclaimer. ////
689
////                                                              ////
690
//// This source file is free software; you can redistribute it   ////
691
//// and/or modify it under the terms of the GNU Lesser General   ////
692
//// Public License as published by the Free Software Foundation; ////
693
//// either version 2.1 of the License, or (at your option) any   ////
694
//// later version.                                               ////
695
////                                                              ////
696
//// This source is distributed in the hope that it will be       ////
697
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
698
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
699
//// PURPOSE.  See the GNU Lesser General Public License for more ////
700
//// details.                                                     ////
701
////                                                              ////
702
//// You should have received a copy of the GNU Lesser General    ////
703
//// Public License along with this source; if not, download it   ////
704
//// from http://www.opencores.org/lgpl.shtml                     ////
705
////                                                              ////
706
//////////////////////////////////////////////////////////////////////
707
// binary counter
708 22 unneback
module vl_cnt_bin ( q, rst, clk);
709
   parameter length = 4;
710
   output [length:1] q;
711
   input rst;
712
   input clk;
713
   parameter clear_value = 0;
714
   parameter set_value = 1;
715
   parameter wrap_value = 0;
716
   parameter level1_value = 15;
717
   reg  [length:1] qi;
718
   wire [length:1] q_next;
719
   assign q_next = qi + {{length-1{1'b0}},1'b1};
720
   always @ (posedge clk or posedge rst)
721
     if (rst)
722
       qi <= {length{1'b0}};
723
     else
724
       qi <= q_next;
725
   assign q = qi;
726
endmodule
727
//////////////////////////////////////////////////////////////////////
728
////                                                              ////
729
////  Versatile counter                                           ////
730
////                                                              ////
731
////  Description                                                 ////
732
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
733
////  counter                                                     ////
734
////                                                              ////
735
////  To Do:                                                      ////
736
////   - add LFSR with more taps                                  ////
737
////                                                              ////
738
////  Author(s):                                                  ////
739
////      - Michael Unneback, unneback@opencores.org              ////
740
////        ORSoC AB                                              ////
741
////                                                              ////
742
//////////////////////////////////////////////////////////////////////
743
////                                                              ////
744
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
745
////                                                              ////
746
//// This source file may be used and distributed without         ////
747
//// restriction provided that this copyright statement is not    ////
748
//// removed from the file and that any derivative work contains  ////
749
//// the original copyright notice and the associated disclaimer. ////
750
////                                                              ////
751
//// This source file is free software; you can redistribute it   ////
752
//// and/or modify it under the terms of the GNU Lesser General   ////
753
//// Public License as published by the Free Software Foundation; ////
754
//// either version 2.1 of the License, or (at your option) any   ////
755
//// later version.                                               ////
756
////                                                              ////
757
//// This source is distributed in the hope that it will be       ////
758
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
759
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
760
//// PURPOSE.  See the GNU Lesser General Public License for more ////
761
//// details.                                                     ////
762
////                                                              ////
763
//// You should have received a copy of the GNU Lesser General    ////
764
//// Public License along with this source; if not, download it   ////
765
//// from http://www.opencores.org/lgpl.shtml                     ////
766
////                                                              ////
767
//////////////////////////////////////////////////////////////////////
768
// binary counter
769
module vl_cnt_bin_clear ( clear, q, rst, clk);
770
   parameter length = 4;
771
   input clear;
772
   output [length:1] q;
773
   input rst;
774
   input clk;
775
   parameter clear_value = 0;
776
   parameter set_value = 1;
777
   parameter wrap_value = 0;
778
   parameter level1_value = 15;
779
   reg  [length:1] qi;
780
   wire [length:1] q_next;
781
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
782
   always @ (posedge clk or posedge rst)
783
     if (rst)
784
       qi <= {length{1'b0}};
785
     else
786
       qi <= q_next;
787
   assign q = qi;
788
endmodule
789
//////////////////////////////////////////////////////////////////////
790
////                                                              ////
791
////  Versatile counter                                           ////
792
////                                                              ////
793
////  Description                                                 ////
794
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
795
////  counter                                                     ////
796
////                                                              ////
797
////  To Do:                                                      ////
798
////   - add LFSR with more taps                                  ////
799
////                                                              ////
800
////  Author(s):                                                  ////
801
////      - Michael Unneback, unneback@opencores.org              ////
802
////        ORSoC AB                                              ////
803
////                                                              ////
804
//////////////////////////////////////////////////////////////////////
805
////                                                              ////
806
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
807
////                                                              ////
808
//// This source file may be used and distributed without         ////
809
//// restriction provided that this copyright statement is not    ////
810
//// removed from the file and that any derivative work contains  ////
811
//// the original copyright notice and the associated disclaimer. ////
812
////                                                              ////
813
//// This source file is free software; you can redistribute it   ////
814
//// and/or modify it under the terms of the GNU Lesser General   ////
815
//// Public License as published by the Free Software Foundation; ////
816
//// either version 2.1 of the License, or (at your option) any   ////
817
//// later version.                                               ////
818
////                                                              ////
819
//// This source is distributed in the hope that it will be       ////
820
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
821
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
822
//// PURPOSE.  See the GNU Lesser General Public License for more ////
823
//// details.                                                     ////
824
////                                                              ////
825
//// You should have received a copy of the GNU Lesser General    ////
826
//// Public License along with this source; if not, download it   ////
827
//// from http://www.opencores.org/lgpl.shtml                     ////
828
////                                                              ////
829
//////////////////////////////////////////////////////////////////////
830
// binary counter
831 18 unneback
module vl_cnt_bin_ce ( cke, q, rst, clk);
832 6 unneback
   parameter length = 4;
833
   input cke;
834
   output [length:1] q;
835
   input rst;
836
   input clk;
837
   parameter clear_value = 0;
838
   parameter set_value = 1;
839
   parameter wrap_value = 0;
840
   parameter level1_value = 15;
841
   reg  [length:1] qi;
842
   wire [length:1] q_next;
843
   assign q_next = qi + {{length-1{1'b0}},1'b1};
844
   always @ (posedge clk or posedge rst)
845
     if (rst)
846
       qi <= {length{1'b0}};
847
     else
848
     if (cke)
849
       qi <= q_next;
850
   assign q = qi;
851
endmodule
852
//////////////////////////////////////////////////////////////////////
853
////                                                              ////
854
////  Versatile counter                                           ////
855
////                                                              ////
856
////  Description                                                 ////
857
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
858
////  counter                                                     ////
859
////                                                              ////
860
////  To Do:                                                      ////
861
////   - add LFSR with more taps                                  ////
862
////                                                              ////
863
////  Author(s):                                                  ////
864
////      - Michael Unneback, unneback@opencores.org              ////
865
////        ORSoC AB                                              ////
866
////                                                              ////
867
//////////////////////////////////////////////////////////////////////
868
////                                                              ////
869
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
870
////                                                              ////
871
//// This source file may be used and distributed without         ////
872
//// restriction provided that this copyright statement is not    ////
873
//// removed from the file and that any derivative work contains  ////
874
//// the original copyright notice and the associated disclaimer. ////
875
////                                                              ////
876
//// This source file is free software; you can redistribute it   ////
877
//// and/or modify it under the terms of the GNU Lesser General   ////
878
//// Public License as published by the Free Software Foundation; ////
879
//// either version 2.1 of the License, or (at your option) any   ////
880
//// later version.                                               ////
881
////                                                              ////
882
//// This source is distributed in the hope that it will be       ////
883
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
884
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
885
//// PURPOSE.  See the GNU Lesser General Public License for more ////
886
//// details.                                                     ////
887
////                                                              ////
888
//// You should have received a copy of the GNU Lesser General    ////
889
//// Public License along with this source; if not, download it   ////
890
//// from http://www.opencores.org/lgpl.shtml                     ////
891
////                                                              ////
892
//////////////////////////////////////////////////////////////////////
893
// binary counter
894 18 unneback
module vl_cnt_bin_ce_clear ( clear, cke, q, rst, clk);
895 6 unneback
   parameter length = 4;
896
   input clear;
897
   input cke;
898
   output [length:1] q;
899
   input rst;
900
   input clk;
901
   parameter clear_value = 0;
902
   parameter set_value = 1;
903
   parameter wrap_value = 0;
904
   parameter level1_value = 15;
905
   reg  [length:1] qi;
906
   wire [length:1] q_next;
907
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
908
   always @ (posedge clk or posedge rst)
909
     if (rst)
910
       qi <= {length{1'b0}};
911
     else
912
     if (cke)
913
       qi <= q_next;
914
   assign q = qi;
915
endmodule
916
//////////////////////////////////////////////////////////////////////
917
////                                                              ////
918
////  Versatile counter                                           ////
919
////                                                              ////
920
////  Description                                                 ////
921
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
922
////  counter                                                     ////
923
////                                                              ////
924
////  To Do:                                                      ////
925
////   - add LFSR with more taps                                  ////
926
////                                                              ////
927
////  Author(s):                                                  ////
928
////      - Michael Unneback, unneback@opencores.org              ////
929
////        ORSoC AB                                              ////
930
////                                                              ////
931
//////////////////////////////////////////////////////////////////////
932
////                                                              ////
933
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
934
////                                                              ////
935
//// This source file may be used and distributed without         ////
936
//// restriction provided that this copyright statement is not    ////
937
//// removed from the file and that any derivative work contains  ////
938
//// the original copyright notice and the associated disclaimer. ////
939
////                                                              ////
940
//// This source file is free software; you can redistribute it   ////
941
//// and/or modify it under the terms of the GNU Lesser General   ////
942
//// Public License as published by the Free Software Foundation; ////
943
//// either version 2.1 of the License, or (at your option) any   ////
944
//// later version.                                               ////
945
////                                                              ////
946
//// This source is distributed in the hope that it will be       ////
947
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
948
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
949
//// PURPOSE.  See the GNU Lesser General Public License for more ////
950
//// details.                                                     ////
951
////                                                              ////
952
//// You should have received a copy of the GNU Lesser General    ////
953
//// Public License along with this source; if not, download it   ////
954
//// from http://www.opencores.org/lgpl.shtml                     ////
955
////                                                              ////
956
//////////////////////////////////////////////////////////////////////
957
// binary counter
958 29 unneback
module vl_cnt_bin_ce_clear_l1_l2 ( clear, cke, q, level1, level2, rst, clk);
959
   parameter length = 4;
960
   input clear;
961
   input cke;
962
   output [length:1] q;
963
   output reg level1;
964
   output reg level2;
965
   input rst;
966
   input clk;
967
   parameter clear_value = 0;
968
   parameter set_value = 1;
969 30 unneback
   parameter wrap_value = 15;
970
   parameter level1_value = 8;
971
   parameter level2_value = 15;
972 29 unneback
   wire rew;
973 30 unneback
   assign rew = 1'b0;
974 29 unneback
   reg  [length:1] qi;
975
   wire [length:1] q_next;
976
   assign q_next =  clear ? {length{1'b0}} :qi + {{length-1{1'b0}},1'b1};
977
   always @ (posedge clk or posedge rst)
978
     if (rst)
979
       qi <= {length{1'b0}};
980
     else
981
     if (cke)
982
       qi <= q_next;
983
   assign q = qi;
984
    always @ (posedge clk or posedge rst)
985
    if (rst)
986
        level1 <= 1'b0;
987
    else
988
    if (cke)
989
    if (clear)
990
        level1 <= 1'b0;
991
    else if (q_next == level1_value)
992
        level1 <= 1'b1;
993
    else if (qi == level1_value & rew)
994
        level1 <= 1'b0;
995
    always @ (posedge clk or posedge rst)
996
    if (rst)
997
        level2 <= 1'b0;
998
    else
999
    if (cke)
1000
    if (clear)
1001
        level2 <= 1'b0;
1002
    else if (q_next == level2_value)
1003
        level2 <= 1'b1;
1004
    else if (qi == level2_value & rew)
1005
        level2 <= 1'b0;
1006
endmodule
1007
//////////////////////////////////////////////////////////////////////
1008
////                                                              ////
1009
////  Versatile counter                                           ////
1010
////                                                              ////
1011
////  Description                                                 ////
1012
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1013
////  counter                                                     ////
1014
////                                                              ////
1015
////  To Do:                                                      ////
1016
////   - add LFSR with more taps                                  ////
1017
////                                                              ////
1018
////  Author(s):                                                  ////
1019
////      - Michael Unneback, unneback@opencores.org              ////
1020
////        ORSoC AB                                              ////
1021
////                                                              ////
1022
//////////////////////////////////////////////////////////////////////
1023
////                                                              ////
1024
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1025
////                                                              ////
1026
//// This source file may be used and distributed without         ////
1027
//// restriction provided that this copyright statement is not    ////
1028
//// removed from the file and that any derivative work contains  ////
1029
//// the original copyright notice and the associated disclaimer. ////
1030
////                                                              ////
1031
//// This source file is free software; you can redistribute it   ////
1032
//// and/or modify it under the terms of the GNU Lesser General   ////
1033
//// Public License as published by the Free Software Foundation; ////
1034
//// either version 2.1 of the License, or (at your option) any   ////
1035
//// later version.                                               ////
1036
////                                                              ////
1037
//// This source is distributed in the hope that it will be       ////
1038
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1039
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1040
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1041
//// details.                                                     ////
1042
////                                                              ////
1043
//// You should have received a copy of the GNU Lesser General    ////
1044
//// Public License along with this source; if not, download it   ////
1045
//// from http://www.opencores.org/lgpl.shtml                     ////
1046
////                                                              ////
1047
//////////////////////////////////////////////////////////////////////
1048
// binary counter
1049 18 unneback
module vl_cnt_bin_ce_clear_set_rew ( clear, set, cke, rew, q, rst, clk);
1050 6 unneback
   parameter length = 4;
1051
   input clear;
1052
   input set;
1053
   input cke;
1054
   input rew;
1055
   output [length:1] q;
1056
   input rst;
1057
   input clk;
1058
   parameter clear_value = 0;
1059
   parameter set_value = 1;
1060
   parameter wrap_value = 0;
1061
   parameter level1_value = 15;
1062
   reg  [length:1] qi;
1063
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1064
   assign q_next_fw  =  clear ? {length{1'b0}} : set ? set_value :qi + {{length-1{1'b0}},1'b1};
1065
   assign q_next_rew =  clear ? clear_value : set ? set_value :qi - {{length-1{1'b0}},1'b1};
1066
   assign q_next = rew ? q_next_rew : q_next_fw;
1067
   always @ (posedge clk or posedge rst)
1068
     if (rst)
1069
       qi <= {length{1'b0}};
1070
     else
1071
     if (cke)
1072
       qi <= q_next;
1073
   assign q = qi;
1074
endmodule
1075
//////////////////////////////////////////////////////////////////////
1076
////                                                              ////
1077
////  Versatile counter                                           ////
1078
////                                                              ////
1079
////  Description                                                 ////
1080
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1081
////  counter                                                     ////
1082
////                                                              ////
1083
////  To Do:                                                      ////
1084
////   - add LFSR with more taps                                  ////
1085
////                                                              ////
1086
////  Author(s):                                                  ////
1087
////      - Michael Unneback, unneback@opencores.org              ////
1088
////        ORSoC AB                                              ////
1089
////                                                              ////
1090
//////////////////////////////////////////////////////////////////////
1091
////                                                              ////
1092
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1093
////                                                              ////
1094
//// This source file may be used and distributed without         ////
1095
//// restriction provided that this copyright statement is not    ////
1096
//// removed from the file and that any derivative work contains  ////
1097
//// the original copyright notice and the associated disclaimer. ////
1098
////                                                              ////
1099
//// This source file is free software; you can redistribute it   ////
1100
//// and/or modify it under the terms of the GNU Lesser General   ////
1101
//// Public License as published by the Free Software Foundation; ////
1102
//// either version 2.1 of the License, or (at your option) any   ////
1103
//// later version.                                               ////
1104
////                                                              ////
1105
//// This source is distributed in the hope that it will be       ////
1106
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1107
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1108
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1109
//// details.                                                     ////
1110
////                                                              ////
1111
//// You should have received a copy of the GNU Lesser General    ////
1112
//// Public License along with this source; if not, download it   ////
1113
//// from http://www.opencores.org/lgpl.shtml                     ////
1114
////                                                              ////
1115
//////////////////////////////////////////////////////////////////////
1116
// binary counter
1117 18 unneback
module vl_cnt_bin_ce_rew_l1 ( cke, rew, level1, rst, clk);
1118 6 unneback
   parameter length = 4;
1119
   input cke;
1120
   input rew;
1121
   output reg level1;
1122
   input rst;
1123
   input clk;
1124
   parameter clear_value = 0;
1125
   parameter set_value = 1;
1126
   parameter wrap_value = 1;
1127
   parameter level1_value = 15;
1128 29 unneback
   wire clear;
1129 30 unneback
   assign clear = 1'b0;
1130 6 unneback
   reg  [length:1] qi;
1131
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1132
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1133
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1134
   assign q_next = rew ? q_next_rew : q_next_fw;
1135
   always @ (posedge clk or posedge rst)
1136
     if (rst)
1137
       qi <= {length{1'b0}};
1138
     else
1139
     if (cke)
1140
       qi <= q_next;
1141
    always @ (posedge clk or posedge rst)
1142
    if (rst)
1143
        level1 <= 1'b0;
1144
    else
1145
    if (cke)
1146 29 unneback
    if (clear)
1147
        level1 <= 1'b0;
1148
    else if (q_next == level1_value)
1149 6 unneback
        level1 <= 1'b1;
1150
    else if (qi == level1_value & rew)
1151
        level1 <= 1'b0;
1152
endmodule
1153
//////////////////////////////////////////////////////////////////////
1154
////                                                              ////
1155
////  Versatile counter                                           ////
1156
////                                                              ////
1157
////  Description                                                 ////
1158
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1159
////  counter                                                     ////
1160
////                                                              ////
1161
////  To Do:                                                      ////
1162
////   - add LFSR with more taps                                  ////
1163
////                                                              ////
1164
////  Author(s):                                                  ////
1165
////      - Michael Unneback, unneback@opencores.org              ////
1166
////        ORSoC AB                                              ////
1167
////                                                              ////
1168
//////////////////////////////////////////////////////////////////////
1169
////                                                              ////
1170
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1171
////                                                              ////
1172
//// This source file may be used and distributed without         ////
1173
//// restriction provided that this copyright statement is not    ////
1174
//// removed from the file and that any derivative work contains  ////
1175
//// the original copyright notice and the associated disclaimer. ////
1176
////                                                              ////
1177
//// This source file is free software; you can redistribute it   ////
1178
//// and/or modify it under the terms of the GNU Lesser General   ////
1179
//// Public License as published by the Free Software Foundation; ////
1180
//// either version 2.1 of the License, or (at your option) any   ////
1181
//// later version.                                               ////
1182
////                                                              ////
1183
//// This source is distributed in the hope that it will be       ////
1184
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1185
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1186
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1187
//// details.                                                     ////
1188
////                                                              ////
1189
//// You should have received a copy of the GNU Lesser General    ////
1190
//// Public License along with this source; if not, download it   ////
1191
//// from http://www.opencores.org/lgpl.shtml                     ////
1192
////                                                              ////
1193
//////////////////////////////////////////////////////////////////////
1194 25 unneback
// binary counter
1195
module vl_cnt_bin_ce_rew_zq_l1 ( cke, rew, zq, level1, rst, clk);
1196
   parameter length = 4;
1197
   input cke;
1198
   input rew;
1199
   output reg zq;
1200
   output reg level1;
1201
   input rst;
1202
   input clk;
1203
   parameter clear_value = 0;
1204
   parameter set_value = 1;
1205
   parameter wrap_value = 1;
1206
   parameter level1_value = 15;
1207 29 unneback
   wire clear;
1208 30 unneback
   assign clear = 1'b0;
1209 25 unneback
   reg  [length:1] qi;
1210
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1211
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1212
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1213
   assign q_next = rew ? q_next_rew : q_next_fw;
1214
   always @ (posedge clk or posedge rst)
1215
     if (rst)
1216
       qi <= {length{1'b0}};
1217
     else
1218
     if (cke)
1219
       qi <= q_next;
1220
   always @ (posedge clk or posedge rst)
1221
     if (rst)
1222
       zq <= 1'b1;
1223
     else
1224
     if (cke)
1225
       zq <= q_next == {length{1'b0}};
1226
    always @ (posedge clk or posedge rst)
1227
    if (rst)
1228
        level1 <= 1'b0;
1229
    else
1230
    if (cke)
1231 29 unneback
    if (clear)
1232
        level1 <= 1'b0;
1233
    else if (q_next == level1_value)
1234 25 unneback
        level1 <= 1'b1;
1235
    else if (qi == level1_value & rew)
1236
        level1 <= 1'b0;
1237
endmodule
1238
//////////////////////////////////////////////////////////////////////
1239
////                                                              ////
1240
////  Versatile counter                                           ////
1241
////                                                              ////
1242
////  Description                                                 ////
1243
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1244
////  counter                                                     ////
1245
////                                                              ////
1246
////  To Do:                                                      ////
1247
////   - add LFSR with more taps                                  ////
1248
////                                                              ////
1249
////  Author(s):                                                  ////
1250
////      - Michael Unneback, unneback@opencores.org              ////
1251
////        ORSoC AB                                              ////
1252
////                                                              ////
1253
//////////////////////////////////////////////////////////////////////
1254
////                                                              ////
1255
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1256
////                                                              ////
1257
//// This source file may be used and distributed without         ////
1258
//// restriction provided that this copyright statement is not    ////
1259
//// removed from the file and that any derivative work contains  ////
1260
//// the original copyright notice and the associated disclaimer. ////
1261
////                                                              ////
1262
//// This source file is free software; you can redistribute it   ////
1263
//// and/or modify it under the terms of the GNU Lesser General   ////
1264
//// Public License as published by the Free Software Foundation; ////
1265
//// either version 2.1 of the License, or (at your option) any   ////
1266
//// later version.                                               ////
1267
////                                                              ////
1268
//// This source is distributed in the hope that it will be       ////
1269
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1270
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1271
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1272
//// details.                                                     ////
1273
////                                                              ////
1274
//// You should have received a copy of the GNU Lesser General    ////
1275
//// Public License along with this source; if not, download it   ////
1276
//// from http://www.opencores.org/lgpl.shtml                     ////
1277
////                                                              ////
1278
//////////////////////////////////////////////////////////////////////
1279
// binary counter
1280
module vl_cnt_bin_ce_rew_q_zq_l1 ( cke, rew, q, zq, level1, rst, clk);
1281
   parameter length = 4;
1282
   input cke;
1283
   input rew;
1284
   output [length:1] q;
1285
   output reg zq;
1286
   output reg level1;
1287
   input rst;
1288
   input clk;
1289
   parameter clear_value = 0;
1290
   parameter set_value = 1;
1291
   parameter wrap_value = 1;
1292
   parameter level1_value = 15;
1293 29 unneback
   wire clear;
1294 30 unneback
   assign clear = 1'b0;
1295 25 unneback
   reg  [length:1] qi;
1296
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1297
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1298
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1299
   assign q_next = rew ? q_next_rew : q_next_fw;
1300
   always @ (posedge clk or posedge rst)
1301
     if (rst)
1302
       qi <= {length{1'b0}};
1303
     else
1304
     if (cke)
1305
       qi <= q_next;
1306
   assign q = qi;
1307
   always @ (posedge clk or posedge rst)
1308
     if (rst)
1309
       zq <= 1'b1;
1310
     else
1311
     if (cke)
1312
       zq <= q_next == {length{1'b0}};
1313
    always @ (posedge clk or posedge rst)
1314
    if (rst)
1315
        level1 <= 1'b0;
1316
    else
1317
    if (cke)
1318 29 unneback
    if (clear)
1319
        level1 <= 1'b0;
1320
    else if (q_next == level1_value)
1321 25 unneback
        level1 <= 1'b1;
1322
    else if (qi == level1_value & rew)
1323
        level1 <= 1'b0;
1324
endmodule
1325
//////////////////////////////////////////////////////////////////////
1326
////                                                              ////
1327
////  Versatile counter                                           ////
1328
////                                                              ////
1329
////  Description                                                 ////
1330
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1331
////  counter                                                     ////
1332
////                                                              ////
1333
////  To Do:                                                      ////
1334
////   - add LFSR with more taps                                  ////
1335
////                                                              ////
1336
////  Author(s):                                                  ////
1337
////      - Michael Unneback, unneback@opencores.org              ////
1338
////        ORSoC AB                                              ////
1339
////                                                              ////
1340
//////////////////////////////////////////////////////////////////////
1341
////                                                              ////
1342
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1343
////                                                              ////
1344
//// This source file may be used and distributed without         ////
1345
//// restriction provided that this copyright statement is not    ////
1346
//// removed from the file and that any derivative work contains  ////
1347
//// the original copyright notice and the associated disclaimer. ////
1348
////                                                              ////
1349
//// This source file is free software; you can redistribute it   ////
1350
//// and/or modify it under the terms of the GNU Lesser General   ////
1351
//// Public License as published by the Free Software Foundation; ////
1352
//// either version 2.1 of the License, or (at your option) any   ////
1353
//// later version.                                               ////
1354
////                                                              ////
1355
//// This source is distributed in the hope that it will be       ////
1356
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1357
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1358
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1359
//// details.                                                     ////
1360
////                                                              ////
1361
//// You should have received a copy of the GNU Lesser General    ////
1362
//// Public License along with this source; if not, download it   ////
1363
//// from http://www.opencores.org/lgpl.shtml                     ////
1364
////                                                              ////
1365
//////////////////////////////////////////////////////////////////////
1366 6 unneback
// LFSR counter
1367 18 unneback
module vl_cnt_lfsr_zq ( zq, rst, clk);
1368 6 unneback
   parameter length = 4;
1369
   output reg zq;
1370
   input rst;
1371
   input clk;
1372
   parameter clear_value = 0;
1373
   parameter set_value = 1;
1374
   parameter wrap_value = 8;
1375
   parameter level1_value = 15;
1376
   reg  [length:1] qi;
1377
   reg lfsr_fb;
1378
   wire [length:1] q_next;
1379
   reg [32:1] polynom;
1380
   integer i;
1381
   always @ (qi)
1382
   begin
1383
        case (length)
1384
         2: polynom = 32'b11;                               // 0x3
1385
         3: polynom = 32'b110;                              // 0x6
1386
         4: polynom = 32'b1100;                             // 0xC
1387
         5: polynom = 32'b10100;                            // 0x14
1388
         6: polynom = 32'b110000;                           // 0x30
1389
         7: polynom = 32'b1100000;                          // 0x60
1390
         8: polynom = 32'b10111000;                         // 0xb8
1391
         9: polynom = 32'b100010000;                        // 0x110
1392
        10: polynom = 32'b1001000000;                       // 0x240
1393
        11: polynom = 32'b10100000000;                      // 0x500
1394
        12: polynom = 32'b100000101001;                     // 0x829
1395
        13: polynom = 32'b1000000001100;                    // 0x100C
1396
        14: polynom = 32'b10000000010101;                   // 0x2015
1397
        15: polynom = 32'b110000000000000;                  // 0x6000
1398
        16: polynom = 32'b1101000000001000;                 // 0xD008
1399
        17: polynom = 32'b10010000000000000;                // 0x12000
1400
        18: polynom = 32'b100000010000000000;               // 0x20400
1401
        19: polynom = 32'b1000000000000100011;              // 0x40023
1402 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
1403 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
1404
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1405
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1406
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1407
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1408
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1409
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1410
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1411
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1412
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1413
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1414
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1415
        default: polynom = 32'b0;
1416
        endcase
1417
        lfsr_fb = qi[length];
1418
        for (i=length-1; i>=1; i=i-1) begin
1419
            if (polynom[i])
1420
                lfsr_fb = lfsr_fb  ~^ qi[i];
1421
        end
1422
    end
1423
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1424
   always @ (posedge clk or posedge rst)
1425
     if (rst)
1426
       qi <= {length{1'b0}};
1427
     else
1428
       qi <= q_next;
1429
   always @ (posedge clk or posedge rst)
1430
     if (rst)
1431
       zq <= 1'b1;
1432
     else
1433
       zq <= q_next == {length{1'b0}};
1434
endmodule
1435
//////////////////////////////////////////////////////////////////////
1436
////                                                              ////
1437
////  Versatile counter                                           ////
1438
////                                                              ////
1439
////  Description                                                 ////
1440
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1441
////  counter                                                     ////
1442
////                                                              ////
1443
////  To Do:                                                      ////
1444
////   - add LFSR with more taps                                  ////
1445
////                                                              ////
1446
////  Author(s):                                                  ////
1447
////      - Michael Unneback, unneback@opencores.org              ////
1448
////        ORSoC AB                                              ////
1449
////                                                              ////
1450
//////////////////////////////////////////////////////////////////////
1451
////                                                              ////
1452
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1453
////                                                              ////
1454
//// This source file may be used and distributed without         ////
1455
//// restriction provided that this copyright statement is not    ////
1456
//// removed from the file and that any derivative work contains  ////
1457
//// the original copyright notice and the associated disclaimer. ////
1458
////                                                              ////
1459
//// This source file is free software; you can redistribute it   ////
1460
//// and/or modify it under the terms of the GNU Lesser General   ////
1461
//// Public License as published by the Free Software Foundation; ////
1462
//// either version 2.1 of the License, or (at your option) any   ////
1463
//// later version.                                               ////
1464
////                                                              ////
1465
//// This source is distributed in the hope that it will be       ////
1466
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1467
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1468
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1469
//// details.                                                     ////
1470
////                                                              ////
1471
//// You should have received a copy of the GNU Lesser General    ////
1472
//// Public License along with this source; if not, download it   ////
1473
//// from http://www.opencores.org/lgpl.shtml                     ////
1474
////                                                              ////
1475
//////////////////////////////////////////////////////////////////////
1476
// LFSR counter
1477 18 unneback
module vl_cnt_lfsr_ce_zq ( cke, zq, rst, clk);
1478 6 unneback
   parameter length = 4;
1479
   input cke;
1480
   output reg zq;
1481
   input rst;
1482
   input clk;
1483
   parameter clear_value = 0;
1484
   parameter set_value = 1;
1485
   parameter wrap_value = 8;
1486
   parameter level1_value = 15;
1487
   reg  [length:1] qi;
1488
   reg lfsr_fb;
1489
   wire [length:1] q_next;
1490
   reg [32:1] polynom;
1491
   integer i;
1492
   always @ (qi)
1493
   begin
1494
        case (length)
1495
         2: polynom = 32'b11;                               // 0x3
1496
         3: polynom = 32'b110;                              // 0x6
1497
         4: polynom = 32'b1100;                             // 0xC
1498
         5: polynom = 32'b10100;                            // 0x14
1499
         6: polynom = 32'b110000;                           // 0x30
1500
         7: polynom = 32'b1100000;                          // 0x60
1501
         8: polynom = 32'b10111000;                         // 0xb8
1502
         9: polynom = 32'b100010000;                        // 0x110
1503
        10: polynom = 32'b1001000000;                       // 0x240
1504
        11: polynom = 32'b10100000000;                      // 0x500
1505
        12: polynom = 32'b100000101001;                     // 0x829
1506
        13: polynom = 32'b1000000001100;                    // 0x100C
1507
        14: polynom = 32'b10000000010101;                   // 0x2015
1508
        15: polynom = 32'b110000000000000;                  // 0x6000
1509
        16: polynom = 32'b1101000000001000;                 // 0xD008
1510
        17: polynom = 32'b10010000000000000;                // 0x12000
1511
        18: polynom = 32'b100000010000000000;               // 0x20400
1512
        19: polynom = 32'b1000000000000100011;              // 0x40023
1513 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
1514 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
1515
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1516
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1517
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1518
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1519
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1520
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1521
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1522
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1523
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1524
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1525
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1526
        default: polynom = 32'b0;
1527
        endcase
1528
        lfsr_fb = qi[length];
1529
        for (i=length-1; i>=1; i=i-1) begin
1530
            if (polynom[i])
1531
                lfsr_fb = lfsr_fb  ~^ qi[i];
1532
        end
1533
    end
1534
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1535
   always @ (posedge clk or posedge rst)
1536
     if (rst)
1537
       qi <= {length{1'b0}};
1538
     else
1539
     if (cke)
1540
       qi <= q_next;
1541
   always @ (posedge clk or posedge rst)
1542
     if (rst)
1543
       zq <= 1'b1;
1544
     else
1545
     if (cke)
1546
       zq <= q_next == {length{1'b0}};
1547
endmodule
1548
//////////////////////////////////////////////////////////////////////
1549
////                                                              ////
1550
////  Versatile counter                                           ////
1551
////                                                              ////
1552
////  Description                                                 ////
1553
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1554
////  counter                                                     ////
1555
////                                                              ////
1556
////  To Do:                                                      ////
1557
////   - add LFSR with more taps                                  ////
1558
////                                                              ////
1559
////  Author(s):                                                  ////
1560
////      - Michael Unneback, unneback@opencores.org              ////
1561
////        ORSoC AB                                              ////
1562
////                                                              ////
1563
//////////////////////////////////////////////////////////////////////
1564
////                                                              ////
1565
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1566
////                                                              ////
1567
//// This source file may be used and distributed without         ////
1568
//// restriction provided that this copyright statement is not    ////
1569
//// removed from the file and that any derivative work contains  ////
1570
//// the original copyright notice and the associated disclaimer. ////
1571
////                                                              ////
1572
//// This source file is free software; you can redistribute it   ////
1573
//// and/or modify it under the terms of the GNU Lesser General   ////
1574
//// Public License as published by the Free Software Foundation; ////
1575
//// either version 2.1 of the License, or (at your option) any   ////
1576
//// later version.                                               ////
1577
////                                                              ////
1578
//// This source is distributed in the hope that it will be       ////
1579
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1580
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1581
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1582
//// details.                                                     ////
1583
////                                                              ////
1584
//// You should have received a copy of the GNU Lesser General    ////
1585
//// Public License along with this source; if not, download it   ////
1586
//// from http://www.opencores.org/lgpl.shtml                     ////
1587
////                                                              ////
1588
//////////////////////////////////////////////////////////////////////
1589
// LFSR counter
1590 27 unneback
module vl_cnt_lfsr_ce_q ( cke, q, rst, clk);
1591
   parameter length = 4;
1592
   input cke;
1593
   output [length:1] q;
1594
   input rst;
1595
   input clk;
1596
   parameter clear_value = 0;
1597
   parameter set_value = 1;
1598
   parameter wrap_value = 8;
1599
   parameter level1_value = 15;
1600
   reg  [length:1] qi;
1601
   reg lfsr_fb;
1602
   wire [length:1] q_next;
1603
   reg [32:1] polynom;
1604
   integer i;
1605
   always @ (qi)
1606
   begin
1607
        case (length)
1608
         2: polynom = 32'b11;                               // 0x3
1609
         3: polynom = 32'b110;                              // 0x6
1610
         4: polynom = 32'b1100;                             // 0xC
1611
         5: polynom = 32'b10100;                            // 0x14
1612
         6: polynom = 32'b110000;                           // 0x30
1613
         7: polynom = 32'b1100000;                          // 0x60
1614
         8: polynom = 32'b10111000;                         // 0xb8
1615
         9: polynom = 32'b100010000;                        // 0x110
1616
        10: polynom = 32'b1001000000;                       // 0x240
1617
        11: polynom = 32'b10100000000;                      // 0x500
1618
        12: polynom = 32'b100000101001;                     // 0x829
1619
        13: polynom = 32'b1000000001100;                    // 0x100C
1620
        14: polynom = 32'b10000000010101;                   // 0x2015
1621
        15: polynom = 32'b110000000000000;                  // 0x6000
1622
        16: polynom = 32'b1101000000001000;                 // 0xD008
1623
        17: polynom = 32'b10010000000000000;                // 0x12000
1624
        18: polynom = 32'b100000010000000000;               // 0x20400
1625
        19: polynom = 32'b1000000000000100011;              // 0x40023
1626 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
1627 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
1628
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1629
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1630
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1631
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1632
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1633
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1634
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1635
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1636
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1637
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1638
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1639
        default: polynom = 32'b0;
1640
        endcase
1641
        lfsr_fb = qi[length];
1642
        for (i=length-1; i>=1; i=i-1) begin
1643
            if (polynom[i])
1644
                lfsr_fb = lfsr_fb  ~^ qi[i];
1645
        end
1646
    end
1647
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1648
   always @ (posedge clk or posedge rst)
1649
     if (rst)
1650
       qi <= {length{1'b0}};
1651
     else
1652
     if (cke)
1653
       qi <= q_next;
1654
   assign q = qi;
1655
endmodule
1656
//////////////////////////////////////////////////////////////////////
1657
////                                                              ////
1658
////  Versatile counter                                           ////
1659
////                                                              ////
1660
////  Description                                                 ////
1661
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1662
////  counter                                                     ////
1663
////                                                              ////
1664
////  To Do:                                                      ////
1665
////   - add LFSR with more taps                                  ////
1666
////                                                              ////
1667
////  Author(s):                                                  ////
1668
////      - Michael Unneback, unneback@opencores.org              ////
1669
////        ORSoC AB                                              ////
1670
////                                                              ////
1671
//////////////////////////////////////////////////////////////////////
1672
////                                                              ////
1673
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1674
////                                                              ////
1675
//// This source file may be used and distributed without         ////
1676
//// restriction provided that this copyright statement is not    ////
1677
//// removed from the file and that any derivative work contains  ////
1678
//// the original copyright notice and the associated disclaimer. ////
1679
////                                                              ////
1680
//// This source file is free software; you can redistribute it   ////
1681
//// and/or modify it under the terms of the GNU Lesser General   ////
1682
//// Public License as published by the Free Software Foundation; ////
1683
//// either version 2.1 of the License, or (at your option) any   ////
1684
//// later version.                                               ////
1685
////                                                              ////
1686
//// This source is distributed in the hope that it will be       ////
1687
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1688
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1689
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1690
//// details.                                                     ////
1691
////                                                              ////
1692
//// You should have received a copy of the GNU Lesser General    ////
1693
//// Public License along with this source; if not, download it   ////
1694
//// from http://www.opencores.org/lgpl.shtml                     ////
1695
////                                                              ////
1696
//////////////////////////////////////////////////////////////////////
1697
// LFSR counter
1698
module vl_cnt_lfsr_ce_clear_q ( clear, cke, q, rst, clk);
1699
   parameter length = 4;
1700
   input clear;
1701
   input cke;
1702
   output [length:1] q;
1703
   input rst;
1704
   input clk;
1705
   parameter clear_value = 0;
1706
   parameter set_value = 1;
1707
   parameter wrap_value = 8;
1708
   parameter level1_value = 15;
1709
   reg  [length:1] qi;
1710
   reg lfsr_fb;
1711
   wire [length:1] q_next;
1712
   reg [32:1] polynom;
1713
   integer i;
1714
   always @ (qi)
1715
   begin
1716
        case (length)
1717
         2: polynom = 32'b11;                               // 0x3
1718
         3: polynom = 32'b110;                              // 0x6
1719
         4: polynom = 32'b1100;                             // 0xC
1720
         5: polynom = 32'b10100;                            // 0x14
1721
         6: polynom = 32'b110000;                           // 0x30
1722
         7: polynom = 32'b1100000;                          // 0x60
1723
         8: polynom = 32'b10111000;                         // 0xb8
1724
         9: polynom = 32'b100010000;                        // 0x110
1725
        10: polynom = 32'b1001000000;                       // 0x240
1726
        11: polynom = 32'b10100000000;                      // 0x500
1727
        12: polynom = 32'b100000101001;                     // 0x829
1728
        13: polynom = 32'b1000000001100;                    // 0x100C
1729
        14: polynom = 32'b10000000010101;                   // 0x2015
1730
        15: polynom = 32'b110000000000000;                  // 0x6000
1731
        16: polynom = 32'b1101000000001000;                 // 0xD008
1732
        17: polynom = 32'b10010000000000000;                // 0x12000
1733
        18: polynom = 32'b100000010000000000;               // 0x20400
1734
        19: polynom = 32'b1000000000000100011;              // 0x40023
1735 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
1736 27 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
1737
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1738
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1739
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1740
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1741
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1742
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1743
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1744
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1745
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1746
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1747
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1748
        default: polynom = 32'b0;
1749
        endcase
1750
        lfsr_fb = qi[length];
1751
        for (i=length-1; i>=1; i=i-1) begin
1752
            if (polynom[i])
1753
                lfsr_fb = lfsr_fb  ~^ qi[i];
1754
        end
1755
    end
1756
   assign q_next =  clear ? {length{1'b0}} :(qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1757
   always @ (posedge clk or posedge rst)
1758
     if (rst)
1759
       qi <= {length{1'b0}};
1760
     else
1761
     if (cke)
1762
       qi <= q_next;
1763
   assign q = qi;
1764
endmodule
1765
//////////////////////////////////////////////////////////////////////
1766
////                                                              ////
1767
////  Versatile counter                                           ////
1768
////                                                              ////
1769
////  Description                                                 ////
1770
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1771
////  counter                                                     ////
1772
////                                                              ////
1773
////  To Do:                                                      ////
1774
////   - add LFSR with more taps                                  ////
1775
////                                                              ////
1776
////  Author(s):                                                  ////
1777
////      - Michael Unneback, unneback@opencores.org              ////
1778
////        ORSoC AB                                              ////
1779
////                                                              ////
1780
//////////////////////////////////////////////////////////////////////
1781
////                                                              ////
1782
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1783
////                                                              ////
1784
//// This source file may be used and distributed without         ////
1785
//// restriction provided that this copyright statement is not    ////
1786
//// removed from the file and that any derivative work contains  ////
1787
//// the original copyright notice and the associated disclaimer. ////
1788
////                                                              ////
1789
//// This source file is free software; you can redistribute it   ////
1790
//// and/or modify it under the terms of the GNU Lesser General   ////
1791
//// Public License as published by the Free Software Foundation; ////
1792
//// either version 2.1 of the License, or (at your option) any   ////
1793
//// later version.                                               ////
1794
////                                                              ////
1795
//// This source is distributed in the hope that it will be       ////
1796
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1797
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1798
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1799
//// details.                                                     ////
1800
////                                                              ////
1801
//// You should have received a copy of the GNU Lesser General    ////
1802
//// Public License along with this source; if not, download it   ////
1803
//// from http://www.opencores.org/lgpl.shtml                     ////
1804
////                                                              ////
1805
//////////////////////////////////////////////////////////////////////
1806
// LFSR counter
1807 22 unneback
module vl_cnt_lfsr_ce_q_zq ( cke, q, zq, rst, clk);
1808
   parameter length = 4;
1809
   input cke;
1810
   output [length:1] q;
1811
   output reg zq;
1812
   input rst;
1813
   input clk;
1814
   parameter clear_value = 0;
1815
   parameter set_value = 1;
1816
   parameter wrap_value = 8;
1817
   parameter level1_value = 15;
1818
   reg  [length:1] qi;
1819
   reg lfsr_fb;
1820
   wire [length:1] q_next;
1821
   reg [32:1] polynom;
1822
   integer i;
1823
   always @ (qi)
1824
   begin
1825
        case (length)
1826
         2: polynom = 32'b11;                               // 0x3
1827
         3: polynom = 32'b110;                              // 0x6
1828
         4: polynom = 32'b1100;                             // 0xC
1829
         5: polynom = 32'b10100;                            // 0x14
1830
         6: polynom = 32'b110000;                           // 0x30
1831
         7: polynom = 32'b1100000;                          // 0x60
1832
         8: polynom = 32'b10111000;                         // 0xb8
1833
         9: polynom = 32'b100010000;                        // 0x110
1834
        10: polynom = 32'b1001000000;                       // 0x240
1835
        11: polynom = 32'b10100000000;                      // 0x500
1836
        12: polynom = 32'b100000101001;                     // 0x829
1837
        13: polynom = 32'b1000000001100;                    // 0x100C
1838
        14: polynom = 32'b10000000010101;                   // 0x2015
1839
        15: polynom = 32'b110000000000000;                  // 0x6000
1840
        16: polynom = 32'b1101000000001000;                 // 0xD008
1841
        17: polynom = 32'b10010000000000000;                // 0x12000
1842
        18: polynom = 32'b100000010000000000;               // 0x20400
1843
        19: polynom = 32'b1000000000000100011;              // 0x40023
1844 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
1845 22 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
1846
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1847
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1848
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1849
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1850
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1851
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1852
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1853
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1854
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1855
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1856
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1857
        default: polynom = 32'b0;
1858
        endcase
1859
        lfsr_fb = qi[length];
1860
        for (i=length-1; i>=1; i=i-1) begin
1861
            if (polynom[i])
1862
                lfsr_fb = lfsr_fb  ~^ qi[i];
1863
        end
1864
    end
1865
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1866
   always @ (posedge clk or posedge rst)
1867
     if (rst)
1868
       qi <= {length{1'b0}};
1869
     else
1870
     if (cke)
1871
       qi <= q_next;
1872
   assign q = qi;
1873
   always @ (posedge clk or posedge rst)
1874
     if (rst)
1875
       zq <= 1'b1;
1876
     else
1877
     if (cke)
1878
       zq <= q_next == {length{1'b0}};
1879
endmodule
1880
//////////////////////////////////////////////////////////////////////
1881
////                                                              ////
1882
////  Versatile counter                                           ////
1883
////                                                              ////
1884
////  Description                                                 ////
1885
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1886
////  counter                                                     ////
1887
////                                                              ////
1888
////  To Do:                                                      ////
1889
////   - add LFSR with more taps                                  ////
1890
////                                                              ////
1891
////  Author(s):                                                  ////
1892
////      - Michael Unneback, unneback@opencores.org              ////
1893
////        ORSoC AB                                              ////
1894
////                                                              ////
1895
//////////////////////////////////////////////////////////////////////
1896
////                                                              ////
1897
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1898
////                                                              ////
1899
//// This source file may be used and distributed without         ////
1900
//// restriction provided that this copyright statement is not    ////
1901
//// removed from the file and that any derivative work contains  ////
1902
//// the original copyright notice and the associated disclaimer. ////
1903
////                                                              ////
1904
//// This source file is free software; you can redistribute it   ////
1905
//// and/or modify it under the terms of the GNU Lesser General   ////
1906
//// Public License as published by the Free Software Foundation; ////
1907
//// either version 2.1 of the License, or (at your option) any   ////
1908
//// later version.                                               ////
1909
////                                                              ////
1910
//// This source is distributed in the hope that it will be       ////
1911
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1912
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1913
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1914
//// details.                                                     ////
1915
////                                                              ////
1916
//// You should have received a copy of the GNU Lesser General    ////
1917
//// Public License along with this source; if not, download it   ////
1918
//// from http://www.opencores.org/lgpl.shtml                     ////
1919
////                                                              ////
1920
//////////////////////////////////////////////////////////////////////
1921
// LFSR counter
1922 18 unneback
module vl_cnt_lfsr_ce_rew_l1 ( cke, rew, level1, rst, clk);
1923 6 unneback
   parameter length = 4;
1924
   input cke;
1925
   input rew;
1926
   output reg level1;
1927
   input rst;
1928
   input clk;
1929
   parameter clear_value = 0;
1930
   parameter set_value = 1;
1931
   parameter wrap_value = 8;
1932
   parameter level1_value = 15;
1933 29 unneback
   wire clear;
1934 30 unneback
   assign clear = 1'b0;
1935 6 unneback
   reg  [length:1] qi;
1936
   reg lfsr_fb, lfsr_fb_rew;
1937
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1938
   reg [32:1] polynom_rew;
1939
   integer j;
1940
   reg [32:1] polynom;
1941
   integer i;
1942
   always @ (qi)
1943
   begin
1944
        case (length)
1945
         2: polynom = 32'b11;                               // 0x3
1946
         3: polynom = 32'b110;                              // 0x6
1947
         4: polynom = 32'b1100;                             // 0xC
1948
         5: polynom = 32'b10100;                            // 0x14
1949
         6: polynom = 32'b110000;                           // 0x30
1950
         7: polynom = 32'b1100000;                          // 0x60
1951
         8: polynom = 32'b10111000;                         // 0xb8
1952
         9: polynom = 32'b100010000;                        // 0x110
1953
        10: polynom = 32'b1001000000;                       // 0x240
1954
        11: polynom = 32'b10100000000;                      // 0x500
1955
        12: polynom = 32'b100000101001;                     // 0x829
1956
        13: polynom = 32'b1000000001100;                    // 0x100C
1957
        14: polynom = 32'b10000000010101;                   // 0x2015
1958
        15: polynom = 32'b110000000000000;                  // 0x6000
1959
        16: polynom = 32'b1101000000001000;                 // 0xD008
1960
        17: polynom = 32'b10010000000000000;                // 0x12000
1961
        18: polynom = 32'b100000010000000000;               // 0x20400
1962
        19: polynom = 32'b1000000000000100011;              // 0x40023
1963 37 unneback
        20: polynom = 32'b10010000000000000000;             // 0x90000
1964 6 unneback
        21: polynom = 32'b101000000000000000000;            // 0x140000
1965
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1966
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1967
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1968
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1969
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1970
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1971
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1972
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1973
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1974
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1975
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1976
        default: polynom = 32'b0;
1977
        endcase
1978
        lfsr_fb = qi[length];
1979
        for (i=length-1; i>=1; i=i-1) begin
1980
            if (polynom[i])
1981
                lfsr_fb = lfsr_fb  ~^ qi[i];
1982
        end
1983
    end
1984
   assign q_next_fw  = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1985
   always @ (qi)
1986
   begin
1987
        case (length)
1988
         2: polynom_rew = 32'b11;
1989
         3: polynom_rew = 32'b110;
1990
         4: polynom_rew = 32'b1100;
1991
         5: polynom_rew = 32'b10100;
1992
         6: polynom_rew = 32'b110000;
1993
         7: polynom_rew = 32'b1100000;
1994
         8: polynom_rew = 32'b10111000;
1995
         9: polynom_rew = 32'b100010000;
1996
        10: polynom_rew = 32'b1001000000;
1997
        11: polynom_rew = 32'b10100000000;
1998
        12: polynom_rew = 32'b100000101001;
1999
        13: polynom_rew = 32'b1000000001100;
2000
        14: polynom_rew = 32'b10000000010101;
2001
        15: polynom_rew = 32'b110000000000000;
2002
        16: polynom_rew = 32'b1101000000001000;
2003
        17: polynom_rew = 32'b10010000000000000;
2004
        18: polynom_rew = 32'b100000010000000000;
2005
        19: polynom_rew = 32'b1000000000000100011;
2006
        20: polynom_rew = 32'b10000010000000000000;
2007
        21: polynom_rew = 32'b101000000000000000000;
2008
        22: polynom_rew = 32'b1100000000000000000000;
2009
        23: polynom_rew = 32'b10000100000000000000000;
2010
        24: polynom_rew = 32'b111000010000000000000000;
2011
        25: polynom_rew = 32'b1001000000000000000000000;
2012
        26: polynom_rew = 32'b10000000000000000000100011;
2013
        27: polynom_rew = 32'b100000000000000000000010011;
2014
        28: polynom_rew = 32'b1100100000000000000000000000;
2015
        29: polynom_rew = 32'b10100000000000000000000000000;
2016
        30: polynom_rew = 32'b100000000000000000000000101001;
2017
        31: polynom_rew = 32'b1001000000000000000000000000000;
2018
        32: polynom_rew = 32'b10000000001000000000000000000011;
2019
        default: polynom_rew = 32'b0;
2020
        endcase
2021
        // rotate left
2022
        polynom_rew[length:1] = { polynom_rew[length-2:1],polynom_rew[length] };
2023
        lfsr_fb_rew = qi[length];
2024
        for (i=length-1; i>=1; i=i-1) begin
2025
            if (polynom_rew[i])
2026
                lfsr_fb_rew = lfsr_fb_rew  ~^ qi[i];
2027
        end
2028
    end
2029
   assign q_next_rew = (qi == wrap_value) ? {length{1'b0}} :{lfsr_fb_rew,qi[length:2]};
2030
   assign q_next = rew ? q_next_rew : q_next_fw;
2031
   always @ (posedge clk or posedge rst)
2032
     if (rst)
2033
       qi <= {length{1'b0}};
2034
     else
2035
     if (cke)
2036
       qi <= q_next;
2037
    always @ (posedge clk or posedge rst)
2038
    if (rst)
2039
        level1 <= 1'b0;
2040
    else
2041
    if (cke)
2042 29 unneback
    if (clear)
2043
        level1 <= 1'b0;
2044
    else if (q_next == level1_value)
2045 6 unneback
        level1 <= 1'b1;
2046
    else if (qi == level1_value & rew)
2047
        level1 <= 1'b0;
2048
endmodule
2049
//////////////////////////////////////////////////////////////////////
2050
////                                                              ////
2051
////  Versatile counter                                           ////
2052
////                                                              ////
2053
////  Description                                                 ////
2054
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2055
////  counter                                                     ////
2056
////                                                              ////
2057
////  To Do:                                                      ////
2058
////   - add LFSR with more taps                                  ////
2059
////                                                              ////
2060
////  Author(s):                                                  ////
2061
////      - Michael Unneback, unneback@opencores.org              ////
2062
////        ORSoC AB                                              ////
2063
////                                                              ////
2064
//////////////////////////////////////////////////////////////////////
2065
////                                                              ////
2066
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2067
////                                                              ////
2068
//// This source file may be used and distributed without         ////
2069
//// restriction provided that this copyright statement is not    ////
2070
//// removed from the file and that any derivative work contains  ////
2071
//// the original copyright notice and the associated disclaimer. ////
2072
////                                                              ////
2073
//// This source file is free software; you can redistribute it   ////
2074
//// and/or modify it under the terms of the GNU Lesser General   ////
2075
//// Public License as published by the Free Software Foundation; ////
2076
//// either version 2.1 of the License, or (at your option) any   ////
2077
//// later version.                                               ////
2078
////                                                              ////
2079
//// This source is distributed in the hope that it will be       ////
2080
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2081
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2082
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2083
//// details.                                                     ////
2084
////                                                              ////
2085
//// You should have received a copy of the GNU Lesser General    ////
2086
//// Public License along with this source; if not, download it   ////
2087
//// from http://www.opencores.org/lgpl.shtml                     ////
2088
////                                                              ////
2089
//////////////////////////////////////////////////////////////////////
2090
// GRAY counter
2091 18 unneback
module vl_cnt_gray ( q, rst, clk);
2092 6 unneback
   parameter length = 4;
2093
   output reg [length:1] q;
2094
   input rst;
2095
   input clk;
2096
   parameter clear_value = 0;
2097
   parameter set_value = 1;
2098
   parameter wrap_value = 8;
2099
   parameter level1_value = 15;
2100
   reg  [length:1] qi;
2101
   wire [length:1] q_next;
2102
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2103
   always @ (posedge clk or posedge rst)
2104
     if (rst)
2105
       qi <= {length{1'b0}};
2106
     else
2107
       qi <= q_next;
2108
   always @ (posedge clk or posedge rst)
2109
     if (rst)
2110
       q <= {length{1'b0}};
2111
     else
2112
         q <= (q_next>>1) ^ q_next;
2113
endmodule
2114
//////////////////////////////////////////////////////////////////////
2115
////                                                              ////
2116
////  Versatile counter                                           ////
2117
////                                                              ////
2118
////  Description                                                 ////
2119
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2120
////  counter                                                     ////
2121
////                                                              ////
2122
////  To Do:                                                      ////
2123
////   - add LFSR with more taps                                  ////
2124
////                                                              ////
2125
////  Author(s):                                                  ////
2126
////      - Michael Unneback, unneback@opencores.org              ////
2127
////        ORSoC AB                                              ////
2128
////                                                              ////
2129
//////////////////////////////////////////////////////////////////////
2130
////                                                              ////
2131
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2132
////                                                              ////
2133
//// This source file may be used and distributed without         ////
2134
//// restriction provided that this copyright statement is not    ////
2135
//// removed from the file and that any derivative work contains  ////
2136
//// the original copyright notice and the associated disclaimer. ////
2137
////                                                              ////
2138
//// This source file is free software; you can redistribute it   ////
2139
//// and/or modify it under the terms of the GNU Lesser General   ////
2140
//// Public License as published by the Free Software Foundation; ////
2141
//// either version 2.1 of the License, or (at your option) any   ////
2142
//// later version.                                               ////
2143
////                                                              ////
2144
//// This source is distributed in the hope that it will be       ////
2145
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2146
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2147
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2148
//// details.                                                     ////
2149
////                                                              ////
2150
//// You should have received a copy of the GNU Lesser General    ////
2151
//// Public License along with this source; if not, download it   ////
2152
//// from http://www.opencores.org/lgpl.shtml                     ////
2153
////                                                              ////
2154
//////////////////////////////////////////////////////////////////////
2155
// GRAY counter
2156 18 unneback
module vl_cnt_gray_ce ( cke, q, rst, clk);
2157 6 unneback
   parameter length = 4;
2158
   input cke;
2159
   output reg [length:1] q;
2160
   input rst;
2161
   input clk;
2162
   parameter clear_value = 0;
2163
   parameter set_value = 1;
2164
   parameter wrap_value = 8;
2165
   parameter level1_value = 15;
2166
   reg  [length:1] qi;
2167
   wire [length:1] q_next;
2168
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2169
   always @ (posedge clk or posedge rst)
2170
     if (rst)
2171
       qi <= {length{1'b0}};
2172
     else
2173
     if (cke)
2174
       qi <= q_next;
2175
   always @ (posedge clk or posedge rst)
2176
     if (rst)
2177
       q <= {length{1'b0}};
2178
     else
2179
       if (cke)
2180
         q <= (q_next>>1) ^ q_next;
2181
endmodule
2182
//////////////////////////////////////////////////////////////////////
2183
////                                                              ////
2184
////  Versatile counter                                           ////
2185
////                                                              ////
2186
////  Description                                                 ////
2187
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
2188
////  counter                                                     ////
2189
////                                                              ////
2190
////  To Do:                                                      ////
2191
////   - add LFSR with more taps                                  ////
2192
////                                                              ////
2193
////  Author(s):                                                  ////
2194
////      - Michael Unneback, unneback@opencores.org              ////
2195
////        ORSoC AB                                              ////
2196
////                                                              ////
2197
//////////////////////////////////////////////////////////////////////
2198
////                                                              ////
2199
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
2200
////                                                              ////
2201
//// This source file may be used and distributed without         ////
2202
//// restriction provided that this copyright statement is not    ////
2203
//// removed from the file and that any derivative work contains  ////
2204
//// the original copyright notice and the associated disclaimer. ////
2205
////                                                              ////
2206
//// This source file is free software; you can redistribute it   ////
2207
//// and/or modify it under the terms of the GNU Lesser General   ////
2208
//// Public License as published by the Free Software Foundation; ////
2209
//// either version 2.1 of the License, or (at your option) any   ////
2210
//// later version.                                               ////
2211
////                                                              ////
2212
//// This source is distributed in the hope that it will be       ////
2213
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2214
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2215
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2216
//// details.                                                     ////
2217
////                                                              ////
2218
//// You should have received a copy of the GNU Lesser General    ////
2219
//// Public License along with this source; if not, download it   ////
2220
//// from http://www.opencores.org/lgpl.shtml                     ////
2221
////                                                              ////
2222
//////////////////////////////////////////////////////////////////////
2223
// GRAY counter
2224 18 unneback
module vl_cnt_gray_ce_bin ( cke, q, q_bin, rst, clk);
2225 6 unneback
   parameter length = 4;
2226
   input cke;
2227
   output reg [length:1] q;
2228
   output [length:1] q_bin;
2229
   input rst;
2230
   input clk;
2231
   parameter clear_value = 0;
2232
   parameter set_value = 1;
2233
   parameter wrap_value = 8;
2234
   parameter level1_value = 15;
2235
   reg  [length:1] qi;
2236
   wire [length:1] q_next;
2237
   assign q_next = qi + {{length-1{1'b0}},1'b1};
2238
   always @ (posedge clk or posedge rst)
2239
     if (rst)
2240
       qi <= {length{1'b0}};
2241
     else
2242
     if (cke)
2243
       qi <= q_next;
2244
   always @ (posedge clk or posedge rst)
2245
     if (rst)
2246
       q <= {length{1'b0}};
2247
     else
2248
       if (cke)
2249
         q <= (q_next>>1) ^ q_next;
2250
   assign q_bin = qi;
2251
endmodule
2252
//////////////////////////////////////////////////////////////////////
2253
////                                                              ////
2254
////  Versatile library, counters                                 ////
2255
////                                                              ////
2256
////  Description                                                 ////
2257
////  counters                                                    ////
2258
////                                                              ////
2259
////                                                              ////
2260
////  To Do:                                                      ////
2261
////   - add more counters                                        ////
2262
////                                                              ////
2263
////  Author(s):                                                  ////
2264
////      - Michael Unneback, unneback@opencores.org              ////
2265
////        ORSoC AB                                              ////
2266
////                                                              ////
2267
//////////////////////////////////////////////////////////////////////
2268
////                                                              ////
2269
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2270
////                                                              ////
2271
//// This source file may be used and distributed without         ////
2272
//// restriction provided that this copyright statement is not    ////
2273
//// removed from the file and that any derivative work contains  ////
2274
//// the original copyright notice and the associated disclaimer. ////
2275
////                                                              ////
2276
//// This source file is free software; you can redistribute it   ////
2277
//// and/or modify it under the terms of the GNU Lesser General   ////
2278
//// Public License as published by the Free Software Foundation; ////
2279
//// either version 2.1 of the License, or (at your option) any   ////
2280
//// later version.                                               ////
2281
////                                                              ////
2282
//// This source is distributed in the hope that it will be       ////
2283
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2284
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2285
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2286
//// details.                                                     ////
2287
////                                                              ////
2288
//// You should have received a copy of the GNU Lesser General    ////
2289
//// Public License along with this source; if not, download it   ////
2290
//// from http://www.opencores.org/lgpl.shtml                     ////
2291
////                                                              ////
2292
//////////////////////////////////////////////////////////////////////
2293 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
2294 6 unneback
   parameter length = 4;
2295
   output reg [0:length-1] q;
2296
   input rst;
2297
   input clk;
2298
    always @ (posedge clk or posedge rst)
2299
    if (rst)
2300
        q <= {1'b1,{length-1{1'b0}}};
2301
    else
2302
        q <= {q[length-1],q[0:length-2]};
2303
endmodule
2304 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
2305 6 unneback
   parameter length = 4;
2306
   input cke;
2307
   output reg [0:length-1] q;
2308
   input rst;
2309
   input clk;
2310
    always @ (posedge clk or posedge rst)
2311
    if (rst)
2312
        q <= {1'b1,{length-1{1'b0}}};
2313
    else
2314
        if (cke)
2315
            q <= {q[length-1],q[0:length-2]};
2316
endmodule
2317 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
2318 6 unneback
   parameter length = 4;
2319
   input cke, clear;
2320
   output reg [0:length-1] q;
2321
   input rst;
2322
   input clk;
2323
    always @ (posedge clk or posedge rst)
2324
    if (rst)
2325
        q <= {1'b1,{length-1{1'b0}}};
2326
    else
2327
        if (cke)
2328
            if (clear)
2329
                q <= {1'b1,{length-1{1'b0}}};
2330
            else
2331
                q <= q >> 1;
2332
endmodule
2333 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
2334 6 unneback
   parameter length = 4;
2335
   input cke, clear;
2336
   output reg [0:length-1] q;
2337
   input rst;
2338
   input clk;
2339
    always @ (posedge clk or posedge rst)
2340
    if (rst)
2341
        q <= {1'b1,{length-1{1'b0}}};
2342
    else
2343
        if (cke)
2344
            if (clear)
2345
                q <= {1'b1,{length-1{1'b0}}};
2346
            else
2347
            q <= {q[length-1],q[0:length-2]};
2348
endmodule
2349
//////////////////////////////////////////////////////////////////////
2350
////                                                              ////
2351
////  Versatile library, memories                                 ////
2352
////                                                              ////
2353
////  Description                                                 ////
2354
////  memories                                                    ////
2355
////                                                              ////
2356
////                                                              ////
2357
////  To Do:                                                      ////
2358
////   - add more memory types                                    ////
2359
////                                                              ////
2360
////  Author(s):                                                  ////
2361
////      - Michael Unneback, unneback@opencores.org              ////
2362
////        ORSoC AB                                              ////
2363
////                                                              ////
2364
//////////////////////////////////////////////////////////////////////
2365
////                                                              ////
2366
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2367
////                                                              ////
2368
//// This source file may be used and distributed without         ////
2369
//// restriction provided that this copyright statement is not    ////
2370
//// removed from the file and that any derivative work contains  ////
2371
//// the original copyright notice and the associated disclaimer. ////
2372
////                                                              ////
2373
//// This source file is free software; you can redistribute it   ////
2374
//// and/or modify it under the terms of the GNU Lesser General   ////
2375
//// Public License as published by the Free Software Foundation; ////
2376
//// either version 2.1 of the License, or (at your option) any   ////
2377
//// later version.                                               ////
2378
////                                                              ////
2379
//// This source is distributed in the hope that it will be       ////
2380
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2381
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2382
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2383
//// details.                                                     ////
2384
////                                                              ////
2385
//// You should have received a copy of the GNU Lesser General    ////
2386
//// Public License along with this source; if not, download it   ////
2387
//// from http://www.opencores.org/lgpl.shtml                     ////
2388
////                                                              ////
2389
//////////////////////////////////////////////////////////////////////
2390
/// ROM
2391 7 unneback
module vl_rom_init ( adr, q, clk);
2392
   parameter data_width = 32;
2393
   parameter addr_width = 8;
2394
   input [(addr_width-1):0]       adr;
2395
   output reg [(data_width-1):0] q;
2396
   input                         clk;
2397
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
2398
   parameter memory_file = "vl_rom.vmem";
2399
   initial
2400
     begin
2401
        $readmemh(memory_file, rom);
2402
     end
2403
   always @ (posedge clk)
2404
     q <= rom[adr];
2405
endmodule
2406 14 unneback
/*
2407 7 unneback
module vl_rom ( adr, q, clk);
2408 6 unneback
parameter data_width = 32;
2409
parameter addr_width = 4;
2410
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
2411
    {32'h18000000},
2412
    {32'hA8200000},
2413
    {32'hA8200000},
2414
    {32'hA8200000},
2415
    {32'h44003000},
2416
    {32'h15000000},
2417
    {32'h15000000},
2418
    {32'h15000000},
2419
    {32'h15000000},
2420
    {32'h15000000},
2421
    {32'h15000000},
2422
    {32'h15000000},
2423
    {32'h15000000},
2424
    {32'h15000000},
2425
    {32'h15000000},
2426
    {32'h15000000}};
2427 7 unneback
input [addr_width-1:0] adr;
2428 6 unneback
output reg [data_width-1:0] q;
2429
input clk;
2430
always @ (posedge clk)
2431 7 unneback
    q <= data[adr];
2432 6 unneback
endmodule
2433 14 unneback
*/
2434 6 unneback
// Single port RAM
2435
module vl_ram ( d, adr, we, q, clk);
2436
   parameter data_width = 32;
2437
   parameter addr_width = 8;
2438
   input [(data_width-1):0]      d;
2439
   input [(addr_width-1):0]       adr;
2440
   input                         we;
2441 7 unneback
   output reg [(data_width-1):0] q;
2442 6 unneback
   input                         clk;
2443
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
2444 7 unneback
   parameter init = 0;
2445
   parameter memory_file = "vl_ram.vmem";
2446
   generate if (init) begin : init_mem
2447
   initial
2448
     begin
2449
        $readmemh(memory_file, ram);
2450
     end
2451
   end
2452
   endgenerate
2453 6 unneback
   always @ (posedge clk)
2454
   begin
2455
   if (we)
2456
     ram[adr] <= d;
2457
   q <= ram[adr];
2458
   end
2459
endmodule
2460 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
2461
   parameter data_width = 32;
2462
   parameter addr_width = 8;
2463
   input [(data_width-1):0]      d;
2464
   input [(addr_width-1):0]       adr;
2465
   input [(addr_width/4)-1:0]    be;
2466
   input                         we;
2467
   output reg [(data_width-1):0] q;
2468
   input                         clk;
2469
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
2470
   parameter init = 0;
2471
   parameter memory_file = "vl_ram.vmem";
2472
   generate if (init) begin : init_mem
2473
   initial
2474
     begin
2475
        $readmemh(memory_file, ram);
2476
     end
2477
   end
2478
   endgenerate
2479
   genvar i;
2480
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
2481
      always @ (posedge clk)
2482
      if (we & be[i])
2483
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
2484
   end
2485
   endgenerate
2486
   always @ (posedge clk)
2487
      q <= ram[adr];
2488
endmodule
2489 6 unneback
// Dual port RAM
2490
// ACTEL FPGA should not use logic to handle rw collision
2491 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
2492 6 unneback
   parameter data_width = 32;
2493
   parameter addr_width = 8;
2494
   input [(data_width-1):0]      d_a;
2495
   input [(addr_width-1):0]       adr_a;
2496
   input [(addr_width-1):0]       adr_b;
2497
   input                         we_a;
2498
   output [(data_width-1):0]      q_b;
2499
   input                         clk_a, clk_b;
2500
   reg [(addr_width-1):0]         adr_b_reg;
2501
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
2502 7 unneback
   parameter init = 0;
2503
   parameter memory_file = "vl_ram.vmem";
2504
   generate if (init) begin : init_mem
2505
   initial
2506
     begin
2507
        $readmemh(memory_file, ram);
2508
     end
2509
   end
2510
   endgenerate
2511 6 unneback
   always @ (posedge clk_a)
2512
   if (we_a)
2513
     ram[adr_a] <= d_a;
2514
   always @ (posedge clk_b)
2515
   adr_b_reg <= adr_b;
2516
   assign q_b = ram[adr_b_reg];
2517
endmodule
2518 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
2519 6 unneback
   parameter data_width = 32;
2520
   parameter addr_width = 8;
2521
   input [(data_width-1):0]      d_a;
2522
   input [(addr_width-1):0]       adr_a;
2523
   input [(addr_width-1):0]       adr_b;
2524
   input                         we_a;
2525
   output [(data_width-1):0]      q_b;
2526
   output reg [(data_width-1):0] q_a;
2527
   input                         clk_a, clk_b;
2528
   reg [(data_width-1):0]         q_b;
2529
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
2530 7 unneback
   parameter init = 0;
2531
   parameter memory_file = "vl_ram.vmem";
2532
   generate if (init) begin : init_mem
2533
   initial
2534
     begin
2535
        $readmemh(memory_file, ram);
2536
     end
2537
   end
2538
   endgenerate
2539 6 unneback
   always @ (posedge clk_a)
2540
     begin
2541
        q_a <= ram[adr_a];
2542
        if (we_a)
2543
             ram[adr_a] <= d_a;
2544
     end
2545
   always @ (posedge clk_b)
2546
          q_b <= ram[adr_b];
2547
endmodule
2548 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
2549 6 unneback
   parameter data_width = 32;
2550
   parameter addr_width = 8;
2551
   input [(data_width-1):0]      d_a;
2552
   input [(addr_width-1):0]       adr_a;
2553
   input [(addr_width-1):0]       adr_b;
2554
   input                         we_a;
2555
   output [(data_width-1):0]      q_b;
2556
   input [(data_width-1):0]       d_b;
2557
   output reg [(data_width-1):0] q_a;
2558
   input                         we_b;
2559
   input                         clk_a, clk_b;
2560
   reg [(data_width-1):0]         q_b;
2561
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
2562 7 unneback
   parameter init = 0;
2563
   parameter memory_file = "vl_ram.vmem";
2564
   generate if (init) begin : init_mem
2565
   initial
2566
     begin
2567
        $readmemh(memory_file, ram);
2568
     end
2569
   end
2570
   endgenerate
2571 6 unneback
   always @ (posedge clk_a)
2572
     begin
2573
        q_a <= ram[adr_a];
2574
        if (we_a)
2575
             ram[adr_a] <= d_a;
2576
     end
2577
   always @ (posedge clk_b)
2578
     begin
2579
        q_b <= ram[adr_b];
2580
        if (we_b)
2581
          ram[adr_b] <= d_b;
2582
     end
2583
endmodule
2584
// Content addresable memory, CAM
2585
// FIFO
2586 25 unneback
module vl_fifo_1r1w_fill_level_sync (
2587
    d, wr, fifo_full,
2588
    q, rd, fifo_empty,
2589
    fill_level,
2590
    clk, rst
2591
    );
2592
parameter data_width = 18;
2593
parameter addr_width = 4;
2594
// write side
2595
input  [data_width-1:0] d;
2596
input                   wr;
2597
output                  fifo_full;
2598
// read side
2599
output [data_width-1:0] q;
2600
input                   rd;
2601
output                  fifo_empty;
2602
// common
2603
output [addr_width:0]   fill_level;
2604
input rst, clk;
2605
wire [addr_width:1] wadr, radr;
2606
vl_cnt_bin_ce
2607
    # ( .length(addr_width))
2608
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
2609
vl_cnt_bin_ce
2610
    # (.length(addr_width))
2611
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
2612
vl_dpram_1r1w
2613
    # (.data_width(data_width), .addr_width(addr_width))
2614
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
2615 31 unneback
vl_cnt_bin_ce_rew_q_zq_l1
2616 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
2617 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
2618
endmodule
2619 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
2620
// RAM is supposed to be larger than the two FIFOs
2621
// LFSR counters used adr pointers
2622
module vl_fifo_2r2w_sync_simplex (
2623
    // a side
2624
    a_d, a_wr, a_fifo_full,
2625
    a_q, a_rd, a_fifo_empty,
2626
    a_fill_level,
2627
    // b side
2628
    b_d, b_wr, b_fifo_full,