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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Blame information for rev 43

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1 6 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Versatile library, clock and reset                          ////
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////                                                              ////
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////  Description                                                 ////
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////  Logic related to clock and reset                            ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   - add more different registers                             ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42
// Global buffer
43
// usage:
44
// use to enable global buffers for high fan out signals such as clock and reset
45 21 unneback
//altera
46 33 unneback
module vl_gbuf ( i, o);
47
input i;
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output o;
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assign o = i;
50
endmodule
51 6 unneback
 // ALTERA
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 //ACTEL
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// sync reset
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// input active lo async reset, normally from external reset generator and/or switch
55 6 unneback
// output active high global reset sync with two DFFs 
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`timescale 1 ns/100 ps
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module vl_sync_rst ( rst_n_i, rst_o, clk);
58
input rst_n_i, clk;
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output rst_o;
60 18 unneback
reg [1:0] tmp;
61 6 unneback
always @ (posedge clk or negedge rst_n_i)
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if (!rst_n_i)
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        tmp <= 2'b11;
64 6 unneback
else
65 33 unneback
        tmp <= {1'b0,tmp[1]};
66 17 unneback
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
67 6 unneback
endmodule
68
// vl_pll
69 32 unneback
///////////////////////////////////////////////////////////////////////////////
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`timescale 1 ps/1 ps
71
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
72
parameter index = 0;
73
parameter number_of_clk = 1;
74
parameter period_time_0 = 20000;
75
parameter period_time_1 = 20000;
76
parameter period_time_2 = 20000;
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parameter period_time_3 = 20000;
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parameter period_time_4 = 20000;
79
parameter lock_delay = 2000000;
80
input clk_i, rst_n_i;
81
output lock;
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output reg [0:number_of_clk-1] clk_o;
83
output [0:number_of_clk-1] rst_o;
84 33 unneback
`ifdef SIM_PLL
85 32 unneback
always
86
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
87
generate if (number_of_clk > 1)
88
always
89
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
90
endgenerate
91
generate if (number_of_clk > 2)
92
always
93
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
94
endgenerate
95 33 unneback
generate if (number_of_clk > 3)
96 32 unneback
always
97
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
98
endgenerate
99 33 unneback
generate if (number_of_clk > 4)
100 32 unneback
always
101
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
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endgenerate
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genvar i;
104
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
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     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
106
end
107
endgenerate
108 33 unneback
//assign #lock_delay lock = rst_n_i;
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assign lock = rst_n_i;
110 32 unneback
endmodule
111 33 unneback
`else
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`ifdef VL_PLL0
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`ifdef VL_PLL0_CLK1
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    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
115
`endif
116
`ifdef VL_PLL0_CLK2
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    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
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`endif
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`ifdef VL_PLL0_CLK3
120
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
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`endif
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`ifdef VL_PLL0_CLK4
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    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
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`endif
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`ifdef VL_PLL0_CLK5
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    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
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`endif
128
`endif
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`ifdef VL_PLL1
130
`ifdef VL_PLL1_CLK1
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    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
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`endif
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`ifdef VL_PLL1_CLK2
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    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
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`endif
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`ifdef VL_PLL1_CLK3
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    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
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`endif
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`ifdef VL_PLL1_CLK4
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    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
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`endif
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`ifdef VL_PLL1_CLK5
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    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
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`endif
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`endif
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`ifdef VL_PLL2
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`ifdef VL_PLL2_CLK1
148
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
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`endif
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`ifdef VL_PLL2_CLK2
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    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
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`endif
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`ifdef VL_PLL2_CLK3
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    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
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`endif
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`ifdef VL_PLL2_CLK4
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    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
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`endif
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`ifdef VL_PLL2_CLK5
160
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
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`endif
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`endif
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`ifdef VL_PLL3
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`ifdef VL_PLL3_CLK1
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    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
166
`endif
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`ifdef VL_PLL3_CLK2
168
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
169
`endif
170
`ifdef VL_PLL3_CLK3
171
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
172
`endif
173
`ifdef VL_PLL3_CLK4
174
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
175
`endif
176
`ifdef VL_PLL3_CLK5
177
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
178
`endif
179
`endif
180 32 unneback
genvar i;
181
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
182 40 unneback
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
183 32 unneback
end
184
endgenerate
185
endmodule
186 33 unneback
`endif
187 32 unneback
///////////////////////////////////////////////////////////////////////////////
188 6 unneback
 //altera
189
 //actel
190
//////////////////////////////////////////////////////////////////////
191
////                                                              ////
192
////  Versatile library, registers                                ////
193
////                                                              ////
194
////  Description                                                 ////
195
////  Different type of registers                                 ////
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////                                                              ////
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////                                                              ////
198
////  To Do:                                                      ////
199
////   - add more different registers                             ////
200
////                                                              ////
201
////  Author(s):                                                  ////
202
////      - Michael Unneback, unneback@opencores.org              ////
203
////        ORSoC AB                                              ////
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////                                                              ////
205
//////////////////////////////////////////////////////////////////////
206
////                                                              ////
207
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
208
////                                                              ////
209
//// This source file may be used and distributed without         ////
210
//// restriction provided that this copyright statement is not    ////
211
//// removed from the file and that any derivative work contains  ////
212
//// the original copyright notice and the associated disclaimer. ////
213
////                                                              ////
214
//// This source file is free software; you can redistribute it   ////
215
//// and/or modify it under the terms of the GNU Lesser General   ////
216
//// Public License as published by the Free Software Foundation; ////
217
//// either version 2.1 of the License, or (at your option) any   ////
218
//// later version.                                               ////
219
////                                                              ////
220
//// This source is distributed in the hope that it will be       ////
221
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
222
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
223
//// PURPOSE.  See the GNU Lesser General Public License for more ////
224
//// details.                                                     ////
225
////                                                              ////
226
//// You should have received a copy of the GNU Lesser General    ////
227
//// Public License along with this source; if not, download it   ////
228
//// from http://www.opencores.org/lgpl.shtml                     ////
229
////                                                              ////
230
//////////////////////////////////////////////////////////////////////
231 18 unneback
module vl_dff ( d, q, clk, rst);
232 6 unneback
        parameter width = 1;
233
        parameter reset_value = 0;
234
        input [width-1:0] d;
235
        input clk, rst;
236
        output reg [width-1:0] q;
237
        always @ (posedge clk or posedge rst)
238
        if (rst)
239
                q <= reset_value;
240
        else
241
                q <= d;
242
endmodule
243 18 unneback
module vl_dff_array ( d, q, clk, rst);
244 6 unneback
        parameter width = 1;
245
        parameter depth = 2;
246
        parameter reset_value = 1'b0;
247
        input [width-1:0] d;
248
        input clk, rst;
249
        output [width-1:0] q;
250
        reg  [0:depth-1] q_tmp [width-1:0];
251
        integer i;
252
        always @ (posedge clk or posedge rst)
253
        if (rst) begin
254
            for (i=0;i<depth;i=i+1)
255
                q_tmp[i] <= {width{reset_value}};
256
        end else begin
257
            q_tmp[0] <= d;
258
            for (i=1;i<depth;i=i+1)
259
                q_tmp[i] <= q_tmp[i-1];
260
        end
261
    assign q = q_tmp[depth-1];
262
endmodule
263 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
264 6 unneback
        parameter width = 1;
265
        parameter reset_value = 0;
266
        input [width-1:0] d;
267
        input ce, clk, rst;
268
        output reg [width-1:0] q;
269
        always @ (posedge clk or posedge rst)
270
        if (rst)
271
                q <= reset_value;
272
        else
273
                if (ce)
274
                        q <= d;
275
endmodule
276 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
277 8 unneback
        parameter width = 1;
278
        parameter reset_value = 0;
279
        input [width-1:0] d;
280 10 unneback
        input ce, clear, clk, rst;
281 8 unneback
        output reg [width-1:0] q;
282
        always @ (posedge clk or posedge rst)
283
        if (rst)
284
            q <= reset_value;
285
        else
286
            if (ce)
287
                if (clear)
288
                    q <= {width{1'b0}};
289
                else
290
                    q <= d;
291
endmodule
292 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
293
        parameter width = 1;
294
        parameter reset_value = 0;
295
        input [width-1:0] d;
296
        input ce, set, clk, rst;
297
        output reg [width-1:0] q;
298
        always @ (posedge clk or posedge rst)
299
        if (rst)
300
            q <= reset_value;
301
        else
302
            if (ce)
303
                if (set)
304
                    q <= {width{1'b1}};
305
                else
306
                    q <= d;
307
endmodule
308 29 unneback
module vl_spr ( sp, r, q, clk, rst);
309
        parameter width = 1;
310
        parameter reset_value = 0;
311
        input sp, r;
312
        output reg q;
313
        input clk, rst;
314
        always @ (posedge clk or posedge rst)
315
        if (rst)
316
            q <= reset_value;
317
        else
318
            if (sp)
319
                q <= 1'b1;
320
            else if (r)
321
                q <= 1'b0;
322
endmodule
323
module vl_srp ( s, rp, q, clk, rst);
324
        parameter width = 1;
325
        parameter reset_value = 0;
326
        input s, rp;
327
        output reg q;
328
        input clk, rst;
329
        always @ (posedge clk or posedge rst)
330
        if (rst)
331
            q <= reset_value;
332
        else
333
            if (rp)
334
                q <= 1'b0;
335
            else if (s)
336
                q <= 1'b1;
337
endmodule
338 6 unneback
// megafunction wizard: %LPM_FF%
339
// GENERATION: STANDARD
340
// VERSION: WM1.0
341
// MODULE: lpm_ff 
342
// ============================================================
343
// File Name: dff_sr.v
344
// Megafunction Name(s):
345
//                      lpm_ff
346
//
347
// Simulation Library Files(s):
348
//                      lpm
349
// ============================================================
350
// ************************************************************
351
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
352
//
353
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
354
// ************************************************************
355
//Copyright (C) 1991-2010 Altera Corporation
356
//Your use of Altera Corporation's design tools, logic functions 
357
//and other software and tools, and its AMPP partner logic 
358
//functions, and any output files from any of the foregoing 
359
//(including device programming or simulation files), and any 
360
//associated documentation or information are expressly subject 
361
//to the terms and conditions of the Altera Program License 
362
//Subscription Agreement, Altera MegaCore Function License 
363
//Agreement, or other applicable license agreement, including, 
364
//without limitation, that your use is for the sole purpose of 
365
//programming logic devices manufactured by Altera and sold by 
366
//Altera or its authorized distributors.  Please refer to the 
367
//applicable agreement for further details.
368
// synopsys translate_off
369
`timescale 1 ps / 1 ps
370
// synopsys translate_on
371 18 unneback
module vl_dff_sr (
372 6 unneback
        aclr,
373
        aset,
374
        clock,
375
        data,
376
        q);
377
        input     aclr;
378
        input     aset;
379
        input     clock;
380
        input     data;
381
        output    q;
382
        wire [0:0] sub_wire0;
383
        wire [0:0] sub_wire1 = sub_wire0[0:0];
384
        wire  q = sub_wire1;
385
        wire  sub_wire2 = data;
386
        wire  sub_wire3 = sub_wire2;
387
        lpm_ff  lpm_ff_component (
388
                                .aclr (aclr),
389
                                .clock (clock),
390
                                .data (sub_wire3),
391
                                .aset (aset),
392
                                .q (sub_wire0)
393
                                // synopsys translate_off
394
                                ,
395
                                .aload (),
396
                                .enable (),
397
                                .sclr (),
398
                                .sload (),
399
                                .sset ()
400
                                // synopsys translate_on
401
                                );
402
        defparam
403
                lpm_ff_component.lpm_fftype = "DFF",
404
                lpm_ff_component.lpm_type = "LPM_FF",
405
                lpm_ff_component.lpm_width = 1;
406
endmodule
407
// ============================================================
408
// CNX file retrieval info
409
// ============================================================
410
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
411
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
412
// Retrieval info: PRIVATE: ASET NUMERIC "1"
413
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
414
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
415
// Retrieval info: PRIVATE: DFF NUMERIC "1"
416
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
417
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
418
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
419
// Retrieval info: PRIVATE: SSET NUMERIC "0"
420
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
421
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
422
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
423
// Retrieval info: PRIVATE: nBit NUMERIC "1"
424
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
425
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
426
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
427
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
428
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
429
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
430
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
431
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
432
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
433
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
434
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
435
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
436
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
437
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
438
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
439
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
440
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
441
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
442
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
443
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
444
// Retrieval info: LIB_FILE: lpm
445
// LATCH
446
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
447 18 unneback
module vl_latch ( d, le, q, clk);
448 6 unneback
input d, le;
449
output q;
450
input clk;
451
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
452
endmodule
453 18 unneback
module vl_shreg ( d, q, clk, rst);
454 17 unneback
parameter depth = 10;
455
input d;
456
output q;
457
input clk, rst;
458
reg [1:depth] dffs;
459
always @ (posedge clk or posedge rst)
460
if (rst)
461
    dffs <= {depth{1'b0}};
462
else
463
    dffs <= {d,dffs[1:depth-1]};
464
assign q = dffs[depth];
465
endmodule
466 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
467 17 unneback
parameter depth = 10;
468
input d, ce;
469
output q;
470
input clk, rst;
471
reg [1:depth] dffs;
472
always @ (posedge clk or posedge rst)
473
if (rst)
474
    dffs <= {depth{1'b0}};
475
else
476
    if (ce)
477
        dffs <= {d,dffs[1:depth-1]};
478
assign q = dffs[depth];
479
endmodule
480 18 unneback
module vl_delay ( d, q, clk, rst);
481 15 unneback
parameter depth = 10;
482
input d;
483
output q;
484
input clk, rst;
485
reg [1:depth] dffs;
486
always @ (posedge clk or posedge rst)
487
if (rst)
488
    dffs <= {depth{1'b0}};
489
else
490
    dffs <= {d,dffs[1:depth-1]};
491
assign q = dffs[depth];
492
endmodule
493 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
494 17 unneback
parameter depth = 10;
495
input d;
496
output q, emptyflag;
497
input clk, rst;
498
reg [1:depth] dffs;
499
always @ (posedge clk or posedge rst)
500
if (rst)
501
    dffs <= {depth{1'b0}};
502
else
503
    dffs <= {d,dffs[1:depth-1]};
504
assign q = dffs[depth];
505
assign emptyflag = !(|dffs);
506
endmodule
507 6 unneback
//////////////////////////////////////////////////////////////////////
508
////                                                              ////
509 18 unneback
////  Logic functions                                             ////
510
////                                                              ////
511
////  Description                                                 ////
512
////  Logic functions such as multiplexers                        ////
513
////                                                              ////
514
////                                                              ////
515
////  To Do:                                                      ////
516
////   -                                                          ////
517
////                                                              ////
518
////  Author(s):                                                  ////
519
////      - Michael Unneback, unneback@opencores.org              ////
520
////        ORSoC AB                                              ////
521
////                                                              ////
522
//////////////////////////////////////////////////////////////////////
523
////                                                              ////
524
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
525
////                                                              ////
526
//// This source file may be used and distributed without         ////
527
//// restriction provided that this copyright statement is not    ////
528
//// removed from the file and that any derivative work contains  ////
529
//// the original copyright notice and the associated disclaimer. ////
530
////                                                              ////
531
//// This source file is free software; you can redistribute it   ////
532
//// and/or modify it under the terms of the GNU Lesser General   ////
533
//// Public License as published by the Free Software Foundation; ////
534
//// either version 2.1 of the License, or (at your option) any   ////
535
//// later version.                                               ////
536
////                                                              ////
537
//// This source is distributed in the hope that it will be       ////
538
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
539
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
540
//// PURPOSE.  See the GNU Lesser General Public License for more ////
541
//// details.                                                     ////
542
////                                                              ////
543
//// You should have received a copy of the GNU Lesser General    ////
544
//// Public License along with this source; if not, download it   ////
545
//// from http://www.opencores.org/lgpl.shtml                     ////
546
////                                                              ////
547
//////////////////////////////////////////////////////////////////////
548 36 unneback
module vl_mux_andor ( a, sel, dout);
549
parameter width = 32;
550
parameter nr_of_ports = 4;
551
input [nr_of_ports*width-1:0] a;
552
input [nr_of_ports-1:0] sel;
553
output reg [width-1:0] dout;
554 38 unneback
integer i,j;
555 36 unneback
always @ (a, sel)
556
begin
557
    dout = a[width-1:0] & {width{sel[0]}};
558 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
559
        for (j=0;j<width;j=j+1)
560
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
561 36 unneback
end
562
endmodule
563 34 unneback
module vl_mux2_andor ( a1, a0, sel, dout);
564
parameter width = 32;
565 35 unneback
localparam nr_of_ports = 2;
566 34 unneback
input [width-1:0] a1, a0;
567
input [nr_of_ports-1:0] sel;
568
output [width-1:0] dout;
569 36 unneback
vl_mux_andor
570 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
571 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
572 34 unneback
endmodule
573
module vl_mux3_andor ( a2, a1, a0, sel, dout);
574
parameter width = 32;
575 35 unneback
localparam nr_of_ports = 3;
576 34 unneback
input [width-1:0] a2, a1, a0;
577
input [nr_of_ports-1:0] sel;
578
output [width-1:0] dout;
579 36 unneback
vl_mux_andor
580 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
581 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
582 34 unneback
endmodule
583 18 unneback
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
584
parameter width = 32;
585 35 unneback
localparam nr_of_ports = 4;
586 18 unneback
input [width-1:0] a3, a2, a1, a0;
587
input [nr_of_ports-1:0] sel;
588 22 unneback
output [width-1:0] dout;
589 36 unneback
vl_mux_andor
590 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
591 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
592 18 unneback
endmodule
593
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
594
parameter width = 32;
595 35 unneback
localparam nr_of_ports = 5;
596 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
597
input [nr_of_ports-1:0] sel;
598 22 unneback
output [width-1:0] dout;
599 36 unneback
vl_mux_andor
600 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
601 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
602 18 unneback
endmodule
603
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
604
parameter width = 32;
605 35 unneback
localparam nr_of_ports = 6;
606 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
607
input [nr_of_ports-1:0] sel;
608 22 unneback
output [width-1:0] dout;
609 36 unneback
vl_mux_andor
610 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
611 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
612 18 unneback
endmodule
613 43 unneback
module vl_parity_generate (data, parity);
614
parameter word_size = 32;
615
parameter chunk_size = 8;
616
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
617
input [word_size-1:0] data;
618
output reg [word_size/chunk_size-1:0] parity;
619
integer i,j;
620
always @ (data)
621
for (i=0;i<word_size/chunk_size;i=i+1) begin
622
    parity[i] = parity_type;
623
    for (j=0;j<chunk_size;j=j+1) begin
624
        parity[i] = data[i+j] ^ parity[i];
625
    end
626
end
627
endmodule
628
module vl_parity_check( data, parity, parity_error);
629
parameter word_size = 32;
630
parameter chunk_size = 8;
631
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
632
input [word_size-1:0] data;
633
input [word_size/chunk_size-1:0] parity;
634
output parity_error;
635
reg [chunk_size-1:0] error_flag;
636
integer i,j;
637
always @ (data or parity)
638
for (i=0;i<word_size/chunk_size;i=i+1) begin
639
    error_flag[i] = parity[i] ^ parity_type;
640
    for (j=0;j<chunk_size;j=j+1) begin
641
        error_flag[i] = data[i+j] ^ error_flag[i];
642
    end
643
end
644
assign parity_error = |error_flag;
645
endmodule
646 18 unneback
//////////////////////////////////////////////////////////////////////
647
////                                                              ////
648 6 unneback
////  Versatile counter                                           ////
649
////                                                              ////
650
////  Description                                                 ////
651
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
652
////  counter                                                     ////
653
////                                                              ////
654
////  To Do:                                                      ////
655
////   - add LFSR with more taps                                  ////
656
////                                                              ////
657
////  Author(s):                                                  ////
658
////      - Michael Unneback, unneback@opencores.org              ////
659
////        ORSoC AB                                              ////
660
////                                                              ////
661
//////////////////////////////////////////////////////////////////////
662
////                                                              ////
663
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
664
////                                                              ////
665
//// This source file may be used and distributed without         ////
666
//// restriction provided that this copyright statement is not    ////
667
//// removed from the file and that any derivative work contains  ////
668
//// the original copyright notice and the associated disclaimer. ////
669
////                                                              ////
670
//// This source file is free software; you can redistribute it   ////
671
//// and/or modify it under the terms of the GNU Lesser General   ////
672
//// Public License as published by the Free Software Foundation; ////
673
//// either version 2.1 of the License, or (at your option) any   ////
674
//// later version.                                               ////
675
////                                                              ////
676
//// This source is distributed in the hope that it will be       ////
677
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
678
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
679
//// PURPOSE.  See the GNU Lesser General Public License for more ////
680
//// details.                                                     ////
681
////                                                              ////
682
//// You should have received a copy of the GNU Lesser General    ////
683
//// Public License along with this source; if not, download it   ////
684
//// from http://www.opencores.org/lgpl.shtml                     ////
685
////                                                              ////
686
//////////////////////////////////////////////////////////////////////
687
// binary counter
688 40 unneback
module vl_cnt_bin_ce (
689
 cke, q, rst, clk);
690 22 unneback
   parameter length = 4;
691 6 unneback
   input cke;
692
   output [length:1] q;
693
   input rst;
694
   input clk;
695
   parameter clear_value = 0;
696
   parameter set_value = 1;
697
   parameter wrap_value = 0;
698
   parameter level1_value = 15;
699
   reg  [length:1] qi;
700
   wire [length:1] q_next;
701
   assign q_next = qi + {{length-1{1'b0}},1'b1};
702
   always @ (posedge clk or posedge rst)
703
     if (rst)
704
       qi <= {length{1'b0}};
705
     else
706
     if (cke)
707
       qi <= q_next;
708
   assign q = qi;
709
endmodule
710
//////////////////////////////////////////////////////////////////////
711
////                                                              ////
712
////  Versatile counter                                           ////
713
////                                                              ////
714
////  Description                                                 ////
715
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
716
////  counter                                                     ////
717
////                                                              ////
718
////  To Do:                                                      ////
719
////   - add LFSR with more taps                                  ////
720
////                                                              ////
721
////  Author(s):                                                  ////
722
////      - Michael Unneback, unneback@opencores.org              ////
723
////        ORSoC AB                                              ////
724
////                                                              ////
725
//////////////////////////////////////////////////////////////////////
726
////                                                              ////
727
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
728
////                                                              ////
729
//// This source file may be used and distributed without         ////
730
//// restriction provided that this copyright statement is not    ////
731
//// removed from the file and that any derivative work contains  ////
732
//// the original copyright notice and the associated disclaimer. ////
733
////                                                              ////
734
//// This source file is free software; you can redistribute it   ////
735
//// and/or modify it under the terms of the GNU Lesser General   ////
736
//// Public License as published by the Free Software Foundation; ////
737
//// either version 2.1 of the License, or (at your option) any   ////
738
//// later version.                                               ////
739
////                                                              ////
740
//// This source is distributed in the hope that it will be       ////
741
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
742
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
743
//// PURPOSE.  See the GNU Lesser General Public License for more ////
744
//// details.                                                     ////
745
////                                                              ////
746
//// You should have received a copy of the GNU Lesser General    ////
747
//// Public License along with this source; if not, download it   ////
748
//// from http://www.opencores.org/lgpl.shtml                     ////
749
////                                                              ////
750
//////////////////////////////////////////////////////////////////////
751
// binary counter
752 40 unneback
module vl_cnt_bin_ce_rew_zq_l1 (
753
 cke, rew, zq, level1, rst, clk);
754 6 unneback
   parameter length = 4;
755
   input cke;
756
   input rew;
757 25 unneback
   output reg zq;
758
   output reg level1;
759
   input rst;
760
   input clk;
761
   parameter clear_value = 0;
762
   parameter set_value = 1;
763
   parameter wrap_value = 1;
764
   parameter level1_value = 15;
765 29 unneback
   wire clear;
766 30 unneback
   assign clear = 1'b0;
767 25 unneback
   reg  [length:1] qi;
768
   wire  [length:1] q_next, q_next_fw, q_next_rew;
769
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
770
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
771
   assign q_next = rew ? q_next_rew : q_next_fw;
772
   always @ (posedge clk or posedge rst)
773
     if (rst)
774
       qi <= {length{1'b0}};
775
     else
776
     if (cke)
777
       qi <= q_next;
778
   always @ (posedge clk or posedge rst)
779
     if (rst)
780
       zq <= 1'b1;
781
     else
782
     if (cke)
783
       zq <= q_next == {length{1'b0}};
784
    always @ (posedge clk or posedge rst)
785
    if (rst)
786
        level1 <= 1'b0;
787
    else
788
    if (cke)
789 29 unneback
    if (clear)
790
        level1 <= 1'b0;
791
    else if (q_next == level1_value)
792 25 unneback
        level1 <= 1'b1;
793
    else if (qi == level1_value & rew)
794
        level1 <= 1'b0;
795
endmodule
796
//////////////////////////////////////////////////////////////////////
797
////                                                              ////
798
////  Versatile counter                                           ////
799
////                                                              ////
800
////  Description                                                 ////
801
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
802
////  counter                                                     ////
803
////                                                              ////
804
////  To Do:                                                      ////
805
////   - add LFSR with more taps                                  ////
806
////                                                              ////
807
////  Author(s):                                                  ////
808
////      - Michael Unneback, unneback@opencores.org              ////
809
////        ORSoC AB                                              ////
810
////                                                              ////
811
//////////////////////////////////////////////////////////////////////
812
////                                                              ////
813
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
814
////                                                              ////
815
//// This source file may be used and distributed without         ////
816
//// restriction provided that this copyright statement is not    ////
817
//// removed from the file and that any derivative work contains  ////
818
//// the original copyright notice and the associated disclaimer. ////
819
////                                                              ////
820
//// This source file is free software; you can redistribute it   ////
821
//// and/or modify it under the terms of the GNU Lesser General   ////
822
//// Public License as published by the Free Software Foundation; ////
823
//// either version 2.1 of the License, or (at your option) any   ////
824
//// later version.                                               ////
825
////                                                              ////
826
//// This source is distributed in the hope that it will be       ////
827
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
828
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
829
//// PURPOSE.  See the GNU Lesser General Public License for more ////
830
//// details.                                                     ////
831
////                                                              ////
832
//// You should have received a copy of the GNU Lesser General    ////
833
//// Public License along with this source; if not, download it   ////
834
//// from http://www.opencores.org/lgpl.shtml                     ////
835
////                                                              ////
836
//////////////////////////////////////////////////////////////////////
837
// binary counter
838 40 unneback
module vl_cnt_bin_ce_rew_q_zq_l1 (
839
 cke, rew, q, zq, level1, rst, clk);
840 25 unneback
   parameter length = 4;
841
   input cke;
842
   input rew;
843
   output [length:1] q;
844
   output reg zq;
845
   output reg level1;
846
   input rst;
847
   input clk;
848
   parameter clear_value = 0;
849
   parameter set_value = 1;
850
   parameter wrap_value = 1;
851
   parameter level1_value = 15;
852 29 unneback
   wire clear;
853 30 unneback
   assign clear = 1'b0;
854 25 unneback
   reg  [length:1] qi;
855
   wire  [length:1] q_next, q_next_fw, q_next_rew;
856
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
857
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
858
   assign q_next = rew ? q_next_rew : q_next_fw;
859
   always @ (posedge clk or posedge rst)
860
     if (rst)
861
       qi <= {length{1'b0}};
862
     else
863
     if (cke)
864
       qi <= q_next;
865
   assign q = qi;
866
   always @ (posedge clk or posedge rst)
867
     if (rst)
868
       zq <= 1'b1;
869
     else
870
     if (cke)
871
       zq <= q_next == {length{1'b0}};
872
    always @ (posedge clk or posedge rst)
873
    if (rst)
874
        level1 <= 1'b0;
875
    else
876
    if (cke)
877 29 unneback
    if (clear)
878
        level1 <= 1'b0;
879
    else if (q_next == level1_value)
880 25 unneback
        level1 <= 1'b1;
881
    else if (qi == level1_value & rew)
882
        level1 <= 1'b0;
883
endmodule
884
//////////////////////////////////////////////////////////////////////
885
////                                                              ////
886
////  Versatile counter                                           ////
887
////                                                              ////
888
////  Description                                                 ////
889
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
890
////  counter                                                     ////
891
////                                                              ////
892
////  To Do:                                                      ////
893
////   - add LFSR with more taps                                  ////
894
////                                                              ////
895
////  Author(s):                                                  ////
896
////      - Michael Unneback, unneback@opencores.org              ////
897
////        ORSoC AB                                              ////
898
////                                                              ////
899
//////////////////////////////////////////////////////////////////////
900
////                                                              ////
901
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
902
////                                                              ////
903
//// This source file may be used and distributed without         ////
904
//// restriction provided that this copyright statement is not    ////
905
//// removed from the file and that any derivative work contains  ////
906
//// the original copyright notice and the associated disclaimer. ////
907
////                                                              ////
908
//// This source file is free software; you can redistribute it   ////
909
//// and/or modify it under the terms of the GNU Lesser General   ////
910
//// Public License as published by the Free Software Foundation; ////
911
//// either version 2.1 of the License, or (at your option) any   ////
912
//// later version.                                               ////
913
////                                                              ////
914
//// This source is distributed in the hope that it will be       ////
915
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
916
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
917
//// PURPOSE.  See the GNU Lesser General Public License for more ////
918
//// details.                                                     ////
919
////                                                              ////
920
//// You should have received a copy of the GNU Lesser General    ////
921
//// Public License along with this source; if not, download it   ////
922
//// from http://www.opencores.org/lgpl.shtml                     ////
923
////                                                              ////
924
//////////////////////////////////////////////////////////////////////
925 6 unneback
// GRAY counter
926 40 unneback
module vl_cnt_gray_ce_bin (
927
 cke, q, q_bin, rst, clk);
928 6 unneback
   parameter length = 4;
929
   input cke;
930
   output reg [length:1] q;
931
   output [length:1] q_bin;
932
   input rst;
933
   input clk;
934
   parameter clear_value = 0;
935
   parameter set_value = 1;
936
   parameter wrap_value = 8;
937
   parameter level1_value = 15;
938
   reg  [length:1] qi;
939
   wire [length:1] q_next;
940
   assign q_next = qi + {{length-1{1'b0}},1'b1};
941
   always @ (posedge clk or posedge rst)
942
     if (rst)
943
       qi <= {length{1'b0}};
944
     else
945
     if (cke)
946
       qi <= q_next;
947
   always @ (posedge clk or posedge rst)
948
     if (rst)
949
       q <= {length{1'b0}};
950
     else
951
       if (cke)
952
         q <= (q_next>>1) ^ q_next;
953
   assign q_bin = qi;
954
endmodule
955
//////////////////////////////////////////////////////////////////////
956
////                                                              ////
957
////  Versatile library, counters                                 ////
958
////                                                              ////
959
////  Description                                                 ////
960
////  counters                                                    ////
961
////                                                              ////
962
////                                                              ////
963
////  To Do:                                                      ////
964
////   - add more counters                                        ////
965
////                                                              ////
966
////  Author(s):                                                  ////
967
////      - Michael Unneback, unneback@opencores.org              ////
968
////        ORSoC AB                                              ////
969
////                                                              ////
970
//////////////////////////////////////////////////////////////////////
971
////                                                              ////
972
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
973
////                                                              ////
974
//// This source file may be used and distributed without         ////
975
//// restriction provided that this copyright statement is not    ////
976
//// removed from the file and that any derivative work contains  ////
977
//// the original copyright notice and the associated disclaimer. ////
978
////                                                              ////
979
//// This source file is free software; you can redistribute it   ////
980
//// and/or modify it under the terms of the GNU Lesser General   ////
981
//// Public License as published by the Free Software Foundation; ////
982
//// either version 2.1 of the License, or (at your option) any   ////
983
//// later version.                                               ////
984
////                                                              ////
985
//// This source is distributed in the hope that it will be       ////
986
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
987
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
988
//// PURPOSE.  See the GNU Lesser General Public License for more ////
989
//// details.                                                     ////
990
////                                                              ////
991
//// You should have received a copy of the GNU Lesser General    ////
992
//// Public License along with this source; if not, download it   ////
993
//// from http://www.opencores.org/lgpl.shtml                     ////
994
////                                                              ////
995
//////////////////////////////////////////////////////////////////////
996 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
997 6 unneback
   parameter length = 4;
998
   output reg [0:length-1] q;
999
   input rst;
1000
   input clk;
1001
    always @ (posedge clk or posedge rst)
1002
    if (rst)
1003
        q <= {1'b1,{length-1{1'b0}}};
1004
    else
1005
        q <= {q[length-1],q[0:length-2]};
1006
endmodule
1007 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
1008 6 unneback
   parameter length = 4;
1009
   input cke;
1010
   output reg [0:length-1] q;
1011
   input rst;
1012
   input clk;
1013
    always @ (posedge clk or posedge rst)
1014
    if (rst)
1015
        q <= {1'b1,{length-1{1'b0}}};
1016
    else
1017
        if (cke)
1018
            q <= {q[length-1],q[0:length-2]};
1019
endmodule
1020 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1021 6 unneback
   parameter length = 4;
1022
   input cke, clear;
1023
   output reg [0:length-1] q;
1024
   input rst;
1025
   input clk;
1026
    always @ (posedge clk or posedge rst)
1027
    if (rst)
1028
        q <= {1'b1,{length-1{1'b0}}};
1029
    else
1030
        if (cke)
1031
            if (clear)
1032
                q <= {1'b1,{length-1{1'b0}}};
1033
            else
1034
                q <= q >> 1;
1035
endmodule
1036 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
1037 6 unneback
   parameter length = 4;
1038
   input cke, clear;
1039
   output reg [0:length-1] q;
1040
   input rst;
1041
   input clk;
1042
    always @ (posedge clk or posedge rst)
1043
    if (rst)
1044
        q <= {1'b1,{length-1{1'b0}}};
1045
    else
1046
        if (cke)
1047
            if (clear)
1048
                q <= {1'b1,{length-1{1'b0}}};
1049
            else
1050
            q <= {q[length-1],q[0:length-2]};
1051
endmodule
1052
//////////////////////////////////////////////////////////////////////
1053
////                                                              ////
1054
////  Versatile library, memories                                 ////
1055
////                                                              ////
1056
////  Description                                                 ////
1057
////  memories                                                    ////
1058
////                                                              ////
1059
////                                                              ////
1060
////  To Do:                                                      ////
1061
////   - add more memory types                                    ////
1062
////                                                              ////
1063
////  Author(s):                                                  ////
1064
////      - Michael Unneback, unneback@opencores.org              ////
1065
////        ORSoC AB                                              ////
1066
////                                                              ////
1067
//////////////////////////////////////////////////////////////////////
1068
////                                                              ////
1069
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1070
////                                                              ////
1071
//// This source file may be used and distributed without         ////
1072
//// restriction provided that this copyright statement is not    ////
1073
//// removed from the file and that any derivative work contains  ////
1074
//// the original copyright notice and the associated disclaimer. ////
1075
////                                                              ////
1076
//// This source file is free software; you can redistribute it   ////
1077
//// and/or modify it under the terms of the GNU Lesser General   ////
1078
//// Public License as published by the Free Software Foundation; ////
1079
//// either version 2.1 of the License, or (at your option) any   ////
1080
//// later version.                                               ////
1081
////                                                              ////
1082
//// This source is distributed in the hope that it will be       ////
1083
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1084
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1085
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1086
//// details.                                                     ////
1087
////                                                              ////
1088
//// You should have received a copy of the GNU Lesser General    ////
1089
//// Public License along with this source; if not, download it   ////
1090
//// from http://www.opencores.org/lgpl.shtml                     ////
1091
////                                                              ////
1092
//////////////////////////////////////////////////////////////////////
1093
/// ROM
1094 7 unneback
module vl_rom_init ( adr, q, clk);
1095
   parameter data_width = 32;
1096
   parameter addr_width = 8;
1097
   input [(addr_width-1):0]       adr;
1098
   output reg [(data_width-1):0] q;
1099
   input                         clk;
1100
   reg [data_width-1:0] rom [(1<<addr_width)-1:0];
1101
   parameter memory_file = "vl_rom.vmem";
1102
   initial
1103
     begin
1104
        $readmemh(memory_file, rom);
1105
     end
1106
   always @ (posedge clk)
1107
     q <= rom[adr];
1108
endmodule
1109 14 unneback
/*
1110 7 unneback
module vl_rom ( adr, q, clk);
1111 6 unneback
parameter data_width = 32;
1112
parameter addr_width = 4;
1113
parameter [0:1>>addr_width-1] data [data_width-1:0] = {
1114
    {32'h18000000},
1115
    {32'hA8200000},
1116
    {32'hA8200000},
1117
    {32'hA8200000},
1118
    {32'h44003000},
1119
    {32'h15000000},
1120
    {32'h15000000},
1121
    {32'h15000000},
1122
    {32'h15000000},
1123
    {32'h15000000},
1124
    {32'h15000000},
1125
    {32'h15000000},
1126
    {32'h15000000},
1127
    {32'h15000000},
1128
    {32'h15000000},
1129
    {32'h15000000}};
1130 7 unneback
input [addr_width-1:0] adr;
1131 6 unneback
output reg [data_width-1:0] q;
1132
input clk;
1133
always @ (posedge clk)
1134 7 unneback
    q <= data[adr];
1135 6 unneback
endmodule
1136 14 unneback
*/
1137 6 unneback
// Single port RAM
1138
module vl_ram ( d, adr, we, q, clk);
1139
   parameter data_width = 32;
1140
   parameter addr_width = 8;
1141
   input [(data_width-1):0]      d;
1142
   input [(addr_width-1):0]       adr;
1143
   input                         we;
1144 7 unneback
   output reg [(data_width-1):0] q;
1145 6 unneback
   input                         clk;
1146
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1147 7 unneback
   parameter init = 0;
1148
   parameter memory_file = "vl_ram.vmem";
1149
   generate if (init) begin : init_mem
1150
   initial
1151
     begin
1152
        $readmemh(memory_file, ram);
1153
     end
1154
   end
1155
   endgenerate
1156 6 unneback
   always @ (posedge clk)
1157
   begin
1158
   if (we)
1159
     ram[adr] <= d;
1160
   q <= ram[adr];
1161
   end
1162
endmodule
1163 7 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
1164
   parameter data_width = 32;
1165
   parameter addr_width = 8;
1166
   input [(data_width-1):0]      d;
1167
   input [(addr_width-1):0]       adr;
1168
   input [(addr_width/4)-1:0]    be;
1169
   input                         we;
1170
   output reg [(data_width-1):0] q;
1171
   input                         clk;
1172
   reg [data_width-1:0] ram [(1<<addr_width)-1:0];
1173
   parameter init = 0;
1174
   parameter memory_file = "vl_ram.vmem";
1175
   generate if (init) begin : init_mem
1176
   initial
1177
     begin
1178
        $readmemh(memory_file, ram);
1179
     end
1180
   end
1181
   endgenerate
1182
   genvar i;
1183
   generate for (i=0;i<addr_width/4;i=i+1) begin : be_ram
1184
      always @ (posedge clk)
1185
      if (we & be[i])
1186
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
1187
   end
1188
   endgenerate
1189
   always @ (posedge clk)
1190
      q <= ram[adr];
1191
endmodule
1192 6 unneback
// Dual port RAM
1193
// ACTEL FPGA should not use logic to handle rw collision
1194 7 unneback
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1195 6 unneback
   parameter data_width = 32;
1196
   parameter addr_width = 8;
1197
   input [(data_width-1):0]      d_a;
1198
   input [(addr_width-1):0]       adr_a;
1199
   input [(addr_width-1):0]       adr_b;
1200
   input                         we_a;
1201
   output [(data_width-1):0]      q_b;
1202
   input                         clk_a, clk_b;
1203
   reg [(addr_width-1):0]         adr_b_reg;
1204
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
1205 7 unneback
   parameter init = 0;
1206
   parameter memory_file = "vl_ram.vmem";
1207
   generate if (init) begin : init_mem
1208
   initial
1209
     begin
1210
        $readmemh(memory_file, ram);
1211
     end
1212
   end
1213
   endgenerate
1214 6 unneback
   always @ (posedge clk_a)
1215
   if (we_a)
1216
     ram[adr_a] <= d_a;
1217
   always @ (posedge clk_b)
1218
   adr_b_reg <= adr_b;
1219
   assign q_b = ram[adr_b_reg];
1220
endmodule
1221 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1222 6 unneback
   parameter data_width = 32;
1223
   parameter addr_width = 8;
1224
   input [(data_width-1):0]      d_a;
1225
   input [(addr_width-1):0]       adr_a;
1226
   input [(addr_width-1):0]       adr_b;
1227
   input                         we_a;
1228
   output [(data_width-1):0]      q_b;
1229
   output reg [(data_width-1):0] q_a;
1230
   input                         clk_a, clk_b;
1231
   reg [(data_width-1):0]         q_b;
1232
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
1233 7 unneback
   parameter init = 0;
1234
   parameter memory_file = "vl_ram.vmem";
1235
   generate if (init) begin : init_mem
1236
   initial
1237
     begin
1238
        $readmemh(memory_file, ram);
1239
     end
1240
   end
1241
   endgenerate
1242 6 unneback
   always @ (posedge clk_a)
1243
     begin
1244
        q_a <= ram[adr_a];
1245
        if (we_a)
1246
             ram[adr_a] <= d_a;
1247
     end
1248
   always @ (posedge clk_b)
1249
          q_b <= ram[adr_b];
1250
endmodule
1251 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
1252 6 unneback
   parameter data_width = 32;
1253
   parameter addr_width = 8;
1254
   input [(data_width-1):0]      d_a;
1255
   input [(addr_width-1):0]       adr_a;
1256
   input [(addr_width-1):0]       adr_b;
1257
   input                         we_a;
1258
   output [(data_width-1):0]      q_b;
1259
   input [(data_width-1):0]       d_b;
1260
   output reg [(data_width-1):0] q_a;
1261
   input                         we_b;
1262
   input                         clk_a, clk_b;
1263
   reg [(data_width-1):0]         q_b;
1264
   reg [data_width-1:0] ram [(1<<addr_width)-1:0] ;
1265 7 unneback
   parameter init = 0;
1266
   parameter memory_file = "vl_ram.vmem";
1267
   generate if (init) begin : init_mem
1268
   initial
1269
     begin
1270
        $readmemh(memory_file, ram);
1271
     end
1272
   end
1273
   endgenerate
1274 6 unneback
   always @ (posedge clk_a)
1275
     begin
1276
        q_a <= ram[adr_a];
1277
        if (we_a)
1278
             ram[adr_a] <= d_a;
1279
     end
1280
   always @ (posedge clk_b)
1281
     begin
1282
        q_b <= ram[adr_b];
1283
        if (we_b)
1284
          ram[adr_b] <= d_b;
1285
     end
1286
endmodule
1287
// Content addresable memory, CAM
1288
// FIFO
1289 25 unneback
module vl_fifo_1r1w_fill_level_sync (
1290
    d, wr, fifo_full,
1291
    q, rd, fifo_empty,
1292
    fill_level,
1293
    clk, rst
1294
    );
1295
parameter data_width = 18;
1296
parameter addr_width = 4;
1297
// write side
1298
input  [data_width-1:0] d;
1299
input                   wr;
1300
output                  fifo_full;
1301
// read side
1302
output [data_width-1:0] q;
1303
input                   rd;
1304
output                  fifo_empty;
1305
// common
1306
output [addr_width:0]   fill_level;
1307
input rst, clk;
1308
wire [addr_width:1] wadr, radr;
1309
vl_cnt_bin_ce
1310
    # ( .length(addr_width))
1311
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
1312
vl_cnt_bin_ce
1313
    # (.length(addr_width))
1314
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
1315
vl_dpram_1r1w
1316
    # (.data_width(data_width), .addr_width(addr_width))
1317
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
1318 31 unneback
vl_cnt_bin_ce_rew_q_zq_l1
1319 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
1320 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
1321
endmodule
1322 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
1323
// RAM is supposed to be larger than the two FIFOs
1324
// LFSR counters used adr pointers
1325
module vl_fifo_2r2w_sync_simplex (
1326
    // a side
1327
    a_d, a_wr, a_fifo_full,
1328
    a_q, a_rd, a_fifo_empty,
1329
    a_fill_level,
1330
    // b side
1331
    b_d, b_wr, b_fifo_full,
1332
    b_q, b_rd, b_fifo_empty,
1333
    b_fill_level,
1334
    // common
1335
    clk, rst
1336
    );
1337
parameter data_width = 8;
1338
parameter addr_width = 5;
1339
parameter fifo_full_level = (1<<addr_width)-1;
1340
// a side
1341
input  [data_width-1:0] a_d;
1342
input                   a_wr;
1343
output                  a_fifo_full;
1344
output [data_width-1:0] a_q;
1345
input                   a_rd;
1346
output                  a_fifo_empty;
1347
output [addr_width-1:0] a_fill_level;
1348
// b side
1349
input  [data_width-1:0] b_d;
1350
input                   b_wr;
1351
output                  b_fifo_full;
1352
output [data_width-1:0] b_q;
1353
input                   b_rd;
1354
output                  b_fifo_empty;
1355
output [addr_width-1:0] b_fill_level;
1356
input                   clk;
1357
input                   rst;
1358
// adr_gen
1359
wire [addr_width:1] a_wadr, a_radr;
1360
wire [addr_width:1] b_wadr, b_radr;
1361
// dpram
1362
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1363
vl_cnt_lfsr_ce
1364
    # ( .length(addr_width))
1365
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
1366
vl_cnt_lfsr_ce
1367
    # (.length(addr_width))
1368
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
1369
vl_cnt_lfsr_ce
1370
    # ( .length(addr_width))
1371
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
1372
vl_cnt_lfsr_ce
1373
    # (.length(addr_width))
1374
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
1375
// mux read or write adr to DPRAM
1376
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
1377
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
1378
vl_dpram_2r2w
1379
    # (.data_width(data_width), .addr_width(addr_width+1))
1380
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1381
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1382
vl_cnt_bin_ce_rew_zq_l1
1383 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
1384 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
1385
vl_cnt_bin_ce_rew_zq_l1
1386 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
1387 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
1388
endmodule
1389 6 unneback
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
1390 11 unneback
   parameter addr_width = 4;
1391
   parameter N = addr_width-1;
1392 6 unneback
   parameter Q1 = 2'b00;
1393
   parameter Q2 = 2'b01;
1394
   parameter Q3 = 2'b11;
1395
   parameter Q4 = 2'b10;
1396
   parameter going_empty = 1'b0;
1397
   parameter going_full  = 1'b1;
1398
   input [N:0]  wptr, rptr;
1399 14 unneback
   output       fifo_empty;
1400 6 unneback
   output       fifo_full;
1401
   input        wclk, rclk, rst;
1402
   wire direction;
1403
   reg  direction_set, direction_clr;
1404
   wire async_empty, async_full;
1405
   wire fifo_full2;
1406 14 unneback
   wire fifo_empty2;
1407 6 unneback
   // direction_set
1408
   always @ (wptr[N:N-1] or rptr[N:N-1])
1409
     case ({wptr[N:N-1],rptr[N:N-1]})
1410
       {Q1,Q2} : direction_set <= 1'b1;
1411
       {Q2,Q3} : direction_set <= 1'b1;
1412
       {Q3,Q4} : direction_set <= 1'b1;
1413
       {Q4,Q1} : direction_set <= 1'b1;
1414
       default : direction_set <= 1'b0;
1415
     endcase
1416
   // direction_clear
1417
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
1418
     if (rst)
1419
       direction_clr <= 1'b1;
1420
     else
1421
       case ({wptr[N:N-1],rptr[N:N-1]})
1422
         {Q2,Q1} : direction_clr <= 1'b1;
1423
         {Q3,Q2} : direction_clr <= 1'b1;
1424
         {Q4,Q3} : direction_clr <= 1'b1;
1425
         {Q1,Q4} : direction_clr <= 1'b1;
1426
         default : direction_clr <= 1'b0;
1427
       endcase
1428 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
1429 6 unneback
   assign async_empty = (wptr == rptr) && (direction==going_empty);
1430
   assign async_full  = (wptr == rptr) && (direction==going_full);
1431 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
1432
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
1433 6 unneback
/*
1434
   always @ (posedge wclk or posedge rst or posedge async_full)
1435
     if (rst)
1436
       {fifo_full, fifo_full2} <= 2'b00;
1437
     else if (async_full)
1438
       {fifo_full, fifo_full2} <= 2'b11;
1439
     else
1440
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
1441
*/
1442 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
1443 6 unneback
     if (async_empty)
1444
       {fifo_empty, fifo_empty2} <= 2'b11;
1445
     else
1446 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
1447 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
1448
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
1449 27 unneback
endmodule // async_compb
1450 6 unneback
module vl_fifo_1r1w_async (
1451
    d, wr, fifo_full, wr_clk, wr_rst,
1452
    q, rd, fifo_empty, rd_clk, rd_rst
1453
    );
1454
parameter data_width = 18;
1455
parameter addr_width = 4;
1456
// write side
1457
input  [data_width-1:0] d;
1458
input                   wr;
1459
output                  fifo_full;
1460
input                   wr_clk;
1461
input                   wr_rst;
1462
// read side
1463
output [data_width-1:0] q;
1464
input                   rd;
1465
output                  fifo_empty;
1466
input                   rd_clk;
1467
input                   rd_rst;
1468
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
1469 18 unneback
vl_cnt_gray_ce_bin
1470 6 unneback
    # ( .length(addr_width))
1471
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
1472 18 unneback
vl_cnt_gray_ce_bin
1473 6 unneback
    # (.length(addr_width))
1474 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
1475 7 unneback
vl_dpram_1r1w
1476 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
1477
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
1478
vl_fifo_cmp_async
1479
    # (.addr_width(addr_width))
1480
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
1481
endmodule
1482 8 unneback
module vl_fifo_2r2w_async (
1483 6 unneback
    // a side
1484
    a_d, a_wr, a_fifo_full,
1485
    a_q, a_rd, a_fifo_empty,
1486
    a_clk, a_rst,
1487
    // b side
1488
    b_d, b_wr, b_fifo_full,
1489
    b_q, b_rd, b_fifo_empty,
1490
    b_clk, b_rst
1491
    );
1492
parameter data_width = 18;
1493
parameter addr_width = 4;
1494
// a side
1495
input  [data_width-1:0] a_d;
1496
input                   a_wr;
1497
output                  a_fifo_full;
1498
output [data_width-1:0] a_q;
1499
input                   a_rd;
1500
output                  a_fifo_empty;
1501
input                   a_clk;
1502
input                   a_rst;
1503
// b side
1504
input  [data_width-1:0] b_d;
1505
input                   b_wr;
1506
output                  b_fifo_full;
1507
output [data_width-1:0] b_q;
1508
input                   b_rd;
1509
output                  b_fifo_empty;
1510
input                   b_clk;
1511
input                   b_rst;
1512
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1513
vl_fifo_1r1w_async_a (
1514
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
1515
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
1516
    );
1517
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1518
vl_fifo_1r1w_async_b (
1519
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
1520
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
1521
    );
1522
endmodule
1523 8 unneback
module vl_fifo_2r2w_async_simplex (
1524 6 unneback
    // a side
1525
    a_d, a_wr, a_fifo_full,
1526
    a_q, a_rd, a_fifo_empty,
1527
    a_clk, a_rst,
1528
    // b side
1529
    b_d, b_wr, b_fifo_full,
1530
    b_q, b_rd, b_fifo_empty,
1531
    b_clk, b_rst
1532
    );
1533
parameter data_width = 18;
1534
parameter addr_width = 4;
1535
// a side
1536
input  [data_width-1:0] a_d;
1537
input                   a_wr;
1538
output                  a_fifo_full;
1539
output [data_width-1:0] a_q;
1540
input                   a_rd;
1541
output                  a_fifo_empty;
1542
input                   a_clk;
1543
input                   a_rst;
1544
// b side
1545
input  [data_width-1:0] b_d;
1546
input                   b_wr;
1547
output                  b_fifo_full;
1548
output [data_width-1:0] b_q;
1549
input                   b_rd;
1550
output                  b_fifo_empty;
1551
input                   b_clk;
1552
input                   b_rst;
1553
// adr_gen
1554
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
1555
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
1556
// dpram
1557
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1558 18 unneback
vl_cnt_gray_ce_bin
1559 6 unneback
    # ( .length(addr_width))
1560
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
1561 18 unneback
vl_cnt_gray_ce_bin
1562 6 unneback
    # (.length(addr_width))
1563
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
1564 18 unneback
vl_cnt_gray_ce_bin
1565 6 unneback
    # ( .length(addr_width))
1566
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
1567 18 unneback
vl_cnt_gray_ce_bin
1568 6 unneback
    # (.length(addr_width))
1569
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
1570
// mux read or write adr to DPRAM
1571
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
1572
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
1573 11 unneback
vl_dpram_2r2w
1574 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
1575
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1576
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1577 11 unneback
vl_fifo_cmp_async
1578 6 unneback
    # (.addr_width(addr_width))
1579
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
1580 11 unneback
vl_fifo_cmp_async
1581 6 unneback
    # (.addr_width(addr_width))
1582
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
1583
endmodule
1584 12 unneback
//////////////////////////////////////////////////////////////////////
1585
////                                                              ////
1586
////  Versatile library, wishbone stuff                           ////
1587
////                                                              ////
1588
////  Description                                                 ////
1589
////  Wishbone compliant modules                                  ////
1590
////                                                              ////
1591
////                                                              ////
1592
////  To Do:                                                      ////
1593
////   -                                                          ////
1594
////                                                              ////
1595
////  Author(s):                                                  ////
1596
////      - Michael Unneback, unneback@opencores.org              ////
1597
////        ORSoC AB                                              ////
1598
////                                                              ////
1599
//////////////////////////////////////////////////////////////////////
1600
////                                                              ////
1601
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1602
////                                                              ////
1603
//// This source file may be used and distributed without         ////
1604
//// restriction provided that this copyright statement is not    ////
1605
//// removed from the file and that any derivative work contains  ////
1606
//// the original copyright notice and the associated disclaimer. ////
1607
////                                                              ////
1608
//// This source file is free software; you can redistribute it   ////
1609
//// and/or modify it under the terms of the GNU Lesser General   ////
1610
//// Public License as published by the Free Software Foundation; ////
1611
//// either version 2.1 of the License, or (at your option) any   ////
1612
//// later version.                                               ////
1613
////                                                              ////
1614
//// This source is distributed in the hope that it will be       ////
1615
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1616
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1617
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1618
//// details.                                                     ////
1619
////                                                              ////
1620
//// You should have received a copy of the GNU Lesser General    ////
1621
//// Public License along with this source; if not, download it   ////
1622
//// from http://www.opencores.org/lgpl.shtml                     ////
1623
////                                                              ////
1624
//////////////////////////////////////////////////////////////////////
1625
// async wb3 - wb3 bridge
1626
`timescale 1ns/1ns
1627 18 unneback
module vl_wb3wb3_bridge (
1628 12 unneback
        // wishbone slave side
1629
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
1630
        // wishbone master side
1631
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
1632
input [31:0] wbs_dat_i;
1633
input [31:2] wbs_adr_i;
1634
input [3:0]  wbs_sel_i;
1635
input [1:0]  wbs_bte_i;
1636
input [2:0]  wbs_cti_i;
1637
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
1638
output [31:0] wbs_dat_o;
1639 14 unneback
output wbs_ack_o;
1640 12 unneback
input wbs_clk, wbs_rst;
1641
output [31:0] wbm_dat_o;
1642
output reg [31:2] wbm_adr_o;
1643
output [3:0]  wbm_sel_o;
1644
output reg [1:0]  wbm_bte_o;
1645
output reg [2:0]  wbm_cti_o;
1646 14 unneback
output reg wbm_we_o;
1647
output wbm_cyc_o;
1648 12 unneback
output wbm_stb_o;
1649
input [31:0]  wbm_dat_i;
1650
input wbm_ack_i;
1651
input wbm_clk, wbm_rst;
1652
parameter addr_width = 4;
1653
// bte
1654
parameter linear       = 2'b00;
1655
parameter wrap4        = 2'b01;
1656
parameter wrap8        = 2'b10;
1657
parameter wrap16       = 2'b11;
1658
// cti
1659
parameter classic      = 3'b000;
1660
parameter incburst     = 3'b010;
1661
parameter endofburst   = 3'b111;
1662
parameter wbs_adr  = 1'b0;
1663
parameter wbs_data = 1'b1;
1664 33 unneback
parameter wbm_adr0      = 2'b00;
1665
parameter wbm_adr1      = 2'b01;
1666
parameter wbm_data      = 2'b10;
1667
parameter wbm_data_wait = 2'b11;
1668 12 unneback
reg [1:0] wbs_bte_reg;
1669
reg wbs;
1670
wire wbs_eoc_alert, wbm_eoc_alert;
1671
reg wbs_eoc, wbm_eoc;
1672
reg [1:0] wbm;
1673 14 unneback
wire [1:16] wbs_count, wbm_count;
1674 12 unneback
wire [35:0] a_d, a_q, b_d, b_q;
1675
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
1676
reg a_rd_reg;
1677
wire b_rd_adr, b_rd_data;
1678 14 unneback
wire b_rd_data_reg;
1679
wire [35:0] temp;
1680 12 unneback
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
1681
always @ (posedge wbs_clk or posedge wbs_rst)
1682
if (wbs_rst)
1683
        wbs_eoc <= 1'b0;
1684
else
1685
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
1686
                wbs_eoc <= wbs_bte_i==linear;
1687
        else if (wbs_eoc_alert & (a_rd | a_wr))
1688
                wbs_eoc <= 1'b1;
1689 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
1690 12 unneback
    cnt0 (
1691
        .cke(wbs_ack_o),
1692
        .clear(wbs_eoc),
1693
        .q(wbs_count),
1694
        .rst(wbs_rst),
1695
        .clk(wbs_clk));
1696
always @ (posedge wbs_clk or posedge wbs_rst)
1697
if (wbs_rst)
1698
        wbs <= wbs_adr;
1699
else
1700
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & !a_fifo_full)
1701
                wbs <= wbs_data;
1702
        else if (wbs_eoc & wbs_ack_o)
1703
                wbs <= wbs_adr;
1704
// wbs FIFO
1705
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,wbs_bte_i,wbs_cti_i} : {wbs_dat_i,wbs_sel_i};
1706
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & !a_fifo_full :
1707
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
1708
              1'b0;
1709
assign a_rd = !a_fifo_empty;
1710
always @ (posedge wbs_clk or posedge wbs_rst)
1711
if (wbs_rst)
1712
        a_rd_reg <= 1'b0;
1713
else
1714
        a_rd_reg <= a_rd;
1715
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
1716
assign wbs_dat_o = a_q[35:4];
1717
always @ (posedge wbs_clk or posedge wbs_rst)
1718
if (wbs_rst)
1719 13 unneback
        wbs_bte_reg <= 2'b00;
1720 12 unneback
else
1721 13 unneback
        wbs_bte_reg <= wbs_bte_i;
1722 12 unneback
// wbm FIFO
1723
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
1724
always @ (posedge wbm_clk or posedge wbm_rst)
1725
if (wbm_rst)
1726
        wbm_eoc <= 1'b0;
1727
else
1728
        if (wbm==wbm_adr0 & !b_fifo_empty)
1729
                wbm_eoc <= b_q[4:3] == linear;
1730
        else if (wbm_eoc_alert & wbm_ack_i)
1731
                wbm_eoc <= 1'b1;
1732
always @ (posedge wbm_clk or posedge wbm_rst)
1733
if (wbm_rst)
1734
        wbm <= wbm_adr0;
1735
else
1736 33 unneback
/*
1737 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
1738
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
1739
        (wbm==wbm_adr1 & !wbm_we_o) |
1740
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
1741
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
1742 33 unneback
*/
1743
    case (wbm)
1744
    wbm_adr0:
1745
        if (!b_fifo_empty)
1746
            wbm <= wbm_adr1;
1747
    wbm_adr1:
1748
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
1749
            wbm <= wbm_data;
1750
    wbm_data:
1751
        if (wbm_ack_i & wbm_eoc)
1752
            wbm <= wbm_adr0;
1753
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
1754
            wbm <= wbm_data_wait;
1755
    wbm_data_wait:
1756
        if (!b_fifo_empty)
1757
            wbm <= wbm_data;
1758
    endcase
1759 12 unneback
assign b_d = {wbm_dat_i,4'b1111};
1760
assign b_wr = !wbm_we_o & wbm_ack_i;
1761
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
1762
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
1763
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
1764 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
1765 12 unneback
                   1'b0;
1766
assign b_rd = b_rd_adr | b_rd_data;
1767 18 unneback
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
1768
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
1769 12 unneback
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
1770 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
1771 12 unneback
    cnt1 (
1772
        .cke(wbm_ack_i),
1773
        .clear(wbm_eoc),
1774
        .q(wbm_count),
1775
        .rst(wbm_rst),
1776
        .clk(wbm_clk));
1777 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
1778
assign wbm_stb_o = (wbm==wbm_data);
1779 12 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
1780
if (wbm_rst)
1781
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
1782
else begin
1783
        if (wbm==wbm_adr0 & !b_fifo_empty)
1784
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
1785
        else if (wbm_eoc_alert & wbm_ack_i)
1786
                wbm_cti_o <= endofburst;
1787
end
1788
//async_fifo_dw_simplex_top
1789
vl_fifo_2r2w_async_simplex
1790
# ( .data_width(36), .addr_width(addr_width))
1791
fifo (
1792
    // a side
1793
    .a_d(a_d),
1794
    .a_wr(a_wr),
1795
    .a_fifo_full(a_fifo_full),
1796
    .a_q(a_q),
1797
    .a_rd(a_rd),
1798
    .a_fifo_empty(a_fifo_empty),
1799
    .a_clk(wbs_clk),
1800
    .a_rst(wbs_rst),
1801
    // b side
1802
    .b_d(b_d),
1803
    .b_wr(b_wr),
1804
    .b_fifo_full(b_fifo_full),
1805
    .b_q(b_q),
1806
    .b_rd(b_rd),
1807
    .b_fifo_empty(b_fifo_empty),
1808
    .b_clk(wbm_clk),
1809
    .b_rst(wbm_rst)
1810
    );
1811
endmodule
1812 39 unneback
module vl_wb3_arbiter_type1 (
1813
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
1814
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
1815
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
1816
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
1817
    wb_clk, wb_rst
1818
);
1819
parameter nr_of_ports = 3;
1820
parameter adr_size = 26;
1821
parameter adr_lo   = 2;
1822
parameter dat_size = 32;
1823
parameter sel_size = dat_size/8;
1824
localparam aw = (adr_size - adr_lo) * nr_of_ports;
1825
localparam dw = dat_size * nr_of_ports;
1826
localparam sw = sel_size * nr_of_ports;
1827
localparam cw = 3 * nr_of_ports;
1828
localparam bw = 2 * nr_of_ports;
1829
input  [dw-1:0] wbm_dat_o;
1830
input  [aw-1:0] wbm_adr_o;
1831
input  [sw-1:0] wbm_sel_o;
1832
input  [cw-1:0] wbm_cti_o;
1833
input  [bw-1:0] wbm_bte_o;
1834
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
1835
output [dw-1:0] wbm_dat_i;
1836
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
1837
output [dat_size-1:0] wbs_dat_i;
1838
output [adr_size-1:adr_lo] wbs_adr_i;
1839
output [sel_size-1:0] wbs_sel_i;
1840
output [2:0] wbs_cti_i;
1841
output [1:0] wbs_bte_i;
1842
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
1843
input  [dat_size-1:0] wbs_dat_o;
1844
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
1845
input wb_clk, wb_rst;
1846
wire [nr_of_ports-1:0] select;
1847
wire [nr_of_ports-1:0] state;
1848
wire [nr_of_ports-1:0] eoc; // end-of-cycle
1849
wire [nr_of_ports-1:0] sel;
1850
wire idle;
1851
genvar i;
1852
assign idle = !(|state);
1853
generate
1854
if (nr_of_ports == 2) begin
1855
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
1856
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
1857
    assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : 2'b00;
1858
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
1859
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
1860
end
1861
endgenerate
1862
generate
1863
if (nr_of_ports == 3) begin
1864
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
1865
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
1866
    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : 3'b000;
1867
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
1868
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
1869
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
1870
end
1871
endgenerate
1872
generate
1873
for (i=0;i<nr_of_ports;i=i+1) begin
1874
    vl_spr sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
1875
end
1876
endgenerate
1877
    assign sel = select | state;
1878
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
1879
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
1880
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
1881
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
1882
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
1883
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
1884
    vl_mux_andor # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
1885
    assign wbs_cyc_i = |sel;
1886
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
1887
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
1888
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
1889
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
1890
endmodule
1891 17 unneback
// WB ROM
1892 18 unneback
module vl_wb_boot_rom (
1893 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
1894 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
1895
    parameter adr_hi = 31;
1896
    parameter adr_lo = 28;
1897
    parameter adr_sel = 4'hf;
1898
    parameter addr_width = 5;
1899 33 unneback
/*
1900
`ifndef BOOT_ROM
1901
`define BOOT_ROM "boot_rom.v"
1902
`endif
1903
*/
1904 18 unneback
    input [adr_hi:2]    wb_adr_i;
1905
    input               wb_stb_i;
1906
    input               wb_cyc_i;
1907
    output [31:0]        wb_dat_o;
1908
    output              wb_ack_o;
1909
    output              hit_o;
1910
    input               wb_clk;
1911
    input               wb_rst;
1912
    wire hit;
1913
    reg [31:0] wb_dat;
1914
    reg wb_ack;
1915
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
1916 17 unneback
always @ (posedge wb_clk or posedge wb_rst)
1917
    if (wb_rst)
1918 18 unneback
        wb_dat <= 32'h15000000;
1919 17 unneback
    else
1920 18 unneback
         case (wb_adr_i[addr_width-1:2])
1921 33 unneback
`ifdef BOOT_ROM
1922
`include `BOOT_ROM
1923
`endif
1924 17 unneback
           /*
1925
            // Zero r0 and jump to 0x00000100
1926 18 unneback
 
1927
            1 : wb_dat <= 32'hA8200000;
1928
            2 : wb_dat <= 32'hA8C00100;
1929
            3 : wb_dat <= 32'h44003000;
1930
            4 : wb_dat <= 32'h15000000;
1931 17 unneback
            */
1932
           default:
1933 18 unneback
             wb_dat <= 32'h00000000;
1934 17 unneback
         endcase // case (wb_adr_i)
1935
always @ (posedge wb_clk or posedge wb_rst)
1936
    if (wb_rst)
1937 18 unneback
        wb_ack <= 1'b0;
1938 17 unneback
    else
1939 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
1940
assign hit_o = hit;
1941
assign wb_dat_o = wb_dat & {32{wb_ack}};
1942
assign wb_ack_o = wb_ack;
1943 17 unneback
endmodule
1944 32 unneback
module vl_wb_dpram (
1945
        // wishbone slave side a
1946
        wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
1947
        wbsa_clk, wbsa_rst,
1948
        // wishbone slave side a
1949
        wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
1950
        wbsb_clk, wbsb_rst);
1951
parameter data_width = 32;
1952
parameter addr_width = 8;
1953
parameter dat_o_mask_a = 1;
1954
parameter dat_o_mask_b = 1;
1955
input [31:0] wbsa_dat_i;
1956
input [addr_width-1:2] wbsa_adr_i;
1957
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
1958
output [31:0] wbsa_dat_o;
1959
output wbsa_ack_o;
1960
input wbsa_clk, wbsa_rst;
1961
input [31:0] wbsb_dat_i;
1962
input [addr_width-1:2] wbsb_adr_i;
1963
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
1964
output [31:0] wbsb_dat_o;
1965
output wbsb_ack_o;
1966
input wbsb_clk, wbsb_rst;
1967
wire wbsa_dat_tmp, wbsb_dat_tmp;
1968
vl_dpram_2r2w # (
1969 33 unneback
    .data_width(data_width), .addr_width(addr_width) )
1970 32 unneback
dpram0(
1971
    .d_a(wbsa_dat_i),
1972
    .q_a(wbsa_dat_tmp),
1973
    .adr_a(wbsa_adr_i),
1974
    .we_a(wbsa_we_i),
1975
    .clk_a(wbsa_clk),
1976
    .d_b(wbsb_dat_i),
1977
    .q_b(wbsb_dat_tmp),
1978
    .adr_b(wbsb_adr_i),
1979
    .we_b(wbsb_we_i),
1980
    .clk_b(wbsb_clk) );
1981 33 unneback
generate if (dat_o_mask_a==1)
1982 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
1983
endgenerate
1984 33 unneback
generate if (dat_o_mask_a==0)
1985 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp;
1986
endgenerate
1987 33 unneback
generate if (dat_o_mask_b==1)
1988 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
1989
endgenerate
1990 33 unneback
generate if (dat_o_mask_b==0)
1991 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp;
1992
endgenerate
1993
vl_spr ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
1994
vl_spr ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
1995
endmodule
1996 18 unneback
//////////////////////////////////////////////////////////////////////
1997
////                                                              ////
1998
////  Arithmetic functions                                        ////
1999
////                                                              ////
2000
////  Description                                                 ////
2001
////  Arithmetic functions for ALU and DSP                        ////
2002
////                                                              ////
2003
////                                                              ////
2004
////  To Do:                                                      ////
2005
////   -                                                          ////
2006
////                                                              ////
2007
////  Author(s):                                                  ////
2008
////      - Michael Unneback, unneback@opencores.org              ////
2009
////        ORSoC AB                                              ////
2010
////                                                              ////
2011
//////////////////////////////////////////////////////////////////////
2012
////                                                              ////
2013
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2014
////                                                              ////
2015
//// This source file may be used and distributed without         ////
2016
//// restriction provided that this copyright statement is not    ////
2017
//// removed from the file and that any derivative work contains  ////
2018
//// the original copyright notice and the associated disclaimer. ////
2019
////                                                              ////
2020
//// This source file is free software; you can redistribute it   ////
2021
//// and/or modify it under the terms of the GNU Lesser General   ////
2022
//// Public License as published by the Free Software Foundation; ////
2023
//// either version 2.1 of the License, or (at your option) any   ////
2024
//// later version.                                               ////
2025
////                                                              ////
2026
//// This source is distributed in the hope that it will be       ////
2027
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2028
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2029
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2030
//// details.                                                     ////
2031
////                                                              ////
2032
//// You should have received a copy of the GNU Lesser General    ////
2033
//// Public License along with this source; if not, download it   ////
2034
//// from http://www.opencores.org/lgpl.shtml                     ////
2035
////                                                              ////
2036
//////////////////////////////////////////////////////////////////////
2037
// signed multiplication
2038
module vl_mults (a,b,p);
2039
parameter operand_a_width = 18;
2040
parameter operand_b_width = 18;
2041
parameter result_hi = 35;
2042
parameter result_lo = 0;
2043
input [operand_a_width-1:0] a;
2044
input [operand_b_width-1:0] b;
2045
output [result_hi:result_lo] p;
2046
wire signed [operand_a_width-1:0] ai;
2047
wire signed [operand_b_width-1:0] bi;
2048
wire signed [operand_a_width+operand_b_width-1:0] result;
2049
    assign ai = a;
2050
    assign bi = b;
2051
    assign result = ai * bi;
2052
    assign p = result[result_hi:result_lo];
2053
endmodule
2054
module vl_mults18x18 (a,b,p);
2055
input [17:0] a,b;
2056
output [35:0] p;
2057
vl_mult
2058
    # (.operand_a_width(18), .operand_b_width(18))
2059
    mult0 (.a(a), .b(b), .p(p));
2060
endmodule
2061
// unsigned multiplication
2062
module vl_mult (a,b,p);
2063
parameter operand_a_width = 18;
2064
parameter operand_b_width = 18;
2065
parameter result_hi = 35;
2066
parameter result_lo = 0;
2067
input [operand_a_width-1:0] a;
2068
input [operand_b_width-1:0] b;
2069
output [result_hi:result_hi] p;
2070
wire [operand_a_width+operand_b_width-1:0] result;
2071
    assign result = a * b;
2072
    assign p = result[result_hi:result_lo];
2073
endmodule
2074
// shift unit
2075
// supporting the following shift functions
2076
//   SLL
2077
//   SRL
2078
//   SRA
2079
module vl_shift_unit_32( din, s, dout, opcode);
2080
input [31:0] din; // data in operand
2081
input [4:0] s; // shift operand
2082
input [1:0] opcode;
2083
output [31:0] dout;
2084
parameter opcode_sll = 2'b00;
2085
//parameter opcode_srl = 2'b01;
2086
parameter opcode_sra = 2'b10;
2087
//parameter opcode_ror = 2'b11;
2088
wire sll, sra;
2089
assign sll = opcode == opcode_sll;
2090
assign sra = opcode == opcode_sra;
2091
wire [15:1] s1;
2092
wire [3:0] sign;
2093
wire [7:0] tmp [0:3];
2094
// first stage is multiplier based
2095
// shift operand as fractional 8.7
2096
assign s1[15] = sll & s[2:0]==3'd7;
2097
assign s1[14] = sll & s[2:0]==3'd6;
2098
assign s1[13] = sll & s[2:0]==3'd5;
2099
assign s1[12] = sll & s[2:0]==3'd4;
2100
assign s1[11] = sll & s[2:0]==3'd3;
2101
assign s1[10] = sll & s[2:0]==3'd2;
2102
assign s1[ 9] = sll & s[2:0]==3'd1;
2103
assign s1[ 8] = s[2:0]==3'd0;
2104
assign s1[ 7] = !sll & s[2:0]==3'd1;
2105
assign s1[ 6] = !sll & s[2:0]==3'd2;
2106
assign s1[ 5] = !sll & s[2:0]==3'd3;
2107
assign s1[ 4] = !sll & s[2:0]==3'd4;
2108
assign s1[ 3] = !sll & s[2:0]==3'd5;
2109
assign s1[ 2] = !sll & s[2:0]==3'd6;
2110
assign s1[ 1] = !sll & s[2:0]==3'd7;
2111
assign sign[3] = din[31] & sra;
2112
assign sign[2] = sign[3] & (&din[31:24]);
2113
assign sign[1] = sign[2] & (&din[23:16]);
2114
assign sign[0] = sign[1] & (&din[15:8]);
2115
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte3 ( .a({sign[3], {8{sign[3]}},din[31:24], din[23:16]}), .b({1'b0,s1}), .p(tmp[3]));
2116
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte2 ( .a({sign[2], din[31:24]  ,din[23:16],  din[15:8]}), .b({1'b0,s1}), .p(tmp[2]));
2117
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte1 ( .a({sign[1], din[23:16]  ,din[15:8],   din[7:0]}), .b({1'b0,s1}), .p(tmp[1]));
2118
vl_mults # ( .operand_a_width(25), .operand_b_width(16), .result_hi(14), .result_lo(7)) mult_byte0 ( .a({sign[0], din[15:8]   ,din[7:0],    8'h00}),      .b({1'b0,s1}), .p(tmp[0]));
2119
// second stage is multiplexer based
2120
// shift on byte level
2121
// mux byte 3
2122
assign dout[31:24] = (s[4:3]==2'b00) ? tmp[3] :
2123
                     (sll & s[4:3]==2'b01) ? tmp[2] :
2124
                     (sll & s[4:3]==2'b10) ? tmp[1] :
2125
                     (sll & s[4:3]==2'b11) ? tmp[0] :
2126
                     {8{sign[3]}};
2127
// mux byte 2
2128
assign dout[23:16] = (s[4:3]==2'b00) ? tmp[2] :
2129
                     (sll & s[4:3]==2'b01) ? tmp[1] :
2130
                     (sll & s[4:3]==2'b10) ? tmp[0] :
2131
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
2132
                     (s[4:3]==2'b01) ? tmp[3] :
2133
                     {8{sign[3]}};
2134
// mux byte 1
2135
assign dout[15:8]  = (s[4:3]==2'b00) ? tmp[1] :
2136
                     (sll & s[4:3]==2'b01) ? tmp[0] :
2137
                     (sll & s[4:3]==2'b10) ? {8{1'b0}} :
2138
                     (sll & s[4:3]==2'b11) ? {8{1'b0}} :
2139
                     (s[4:3]==2'b01) ? tmp[2] :
2140
                     (s[4:3]==2'b10) ? tmp[3] :
2141
                     {8{sign[3]}};
2142
// mux byte 0
2143
assign dout[7:0]   = (s[4:3]==2'b00) ? tmp[0] :
2144
                     (sll) ?  {8{1'b0}}:
2145
                     (s[4:3]==2'b01) ? tmp[1] :
2146
                     (s[4:3]==2'b10) ? tmp[2] :
2147
                     tmp[3];
2148
endmodule
2149
// logic unit
2150
// supporting the following logic functions
2151
//    a and b
2152
//    a or  b
2153
//    a xor b
2154
//    not b
2155
module vl_logic_unit( a, b, result, opcode);
2156
parameter width = 32;
2157
parameter opcode_and = 2'b00;
2158
parameter opcode_or  = 2'b01;
2159
parameter opcode_xor = 2'b10;
2160
input [width-1:0] a,b;
2161
output [width-1:0] result;
2162
input [1:0] opcode;
2163
assign result = (opcode==opcode_and) ? a & b :
2164
                (opcode==opcode_or)  ? a | b :
2165
                (opcode==opcode_xor) ? a ^ b :
2166
                b;
2167
endmodule
2168
module vl_arith_unit ( a, b, c_in, add_sub, sign, result, c_out, z, ovfl);
2169
parameter width = 32;
2170
parameter opcode_add = 1'b0;
2171
parameter opcode_sub = 1'b1;
2172
input [width-1:0] a,b;
2173
input c_in, add_sub, sign;
2174
output [width-1:0] result;
2175
output c_out, z, ovfl;
2176
assign {c_out,result} = {(a[width-1] & sign),a} + ({a[width-1] & sign,b} ^ {(width+1){(add_sub==opcode_sub)}}) + {{(width-1){1'b0}},(c_in | (add_sub==opcode_sub))};
2177
assign z = (result=={width{1'b0}});
2178
assign ovfl = ( a[width-1] &  b[width-1] & ~result[width-1]) |
2179
               (~a[width-1] & ~b[width-1] &  result[width-1]);
2180
endmodule

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