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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Blame information for rev 94

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1 60 unneback
// default SYN_KEEP definition
2 6 unneback
//////////////////////////////////////////////////////////////////////
3
////                                                              ////
4
////  Versatile library, clock and reset                          ////
5
////                                                              ////
6
////  Description                                                 ////
7
////  Logic related to clock and reset                            ////
8
////                                                              ////
9
////                                                              ////
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////  To Do:                                                      ////
11
////   - add more different registers                             ////
12
////                                                              ////
13
////  Author(s):                                                  ////
14
////      - Michael Unneback, unneback@opencores.org              ////
15
////        ORSoC AB                                              ////
16
////                                                              ////
17
//////////////////////////////////////////////////////////////////////
18
////                                                              ////
19
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
20
////                                                              ////
21
//// This source file may be used and distributed without         ////
22
//// restriction provided that this copyright statement is not    ////
23
//// removed from the file and that any derivative work contains  ////
24
//// the original copyright notice and the associated disclaimer. ////
25
////                                                              ////
26
//// This source file is free software; you can redistribute it   ////
27
//// and/or modify it under the terms of the GNU Lesser General   ////
28
//// Public License as published by the Free Software Foundation; ////
29
//// either version 2.1 of the License, or (at your option) any   ////
30
//// later version.                                               ////
31
////                                                              ////
32
//// This source is distributed in the hope that it will be       ////
33
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
34
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
35
//// PURPOSE.  See the GNU Lesser General Public License for more ////
36
//// details.                                                     ////
37
////                                                              ////
38
//// You should have received a copy of the GNU Lesser General    ////
39
//// Public License along with this source; if not, download it   ////
40
//// from http://www.opencores.org/lgpl.shtml                     ////
41
////                                                              ////
42
//////////////////////////////////////////////////////////////////////
43 21 unneback
//altera
44 33 unneback
module vl_gbuf ( i, o);
45
input i;
46
output o;
47
assign o = i;
48
endmodule
49 6 unneback
 // ALTERA
50
 //ACTEL
51
// sync reset
52 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
53 6 unneback
// output active high global reset sync with two DFFs 
54
`timescale 1 ns/100 ps
55
module vl_sync_rst ( rst_n_i, rst_o, clk);
56
input rst_n_i, clk;
57
output rst_o;
58 18 unneback
reg [1:0] tmp;
59 6 unneback
always @ (posedge clk or negedge rst_n_i)
60
if (!rst_n_i)
61 17 unneback
        tmp <= 2'b11;
62 6 unneback
else
63 33 unneback
        tmp <= {1'b0,tmp[1]};
64 17 unneback
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
65 6 unneback
endmodule
66
// vl_pll
67 32 unneback
///////////////////////////////////////////////////////////////////////////////
68
`timescale 1 ps/1 ps
69
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
70
parameter index = 0;
71
parameter number_of_clk = 1;
72
parameter period_time_0 = 20000;
73
parameter period_time_1 = 20000;
74
parameter period_time_2 = 20000;
75
parameter period_time_3 = 20000;
76
parameter period_time_4 = 20000;
77
parameter lock_delay = 2000000;
78
input clk_i, rst_n_i;
79
output lock;
80
output reg [0:number_of_clk-1] clk_o;
81
output [0:number_of_clk-1] rst_o;
82 33 unneback
`ifdef SIM_PLL
83 32 unneback
always
84
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
85
generate if (number_of_clk > 1)
86
always
87
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
88
endgenerate
89
generate if (number_of_clk > 2)
90
always
91
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
92
endgenerate
93 33 unneback
generate if (number_of_clk > 3)
94 32 unneback
always
95
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
96
endgenerate
97 33 unneback
generate if (number_of_clk > 4)
98 32 unneback
always
99
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
100
endgenerate
101
genvar i;
102
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
103
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
104
end
105
endgenerate
106 33 unneback
//assign #lock_delay lock = rst_n_i;
107
assign lock = rst_n_i;
108 32 unneback
endmodule
109 33 unneback
`else
110
`ifdef VL_PLL0
111
`ifdef VL_PLL0_CLK1
112
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
113
`endif
114
`ifdef VL_PLL0_CLK2
115
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
116
`endif
117
`ifdef VL_PLL0_CLK3
118
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
119
`endif
120
`ifdef VL_PLL0_CLK4
121
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
122
`endif
123
`ifdef VL_PLL0_CLK5
124
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
125
`endif
126
`endif
127
`ifdef VL_PLL1
128
`ifdef VL_PLL1_CLK1
129
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
130
`endif
131
`ifdef VL_PLL1_CLK2
132
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
133
`endif
134
`ifdef VL_PLL1_CLK3
135
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
136
`endif
137
`ifdef VL_PLL1_CLK4
138
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
139
`endif
140
`ifdef VL_PLL1_CLK5
141
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
142
`endif
143
`endif
144
`ifdef VL_PLL2
145
`ifdef VL_PLL2_CLK1
146
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
147
`endif
148
`ifdef VL_PLL2_CLK2
149
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
150
`endif
151
`ifdef VL_PLL2_CLK3
152
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
153
`endif
154
`ifdef VL_PLL2_CLK4
155
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
156
`endif
157
`ifdef VL_PLL2_CLK5
158
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
159
`endif
160
`endif
161
`ifdef VL_PLL3
162
`ifdef VL_PLL3_CLK1
163
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
164
`endif
165
`ifdef VL_PLL3_CLK2
166
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
167
`endif
168
`ifdef VL_PLL3_CLK3
169
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
170
`endif
171
`ifdef VL_PLL3_CLK4
172
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
173
`endif
174
`ifdef VL_PLL3_CLK5
175
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
176
`endif
177
`endif
178 32 unneback
genvar i;
179
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
180 40 unneback
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
181 32 unneback
end
182
endgenerate
183
endmodule
184 33 unneback
`endif
185 32 unneback
///////////////////////////////////////////////////////////////////////////////
186 6 unneback
 //altera
187
 //actel
188
//////////////////////////////////////////////////////////////////////
189
////                                                              ////
190
////  Versatile library, registers                                ////
191
////                                                              ////
192
////  Description                                                 ////
193
////  Different type of registers                                 ////
194
////                                                              ////
195
////                                                              ////
196
////  To Do:                                                      ////
197
////   - add more different registers                             ////
198
////                                                              ////
199
////  Author(s):                                                  ////
200
////      - Michael Unneback, unneback@opencores.org              ////
201
////        ORSoC AB                                              ////
202
////                                                              ////
203
//////////////////////////////////////////////////////////////////////
204
////                                                              ////
205
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
206
////                                                              ////
207
//// This source file may be used and distributed without         ////
208
//// restriction provided that this copyright statement is not    ////
209
//// removed from the file and that any derivative work contains  ////
210
//// the original copyright notice and the associated disclaimer. ////
211
////                                                              ////
212
//// This source file is free software; you can redistribute it   ////
213
//// and/or modify it under the terms of the GNU Lesser General   ////
214
//// Public License as published by the Free Software Foundation; ////
215
//// either version 2.1 of the License, or (at your option) any   ////
216
//// later version.                                               ////
217
////                                                              ////
218
//// This source is distributed in the hope that it will be       ////
219
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
220
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
221
//// PURPOSE.  See the GNU Lesser General Public License for more ////
222
//// details.                                                     ////
223
////                                                              ////
224
//// You should have received a copy of the GNU Lesser General    ////
225
//// Public License along with this source; if not, download it   ////
226
//// from http://www.opencores.org/lgpl.shtml                     ////
227
////                                                              ////
228
//////////////////////////////////////////////////////////////////////
229 18 unneback
module vl_dff ( d, q, clk, rst);
230 6 unneback
        parameter width = 1;
231
        parameter reset_value = 0;
232
        input [width-1:0] d;
233
        input clk, rst;
234
        output reg [width-1:0] q;
235
        always @ (posedge clk or posedge rst)
236
        if (rst)
237
                q <= reset_value;
238
        else
239
                q <= d;
240
endmodule
241 18 unneback
module vl_dff_array ( d, q, clk, rst);
242 6 unneback
        parameter width = 1;
243
        parameter depth = 2;
244
        parameter reset_value = 1'b0;
245
        input [width-1:0] d;
246
        input clk, rst;
247
        output [width-1:0] q;
248
        reg  [0:depth-1] q_tmp [width-1:0];
249
        integer i;
250
        always @ (posedge clk or posedge rst)
251
        if (rst) begin
252
            for (i=0;i<depth;i=i+1)
253
                q_tmp[i] <= {width{reset_value}};
254
        end else begin
255
            q_tmp[0] <= d;
256
            for (i=1;i<depth;i=i+1)
257
                q_tmp[i] <= q_tmp[i-1];
258
        end
259
    assign q = q_tmp[depth-1];
260
endmodule
261 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
262 6 unneback
        parameter width = 1;
263
        parameter reset_value = 0;
264
        input [width-1:0] d;
265
        input ce, clk, rst;
266
        output reg [width-1:0] q;
267
        always @ (posedge clk or posedge rst)
268
        if (rst)
269
                q <= reset_value;
270
        else
271
                if (ce)
272
                        q <= d;
273
endmodule
274 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
275 8 unneback
        parameter width = 1;
276
        parameter reset_value = 0;
277
        input [width-1:0] d;
278 10 unneback
        input ce, clear, clk, rst;
279 8 unneback
        output reg [width-1:0] q;
280
        always @ (posedge clk or posedge rst)
281
        if (rst)
282
            q <= reset_value;
283
        else
284
            if (ce)
285
                if (clear)
286
                    q <= {width{1'b0}};
287
                else
288
                    q <= d;
289
endmodule
290 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
291
        parameter width = 1;
292
        parameter reset_value = 0;
293
        input [width-1:0] d;
294
        input ce, set, clk, rst;
295
        output reg [width-1:0] q;
296
        always @ (posedge clk or posedge rst)
297
        if (rst)
298
            q <= reset_value;
299
        else
300
            if (ce)
301
                if (set)
302
                    q <= {width{1'b1}};
303
                else
304
                    q <= d;
305
endmodule
306 29 unneback
module vl_spr ( sp, r, q, clk, rst);
307 64 unneback
        //parameter width = 1;
308
        parameter reset_value = 1'b0;
309 29 unneback
        input sp, r;
310
        output reg q;
311
        input clk, rst;
312
        always @ (posedge clk or posedge rst)
313
        if (rst)
314
            q <= reset_value;
315
        else
316
            if (sp)
317
                q <= 1'b1;
318
            else if (r)
319
                q <= 1'b0;
320
endmodule
321
module vl_srp ( s, rp, q, clk, rst);
322
        parameter width = 1;
323
        parameter reset_value = 0;
324
        input s, rp;
325
        output reg q;
326
        input clk, rst;
327
        always @ (posedge clk or posedge rst)
328
        if (rst)
329
            q <= reset_value;
330
        else
331
            if (rp)
332
                q <= 1'b0;
333
            else if (s)
334
                q <= 1'b1;
335
endmodule
336 6 unneback
// megafunction wizard: %LPM_FF%
337
// GENERATION: STANDARD
338
// VERSION: WM1.0
339
// MODULE: lpm_ff 
340
// ============================================================
341
// File Name: dff_sr.v
342
// Megafunction Name(s):
343
//                      lpm_ff
344
//
345
// Simulation Library Files(s):
346
//                      lpm
347
// ============================================================
348
// ************************************************************
349
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
350
//
351
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
352
// ************************************************************
353
//Copyright (C) 1991-2010 Altera Corporation
354
//Your use of Altera Corporation's design tools, logic functions 
355
//and other software and tools, and its AMPP partner logic 
356
//functions, and any output files from any of the foregoing 
357
//(including device programming or simulation files), and any 
358
//associated documentation or information are expressly subject 
359
//to the terms and conditions of the Altera Program License 
360
//Subscription Agreement, Altera MegaCore Function License 
361
//Agreement, or other applicable license agreement, including, 
362
//without limitation, that your use is for the sole purpose of 
363
//programming logic devices manufactured by Altera and sold by 
364
//Altera or its authorized distributors.  Please refer to the 
365
//applicable agreement for further details.
366
// synopsys translate_off
367
`timescale 1 ps / 1 ps
368
// synopsys translate_on
369 18 unneback
module vl_dff_sr (
370 6 unneback
        aclr,
371
        aset,
372
        clock,
373
        data,
374
        q);
375
        input     aclr;
376
        input     aset;
377
        input     clock;
378
        input     data;
379
        output    q;
380
        wire [0:0] sub_wire0;
381
        wire [0:0] sub_wire1 = sub_wire0[0:0];
382
        wire  q = sub_wire1;
383
        wire  sub_wire2 = data;
384
        wire  sub_wire3 = sub_wire2;
385
        lpm_ff  lpm_ff_component (
386
                                .aclr (aclr),
387
                                .clock (clock),
388
                                .data (sub_wire3),
389
                                .aset (aset),
390
                                .q (sub_wire0)
391
                                // synopsys translate_off
392
                                ,
393
                                .aload (),
394
                                .enable (),
395
                                .sclr (),
396
                                .sload (),
397
                                .sset ()
398
                                // synopsys translate_on
399
                                );
400
        defparam
401
                lpm_ff_component.lpm_fftype = "DFF",
402
                lpm_ff_component.lpm_type = "LPM_FF",
403
                lpm_ff_component.lpm_width = 1;
404
endmodule
405
// ============================================================
406
// CNX file retrieval info
407
// ============================================================
408
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
409
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
410
// Retrieval info: PRIVATE: ASET NUMERIC "1"
411
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
412
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
413
// Retrieval info: PRIVATE: DFF NUMERIC "1"
414
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
415
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
416
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
417
// Retrieval info: PRIVATE: SSET NUMERIC "0"
418
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
419
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
420
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
421
// Retrieval info: PRIVATE: nBit NUMERIC "1"
422
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
423
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
424
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
425
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
426
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
427
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
428
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
429
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
430
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
431
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
432
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
433
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
434
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
435
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
436
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
437
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
438
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
439
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
440
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
441
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
442
// Retrieval info: LIB_FILE: lpm
443
// LATCH
444
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
445 18 unneback
module vl_latch ( d, le, q, clk);
446 6 unneback
input d, le;
447
output q;
448
input clk;
449
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
450
endmodule
451 18 unneback
module vl_shreg ( d, q, clk, rst);
452 17 unneback
parameter depth = 10;
453
input d;
454
output q;
455
input clk, rst;
456
reg [1:depth] dffs;
457
always @ (posedge clk or posedge rst)
458
if (rst)
459
    dffs <= {depth{1'b0}};
460
else
461
    dffs <= {d,dffs[1:depth-1]};
462
assign q = dffs[depth];
463
endmodule
464 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
465 17 unneback
parameter depth = 10;
466
input d, ce;
467
output q;
468
input clk, rst;
469
reg [1:depth] dffs;
470
always @ (posedge clk or posedge rst)
471
if (rst)
472
    dffs <= {depth{1'b0}};
473
else
474
    if (ce)
475
        dffs <= {d,dffs[1:depth-1]};
476
assign q = dffs[depth];
477
endmodule
478 18 unneback
module vl_delay ( d, q, clk, rst);
479 15 unneback
parameter depth = 10;
480
input d;
481
output q;
482
input clk, rst;
483
reg [1:depth] dffs;
484
always @ (posedge clk or posedge rst)
485
if (rst)
486
    dffs <= {depth{1'b0}};
487
else
488
    dffs <= {d,dffs[1:depth-1]};
489
assign q = dffs[depth];
490
endmodule
491 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
492 17 unneback
parameter depth = 10;
493
input d;
494
output q, emptyflag;
495
input clk, rst;
496
reg [1:depth] dffs;
497
always @ (posedge clk or posedge rst)
498
if (rst)
499
    dffs <= {depth{1'b0}};
500
else
501
    dffs <= {d,dffs[1:depth-1]};
502
assign q = dffs[depth];
503
assign emptyflag = !(|dffs);
504
endmodule
505 94 unneback
module vl_pules2toggle ( pl, q, clk, rst)
506
input pl;
507
output q;
508
input clk, rst;
509
input
510
always @ (posedge clk or posedge rst)
511
if (rst)
512
    q <= 1'b0;
513
else
514
    q <= pl ^ q;
515
endmodule
516
module vl_toggle2pulse; (d, pl, clk, rst);
517
input d;
518
output pl;
519
input clk, rst;
520
reg dff;
521
always @ (posedge clk or posedge rst)
522
if (rst)
523
    dff <= 1'b0;
524
else
525
    dff <= d;
526
assign d ^ dff;
527
endmodule
528
module vl_synchronizer (d, q, clk, rst);
529
input d;
530
output reg q;
531
output clk, rst;
532
reg dff;
533
always @ (posedge clk or posedge rst)
534
if (rst)
535
    {dff,q} <= 2'b00;
536
else
537
    {dff,q} <= {d,dff};
538
endmodule
539
module vl_cdc ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst)
540
input start_pl;
541
output take_it_pl;
542
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
543
output got_it_pl;
544
input clk_src, rst_src;
545
input clk_dst, rst_dst;
546
wire take_it_tg, take_it_tg_sync;
547
wire got_it_tg, got_it_tg_sync;
548
// src -> dst
549
vl_pulse2toggle p2t0 (
550
    .pl(start_pl),
551
    .q(take_it_tg),
552
    .clk(clk_src),
553
    .rst(rst_src));
554
vl_synchronizer sync0 (
555
    .d(take_it_tg),
556
    .q(take_it_tg_sync),
557
    .clk(clk_dst),
558
    .rst(rst_dst));
559
vl_toggle2pulse t2p0 (
560
    .d(take_it_sync),
561
    .pl(take_it_pl),
562
    .clk(clk_dst),
563
    .rst(rst_dst));
564
// dst -> src
565
vl_pulse2toggle p2t0 (
566
    .pl(take_it_grant_pl),
567
    .q(got_it_tg),
568
    .clk(clk_dst),
569
    .rst(rst_dst));
570
vl_synchronizer sync1 (
571
    .d(got_it_tg),
572
    .q(got_it_tg_sync),
573
    .clk(clk_src),
574
    .rst(rst_src));
575
vl_toggle2pulse t2p1 (
576
    .d(take_it_grant_tg_sync),
577
    .pl(got_it_pl),
578
    .clk(clk_src),
579
    .rst(rst_src));
580
endmodule
581 6 unneback
//////////////////////////////////////////////////////////////////////
582
////                                                              ////
583 18 unneback
////  Logic functions                                             ////
584
////                                                              ////
585
////  Description                                                 ////
586
////  Logic functions such as multiplexers                        ////
587
////                                                              ////
588
////                                                              ////
589
////  To Do:                                                      ////
590
////   -                                                          ////
591
////                                                              ////
592
////  Author(s):                                                  ////
593
////      - Michael Unneback, unneback@opencores.org              ////
594
////        ORSoC AB                                              ////
595
////                                                              ////
596
//////////////////////////////////////////////////////////////////////
597
////                                                              ////
598
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
599
////                                                              ////
600
//// This source file may be used and distributed without         ////
601
//// restriction provided that this copyright statement is not    ////
602
//// removed from the file and that any derivative work contains  ////
603
//// the original copyright notice and the associated disclaimer. ////
604
////                                                              ////
605
//// This source file is free software; you can redistribute it   ////
606
//// and/or modify it under the terms of the GNU Lesser General   ////
607
//// Public License as published by the Free Software Foundation; ////
608
//// either version 2.1 of the License, or (at your option) any   ////
609
//// later version.                                               ////
610
////                                                              ////
611
//// This source is distributed in the hope that it will be       ////
612
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
613
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
614
//// PURPOSE.  See the GNU Lesser General Public License for more ////
615
//// details.                                                     ////
616
////                                                              ////
617
//// You should have received a copy of the GNU Lesser General    ////
618
//// Public License along with this source; if not, download it   ////
619
//// from http://www.opencores.org/lgpl.shtml                     ////
620
////                                                              ////
621
//////////////////////////////////////////////////////////////////////
622 36 unneback
module vl_mux_andor ( a, sel, dout);
623
parameter width = 32;
624
parameter nr_of_ports = 4;
625
input [nr_of_ports*width-1:0] a;
626
input [nr_of_ports-1:0] sel;
627
output reg [width-1:0] dout;
628 38 unneback
integer i,j;
629 36 unneback
always @ (a, sel)
630
begin
631
    dout = a[width-1:0] & {width{sel[0]}};
632 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
633
        for (j=0;j<width;j=j+1)
634
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
635 36 unneback
end
636
endmodule
637 34 unneback
module vl_mux2_andor ( a1, a0, sel, dout);
638
parameter width = 32;
639 35 unneback
localparam nr_of_ports = 2;
640 34 unneback
input [width-1:0] a1, a0;
641
input [nr_of_ports-1:0] sel;
642
output [width-1:0] dout;
643 36 unneback
vl_mux_andor
644 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
645 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
646 34 unneback
endmodule
647
module vl_mux3_andor ( a2, a1, a0, sel, dout);
648
parameter width = 32;
649 35 unneback
localparam nr_of_ports = 3;
650 34 unneback
input [width-1:0] a2, a1, a0;
651
input [nr_of_ports-1:0] sel;
652
output [width-1:0] dout;
653 36 unneback
vl_mux_andor
654 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
655 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
656 34 unneback
endmodule
657 18 unneback
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
658
parameter width = 32;
659 35 unneback
localparam nr_of_ports = 4;
660 18 unneback
input [width-1:0] a3, a2, a1, a0;
661
input [nr_of_ports-1:0] sel;
662 22 unneback
output [width-1:0] dout;
663 36 unneback
vl_mux_andor
664 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
665 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
666 18 unneback
endmodule
667
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
668
parameter width = 32;
669 35 unneback
localparam nr_of_ports = 5;
670 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
671
input [nr_of_ports-1:0] sel;
672 22 unneback
output [width-1:0] dout;
673 36 unneback
vl_mux_andor
674 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
675 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
676 18 unneback
endmodule
677
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
678
parameter width = 32;
679 35 unneback
localparam nr_of_ports = 6;
680 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
681
input [nr_of_ports-1:0] sel;
682 22 unneback
output [width-1:0] dout;
683 36 unneback
vl_mux_andor
684 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
685 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
686 18 unneback
endmodule
687 43 unneback
module vl_parity_generate (data, parity);
688
parameter word_size = 32;
689
parameter chunk_size = 8;
690
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
691
input [word_size-1:0] data;
692
output reg [word_size/chunk_size-1:0] parity;
693
integer i,j;
694
always @ (data)
695
for (i=0;i<word_size/chunk_size;i=i+1) begin
696
    parity[i] = parity_type;
697
    for (j=0;j<chunk_size;j=j+1) begin
698 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
699 43 unneback
    end
700
end
701
endmodule
702
module vl_parity_check( data, parity, parity_error);
703
parameter word_size = 32;
704
parameter chunk_size = 8;
705
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
706
input [word_size-1:0] data;
707
input [word_size/chunk_size-1:0] parity;
708
output parity_error;
709 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
710 43 unneback
integer i,j;
711
always @ (data or parity)
712
for (i=0;i<word_size/chunk_size;i=i+1) begin
713
    error_flag[i] = parity[i] ^ parity_type;
714
    for (j=0;j<chunk_size;j=j+1) begin
715 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
716 43 unneback
    end
717
end
718
assign parity_error = |error_flag;
719
endmodule
720 18 unneback
//////////////////////////////////////////////////////////////////////
721
////                                                              ////
722 44 unneback
////  IO functions                                                ////
723
////                                                              ////
724
////  Description                                                 ////
725
////  IO functions such as IOB flip-flops                         ////
726
////                                                              ////
727
////                                                              ////
728
////  To Do:                                                      ////
729
////   -                                                          ////
730
////                                                              ////
731
////  Author(s):                                                  ////
732
////      - Michael Unneback, unneback@opencores.org              ////
733
////        ORSoC AB                                              ////
734
////                                                              ////
735
//////////////////////////////////////////////////////////////////////
736
////                                                              ////
737
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
738
////                                                              ////
739
//// This source file may be used and distributed without         ////
740
//// restriction provided that this copyright statement is not    ////
741
//// removed from the file and that any derivative work contains  ////
742
//// the original copyright notice and the associated disclaimer. ////
743
////                                                              ////
744
//// This source file is free software; you can redistribute it   ////
745
//// and/or modify it under the terms of the GNU Lesser General   ////
746
//// Public License as published by the Free Software Foundation; ////
747
//// either version 2.1 of the License, or (at your option) any   ////
748
//// later version.                                               ////
749
////                                                              ////
750
//// This source is distributed in the hope that it will be       ////
751
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
752
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
753
//// PURPOSE.  See the GNU Lesser General Public License for more ////
754
//// details.                                                     ////
755
////                                                              ////
756
//// You should have received a copy of the GNU Lesser General    ////
757
//// Public License along with this source; if not, download it   ////
758
//// from http://www.opencores.org/lgpl.shtml                     ////
759
////                                                              ////
760
//////////////////////////////////////////////////////////////////////
761 45 unneback
`timescale 1ns/1ns
762 44 unneback
module vl_o_dff (d_i, o_pad, clk, rst);
763
parameter width = 1;
764 45 unneback
parameter reset_value = {width{1'b0}};
765
input  [width-1:0]  d_i;
766 44 unneback
output [width-1:0] o_pad;
767
input clk, rst;
768 60 unneback
wire [width-1:0] d_i_int /*synthesis syn_keep = 1*/;
769 45 unneback
reg  [width-1:0] o_pad_int;
770 44 unneback
assign d_i_int = d_i;
771
genvar i;
772 45 unneback
generate
773 44 unneback
for (i=0;i<width;i=i+1) begin
774
    always @ (posedge clk or posedge rst)
775
    if (rst)
776 45 unneback
        o_pad_int[i] <= reset_value[i];
777 44 unneback
    else
778 45 unneback
        o_pad_int[i] <= d_i_int[i];
779
    assign #1 o_pad[i] = o_pad_int[i];
780 44 unneback
end
781
endgenerate
782
endmodule
783 45 unneback
`timescale 1ns/1ns
784 44 unneback
module vl_io_dff_oe ( d_i, d_o, oe, io_pad, clk, rst);
785
parameter width = 1;
786
input  [width-1:0] d_o;
787
output reg [width-1:0] d_i;
788
input oe;
789
inout [width-1:0] io_pad;
790
input clk, rst;
791 60 unneback
wire [width-1:0] oe_d /*synthesis syn_keep = 1*/;
792 44 unneback
reg [width-1:0] oe_q;
793
reg [width-1:0] d_o_q;
794
assign oe_d = {width{oe}};
795
genvar i;
796
generate
797
for (i=0;i<width;i=i+1) begin
798
    always @ (posedge clk or posedge rst)
799
    if (rst)
800
        oe_q[i] <= 1'b0;
801
    else
802
        oe_q[i] <= oe_d[i];
803
    always @ (posedge clk or posedge rst)
804
    if (rst)
805
        d_o_q[i] <= 1'b0;
806
    else
807
        d_o_q[i] <= d_o[i];
808
    always @ (posedge clk or posedge rst)
809
    if (rst)
810
        d_i[i] <= 1'b0;
811
    else
812
        d_i[i] <= io_pad[i];
813 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
814 44 unneback
end
815
endgenerate
816
endmodule
817
//////////////////////////////////////////////////////////////////////
818
////                                                              ////
819 6 unneback
////  Versatile counter                                           ////
820
////                                                              ////
821
////  Description                                                 ////
822
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
823
////  counter                                                     ////
824
////                                                              ////
825
////  To Do:                                                      ////
826
////   - add LFSR with more taps                                  ////
827
////                                                              ////
828
////  Author(s):                                                  ////
829
////      - Michael Unneback, unneback@opencores.org              ////
830
////        ORSoC AB                                              ////
831
////                                                              ////
832
//////////////////////////////////////////////////////////////////////
833
////                                                              ////
834
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
835
////                                                              ////
836
//// This source file may be used and distributed without         ////
837
//// restriction provided that this copyright statement is not    ////
838
//// removed from the file and that any derivative work contains  ////
839
//// the original copyright notice and the associated disclaimer. ////
840
////                                                              ////
841
//// This source file is free software; you can redistribute it   ////
842
//// and/or modify it under the terms of the GNU Lesser General   ////
843
//// Public License as published by the Free Software Foundation; ////
844
//// either version 2.1 of the License, or (at your option) any   ////
845
//// later version.                                               ////
846
////                                                              ////
847
//// This source is distributed in the hope that it will be       ////
848
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
849
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
850
//// PURPOSE.  See the GNU Lesser General Public License for more ////
851
//// details.                                                     ////
852
////                                                              ////
853
//// You should have received a copy of the GNU Lesser General    ////
854
//// Public License along with this source; if not, download it   ////
855
//// from http://www.opencores.org/lgpl.shtml                     ////
856
////                                                              ////
857
//////////////////////////////////////////////////////////////////////
858
// binary counter
859 40 unneback
module vl_cnt_bin_ce (
860
 cke, q, rst, clk);
861 22 unneback
   parameter length = 4;
862 6 unneback
   input cke;
863
   output [length:1] q;
864
   input rst;
865
   input clk;
866
   parameter clear_value = 0;
867
   parameter set_value = 1;
868
   parameter wrap_value = 0;
869
   parameter level1_value = 15;
870
   reg  [length:1] qi;
871
   wire [length:1] q_next;
872
   assign q_next = qi + {{length-1{1'b0}},1'b1};
873
   always @ (posedge clk or posedge rst)
874
     if (rst)
875
       qi <= {length{1'b0}};
876
     else
877
     if (cke)
878
       qi <= q_next;
879
   assign q = qi;
880
endmodule
881
//////////////////////////////////////////////////////////////////////
882
////                                                              ////
883
////  Versatile counter                                           ////
884
////                                                              ////
885
////  Description                                                 ////
886
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
887
////  counter                                                     ////
888
////                                                              ////
889
////  To Do:                                                      ////
890
////   - add LFSR with more taps                                  ////
891
////                                                              ////
892
////  Author(s):                                                  ////
893
////      - Michael Unneback, unneback@opencores.org              ////
894
////        ORSoC AB                                              ////
895
////                                                              ////
896
//////////////////////////////////////////////////////////////////////
897
////                                                              ////
898
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
899
////                                                              ////
900
//// This source file may be used and distributed without         ////
901
//// restriction provided that this copyright statement is not    ////
902
//// removed from the file and that any derivative work contains  ////
903
//// the original copyright notice and the associated disclaimer. ////
904
////                                                              ////
905
//// This source file is free software; you can redistribute it   ////
906
//// and/or modify it under the terms of the GNU Lesser General   ////
907
//// Public License as published by the Free Software Foundation; ////
908
//// either version 2.1 of the License, or (at your option) any   ////
909
//// later version.                                               ////
910
////                                                              ////
911
//// This source is distributed in the hope that it will be       ////
912
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
913
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
914
//// PURPOSE.  See the GNU Lesser General Public License for more ////
915
//// details.                                                     ////
916
////                                                              ////
917
//// You should have received a copy of the GNU Lesser General    ////
918
//// Public License along with this source; if not, download it   ////
919
//// from http://www.opencores.org/lgpl.shtml                     ////
920
////                                                              ////
921
//////////////////////////////////////////////////////////////////////
922
// binary counter
923 40 unneback
module vl_cnt_bin_ce_rew_zq_l1 (
924
 cke, rew, zq, level1, rst, clk);
925 6 unneback
   parameter length = 4;
926
   input cke;
927
   input rew;
928 25 unneback
   output reg zq;
929
   output reg level1;
930
   input rst;
931
   input clk;
932
   parameter clear_value = 0;
933
   parameter set_value = 1;
934
   parameter wrap_value = 1;
935
   parameter level1_value = 15;
936 29 unneback
   wire clear;
937 30 unneback
   assign clear = 1'b0;
938 25 unneback
   reg  [length:1] qi;
939
   wire  [length:1] q_next, q_next_fw, q_next_rew;
940
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
941
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
942
   assign q_next = rew ? q_next_rew : q_next_fw;
943
   always @ (posedge clk or posedge rst)
944
     if (rst)
945
       qi <= {length{1'b0}};
946
     else
947
     if (cke)
948
       qi <= q_next;
949
   always @ (posedge clk or posedge rst)
950
     if (rst)
951
       zq <= 1'b1;
952
     else
953
     if (cke)
954
       zq <= q_next == {length{1'b0}};
955
    always @ (posedge clk or posedge rst)
956
    if (rst)
957
        level1 <= 1'b0;
958
    else
959
    if (cke)
960 29 unneback
    if (clear)
961
        level1 <= 1'b0;
962
    else if (q_next == level1_value)
963 25 unneback
        level1 <= 1'b1;
964
    else if (qi == level1_value & rew)
965
        level1 <= 1'b0;
966
endmodule
967
//////////////////////////////////////////////////////////////////////
968
////                                                              ////
969
////  Versatile counter                                           ////
970
////                                                              ////
971
////  Description                                                 ////
972
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
973
////  counter                                                     ////
974
////                                                              ////
975
////  To Do:                                                      ////
976
////   - add LFSR with more taps                                  ////
977
////                                                              ////
978
////  Author(s):                                                  ////
979
////      - Michael Unneback, unneback@opencores.org              ////
980
////        ORSoC AB                                              ////
981
////                                                              ////
982
//////////////////////////////////////////////////////////////////////
983
////                                                              ////
984
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
985
////                                                              ////
986
//// This source file may be used and distributed without         ////
987
//// restriction provided that this copyright statement is not    ////
988
//// removed from the file and that any derivative work contains  ////
989
//// the original copyright notice and the associated disclaimer. ////
990
////                                                              ////
991
//// This source file is free software; you can redistribute it   ////
992
//// and/or modify it under the terms of the GNU Lesser General   ////
993
//// Public License as published by the Free Software Foundation; ////
994
//// either version 2.1 of the License, or (at your option) any   ////
995
//// later version.                                               ////
996
////                                                              ////
997
//// This source is distributed in the hope that it will be       ////
998
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
999
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1000
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1001
//// details.                                                     ////
1002
////                                                              ////
1003
//// You should have received a copy of the GNU Lesser General    ////
1004
//// Public License along with this source; if not, download it   ////
1005
//// from http://www.opencores.org/lgpl.shtml                     ////
1006
////                                                              ////
1007
//////////////////////////////////////////////////////////////////////
1008
// binary counter
1009 40 unneback
module vl_cnt_bin_ce_rew_q_zq_l1 (
1010
 cke, rew, q, zq, level1, rst, clk);
1011 25 unneback
   parameter length = 4;
1012
   input cke;
1013
   input rew;
1014
   output [length:1] q;
1015
   output reg zq;
1016
   output reg level1;
1017
   input rst;
1018
   input clk;
1019
   parameter clear_value = 0;
1020
   parameter set_value = 1;
1021
   parameter wrap_value = 1;
1022
   parameter level1_value = 15;
1023 29 unneback
   wire clear;
1024 30 unneback
   assign clear = 1'b0;
1025 25 unneback
   reg  [length:1] qi;
1026
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1027
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1028
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1029
   assign q_next = rew ? q_next_rew : q_next_fw;
1030
   always @ (posedge clk or posedge rst)
1031
     if (rst)
1032
       qi <= {length{1'b0}};
1033
     else
1034
     if (cke)
1035
       qi <= q_next;
1036
   assign q = qi;
1037
   always @ (posedge clk or posedge rst)
1038
     if (rst)
1039
       zq <= 1'b1;
1040
     else
1041
     if (cke)
1042
       zq <= q_next == {length{1'b0}};
1043
    always @ (posedge clk or posedge rst)
1044
    if (rst)
1045
        level1 <= 1'b0;
1046
    else
1047
    if (cke)
1048 29 unneback
    if (clear)
1049
        level1 <= 1'b0;
1050
    else if (q_next == level1_value)
1051 25 unneback
        level1 <= 1'b1;
1052
    else if (qi == level1_value & rew)
1053
        level1 <= 1'b0;
1054
endmodule
1055
//////////////////////////////////////////////////////////////////////
1056
////                                                              ////
1057
////  Versatile counter                                           ////
1058
////                                                              ////
1059
////  Description                                                 ////
1060
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1061
////  counter                                                     ////
1062
////                                                              ////
1063
////  To Do:                                                      ////
1064
////   - add LFSR with more taps                                  ////
1065
////                                                              ////
1066
////  Author(s):                                                  ////
1067
////      - Michael Unneback, unneback@opencores.org              ////
1068
////        ORSoC AB                                              ////
1069
////                                                              ////
1070
//////////////////////////////////////////////////////////////////////
1071
////                                                              ////
1072
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1073
////                                                              ////
1074
//// This source file may be used and distributed without         ////
1075
//// restriction provided that this copyright statement is not    ////
1076
//// removed from the file and that any derivative work contains  ////
1077
//// the original copyright notice and the associated disclaimer. ////
1078
////                                                              ////
1079
//// This source file is free software; you can redistribute it   ////
1080
//// and/or modify it under the terms of the GNU Lesser General   ////
1081
//// Public License as published by the Free Software Foundation; ////
1082
//// either version 2.1 of the License, or (at your option) any   ////
1083
//// later version.                                               ////
1084
////                                                              ////
1085
//// This source is distributed in the hope that it will be       ////
1086
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1087
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1088
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1089
//// details.                                                     ////
1090
////                                                              ////
1091
//// You should have received a copy of the GNU Lesser General    ////
1092
//// Public License along with this source; if not, download it   ////
1093
//// from http://www.opencores.org/lgpl.shtml                     ////
1094
////                                                              ////
1095
//////////////////////////////////////////////////////////////////////
1096 75 unneback
// LFSR counter
1097
module vl_cnt_lfsr_ce (
1098
 cke, zq, rst, clk);
1099
   parameter length = 4;
1100
   input cke;
1101
   output reg zq;
1102
   input rst;
1103
   input clk;
1104
   parameter clear_value = 0;
1105
   parameter set_value = 1;
1106
   parameter wrap_value = 0;
1107
   parameter level1_value = 15;
1108
   reg  [length:1] qi;
1109
   reg lfsr_fb;
1110
   wire [length:1] q_next;
1111
   reg [32:1] polynom;
1112
   integer i;
1113
   always @ (qi)
1114
   begin
1115
        case (length)
1116
         2: polynom = 32'b11;                               // 0x3
1117
         3: polynom = 32'b110;                              // 0x6
1118
         4: polynom = 32'b1100;                             // 0xC
1119
         5: polynom = 32'b10100;                            // 0x14
1120
         6: polynom = 32'b110000;                           // 0x30
1121
         7: polynom = 32'b1100000;                          // 0x60
1122
         8: polynom = 32'b10111000;                         // 0xb8
1123
         9: polynom = 32'b100010000;                        // 0x110
1124
        10: polynom = 32'b1001000000;                       // 0x240
1125
        11: polynom = 32'b10100000000;                      // 0x500
1126
        12: polynom = 32'b100000101001;                     // 0x829
1127
        13: polynom = 32'b1000000001100;                    // 0x100C
1128
        14: polynom = 32'b10000000010101;                   // 0x2015
1129
        15: polynom = 32'b110000000000000;                  // 0x6000
1130
        16: polynom = 32'b1101000000001000;                 // 0xD008
1131
        17: polynom = 32'b10010000000000000;                // 0x12000
1132
        18: polynom = 32'b100000010000000000;               // 0x20400
1133
        19: polynom = 32'b1000000000000100011;              // 0x40023
1134
        20: polynom = 32'b10010000000000000000;             // 0x90000
1135
        21: polynom = 32'b101000000000000000000;            // 0x140000
1136
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1137
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1138
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1139
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1140
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1141
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1142
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1143
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1144
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1145
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1146
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1147
        default: polynom = 32'b0;
1148
        endcase
1149
        lfsr_fb = qi[length];
1150
        for (i=length-1; i>=1; i=i-1) begin
1151
            if (polynom[i])
1152
                lfsr_fb = lfsr_fb  ~^ qi[i];
1153
        end
1154
    end
1155
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1156
   always @ (posedge clk or posedge rst)
1157
     if (rst)
1158
       qi <= {length{1'b0}};
1159
     else
1160
     if (cke)
1161
       qi <= q_next;
1162
   always @ (posedge clk or posedge rst)
1163
     if (rst)
1164
       zq <= 1'b1;
1165
     else
1166
     if (cke)
1167
       zq <= q_next == {length{1'b0}};
1168
endmodule
1169
//////////////////////////////////////////////////////////////////////
1170
////                                                              ////
1171
////  Versatile counter                                           ////
1172
////                                                              ////
1173
////  Description                                                 ////
1174
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1175
////  counter                                                     ////
1176
////                                                              ////
1177
////  To Do:                                                      ////
1178
////   - add LFSR with more taps                                  ////
1179
////                                                              ////
1180
////  Author(s):                                                  ////
1181
////      - Michael Unneback, unneback@opencores.org              ////
1182
////        ORSoC AB                                              ////
1183
////                                                              ////
1184
//////////////////////////////////////////////////////////////////////
1185
////                                                              ////
1186
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1187
////                                                              ////
1188
//// This source file may be used and distributed without         ////
1189
//// restriction provided that this copyright statement is not    ////
1190
//// removed from the file and that any derivative work contains  ////
1191
//// the original copyright notice and the associated disclaimer. ////
1192
////                                                              ////
1193
//// This source file is free software; you can redistribute it   ////
1194
//// and/or modify it under the terms of the GNU Lesser General   ////
1195
//// Public License as published by the Free Software Foundation; ////
1196
//// either version 2.1 of the License, or (at your option) any   ////
1197
//// later version.                                               ////
1198
////                                                              ////
1199
//// This source is distributed in the hope that it will be       ////
1200
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1201
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1202
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1203
//// details.                                                     ////
1204
////                                                              ////
1205
//// You should have received a copy of the GNU Lesser General    ////
1206
//// Public License along with this source; if not, download it   ////
1207
//// from http://www.opencores.org/lgpl.shtml                     ////
1208
////                                                              ////
1209
//////////////////////////////////////////////////////////////////////
1210 6 unneback
// GRAY counter
1211 40 unneback
module vl_cnt_gray_ce_bin (
1212
 cke, q, q_bin, rst, clk);
1213 6 unneback
   parameter length = 4;
1214
   input cke;
1215
   output reg [length:1] q;
1216
   output [length:1] q_bin;
1217
   input rst;
1218
   input clk;
1219
   parameter clear_value = 0;
1220
   parameter set_value = 1;
1221
   parameter wrap_value = 8;
1222
   parameter level1_value = 15;
1223
   reg  [length:1] qi;
1224
   wire [length:1] q_next;
1225
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1226
   always @ (posedge clk or posedge rst)
1227
     if (rst)
1228
       qi <= {length{1'b0}};
1229
     else
1230
     if (cke)
1231
       qi <= q_next;
1232
   always @ (posedge clk or posedge rst)
1233
     if (rst)
1234
       q <= {length{1'b0}};
1235
     else
1236
       if (cke)
1237
         q <= (q_next>>1) ^ q_next;
1238
   assign q_bin = qi;
1239
endmodule
1240
//////////////////////////////////////////////////////////////////////
1241
////                                                              ////
1242
////  Versatile library, counters                                 ////
1243
////                                                              ////
1244
////  Description                                                 ////
1245
////  counters                                                    ////
1246
////                                                              ////
1247
////                                                              ////
1248
////  To Do:                                                      ////
1249
////   - add more counters                                        ////
1250
////                                                              ////
1251
////  Author(s):                                                  ////
1252
////      - Michael Unneback, unneback@opencores.org              ////
1253
////        ORSoC AB                                              ////
1254
////                                                              ////
1255
//////////////////////////////////////////////////////////////////////
1256
////                                                              ////
1257
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1258
////                                                              ////
1259
//// This source file may be used and distributed without         ////
1260
//// restriction provided that this copyright statement is not    ////
1261
//// removed from the file and that any derivative work contains  ////
1262
//// the original copyright notice and the associated disclaimer. ////
1263
////                                                              ////
1264
//// This source file is free software; you can redistribute it   ////
1265
//// and/or modify it under the terms of the GNU Lesser General   ////
1266
//// Public License as published by the Free Software Foundation; ////
1267
//// either version 2.1 of the License, or (at your option) any   ////
1268
//// later version.                                               ////
1269
////                                                              ////
1270
//// This source is distributed in the hope that it will be       ////
1271
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1272
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1273
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1274
//// details.                                                     ////
1275
////                                                              ////
1276
//// You should have received a copy of the GNU Lesser General    ////
1277
//// Public License along with this source; if not, download it   ////
1278
//// from http://www.opencores.org/lgpl.shtml                     ////
1279
////                                                              ////
1280
//////////////////////////////////////////////////////////////////////
1281 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
1282 6 unneback
   parameter length = 4;
1283
   output reg [0:length-1] q;
1284
   input rst;
1285
   input clk;
1286
    always @ (posedge clk or posedge rst)
1287
    if (rst)
1288
        q <= {1'b1,{length-1{1'b0}}};
1289
    else
1290
        q <= {q[length-1],q[0:length-2]};
1291
endmodule
1292 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
1293 6 unneback
   parameter length = 4;
1294
   input cke;
1295
   output reg [0:length-1] q;
1296
   input rst;
1297
   input clk;
1298
    always @ (posedge clk or posedge rst)
1299
    if (rst)
1300
        q <= {1'b1,{length-1{1'b0}}};
1301
    else
1302
        if (cke)
1303
            q <= {q[length-1],q[0:length-2]};
1304
endmodule
1305 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1306 6 unneback
   parameter length = 4;
1307
   input cke, clear;
1308
   output reg [0:length-1] q;
1309
   input rst;
1310
   input clk;
1311
    always @ (posedge clk or posedge rst)
1312
    if (rst)
1313
        q <= {1'b1,{length-1{1'b0}}};
1314
    else
1315
        if (cke)
1316
            if (clear)
1317
                q <= {1'b1,{length-1{1'b0}}};
1318
            else
1319
                q <= q >> 1;
1320
endmodule
1321 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
1322 6 unneback
   parameter length = 4;
1323
   input cke, clear;
1324
   output reg [0:length-1] q;
1325
   input rst;
1326
   input clk;
1327
    always @ (posedge clk or posedge rst)
1328
    if (rst)
1329
        q <= {1'b1,{length-1{1'b0}}};
1330
    else
1331
        if (cke)
1332
            if (clear)
1333
                q <= {1'b1,{length-1{1'b0}}};
1334
            else
1335
            q <= {q[length-1],q[0:length-2]};
1336
endmodule
1337
//////////////////////////////////////////////////////////////////////
1338
////                                                              ////
1339
////  Versatile library, memories                                 ////
1340
////                                                              ////
1341
////  Description                                                 ////
1342
////  memories                                                    ////
1343
////                                                              ////
1344
////                                                              ////
1345
////  To Do:                                                      ////
1346
////   - add more memory types                                    ////
1347
////                                                              ////
1348
////  Author(s):                                                  ////
1349
////      - Michael Unneback, unneback@opencores.org              ////
1350
////        ORSoC AB                                              ////
1351
////                                                              ////
1352
//////////////////////////////////////////////////////////////////////
1353
////                                                              ////
1354
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1355
////                                                              ////
1356
//// This source file may be used and distributed without         ////
1357
//// restriction provided that this copyright statement is not    ////
1358
//// removed from the file and that any derivative work contains  ////
1359
//// the original copyright notice and the associated disclaimer. ////
1360
////                                                              ////
1361
//// This source file is free software; you can redistribute it   ////
1362
//// and/or modify it under the terms of the GNU Lesser General   ////
1363
//// Public License as published by the Free Software Foundation; ////
1364
//// either version 2.1 of the License, or (at your option) any   ////
1365
//// later version.                                               ////
1366
////                                                              ////
1367
//// This source is distributed in the hope that it will be       ////
1368
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1369
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1370
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1371
//// details.                                                     ////
1372
////                                                              ////
1373
//// You should have received a copy of the GNU Lesser General    ////
1374
//// Public License along with this source; if not, download it   ////
1375
//// from http://www.opencores.org/lgpl.shtml                     ////
1376
////                                                              ////
1377
//////////////////////////////////////////////////////////////////////
1378
/// ROM
1379 7 unneback
module vl_rom_init ( adr, q, clk);
1380
   parameter data_width = 32;
1381
   parameter addr_width = 8;
1382 75 unneback
   parameter mem_size = 1<<addr_width;
1383 7 unneback
   input [(addr_width-1):0]       adr;
1384
   output reg [(data_width-1):0] q;
1385
   input                         clk;
1386 75 unneback
   reg [data_width-1:0] rom [mem_size-1:0];
1387 7 unneback
   parameter memory_file = "vl_rom.vmem";
1388
   initial
1389
     begin
1390
        $readmemh(memory_file, rom);
1391
     end
1392
   always @ (posedge clk)
1393
     q <= rom[adr];
1394
endmodule
1395 6 unneback
// Single port RAM
1396
module vl_ram ( d, adr, we, q, clk);
1397
   parameter data_width = 32;
1398
   parameter addr_width = 8;
1399 75 unneback
   parameter mem_size = 1<<addr_width;
1400 6 unneback
   input [(data_width-1):0]      d;
1401
   input [(addr_width-1):0]       adr;
1402
   input                         we;
1403 7 unneback
   output reg [(data_width-1):0] q;
1404 6 unneback
   input                         clk;
1405 75 unneback
   reg [data_width-1:0] ram [mem_szie-1:0];
1406 7 unneback
   parameter init = 0;
1407
   parameter memory_file = "vl_ram.vmem";
1408
   generate if (init) begin : init_mem
1409
   initial
1410
     begin
1411
        $readmemh(memory_file, ram);
1412
     end
1413
   end
1414
   endgenerate
1415 6 unneback
   always @ (posedge clk)
1416
   begin
1417
   if (we)
1418
     ram[adr] <= d;
1419
   q <= ram[adr];
1420
   end
1421
endmodule
1422 91 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
1423 7 unneback
   parameter data_width = 32;
1424 72 unneback
   parameter addr_width = 6;
1425 75 unneback
   parameter mem_size = 1<<addr_width;
1426 7 unneback
   input [(data_width-1):0]      d;
1427
   input [(addr_width-1):0]       adr;
1428 73 unneback
   input [(data_width/8)-1:0]    be;
1429 7 unneback
   input                         we;
1430
   output reg [(data_width-1):0] q;
1431
   input                         clk;
1432 65 unneback
`ifdef SYSTEMVERILOG
1433 68 unneback
   logic [data_width/8-1:0][7:0] ram[0:mem_size-1];// # words = 1 << address width
1434 65 unneback
`else
1435 85 unneback
    reg [data_width-1:0] ram [mem_size-1:0];
1436
    wire [data_width/8-1:0] cke;
1437 65 unneback
`endif
1438 60 unneback
   parameter memory_init = 0;
1439 7 unneback
   parameter memory_file = "vl_ram.vmem";
1440 60 unneback
   generate if (memory_init) begin : init_mem
1441 7 unneback
   initial
1442
     begin
1443
        $readmemh(memory_file, ram);
1444
     end
1445
   end
1446
   endgenerate
1447 60 unneback
`ifdef SYSTEMVERILOG
1448
// use a multi-dimensional packed array
1449
//to model individual bytes within the word
1450
always_ff@(posedge clk)
1451
begin
1452
    if(we) begin // note: we should have a for statement to support any bus width
1453 86 unneback
        if(be[3]) ram[adr][3] <= d[31:24];
1454
        if(be[2]) ram[adr][2] <= d[23:16];
1455
        if(be[1]) ram[adr][1] <= d[15:8];
1456
        if(be[0]) ram[adr][0] <= d[7:0];
1457 60 unneback
    end
1458 90 unneback
        q <= ram[adr];
1459 60 unneback
end
1460
`else
1461 85 unneback
assign cke = {data_width/8{we}} & be;
1462 7 unneback
   genvar i;
1463 85 unneback
   generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
1464 7 unneback
      always @ (posedge clk)
1465 85 unneback
      if (cke[i])
1466 7 unneback
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
1467
   end
1468
   endgenerate
1469
   always @ (posedge clk)
1470
      q <= ram[adr];
1471 60 unneback
`endif
1472 93 unneback
`ifdef verilator
1473 85 unneback
   // Function to access RAM (for use by Verilator).
1474
   function [31:0] get_mem;
1475
      // verilator public
1476 90 unneback
      input [addr_width-1:0]             addr;
1477 85 unneback
      get_mem = ram[addr];
1478
   endfunction // get_mem
1479
   // Function to write RAM (for use by Verilator).
1480
   function set_mem;
1481
      // verilator public
1482 90 unneback
      input [addr_width-1:0]             addr;
1483
      input [data_width-1:0]             data;
1484 85 unneback
      ram[addr] = data;
1485
   endfunction // set_mem
1486 93 unneback
`endif
1487 7 unneback
endmodule
1488
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1489 6 unneback
   parameter data_width = 32;
1490
   parameter addr_width = 8;
1491 75 unneback
   parameter mem_size = 1<<addr_width;
1492 6 unneback
   input [(data_width-1):0]      d_a;
1493
   input [(addr_width-1):0]       adr_a;
1494
   input [(addr_width-1):0]       adr_b;
1495
   input                         we_a;
1496
   output [(data_width-1):0]      q_b;
1497
   input                         clk_a, clk_b;
1498
   reg [(addr_width-1):0]         adr_b_reg;
1499 75 unneback
   reg [data_width-1:0] ram [mem_szie-1:0] ;
1500 7 unneback
   parameter init = 0;
1501
   parameter memory_file = "vl_ram.vmem";
1502
   generate if (init) begin : init_mem
1503
   initial
1504
     begin
1505
        $readmemh(memory_file, ram);
1506
     end
1507
   end
1508
   endgenerate
1509 6 unneback
   always @ (posedge clk_a)
1510
   if (we_a)
1511
     ram[adr_a] <= d_a;
1512
   always @ (posedge clk_b)
1513
   adr_b_reg <= adr_b;
1514
   assign q_b = ram[adr_b_reg];
1515
endmodule
1516 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1517 6 unneback
   parameter data_width = 32;
1518
   parameter addr_width = 8;
1519 75 unneback
   parameter mem_size = 1<<addr_width;
1520 6 unneback
   input [(data_width-1):0]      d_a;
1521
   input [(addr_width-1):0]       adr_a;
1522
   input [(addr_width-1):0]       adr_b;
1523
   input                         we_a;
1524
   output [(data_width-1):0]      q_b;
1525
   output reg [(data_width-1):0] q_a;
1526
   input                         clk_a, clk_b;
1527
   reg [(data_width-1):0]         q_b;
1528 75 unneback
   reg [data_width-1:0] ram [mem_szie-1:0] ;
1529 7 unneback
   parameter init = 0;
1530
   parameter memory_file = "vl_ram.vmem";
1531
   generate if (init) begin : init_mem
1532
   initial
1533
     begin
1534
        $readmemh(memory_file, ram);
1535
     end
1536
   end
1537
   endgenerate
1538 6 unneback
   always @ (posedge clk_a)
1539
     begin
1540
        q_a <= ram[adr_a];
1541
        if (we_a)
1542
             ram[adr_a] <= d_a;
1543
     end
1544
   always @ (posedge clk_b)
1545
          q_b <= ram[adr_b];
1546
endmodule
1547 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
1548 6 unneback
   parameter data_width = 32;
1549
   parameter addr_width = 8;
1550 75 unneback
   parameter mem_size = 1<<addr_width;
1551 6 unneback
   input [(data_width-1):0]      d_a;
1552
   input [(addr_width-1):0]       adr_a;
1553
   input [(addr_width-1):0]       adr_b;
1554
   input                         we_a;
1555
   output [(data_width-1):0]      q_b;
1556
   input [(data_width-1):0]       d_b;
1557
   output reg [(data_width-1):0] q_a;
1558
   input                         we_b;
1559
   input                         clk_a, clk_b;
1560
   reg [(data_width-1):0]         q_b;
1561 75 unneback
   reg [data_width-1:0] ram [mem_size-1:0] ;
1562 7 unneback
   parameter init = 0;
1563
   parameter memory_file = "vl_ram.vmem";
1564
   generate if (init) begin : init_mem
1565
   initial
1566
     begin
1567
        $readmemh(memory_file, ram);
1568
     end
1569
   end
1570
   endgenerate
1571 6 unneback
   always @ (posedge clk_a)
1572
     begin
1573
        q_a <= ram[adr_a];
1574
        if (we_a)
1575
             ram[adr_a] <= d_a;
1576
     end
1577
   always @ (posedge clk_b)
1578
     begin
1579
        q_b <= ram[adr_b];
1580
        if (we_b)
1581
          ram[adr_b] <= d_b;
1582
     end
1583
endmodule
1584 92 unneback
module vl_dpram_be_2r2w ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
1585 75 unneback
   parameter a_data_width = 32;
1586
   parameter a_addr_width = 8;
1587 92 unneback
   parameter b_data_width = a_data_width;
1588 91 unneback
   localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
1589
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<a_addr_width) : (1<<b_addr_width);
1590 75 unneback
   input [(a_data_width-1):0]      d_a;
1591 91 unneback
   input [(a_addr_width-1):0]       adr_a;
1592
   input [(a_data_width/8-1):0]    be_a;
1593
   input                           we_a;
1594 75 unneback
   output reg [(a_data_width-1):0] q_a;
1595 91 unneback
   input [(b_data_width-1):0]       d_b;
1596
   input [(b_addr_width-1):0]       adr_b;
1597 92 unneback
   input [(b_data_width/8-1):0]    be_b;
1598
   input                           we_b;
1599
   output reg [(b_data_width-1):0]          q_b;
1600 91 unneback
   input                           clk_a, clk_b;
1601
`ifdef SYSTEMVERILOG
1602
// use a multi-dimensional packed array
1603
//to model individual bytes within the word
1604 75 unneback
generate
1605 91 unneback
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
1606
   logic [3:0][7:0] ram [0:mem_size-1];
1607
    always_ff@(posedge clk_a)
1608
    begin
1609
        if(we_a) begin
1610
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
1611
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
1612
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
1613
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
1614
        end
1615
    end
1616 92 unneback
    always@(posedge clk_a)
1617
        q_a = ram[adr_a];
1618 91 unneback
    always_ff@(posedge clk_b)
1619 92 unneback
    begin
1620
        if(we_b) begin
1621
            if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
1622
            if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
1623
            if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
1624
            if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
1625
        end
1626
    end
1627
    always@(posedge clk_b)
1628
        q_b = ram[adr_b];
1629 75 unneback
end
1630
endgenerate
1631 91 unneback
`else
1632 92 unneback
    // This modules requires SystemVerilog
1633 91 unneback
`endif
1634 75 unneback
endmodule
1635 6 unneback
// FIFO
1636 25 unneback
module vl_fifo_1r1w_fill_level_sync (
1637
    d, wr, fifo_full,
1638
    q, rd, fifo_empty,
1639
    fill_level,
1640
    clk, rst
1641
    );
1642
parameter data_width = 18;
1643
parameter addr_width = 4;
1644
// write side
1645
input  [data_width-1:0] d;
1646
input                   wr;
1647
output                  fifo_full;
1648
// read side
1649
output [data_width-1:0] q;
1650
input                   rd;
1651
output                  fifo_empty;
1652
// common
1653
output [addr_width:0]   fill_level;
1654
input rst, clk;
1655
wire [addr_width:1] wadr, radr;
1656
vl_cnt_bin_ce
1657
    # ( .length(addr_width))
1658
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
1659
vl_cnt_bin_ce
1660
    # (.length(addr_width))
1661
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
1662
vl_dpram_1r1w
1663
    # (.data_width(data_width), .addr_width(addr_width))
1664
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
1665 31 unneback
vl_cnt_bin_ce_rew_q_zq_l1
1666 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
1667 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
1668
endmodule
1669 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
1670
// RAM is supposed to be larger than the two FIFOs
1671
// LFSR counters used adr pointers
1672
module vl_fifo_2r2w_sync_simplex (
1673
    // a side
1674
    a_d, a_wr, a_fifo_full,
1675
    a_q, a_rd, a_fifo_empty,
1676
    a_fill_level,
1677
    // b side
1678
    b_d, b_wr, b_fifo_full,
1679
    b_q, b_rd, b_fifo_empty,
1680
    b_fill_level,
1681
    // common
1682
    clk, rst
1683
    );
1684
parameter data_width = 8;
1685
parameter addr_width = 5;
1686
parameter fifo_full_level = (1<<addr_width)-1;
1687
// a side
1688
input  [data_width-1:0] a_d;
1689
input                   a_wr;
1690
output                  a_fifo_full;
1691
output [data_width-1:0] a_q;
1692
input                   a_rd;
1693
output                  a_fifo_empty;
1694
output [addr_width-1:0] a_fill_level;
1695
// b side
1696
input  [data_width-1:0] b_d;
1697
input                   b_wr;
1698
output                  b_fifo_full;
1699
output [data_width-1:0] b_q;
1700
input                   b_rd;
1701
output                  b_fifo_empty;
1702
output [addr_width-1:0] b_fill_level;
1703
input                   clk;
1704
input                   rst;
1705
// adr_gen
1706
wire [addr_width:1] a_wadr, a_radr;
1707
wire [addr_width:1] b_wadr, b_radr;
1708
// dpram
1709
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1710
vl_cnt_lfsr_ce
1711
    # ( .length(addr_width))
1712
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
1713
vl_cnt_lfsr_ce
1714
    # (.length(addr_width))
1715
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
1716
vl_cnt_lfsr_ce
1717
    # ( .length(addr_width))
1718
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
1719
vl_cnt_lfsr_ce
1720
    # (.length(addr_width))
1721
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
1722
// mux read or write adr to DPRAM
1723
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
1724
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
1725
vl_dpram_2r2w
1726
    # (.data_width(data_width), .addr_width(addr_width+1))
1727
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1728
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1729
vl_cnt_bin_ce_rew_zq_l1
1730 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
1731 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
1732
vl_cnt_bin_ce_rew_zq_l1
1733 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
1734 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
1735
endmodule
1736 6 unneback
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
1737 11 unneback
   parameter addr_width = 4;
1738
   parameter N = addr_width-1;
1739 6 unneback
   parameter Q1 = 2'b00;
1740
   parameter Q2 = 2'b01;
1741
   parameter Q3 = 2'b11;
1742
   parameter Q4 = 2'b10;
1743
   parameter going_empty = 1'b0;
1744
   parameter going_full  = 1'b1;
1745
   input [N:0]  wptr, rptr;
1746 14 unneback
   output       fifo_empty;
1747 6 unneback
   output       fifo_full;
1748
   input        wclk, rclk, rst;
1749
   wire direction;
1750
   reg  direction_set, direction_clr;
1751
   wire async_empty, async_full;
1752
   wire fifo_full2;
1753 14 unneback
   wire fifo_empty2;
1754 6 unneback
   // direction_set
1755
   always @ (wptr[N:N-1] or rptr[N:N-1])
1756
     case ({wptr[N:N-1],rptr[N:N-1]})
1757
       {Q1,Q2} : direction_set <= 1'b1;
1758
       {Q2,Q3} : direction_set <= 1'b1;
1759
       {Q3,Q4} : direction_set <= 1'b1;
1760
       {Q4,Q1} : direction_set <= 1'b1;
1761
       default : direction_set <= 1'b0;
1762
     endcase
1763
   // direction_clear
1764
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
1765
     if (rst)
1766
       direction_clr <= 1'b1;
1767
     else
1768
       case ({wptr[N:N-1],rptr[N:N-1]})
1769
         {Q2,Q1} : direction_clr <= 1'b1;
1770
         {Q3,Q2} : direction_clr <= 1'b1;
1771
         {Q4,Q3} : direction_clr <= 1'b1;
1772
         {Q1,Q4} : direction_clr <= 1'b1;
1773
         default : direction_clr <= 1'b0;
1774
       endcase
1775 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
1776 6 unneback
   assign async_empty = (wptr == rptr) && (direction==going_empty);
1777
   assign async_full  = (wptr == rptr) && (direction==going_full);
1778 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
1779
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
1780 6 unneback
/*
1781
   always @ (posedge wclk or posedge rst or posedge async_full)
1782
     if (rst)
1783
       {fifo_full, fifo_full2} <= 2'b00;
1784
     else if (async_full)
1785
       {fifo_full, fifo_full2} <= 2'b11;
1786
     else
1787
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
1788
*/
1789 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
1790 6 unneback
     if (async_empty)
1791
       {fifo_empty, fifo_empty2} <= 2'b11;
1792
     else
1793 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
1794 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
1795
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
1796 27 unneback
endmodule // async_compb
1797 6 unneback
module vl_fifo_1r1w_async (
1798
    d, wr, fifo_full, wr_clk, wr_rst,
1799
    q, rd, fifo_empty, rd_clk, rd_rst
1800
    );
1801
parameter data_width = 18;
1802
parameter addr_width = 4;
1803
// write side
1804
input  [data_width-1:0] d;
1805
input                   wr;
1806
output                  fifo_full;
1807
input                   wr_clk;
1808
input                   wr_rst;
1809
// read side
1810
output [data_width-1:0] q;
1811
input                   rd;
1812
output                  fifo_empty;
1813
input                   rd_clk;
1814
input                   rd_rst;
1815
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
1816 18 unneback
vl_cnt_gray_ce_bin
1817 6 unneback
    # ( .length(addr_width))
1818
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
1819 18 unneback
vl_cnt_gray_ce_bin
1820 6 unneback
    # (.length(addr_width))
1821 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
1822 7 unneback
vl_dpram_1r1w
1823 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
1824
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
1825
vl_fifo_cmp_async
1826
    # (.addr_width(addr_width))
1827
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
1828
endmodule
1829 8 unneback
module vl_fifo_2r2w_async (
1830 6 unneback
    // a side
1831
    a_d, a_wr, a_fifo_full,
1832
    a_q, a_rd, a_fifo_empty,
1833
    a_clk, a_rst,
1834
    // b side
1835
    b_d, b_wr, b_fifo_full,
1836
    b_q, b_rd, b_fifo_empty,
1837
    b_clk, b_rst
1838
    );
1839
parameter data_width = 18;
1840
parameter addr_width = 4;
1841
// a side
1842
input  [data_width-1:0] a_d;
1843
input                   a_wr;
1844
output                  a_fifo_full;
1845
output [data_width-1:0] a_q;
1846
input                   a_rd;
1847
output                  a_fifo_empty;
1848
input                   a_clk;
1849
input                   a_rst;
1850
// b side
1851
input  [data_width-1:0] b_d;
1852
input                   b_wr;
1853
output                  b_fifo_full;
1854
output [data_width-1:0] b_q;
1855
input                   b_rd;
1856
output                  b_fifo_empty;
1857
input                   b_clk;
1858
input                   b_rst;
1859
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1860
vl_fifo_1r1w_async_a (
1861
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
1862
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
1863
    );
1864
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1865
vl_fifo_1r1w_async_b (
1866
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
1867
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
1868
    );
1869
endmodule
1870 8 unneback
module vl_fifo_2r2w_async_simplex (
1871 6 unneback
    // a side
1872
    a_d, a_wr, a_fifo_full,
1873
    a_q, a_rd, a_fifo_empty,
1874
    a_clk, a_rst,
1875
    // b side
1876
    b_d, b_wr, b_fifo_full,
1877
    b_q, b_rd, b_fifo_empty,
1878
    b_clk, b_rst
1879
    );
1880
parameter data_width = 18;
1881
parameter addr_width = 4;
1882
// a side
1883
input  [data_width-1:0] a_d;
1884
input                   a_wr;
1885
output                  a_fifo_full;
1886
output [data_width-1:0] a_q;
1887
input                   a_rd;
1888
output                  a_fifo_empty;
1889
input                   a_clk;
1890
input                   a_rst;
1891
// b side
1892
input  [data_width-1:0] b_d;
1893
input                   b_wr;
1894
output                  b_fifo_full;
1895
output [data_width-1:0] b_q;
1896
input                   b_rd;
1897
output                  b_fifo_empty;
1898
input                   b_clk;
1899
input                   b_rst;
1900
// adr_gen
1901
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
1902
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
1903
// dpram
1904
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1905 18 unneback
vl_cnt_gray_ce_bin
1906 6 unneback
    # ( .length(addr_width))
1907
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
1908 18 unneback
vl_cnt_gray_ce_bin
1909 6 unneback
    # (.length(addr_width))
1910
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
1911 18 unneback
vl_cnt_gray_ce_bin
1912 6 unneback
    # ( .length(addr_width))
1913
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
1914 18 unneback
vl_cnt_gray_ce_bin
1915 6 unneback
    # (.length(addr_width))
1916
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
1917
// mux read or write adr to DPRAM
1918
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
1919
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
1920 11 unneback
vl_dpram_2r2w
1921 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
1922
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1923
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1924 11 unneback
vl_fifo_cmp_async
1925 6 unneback
    # (.addr_width(addr_width))
1926
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
1927 11 unneback
vl_fifo_cmp_async
1928 6 unneback
    # (.addr_width(addr_width))
1929
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
1930
endmodule
1931 48 unneback
module vl_reg_file (
1932
    a1, a2, a3, wd3, we3, rd1, rd2, clk
1933
);
1934
parameter data_width = 32;
1935
parameter addr_width = 5;
1936
input [addr_width-1:0] a1, a2, a3;
1937
input [data_width-1:0] wd3;
1938
input we3;
1939
output [data_width-1:0] rd1, rd2;
1940
input clk;
1941
vl_dpram_1r1w
1942
    # ( .data_width(data_width), .addr_width(addr_width))
1943
    ram1 (
1944
        .d_a(wd3),
1945
        .adr_a(a3),
1946
        .we_a(we3),
1947
        .clk_a(clk),
1948
        .q_b(rd1),
1949
        .adr_b(a1),
1950
        .clk_b(clk) );
1951
vl_dpram_1r1w
1952
    # ( .data_width(data_width), .addr_width(addr_width))
1953
    ram2 (
1954
        .d_a(wd3),
1955
        .adr_a(a3),
1956
        .we_a(we3),
1957
        .clk_a(clk),
1958
        .q_b(rd2),
1959
        .adr_b(a2),
1960
        .clk_b(clk) );
1961
endmodule
1962 12 unneback
//////////////////////////////////////////////////////////////////////
1963
////                                                              ////
1964
////  Versatile library, wishbone stuff                           ////
1965
////                                                              ////
1966
////  Description                                                 ////
1967
////  Wishbone compliant modules                                  ////
1968
////                                                              ////
1969
////                                                              ////
1970
////  To Do:                                                      ////
1971
////   -                                                          ////
1972
////                                                              ////
1973
////  Author(s):                                                  ////
1974
////      - Michael Unneback, unneback@opencores.org              ////
1975
////        ORSoC AB                                              ////
1976
////                                                              ////
1977
//////////////////////////////////////////////////////////////////////
1978
////                                                              ////
1979
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1980
////                                                              ////
1981
//// This source file may be used and distributed without         ////
1982
//// restriction provided that this copyright statement is not    ////
1983
//// removed from the file and that any derivative work contains  ////
1984
//// the original copyright notice and the associated disclaimer. ////
1985
////                                                              ////
1986
//// This source file is free software; you can redistribute it   ////
1987
//// and/or modify it under the terms of the GNU Lesser General   ////
1988
//// Public License as published by the Free Software Foundation; ////
1989
//// either version 2.1 of the License, or (at your option) any   ////
1990
//// later version.                                               ////
1991
////                                                              ////
1992
//// This source is distributed in the hope that it will be       ////
1993
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1994
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1995
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1996
//// details.                                                     ////
1997
////                                                              ////
1998
//// You should have received a copy of the GNU Lesser General    ////
1999
//// Public License along with this source; if not, download it   ////
2000
//// from http://www.opencores.org/lgpl.shtml                     ////
2001
////                                                              ////
2002
//////////////////////////////////////////////////////////////////////
2003
// async wb3 - wb3 bridge
2004
`timescale 1ns/1ns
2005 85 unneback
module vl_wb_adr_inc ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
2006 83 unneback
parameter adr_width = 10;
2007
parameter max_burst_width = 4;
2008 85 unneback
input cyc_i, stb_i, we_i;
2009 83 unneback
input [2:0] cti_i;
2010
input [1:0] bte_i;
2011
input [adr_width-1:0] adr_i;
2012
output [adr_width-1:0] adr_o;
2013
output ack_o;
2014
input clk, rst;
2015
reg [adr_width-1:0] adr;
2016 90 unneback
wire [max_burst_width-1:0] to_adr;
2017 91 unneback
reg [max_burst_width-1:0] last_adr;
2018 92 unneback
reg last_cycle;
2019
localparam idle_or_eoc = 1'b0;
2020
localparam cyc_or_ws   = 1'b1;
2021 91 unneback
always @ (posedge clk or posedge rst)
2022
if (rst)
2023
    last_adr <= {max_burst_width{1'b0}};
2024
else
2025
    if (stb_i)
2026 92 unneback
        last_adr <=adr_o[max_burst_width-1:0];
2027 83 unneback
generate
2028
if (max_burst_width==0) begin : inst_0
2029
    reg ack_o;
2030
    assign adr_o = adr_i;
2031
    always @ (posedge clk or posedge rst)
2032
    if (rst)
2033
        ack_o <= 1'b0;
2034
    else
2035
        ack_o <= cyc_i & stb_i & !ack_o;
2036
end else begin
2037
    always @ (posedge clk or posedge rst)
2038
    if (rst)
2039 92 unneback
        last_cycle <= idle_or_eoc;
2040 83 unneback
    else
2041 92 unneback
        last_cycle <= (!cyc_i) ? idle_or_eoc : //idle
2042
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? idle_or_eoc : // eoc
2043
                      (cyc_i & !stb_i) ? cyc_or_ws : //ws
2044
                      cyc_or_ws; // cyc
2045
    assign to_adr = (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
2046 85 unneback
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
2047 91 unneback
                                        (!stb_i) ? last_adr :
2048 92 unneback
                                        (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] :
2049 85 unneback
                                        adr[max_burst_width-1:0];
2050 92 unneback
    assign ack_o = (last_cycle==cyc_or_ws) & stb_i;
2051 83 unneback
end
2052
endgenerate
2053
generate
2054
if (max_burst_width==2) begin : inst_2
2055
    always @ (posedge clk or posedge rst)
2056
    if (rst)
2057
        adr <= 2'h0;
2058
    else
2059
        if (cyc_i & stb_i)
2060
            adr[1:0] <= to_adr[1:0] + 2'd1;
2061
        else
2062
            adr <= to_adr[1:0];
2063
end
2064
endgenerate
2065
generate
2066
if (max_burst_width==3) begin : inst_3
2067
    always @ (posedge clk or posedge rst)
2068
    if (rst)
2069
        adr <= 3'h0;
2070
    else
2071
        if (cyc_i & stb_i)
2072
            case (bte_i)
2073
            2'b01: adr[2:0] <= {to_adr[2],to_adr[1:0] + 2'd1};
2074
            default: adr[3:0] <= to_adr[2:0] + 3'd1;
2075
            endcase
2076
        else
2077
            adr <= to_adr[2:0];
2078
end
2079
endgenerate
2080
generate
2081
if (max_burst_width==4) begin : inst_4
2082
    always @ (posedge clk or posedge rst)
2083
    if (rst)
2084
        adr <= 4'h0;
2085
    else
2086 91 unneback
        if (stb_i) // | (!stb_i & last_cycle!=ws)) // for !stb_i restart with adr_i +1, only inc once
2087 83 unneback
            case (bte_i)
2088
            2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
2089
            2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
2090
            default: adr[3:0] <= to_adr + 4'd1;
2091
            endcase
2092
        else
2093
            adr <= to_adr[3:0];
2094
end
2095
endgenerate
2096
generate
2097
if (adr_width > max_burst_width) begin : pass_through
2098
    assign adr_o[adr_width-1:max_burst_width] = adr_i[adr_width-1:max_burst_width];
2099
end
2100
endgenerate
2101
endmodule
2102
// async wb3 - wb3 bridge
2103
`timescale 1ns/1ns
2104 18 unneback
module vl_wb3wb3_bridge (
2105 12 unneback
        // wishbone slave side
2106
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
2107
        // wishbone master side
2108
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
2109
input [31:0] wbs_dat_i;
2110
input [31:2] wbs_adr_i;
2111
input [3:0]  wbs_sel_i;
2112
input [1:0]  wbs_bte_i;
2113
input [2:0]  wbs_cti_i;
2114
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
2115
output [31:0] wbs_dat_o;
2116 14 unneback
output wbs_ack_o;
2117 12 unneback
input wbs_clk, wbs_rst;
2118
output [31:0] wbm_dat_o;
2119
output reg [31:2] wbm_adr_o;
2120
output [3:0]  wbm_sel_o;
2121
output reg [1:0]  wbm_bte_o;
2122
output reg [2:0]  wbm_cti_o;
2123 14 unneback
output reg wbm_we_o;
2124
output wbm_cyc_o;
2125 12 unneback
output wbm_stb_o;
2126
input [31:0]  wbm_dat_i;
2127
input wbm_ack_i;
2128
input wbm_clk, wbm_rst;
2129
parameter addr_width = 4;
2130
// bte
2131
parameter linear       = 2'b00;
2132
parameter wrap4        = 2'b01;
2133
parameter wrap8        = 2'b10;
2134
parameter wrap16       = 2'b11;
2135
// cti
2136
parameter classic      = 3'b000;
2137
parameter incburst     = 3'b010;
2138
parameter endofburst   = 3'b111;
2139
parameter wbs_adr  = 1'b0;
2140
parameter wbs_data = 1'b1;
2141 33 unneback
parameter wbm_adr0      = 2'b00;
2142
parameter wbm_adr1      = 2'b01;
2143
parameter wbm_data      = 2'b10;
2144
parameter wbm_data_wait = 2'b11;
2145 12 unneback
reg [1:0] wbs_bte_reg;
2146
reg wbs;
2147
wire wbs_eoc_alert, wbm_eoc_alert;
2148
reg wbs_eoc, wbm_eoc;
2149
reg [1:0] wbm;
2150 14 unneback
wire [1:16] wbs_count, wbm_count;
2151 12 unneback
wire [35:0] a_d, a_q, b_d, b_q;
2152
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
2153
reg a_rd_reg;
2154
wire b_rd_adr, b_rd_data;
2155 14 unneback
wire b_rd_data_reg;
2156
wire [35:0] temp;
2157 12 unneback
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
2158
always @ (posedge wbs_clk or posedge wbs_rst)
2159
if (wbs_rst)
2160
        wbs_eoc <= 1'b0;
2161
else
2162
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
2163 78 unneback
                wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111);
2164 12 unneback
        else if (wbs_eoc_alert & (a_rd | a_wr))
2165
                wbs_eoc <= 1'b1;
2166 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
2167 12 unneback
    cnt0 (
2168
        .cke(wbs_ack_o),
2169
        .clear(wbs_eoc),
2170
        .q(wbs_count),
2171
        .rst(wbs_rst),
2172
        .clk(wbs_clk));
2173
always @ (posedge wbs_clk or posedge wbs_rst)
2174
if (wbs_rst)
2175
        wbs <= wbs_adr;
2176
else
2177 75 unneback
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)
2178 12 unneback
                wbs <= wbs_data;
2179
        else if (wbs_eoc & wbs_ack_o)
2180
                wbs <= wbs_adr;
2181
// wbs FIFO
2182 75 unneback
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};
2183
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :
2184 12 unneback
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
2185
              1'b0;
2186
assign a_rd = !a_fifo_empty;
2187
always @ (posedge wbs_clk or posedge wbs_rst)
2188
if (wbs_rst)
2189
        a_rd_reg <= 1'b0;
2190
else
2191
        a_rd_reg <= a_rd;
2192
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
2193
assign wbs_dat_o = a_q[35:4];
2194
always @ (posedge wbs_clk or posedge wbs_rst)
2195
if (wbs_rst)
2196 13 unneback
        wbs_bte_reg <= 2'b00;
2197 12 unneback
else
2198 13 unneback
        wbs_bte_reg <= wbs_bte_i;
2199 12 unneback
// wbm FIFO
2200
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
2201
always @ (posedge wbm_clk or posedge wbm_rst)
2202
if (wbm_rst)
2203
        wbm_eoc <= 1'b0;
2204
else
2205
        if (wbm==wbm_adr0 & !b_fifo_empty)
2206
                wbm_eoc <= b_q[4:3] == linear;
2207
        else if (wbm_eoc_alert & wbm_ack_i)
2208
                wbm_eoc <= 1'b1;
2209
always @ (posedge wbm_clk or posedge wbm_rst)
2210
if (wbm_rst)
2211
        wbm <= wbm_adr0;
2212
else
2213 33 unneback
/*
2214 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
2215
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
2216
        (wbm==wbm_adr1 & !wbm_we_o) |
2217
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
2218
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
2219 33 unneback
*/
2220
    case (wbm)
2221
    wbm_adr0:
2222
        if (!b_fifo_empty)
2223
            wbm <= wbm_adr1;
2224
    wbm_adr1:
2225
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
2226
            wbm <= wbm_data;
2227
    wbm_data:
2228
        if (wbm_ack_i & wbm_eoc)
2229
            wbm <= wbm_adr0;
2230
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
2231
            wbm <= wbm_data_wait;
2232
    wbm_data_wait:
2233
        if (!b_fifo_empty)
2234
            wbm <= wbm_data;
2235
    endcase
2236 12 unneback
assign b_d = {wbm_dat_i,4'b1111};
2237
assign b_wr = !wbm_we_o & wbm_ack_i;
2238
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
2239
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
2240
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
2241 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
2242 12 unneback
                   1'b0;
2243
assign b_rd = b_rd_adr | b_rd_data;
2244 18 unneback
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
2245
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
2246 12 unneback
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
2247 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
2248 12 unneback
    cnt1 (
2249
        .cke(wbm_ack_i),
2250
        .clear(wbm_eoc),
2251
        .q(wbm_count),
2252
        .rst(wbm_rst),
2253
        .clk(wbm_clk));
2254 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
2255
assign wbm_stb_o = (wbm==wbm_data);
2256 12 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
2257
if (wbm_rst)
2258
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
2259
else begin
2260
        if (wbm==wbm_adr0 & !b_fifo_empty)
2261
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
2262
        else if (wbm_eoc_alert & wbm_ack_i)
2263
                wbm_cti_o <= endofburst;
2264
end
2265
//async_fifo_dw_simplex_top
2266
vl_fifo_2r2w_async_simplex
2267
# ( .data_width(36), .addr_width(addr_width))
2268
fifo (
2269
    // a side
2270
    .a_d(a_d),
2271
    .a_wr(a_wr),
2272
    .a_fifo_full(a_fifo_full),
2273
    .a_q(a_q),
2274
    .a_rd(a_rd),
2275
    .a_fifo_empty(a_fifo_empty),
2276
    .a_clk(wbs_clk),
2277
    .a_rst(wbs_rst),
2278
    // b side
2279
    .b_d(b_d),
2280
    .b_wr(b_wr),
2281
    .b_fifo_full(b_fifo_full),
2282
    .b_q(b_q),
2283
    .b_rd(b_rd),
2284
    .b_fifo_empty(b_fifo_empty),
2285
    .b_clk(wbm_clk),
2286
    .b_rst(wbm_rst)
2287
    );
2288
endmodule
2289 75 unneback
module vl_wb3avalon_bridge (
2290
        // wishbone slave side
2291
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
2292 77 unneback
        // avalon master side
2293 75 unneback
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
2294 85 unneback
parameter linewrapburst = 1'b0;
2295 75 unneback
input [31:0] wbs_dat_i;
2296
input [31:2] wbs_adr_i;
2297
input [3:0]  wbs_sel_i;
2298
input [1:0]  wbs_bte_i;
2299
input [2:0]  wbs_cti_i;
2300 83 unneback
input wbs_we_i;
2301
input wbs_cyc_i;
2302
input wbs_stb_i;
2303 75 unneback
output [31:0] wbs_dat_o;
2304
output wbs_ack_o;
2305
input wbs_clk, wbs_rst;
2306
input [31:0] readdata;
2307
output [31:0] writedata;
2308
output [31:2] address;
2309
output [3:0]  be;
2310
output write;
2311 81 unneback
output read;
2312 75 unneback
output beginbursttransfer;
2313
output [3:0] burstcount;
2314
input readdatavalid;
2315
input waitrequest;
2316
input clk;
2317
input rst;
2318
wire [1:0] wbm_bte_o;
2319
wire [2:0] wbm_cti_o;
2320
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
2321
reg last_cyc;
2322 79 unneback
reg [3:0] counter;
2323 82 unneback
reg read_busy;
2324 75 unneback
always @ (posedge clk or posedge rst)
2325
if (rst)
2326
    last_cyc <= 1'b0;
2327
else
2328
    last_cyc <= wbm_cyc_o;
2329 79 unneback
always @ (posedge clk or posedge rst)
2330
if (rst)
2331 82 unneback
    read_busy <= 1'b0;
2332 79 unneback
else
2333 82 unneback
    if (read & !waitrequest)
2334
        read_busy <= 1'b1;
2335
    else if (wbm_ack_i & wbm_cti_o!=3'b010)
2336
        read_busy <= 1'b0;
2337
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;
2338 75 unneback
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
2339
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
2340
                    (wbm_bte_o==2'b10) ? 4'd8 :
2341 78 unneback
                    (wbm_bte_o==2'b11) ? 4'd16:
2342
                    4'd1;
2343 82 unneback
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);
2344 79 unneback
always @ (posedge clk or posedge rst)
2345
if (rst) begin
2346
    counter <= 4'd0;
2347
end else
2348 80 unneback
    if (wbm_we_o) begin
2349
        if (!waitrequest & !last_cyc & wbm_cyc_o) begin
2350 85 unneback
            counter <= burstcount -4'd1;
2351 80 unneback
        end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
2352
            counter <= burstcount;
2353
        end else if (!waitrequest & wbm_stb_o) begin
2354
            counter <= counter - 4'd1;
2355
        end
2356 82 unneback
    end
2357 81 unneback
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
2358 77 unneback
vl_wb3wb3_bridge wbwb3inst (
2359 75 unneback
    // wishbone slave side
2360
    .wbs_dat_i(wbs_dat_i),
2361
    .wbs_adr_i(wbs_adr_i),
2362
    .wbs_sel_i(wbs_sel_i),
2363
    .wbs_bte_i(wbs_bte_i),
2364
    .wbs_cti_i(wbs_cti_i),
2365
    .wbs_we_i(wbs_we_i),
2366
    .wbs_cyc_i(wbs_cyc_i),
2367
    .wbs_stb_i(wbs_stb_i),
2368
    .wbs_dat_o(wbs_dat_o),
2369
    .wbs_ack_o(wbs_ack_o),
2370
    .wbs_clk(wbs_clk),
2371
    .wbs_rst(wbs_rst),
2372
    // wishbone master side
2373
    .wbm_dat_o(writedata),
2374 78 unneback
    .wbm_adr_o(address),
2375 75 unneback
    .wbm_sel_o(be),
2376
    .wbm_bte_o(wbm_bte_o),
2377
    .wbm_cti_o(wbm_cti_o),
2378
    .wbm_we_o(wbm_we_o),
2379
    .wbm_cyc_o(wbm_cyc_o),
2380
    .wbm_stb_o(wbm_stb_o),
2381
    .wbm_dat_i(readdata),
2382
    .wbm_ack_i(wbm_ack_i),
2383
    .wbm_clk(clk),
2384
    .wbm_rst(rst));
2385
endmodule
2386 39 unneback
module vl_wb3_arbiter_type1 (
2387
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
2388
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
2389
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
2390
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
2391
    wb_clk, wb_rst
2392
);
2393
parameter nr_of_ports = 3;
2394
parameter adr_size = 26;
2395
parameter adr_lo   = 2;
2396
parameter dat_size = 32;
2397
parameter sel_size = dat_size/8;
2398
localparam aw = (adr_size - adr_lo) * nr_of_ports;
2399
localparam dw = dat_size * nr_of_ports;
2400
localparam sw = sel_size * nr_of_ports;
2401
localparam cw = 3 * nr_of_ports;
2402
localparam bw = 2 * nr_of_ports;
2403
input  [dw-1:0] wbm_dat_o;
2404
input  [aw-1:0] wbm_adr_o;
2405
input  [sw-1:0] wbm_sel_o;
2406
input  [cw-1:0] wbm_cti_o;
2407
input  [bw-1:0] wbm_bte_o;
2408
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
2409
output [dw-1:0] wbm_dat_i;
2410
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
2411
output [dat_size-1:0] wbs_dat_i;
2412
output [adr_size-1:adr_lo] wbs_adr_i;
2413
output [sel_size-1:0] wbs_sel_i;
2414
output [2:0] wbs_cti_i;
2415
output [1:0] wbs_bte_i;
2416
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
2417
input  [dat_size-1:0] wbs_dat_o;
2418
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
2419
input wb_clk, wb_rst;
2420 44 unneback
reg  [nr_of_ports-1:0] select;
2421 39 unneback
wire &