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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library_altera.v] - Blame information for rev 98

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1 60 unneback
// default SYN_KEEP definition
2 97 unneback
// size to width
3 6 unneback
//////////////////////////////////////////////////////////////////////
4
////                                                              ////
5
////  Versatile library, clock and reset                          ////
6
////                                                              ////
7
////  Description                                                 ////
8
////  Logic related to clock and reset                            ////
9
////                                                              ////
10
////                                                              ////
11
////  To Do:                                                      ////
12
////   - add more different registers                             ////
13
////                                                              ////
14
////  Author(s):                                                  ////
15
////      - Michael Unneback, unneback@opencores.org              ////
16
////        ORSoC AB                                              ////
17
////                                                              ////
18
//////////////////////////////////////////////////////////////////////
19
////                                                              ////
20
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
21
////                                                              ////
22
//// This source file may be used and distributed without         ////
23
//// restriction provided that this copyright statement is not    ////
24
//// removed from the file and that any derivative work contains  ////
25
//// the original copyright notice and the associated disclaimer. ////
26
////                                                              ////
27
//// This source file is free software; you can redistribute it   ////
28
//// and/or modify it under the terms of the GNU Lesser General   ////
29
//// Public License as published by the Free Software Foundation; ////
30
//// either version 2.1 of the License, or (at your option) any   ////
31
//// later version.                                               ////
32
////                                                              ////
33
//// This source is distributed in the hope that it will be       ////
34
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
35
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
36
//// PURPOSE.  See the GNU Lesser General Public License for more ////
37
//// details.                                                     ////
38
////                                                              ////
39
//// You should have received a copy of the GNU Lesser General    ////
40
//// Public License along with this source; if not, download it   ////
41
//// from http://www.opencores.org/lgpl.shtml                     ////
42
////                                                              ////
43
//////////////////////////////////////////////////////////////////////
44 21 unneback
//altera
45 33 unneback
module vl_gbuf ( i, o);
46
input i;
47
output o;
48
assign o = i;
49
endmodule
50 6 unneback
 // ALTERA
51
 //ACTEL
52
// sync reset
53 17 unneback
// input active lo async reset, normally from external reset generator and/or switch
54 6 unneback
// output active high global reset sync with two DFFs 
55
`timescale 1 ns/100 ps
56
module vl_sync_rst ( rst_n_i, rst_o, clk);
57
input rst_n_i, clk;
58
output rst_o;
59 18 unneback
reg [1:0] tmp;
60 6 unneback
always @ (posedge clk or negedge rst_n_i)
61
if (!rst_n_i)
62 17 unneback
        tmp <= 2'b11;
63 6 unneback
else
64 33 unneback
        tmp <= {1'b0,tmp[1]};
65 17 unneback
vl_gbuf buf_i0( .i(tmp[0]), .o(rst_o));
66 6 unneback
endmodule
67
// vl_pll
68 32 unneback
///////////////////////////////////////////////////////////////////////////////
69
`timescale 1 ps/1 ps
70
module vl_pll ( clk_i, rst_n_i, lock, clk_o, rst_o);
71
parameter index = 0;
72
parameter number_of_clk = 1;
73
parameter period_time_0 = 20000;
74
parameter period_time_1 = 20000;
75
parameter period_time_2 = 20000;
76
parameter period_time_3 = 20000;
77
parameter period_time_4 = 20000;
78
parameter lock_delay = 2000000;
79
input clk_i, rst_n_i;
80
output lock;
81
output reg [0:number_of_clk-1] clk_o;
82
output [0:number_of_clk-1] rst_o;
83 33 unneback
`ifdef SIM_PLL
84 32 unneback
always
85
     #((period_time_0)/2) clk_o[0] <=  (!rst_n_i) ? 0 : ~clk_o[0];
86
generate if (number_of_clk > 1)
87
always
88
     #((period_time_1)/2) clk_o[1] <=  (!rst_n_i) ? 0 : ~clk_o[1];
89
endgenerate
90
generate if (number_of_clk > 2)
91
always
92
     #((period_time_2)/2) clk_o[2] <=  (!rst_n_i) ? 0 : ~clk_o[2];
93
endgenerate
94 33 unneback
generate if (number_of_clk > 3)
95 32 unneback
always
96
     #((period_time_3)/2) clk_o[3] <=  (!rst_n_i) ? 0 : ~clk_o[3];
97
endgenerate
98 33 unneback
generate if (number_of_clk > 4)
99 32 unneback
always
100
     #((period_time_4)/2) clk_o[4] <=  (!rst_n_i) ? 0 : ~clk_o[4];
101
endgenerate
102
genvar i;
103
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
104
     vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
105
end
106
endgenerate
107 33 unneback
//assign #lock_delay lock = rst_n_i;
108
assign lock = rst_n_i;
109 32 unneback
endmodule
110 33 unneback
`else
111
`ifdef VL_PLL0
112
`ifdef VL_PLL0_CLK1
113
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
114
`endif
115
`ifdef VL_PLL0_CLK2
116
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
117
`endif
118
`ifdef VL_PLL0_CLK3
119
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
120
`endif
121
`ifdef VL_PLL0_CLK4
122
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
123
`endif
124
`ifdef VL_PLL0_CLK5
125
    pll0 pll0_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
126
`endif
127
`endif
128
`ifdef VL_PLL1
129
`ifdef VL_PLL1_CLK1
130
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
131
`endif
132
`ifdef VL_PLL1_CLK2
133
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
134
`endif
135
`ifdef VL_PLL1_CLK3
136
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
137
`endif
138
`ifdef VL_PLL1_CLK4
139
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
140
`endif
141
`ifdef VL_PLL1_CLK5
142
    pll1 pll1_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
143
`endif
144
`endif
145
`ifdef VL_PLL2
146
`ifdef VL_PLL2_CLK1
147
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
148
`endif
149
`ifdef VL_PLL2_CLK2
150
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
151
`endif
152
`ifdef VL_PLL2_CLK3
153
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
154
`endif
155
`ifdef VL_PLL2_CLK4
156
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
157
`endif
158
`ifdef VL_PLL2_CLK5
159
    pll2 pll2_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
160
`endif
161
`endif
162
`ifdef VL_PLL3
163
`ifdef VL_PLL3_CLK1
164
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]));
165
`endif
166
`ifdef VL_PLL3_CLK2
167
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]));
168
`endif
169
`ifdef VL_PLL3_CLK3
170
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]));
171
`endif
172
`ifdef VL_PLL3_CLK4
173
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]));
174
`endif
175
`ifdef VL_PLL3_CLK5
176
    pll3 pll3_i0 (.areset(rst_n_i), .inclk0(clk_i), .locked(lock), .c0(clk_o[0]), .c1(clk_o[1]), .c2(clk_o[2]), .c3(clk_o[3]), .c4(clk_o[4]));
177
`endif
178
`endif
179 32 unneback
genvar i;
180
generate for (i=0;i<number_of_clk;i=i+1) begin: clock
181 40 unneback
        vl_sync_rst rst_i0 ( .rst_n_i(rst_n_i | lock), .rst_o(rst_o[i]), .clk(clk_o[i]));
182 32 unneback
end
183
endgenerate
184
endmodule
185 33 unneback
`endif
186 32 unneback
///////////////////////////////////////////////////////////////////////////////
187 6 unneback
 //altera
188
 //actel
189
//////////////////////////////////////////////////////////////////////
190
////                                                              ////
191
////  Versatile library, registers                                ////
192
////                                                              ////
193
////  Description                                                 ////
194
////  Different type of registers                                 ////
195
////                                                              ////
196
////                                                              ////
197
////  To Do:                                                      ////
198
////   - add more different registers                             ////
199
////                                                              ////
200
////  Author(s):                                                  ////
201
////      - Michael Unneback, unneback@opencores.org              ////
202
////        ORSoC AB                                              ////
203
////                                                              ////
204
//////////////////////////////////////////////////////////////////////
205
////                                                              ////
206
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
207
////                                                              ////
208
//// This source file may be used and distributed without         ////
209
//// restriction provided that this copyright statement is not    ////
210
//// removed from the file and that any derivative work contains  ////
211
//// the original copyright notice and the associated disclaimer. ////
212
////                                                              ////
213
//// This source file is free software; you can redistribute it   ////
214
//// and/or modify it under the terms of the GNU Lesser General   ////
215
//// Public License as published by the Free Software Foundation; ////
216
//// either version 2.1 of the License, or (at your option) any   ////
217
//// later version.                                               ////
218
////                                                              ////
219
//// This source is distributed in the hope that it will be       ////
220
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
221
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
222
//// PURPOSE.  See the GNU Lesser General Public License for more ////
223
//// details.                                                     ////
224
////                                                              ////
225
//// You should have received a copy of the GNU Lesser General    ////
226
//// Public License along with this source; if not, download it   ////
227
//// from http://www.opencores.org/lgpl.shtml                     ////
228
////                                                              ////
229
//////////////////////////////////////////////////////////////////////
230 18 unneback
module vl_dff ( d, q, clk, rst);
231 6 unneback
        parameter width = 1;
232
        parameter reset_value = 0;
233
        input [width-1:0] d;
234
        input clk, rst;
235
        output reg [width-1:0] q;
236
        always @ (posedge clk or posedge rst)
237
        if (rst)
238
                q <= reset_value;
239
        else
240
                q <= d;
241
endmodule
242 18 unneback
module vl_dff_array ( d, q, clk, rst);
243 6 unneback
        parameter width = 1;
244
        parameter depth = 2;
245
        parameter reset_value = 1'b0;
246
        input [width-1:0] d;
247
        input clk, rst;
248
        output [width-1:0] q;
249
        reg  [0:depth-1] q_tmp [width-1:0];
250
        integer i;
251
        always @ (posedge clk or posedge rst)
252
        if (rst) begin
253
            for (i=0;i<depth;i=i+1)
254
                q_tmp[i] <= {width{reset_value}};
255
        end else begin
256
            q_tmp[0] <= d;
257
            for (i=1;i<depth;i=i+1)
258
                q_tmp[i] <= q_tmp[i-1];
259
        end
260
    assign q = q_tmp[depth-1];
261
endmodule
262 18 unneback
module vl_dff_ce ( d, ce, q, clk, rst);
263 6 unneback
        parameter width = 1;
264
        parameter reset_value = 0;
265
        input [width-1:0] d;
266
        input ce, clk, rst;
267
        output reg [width-1:0] q;
268
        always @ (posedge clk or posedge rst)
269
        if (rst)
270
                q <= reset_value;
271
        else
272
                if (ce)
273
                        q <= d;
274
endmodule
275 18 unneback
module vl_dff_ce_clear ( d, ce, clear, q, clk, rst);
276 8 unneback
        parameter width = 1;
277
        parameter reset_value = 0;
278
        input [width-1:0] d;
279 10 unneback
        input ce, clear, clk, rst;
280 8 unneback
        output reg [width-1:0] q;
281
        always @ (posedge clk or posedge rst)
282
        if (rst)
283
            q <= reset_value;
284
        else
285
            if (ce)
286
                if (clear)
287
                    q <= {width{1'b0}};
288
                else
289
                    q <= d;
290
endmodule
291 24 unneback
module vl_dff_ce_set ( d, ce, set, q, clk, rst);
292
        parameter width = 1;
293
        parameter reset_value = 0;
294
        input [width-1:0] d;
295
        input ce, set, clk, rst;
296
        output reg [width-1:0] q;
297
        always @ (posedge clk or posedge rst)
298
        if (rst)
299
            q <= reset_value;
300
        else
301
            if (ce)
302
                if (set)
303
                    q <= {width{1'b1}};
304
                else
305
                    q <= d;
306
endmodule
307 29 unneback
module vl_spr ( sp, r, q, clk, rst);
308 64 unneback
        //parameter width = 1;
309
        parameter reset_value = 1'b0;
310 29 unneback
        input sp, r;
311
        output reg q;
312
        input clk, rst;
313
        always @ (posedge clk or posedge rst)
314
        if (rst)
315
            q <= reset_value;
316
        else
317
            if (sp)
318
                q <= 1'b1;
319
            else if (r)
320
                q <= 1'b0;
321
endmodule
322
module vl_srp ( s, rp, q, clk, rst);
323
        parameter width = 1;
324
        parameter reset_value = 0;
325
        input s, rp;
326
        output reg q;
327
        input clk, rst;
328
        always @ (posedge clk or posedge rst)
329
        if (rst)
330
            q <= reset_value;
331
        else
332
            if (rp)
333
                q <= 1'b0;
334
            else if (s)
335
                q <= 1'b1;
336
endmodule
337 6 unneback
// megafunction wizard: %LPM_FF%
338
// GENERATION: STANDARD
339
// VERSION: WM1.0
340
// MODULE: lpm_ff 
341
// ============================================================
342
// File Name: dff_sr.v
343
// Megafunction Name(s):
344
//                      lpm_ff
345
//
346
// Simulation Library Files(s):
347
//                      lpm
348
// ============================================================
349
// ************************************************************
350
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
351
//
352
// 9.1 Build 304 01/25/2010 SP 1 SJ Full Version
353
// ************************************************************
354
//Copyright (C) 1991-2010 Altera Corporation
355
//Your use of Altera Corporation's design tools, logic functions 
356
//and other software and tools, and its AMPP partner logic 
357
//functions, and any output files from any of the foregoing 
358
//(including device programming or simulation files), and any 
359
//associated documentation or information are expressly subject 
360
//to the terms and conditions of the Altera Program License 
361
//Subscription Agreement, Altera MegaCore Function License 
362
//Agreement, or other applicable license agreement, including, 
363
//without limitation, that your use is for the sole purpose of 
364
//programming logic devices manufactured by Altera and sold by 
365
//Altera or its authorized distributors.  Please refer to the 
366
//applicable agreement for further details.
367
// synopsys translate_off
368
`timescale 1 ps / 1 ps
369
// synopsys translate_on
370 18 unneback
module vl_dff_sr (
371 6 unneback
        aclr,
372
        aset,
373
        clock,
374
        data,
375
        q);
376
        input     aclr;
377
        input     aset;
378
        input     clock;
379
        input     data;
380
        output    q;
381
        wire [0:0] sub_wire0;
382
        wire [0:0] sub_wire1 = sub_wire0[0:0];
383
        wire  q = sub_wire1;
384
        wire  sub_wire2 = data;
385
        wire  sub_wire3 = sub_wire2;
386
        lpm_ff  lpm_ff_component (
387
                                .aclr (aclr),
388
                                .clock (clock),
389
                                .data (sub_wire3),
390
                                .aset (aset),
391
                                .q (sub_wire0)
392
                                // synopsys translate_off
393
                                ,
394
                                .aload (),
395
                                .enable (),
396
                                .sclr (),
397
                                .sload (),
398
                                .sset ()
399
                                // synopsys translate_on
400
                                );
401
        defparam
402
                lpm_ff_component.lpm_fftype = "DFF",
403
                lpm_ff_component.lpm_type = "LPM_FF",
404
                lpm_ff_component.lpm_width = 1;
405
endmodule
406
// ============================================================
407
// CNX file retrieval info
408
// ============================================================
409
// Retrieval info: PRIVATE: ACLR NUMERIC "1"
410
// Retrieval info: PRIVATE: ALOAD NUMERIC "0"
411
// Retrieval info: PRIVATE: ASET NUMERIC "1"
412
// Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
413
// Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
414
// Retrieval info: PRIVATE: DFF NUMERIC "1"
415
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
416
// Retrieval info: PRIVATE: SCLR NUMERIC "0"
417
// Retrieval info: PRIVATE: SLOAD NUMERIC "0"
418
// Retrieval info: PRIVATE: SSET NUMERIC "0"
419
// Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
420
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
421
// Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
422
// Retrieval info: PRIVATE: nBit NUMERIC "1"
423
// Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
424
// Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
425
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "1"
426
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
427
// Retrieval info: USED_PORT: aset 0 0 0 0 INPUT NODEFVAL aset
428
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
429
// Retrieval info: USED_PORT: data 0 0 0 0 INPUT NODEFVAL data
430
// Retrieval info: USED_PORT: q 0 0 0 0 OUTPUT NODEFVAL q
431
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
432
// Retrieval info: CONNECT: q 0 0 0 0 @q 0 0 1 0
433
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
434
// Retrieval info: CONNECT: @aset 0 0 0 0 aset 0 0 0 0
435
// Retrieval info: CONNECT: @data 0 0 1 0 data 0 0 0 0
436
// Retrieval info: LIBRARY: lpm lpm.lpm_components.all
437
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.v TRUE
438
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.inc FALSE
439
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.cmp FALSE
440
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr.bsf FALSE
441
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_inst.v FALSE
442
// Retrieval info: GEN_FILE: TYPE_NORMAL dff_sr_bb.v FALSE
443
// Retrieval info: LIB_FILE: lpm
444
// LATCH
445
// For targtes not supporting LATCH use dff_sr with clk=1 and data=1
446 18 unneback
module vl_latch ( d, le, q, clk);
447 6 unneback
input d, le;
448
output q;
449
input clk;
450
dff_sr i0 (.aclr(), .aset(), .clock(1'b1), .data(1'b1), .q(q));
451
endmodule
452 18 unneback
module vl_shreg ( d, q, clk, rst);
453 17 unneback
parameter depth = 10;
454
input d;
455
output q;
456
input clk, rst;
457
reg [1:depth] dffs;
458
always @ (posedge clk or posedge rst)
459
if (rst)
460
    dffs <= {depth{1'b0}};
461
else
462
    dffs <= {d,dffs[1:depth-1]};
463
assign q = dffs[depth];
464
endmodule
465 18 unneback
module vl_shreg_ce ( d, ce, q, clk, rst);
466 17 unneback
parameter depth = 10;
467
input d, ce;
468
output q;
469
input clk, rst;
470
reg [1:depth] dffs;
471
always @ (posedge clk or posedge rst)
472
if (rst)
473
    dffs <= {depth{1'b0}};
474
else
475
    if (ce)
476
        dffs <= {d,dffs[1:depth-1]};
477
assign q = dffs[depth];
478
endmodule
479 18 unneback
module vl_delay ( d, q, clk, rst);
480 15 unneback
parameter depth = 10;
481
input d;
482
output q;
483
input clk, rst;
484
reg [1:depth] dffs;
485
always @ (posedge clk or posedge rst)
486
if (rst)
487
    dffs <= {depth{1'b0}};
488
else
489
    dffs <= {d,dffs[1:depth-1]};
490
assign q = dffs[depth];
491
endmodule
492 18 unneback
module vl_delay_emptyflag ( d, q, emptyflag, clk, rst);
493 17 unneback
parameter depth = 10;
494
input d;
495
output q, emptyflag;
496
input clk, rst;
497
reg [1:depth] dffs;
498
always @ (posedge clk or posedge rst)
499
if (rst)
500
    dffs <= {depth{1'b0}};
501
else
502
    dffs <= {d,dffs[1:depth-1]};
503
assign q = dffs[depth];
504
assign emptyflag = !(|dffs);
505
endmodule
506 98 unneback
module vl_pulse2toggle ( pl, q, clk, rst);
507 94 unneback
input pl;
508 98 unneback
output reg q;
509 94 unneback
input clk, rst;
510
always @ (posedge clk or posedge rst)
511
if (rst)
512
    q <= 1'b0;
513
else
514
    q <= pl ^ q;
515
endmodule
516 98 unneback
module vl_toggle2pulse (d, pl, clk, rst);
517 94 unneback
input d;
518
output pl;
519
input clk, rst;
520
reg dff;
521
always @ (posedge clk or posedge rst)
522
if (rst)
523
    dff <= 1'b0;
524
else
525
    dff <= d;
526 98 unneback
assign pl = d ^ dff;
527 94 unneback
endmodule
528
module vl_synchronizer (d, q, clk, rst);
529
input d;
530
output reg q;
531
output clk, rst;
532
reg dff;
533
always @ (posedge clk or posedge rst)
534
if (rst)
535
    {dff,q} <= 2'b00;
536
else
537
    {dff,q} <= {d,dff};
538
endmodule
539 97 unneback
module vl_cdc ( start_pl, take_it_pl, take_it_grant_pl, got_it_pl, clk_src, rst_src, clk_dst, rst_dst);
540 94 unneback
input start_pl;
541
output take_it_pl;
542
input take_it_grant_pl; // note: connect to take_it_pl to generate automatic ack
543
output got_it_pl;
544
input clk_src, rst_src;
545
input clk_dst, rst_dst;
546
wire take_it_tg, take_it_tg_sync;
547
wire got_it_tg, got_it_tg_sync;
548
// src -> dst
549
vl_pulse2toggle p2t0 (
550
    .pl(start_pl),
551
    .q(take_it_tg),
552
    .clk(clk_src),
553
    .rst(rst_src));
554
vl_synchronizer sync0 (
555
    .d(take_it_tg),
556
    .q(take_it_tg_sync),
557
    .clk(clk_dst),
558
    .rst(rst_dst));
559
vl_toggle2pulse t2p0 (
560
    .d(take_it_sync),
561
    .pl(take_it_pl),
562
    .clk(clk_dst),
563
    .rst(rst_dst));
564
// dst -> src
565 98 unneback
vl_pulse2toggle p2t1 (
566 94 unneback
    .pl(take_it_grant_pl),
567
    .q(got_it_tg),
568
    .clk(clk_dst),
569
    .rst(rst_dst));
570
vl_synchronizer sync1 (
571
    .d(got_it_tg),
572
    .q(got_it_tg_sync),
573
    .clk(clk_src),
574
    .rst(rst_src));
575
vl_toggle2pulse t2p1 (
576
    .d(take_it_grant_tg_sync),
577
    .pl(got_it_pl),
578
    .clk(clk_src),
579
    .rst(rst_src));
580
endmodule
581 6 unneback
//////////////////////////////////////////////////////////////////////
582
////                                                              ////
583 18 unneback
////  Logic functions                                             ////
584
////                                                              ////
585
////  Description                                                 ////
586
////  Logic functions such as multiplexers                        ////
587
////                                                              ////
588
////                                                              ////
589
////  To Do:                                                      ////
590
////   -                                                          ////
591
////                                                              ////
592
////  Author(s):                                                  ////
593
////      - Michael Unneback, unneback@opencores.org              ////
594
////        ORSoC AB                                              ////
595
////                                                              ////
596
//////////////////////////////////////////////////////////////////////
597
////                                                              ////
598
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
599
////                                                              ////
600
//// This source file may be used and distributed without         ////
601
//// restriction provided that this copyright statement is not    ////
602
//// removed from the file and that any derivative work contains  ////
603
//// the original copyright notice and the associated disclaimer. ////
604
////                                                              ////
605
//// This source file is free software; you can redistribute it   ////
606
//// and/or modify it under the terms of the GNU Lesser General   ////
607
//// Public License as published by the Free Software Foundation; ////
608
//// either version 2.1 of the License, or (at your option) any   ////
609
//// later version.                                               ////
610
////                                                              ////
611
//// This source is distributed in the hope that it will be       ////
612
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
613
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
614
//// PURPOSE.  See the GNU Lesser General Public License for more ////
615
//// details.                                                     ////
616
////                                                              ////
617
//// You should have received a copy of the GNU Lesser General    ////
618
//// Public License along with this source; if not, download it   ////
619
//// from http://www.opencores.org/lgpl.shtml                     ////
620
////                                                              ////
621
//////////////////////////////////////////////////////////////////////
622 36 unneback
module vl_mux_andor ( a, sel, dout);
623
parameter width = 32;
624
parameter nr_of_ports = 4;
625
input [nr_of_ports*width-1:0] a;
626
input [nr_of_ports-1:0] sel;
627
output reg [width-1:0] dout;
628 38 unneback
integer i,j;
629 36 unneback
always @ (a, sel)
630
begin
631
    dout = a[width-1:0] & {width{sel[0]}};
632 42 unneback
    for (i=1;i<nr_of_ports;i=i+1)
633
        for (j=0;j<width;j=j+1)
634
            dout[j] = (a[i*width + j] & sel[i]) | dout[j];
635 36 unneback
end
636
endmodule
637 34 unneback
module vl_mux2_andor ( a1, a0, sel, dout);
638
parameter width = 32;
639 35 unneback
localparam nr_of_ports = 2;
640 34 unneback
input [width-1:0] a1, a0;
641
input [nr_of_ports-1:0] sel;
642
output [width-1:0] dout;
643 36 unneback
vl_mux_andor
644 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
645 36 unneback
    mux0( .a({a1,a0}), .sel(sel), .dout(dout));
646 34 unneback
endmodule
647
module vl_mux3_andor ( a2, a1, a0, sel, dout);
648
parameter width = 32;
649 35 unneback
localparam nr_of_ports = 3;
650 34 unneback
input [width-1:0] a2, a1, a0;
651
input [nr_of_ports-1:0] sel;
652
output [width-1:0] dout;
653 36 unneback
vl_mux_andor
654 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
655 36 unneback
    mux0( .a({a2,a1,a0}), .sel(sel), .dout(dout));
656 34 unneback
endmodule
657 18 unneback
module vl_mux4_andor ( a3, a2, a1, a0, sel, dout);
658
parameter width = 32;
659 35 unneback
localparam nr_of_ports = 4;
660 18 unneback
input [width-1:0] a3, a2, a1, a0;
661
input [nr_of_ports-1:0] sel;
662 22 unneback
output [width-1:0] dout;
663 36 unneback
vl_mux_andor
664 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
665 36 unneback
    mux0( .a({a3,a2,a1,a0}), .sel(sel), .dout(dout));
666 18 unneback
endmodule
667
module vl_mux5_andor ( a4, a3, a2, a1, a0, sel, dout);
668
parameter width = 32;
669 35 unneback
localparam nr_of_ports = 5;
670 18 unneback
input [width-1:0] a4, a3, a2, a1, a0;
671
input [nr_of_ports-1:0] sel;
672 22 unneback
output [width-1:0] dout;
673 36 unneback
vl_mux_andor
674 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
675 36 unneback
    mux0( .a({a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
676 18 unneback
endmodule
677
module vl_mux6_andor ( a5, a4, a3, a2, a1, a0, sel, dout);
678
parameter width = 32;
679 35 unneback
localparam nr_of_ports = 6;
680 18 unneback
input [width-1:0] a5, a4, a3, a2, a1, a0;
681
input [nr_of_ports-1:0] sel;
682 22 unneback
output [width-1:0] dout;
683 36 unneback
vl_mux_andor
684 38 unneback
    # ( .width(width), .nr_of_ports(nr_of_ports))
685 36 unneback
    mux0( .a({a5,a4,a3,a2,a1,a0}), .sel(sel), .dout(dout));
686 18 unneback
endmodule
687 43 unneback
module vl_parity_generate (data, parity);
688
parameter word_size = 32;
689
parameter chunk_size = 8;
690
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
691
input [word_size-1:0] data;
692
output reg [word_size/chunk_size-1:0] parity;
693
integer i,j;
694
always @ (data)
695
for (i=0;i<word_size/chunk_size;i=i+1) begin
696
    parity[i] = parity_type;
697
    for (j=0;j<chunk_size;j=j+1) begin
698 46 unneback
        parity[i] = data[i*chunk_size+j] ^ parity[i];
699 43 unneback
    end
700
end
701
endmodule
702
module vl_parity_check( data, parity, parity_error);
703
parameter word_size = 32;
704
parameter chunk_size = 8;
705
parameter parity_type = 1'b0; // 0 - even, 1 - odd parity
706
input [word_size-1:0] data;
707
input [word_size/chunk_size-1:0] parity;
708
output parity_error;
709 44 unneback
reg [word_size/chunk_size-1:0] error_flag;
710 43 unneback
integer i,j;
711
always @ (data or parity)
712
for (i=0;i<word_size/chunk_size;i=i+1) begin
713
    error_flag[i] = parity[i] ^ parity_type;
714
    for (j=0;j<chunk_size;j=j+1) begin
715 46 unneback
        error_flag[i] = data[i*chunk_size+j] ^ error_flag[i];
716 43 unneback
    end
717
end
718
assign parity_error = |error_flag;
719
endmodule
720 18 unneback
//////////////////////////////////////////////////////////////////////
721
////                                                              ////
722 44 unneback
////  IO functions                                                ////
723
////                                                              ////
724
////  Description                                                 ////
725
////  IO functions such as IOB flip-flops                         ////
726
////                                                              ////
727
////                                                              ////
728
////  To Do:                                                      ////
729
////   -                                                          ////
730
////                                                              ////
731
////  Author(s):                                                  ////
732
////      - Michael Unneback, unneback@opencores.org              ////
733
////        ORSoC AB                                              ////
734
////                                                              ////
735
//////////////////////////////////////////////////////////////////////
736
////                                                              ////
737
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
738
////                                                              ////
739
//// This source file may be used and distributed without         ////
740
//// restriction provided that this copyright statement is not    ////
741
//// removed from the file and that any derivative work contains  ////
742
//// the original copyright notice and the associated disclaimer. ////
743
////                                                              ////
744
//// This source file is free software; you can redistribute it   ////
745
//// and/or modify it under the terms of the GNU Lesser General   ////
746
//// Public License as published by the Free Software Foundation; ////
747
//// either version 2.1 of the License, or (at your option) any   ////
748
//// later version.                                               ////
749
////                                                              ////
750
//// This source is distributed in the hope that it will be       ////
751
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
752
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
753
//// PURPOSE.  See the GNU Lesser General Public License for more ////
754
//// details.                                                     ////
755
////                                                              ////
756
//// You should have received a copy of the GNU Lesser General    ////
757
//// Public License along with this source; if not, download it   ////
758
//// from http://www.opencores.org/lgpl.shtml                     ////
759
////                                                              ////
760
//////////////////////////////////////////////////////////////////////
761 45 unneback
`timescale 1ns/1ns
762 44 unneback
module vl_o_dff (d_i, o_pad, clk, rst);
763
parameter width = 1;
764 45 unneback
parameter reset_value = {width{1'b0}};
765
input  [width-1:0]  d_i;
766 44 unneback
output [width-1:0] o_pad;
767
input clk, rst;
768 60 unneback
wire [width-1:0] d_i_int /*synthesis syn_keep = 1*/;
769 45 unneback
reg  [width-1:0] o_pad_int;
770 44 unneback
assign d_i_int = d_i;
771
genvar i;
772 45 unneback
generate
773 44 unneback
for (i=0;i<width;i=i+1) begin
774
    always @ (posedge clk or posedge rst)
775
    if (rst)
776 45 unneback
        o_pad_int[i] <= reset_value[i];
777 44 unneback
    else
778 45 unneback
        o_pad_int[i] <= d_i_int[i];
779
    assign #1 o_pad[i] = o_pad_int[i];
780 44 unneback
end
781
endgenerate
782
endmodule
783 45 unneback
`timescale 1ns/1ns
784 44 unneback
module vl_io_dff_oe ( d_i, d_o, oe, io_pad, clk, rst);
785
parameter width = 1;
786
input  [width-1:0] d_o;
787
output reg [width-1:0] d_i;
788
input oe;
789
inout [width-1:0] io_pad;
790
input clk, rst;
791 60 unneback
wire [width-1:0] oe_d /*synthesis syn_keep = 1*/;
792 44 unneback
reg [width-1:0] oe_q;
793
reg [width-1:0] d_o_q;
794
assign oe_d = {width{oe}};
795
genvar i;
796
generate
797
for (i=0;i<width;i=i+1) begin
798
    always @ (posedge clk or posedge rst)
799
    if (rst)
800
        oe_q[i] <= 1'b0;
801
    else
802
        oe_q[i] <= oe_d[i];
803
    always @ (posedge clk or posedge rst)
804
    if (rst)
805
        d_o_q[i] <= 1'b0;
806
    else
807
        d_o_q[i] <= d_o[i];
808
    always @ (posedge clk or posedge rst)
809
    if (rst)
810
        d_i[i] <= 1'b0;
811
    else
812
        d_i[i] <= io_pad[i];
813 45 unneback
    assign #1 io_pad[i] = (oe_q[i]) ? d_o_q[i] : 1'bz;
814 44 unneback
end
815
endgenerate
816
endmodule
817
//////////////////////////////////////////////////////////////////////
818
////                                                              ////
819 6 unneback
////  Versatile counter                                           ////
820
////                                                              ////
821
////  Description                                                 ////
822
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
823
////  counter                                                     ////
824
////                                                              ////
825
////  To Do:                                                      ////
826
////   - add LFSR with more taps                                  ////
827
////                                                              ////
828
////  Author(s):                                                  ////
829
////      - Michael Unneback, unneback@opencores.org              ////
830
////        ORSoC AB                                              ////
831
////                                                              ////
832
//////////////////////////////////////////////////////////////////////
833
////                                                              ////
834
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
835
////                                                              ////
836
//// This source file may be used and distributed without         ////
837
//// restriction provided that this copyright statement is not    ////
838
//// removed from the file and that any derivative work contains  ////
839
//// the original copyright notice and the associated disclaimer. ////
840
////                                                              ////
841
//// This source file is free software; you can redistribute it   ////
842
//// and/or modify it under the terms of the GNU Lesser General   ////
843
//// Public License as published by the Free Software Foundation; ////
844
//// either version 2.1 of the License, or (at your option) any   ////
845
//// later version.                                               ////
846
////                                                              ////
847
//// This source is distributed in the hope that it will be       ////
848
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
849
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
850
//// PURPOSE.  See the GNU Lesser General Public License for more ////
851
//// details.                                                     ////
852
////                                                              ////
853
//// You should have received a copy of the GNU Lesser General    ////
854
//// Public License along with this source; if not, download it   ////
855
//// from http://www.opencores.org/lgpl.shtml                     ////
856
////                                                              ////
857
//////////////////////////////////////////////////////////////////////
858
// binary counter
859 40 unneback
module vl_cnt_bin_ce (
860
 cke, q, rst, clk);
861 22 unneback
   parameter length = 4;
862 6 unneback
   input cke;
863
   output [length:1] q;
864
   input rst;
865
   input clk;
866
   parameter clear_value = 0;
867
   parameter set_value = 1;
868
   parameter wrap_value = 0;
869
   parameter level1_value = 15;
870
   reg  [length:1] qi;
871
   wire [length:1] q_next;
872
   assign q_next = qi + {{length-1{1'b0}},1'b1};
873
   always @ (posedge clk or posedge rst)
874
     if (rst)
875
       qi <= {length{1'b0}};
876
     else
877
     if (cke)
878
       qi <= q_next;
879
   assign q = qi;
880
endmodule
881
//////////////////////////////////////////////////////////////////////
882
////                                                              ////
883
////  Versatile counter                                           ////
884
////                                                              ////
885
////  Description                                                 ////
886
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
887
////  counter                                                     ////
888
////                                                              ////
889
////  To Do:                                                      ////
890
////   - add LFSR with more taps                                  ////
891
////                                                              ////
892
////  Author(s):                                                  ////
893
////      - Michael Unneback, unneback@opencores.org              ////
894
////        ORSoC AB                                              ////
895
////                                                              ////
896
//////////////////////////////////////////////////////////////////////
897
////                                                              ////
898
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
899
////                                                              ////
900
//// This source file may be used and distributed without         ////
901
//// restriction provided that this copyright statement is not    ////
902
//// removed from the file and that any derivative work contains  ////
903
//// the original copyright notice and the associated disclaimer. ////
904
////                                                              ////
905
//// This source file is free software; you can redistribute it   ////
906
//// and/or modify it under the terms of the GNU Lesser General   ////
907
//// Public License as published by the Free Software Foundation; ////
908
//// either version 2.1 of the License, or (at your option) any   ////
909
//// later version.                                               ////
910
////                                                              ////
911
//// This source is distributed in the hope that it will be       ////
912
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
913
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
914
//// PURPOSE.  See the GNU Lesser General Public License for more ////
915
//// details.                                                     ////
916
////                                                              ////
917
//// You should have received a copy of the GNU Lesser General    ////
918
//// Public License along with this source; if not, download it   ////
919
//// from http://www.opencores.org/lgpl.shtml                     ////
920
////                                                              ////
921
//////////////////////////////////////////////////////////////////////
922
// binary counter
923 40 unneback
module vl_cnt_bin_ce_rew_zq_l1 (
924
 cke, rew, zq, level1, rst, clk);
925 6 unneback
   parameter length = 4;
926
   input cke;
927
   input rew;
928 25 unneback
   output reg zq;
929
   output reg level1;
930
   input rst;
931
   input clk;
932
   parameter clear_value = 0;
933
   parameter set_value = 1;
934
   parameter wrap_value = 1;
935
   parameter level1_value = 15;
936 29 unneback
   wire clear;
937 30 unneback
   assign clear = 1'b0;
938 25 unneback
   reg  [length:1] qi;
939
   wire  [length:1] q_next, q_next_fw, q_next_rew;
940
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
941
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
942
   assign q_next = rew ? q_next_rew : q_next_fw;
943
   always @ (posedge clk or posedge rst)
944
     if (rst)
945
       qi <= {length{1'b0}};
946
     else
947
     if (cke)
948
       qi <= q_next;
949
   always @ (posedge clk or posedge rst)
950
     if (rst)
951
       zq <= 1'b1;
952
     else
953
     if (cke)
954
       zq <= q_next == {length{1'b0}};
955
    always @ (posedge clk or posedge rst)
956
    if (rst)
957
        level1 <= 1'b0;
958
    else
959
    if (cke)
960 29 unneback
    if (clear)
961
        level1 <= 1'b0;
962
    else if (q_next == level1_value)
963 25 unneback
        level1 <= 1'b1;
964
    else if (qi == level1_value & rew)
965
        level1 <= 1'b0;
966
endmodule
967
//////////////////////////////////////////////////////////////////////
968
////                                                              ////
969
////  Versatile counter                                           ////
970
////                                                              ////
971
////  Description                                                 ////
972
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
973
////  counter                                                     ////
974
////                                                              ////
975
////  To Do:                                                      ////
976
////   - add LFSR with more taps                                  ////
977
////                                                              ////
978
////  Author(s):                                                  ////
979
////      - Michael Unneback, unneback@opencores.org              ////
980
////        ORSoC AB                                              ////
981
////                                                              ////
982
//////////////////////////////////////////////////////////////////////
983
////                                                              ////
984
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
985
////                                                              ////
986
//// This source file may be used and distributed without         ////
987
//// restriction provided that this copyright statement is not    ////
988
//// removed from the file and that any derivative work contains  ////
989
//// the original copyright notice and the associated disclaimer. ////
990
////                                                              ////
991
//// This source file is free software; you can redistribute it   ////
992
//// and/or modify it under the terms of the GNU Lesser General   ////
993
//// Public License as published by the Free Software Foundation; ////
994
//// either version 2.1 of the License, or (at your option) any   ////
995
//// later version.                                               ////
996
////                                                              ////
997
//// This source is distributed in the hope that it will be       ////
998
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
999
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1000
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1001
//// details.                                                     ////
1002
////                                                              ////
1003
//// You should have received a copy of the GNU Lesser General    ////
1004
//// Public License along with this source; if not, download it   ////
1005
//// from http://www.opencores.org/lgpl.shtml                     ////
1006
////                                                              ////
1007
//////////////////////////////////////////////////////////////////////
1008
// binary counter
1009 40 unneback
module vl_cnt_bin_ce_rew_q_zq_l1 (
1010
 cke, rew, q, zq, level1, rst, clk);
1011 25 unneback
   parameter length = 4;
1012
   input cke;
1013
   input rew;
1014
   output [length:1] q;
1015
   output reg zq;
1016
   output reg level1;
1017
   input rst;
1018
   input clk;
1019
   parameter clear_value = 0;
1020
   parameter set_value = 1;
1021
   parameter wrap_value = 1;
1022
   parameter level1_value = 15;
1023 29 unneback
   wire clear;
1024 30 unneback
   assign clear = 1'b0;
1025 25 unneback
   reg  [length:1] qi;
1026
   wire  [length:1] q_next, q_next_fw, q_next_rew;
1027
   assign q_next_fw  = qi + {{length-1{1'b0}},1'b1};
1028
   assign q_next_rew = qi - {{length-1{1'b0}},1'b1};
1029
   assign q_next = rew ? q_next_rew : q_next_fw;
1030
   always @ (posedge clk or posedge rst)
1031
     if (rst)
1032
       qi <= {length{1'b0}};
1033
     else
1034
     if (cke)
1035
       qi <= q_next;
1036
   assign q = qi;
1037
   always @ (posedge clk or posedge rst)
1038
     if (rst)
1039
       zq <= 1'b1;
1040
     else
1041
     if (cke)
1042
       zq <= q_next == {length{1'b0}};
1043
    always @ (posedge clk or posedge rst)
1044
    if (rst)
1045
        level1 <= 1'b0;
1046
    else
1047
    if (cke)
1048 29 unneback
    if (clear)
1049
        level1 <= 1'b0;
1050
    else if (q_next == level1_value)
1051 25 unneback
        level1 <= 1'b1;
1052
    else if (qi == level1_value & rew)
1053
        level1 <= 1'b0;
1054
endmodule
1055
//////////////////////////////////////////////////////////////////////
1056
////                                                              ////
1057
////  Versatile counter                                           ////
1058
////                                                              ////
1059
////  Description                                                 ////
1060
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1061
////  counter                                                     ////
1062
////                                                              ////
1063
////  To Do:                                                      ////
1064
////   - add LFSR with more taps                                  ////
1065
////                                                              ////
1066
////  Author(s):                                                  ////
1067
////      - Michael Unneback, unneback@opencores.org              ////
1068
////        ORSoC AB                                              ////
1069
////                                                              ////
1070
//////////////////////////////////////////////////////////////////////
1071
////                                                              ////
1072
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1073
////                                                              ////
1074
//// This source file may be used and distributed without         ////
1075
//// restriction provided that this copyright statement is not    ////
1076
//// removed from the file and that any derivative work contains  ////
1077
//// the original copyright notice and the associated disclaimer. ////
1078
////                                                              ////
1079
//// This source file is free software; you can redistribute it   ////
1080
//// and/or modify it under the terms of the GNU Lesser General   ////
1081
//// Public License as published by the Free Software Foundation; ////
1082
//// either version 2.1 of the License, or (at your option) any   ////
1083
//// later version.                                               ////
1084
////                                                              ////
1085
//// This source is distributed in the hope that it will be       ////
1086
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1087
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1088
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1089
//// details.                                                     ////
1090
////                                                              ////
1091
//// You should have received a copy of the GNU Lesser General    ////
1092
//// Public License along with this source; if not, download it   ////
1093
//// from http://www.opencores.org/lgpl.shtml                     ////
1094
////                                                              ////
1095
//////////////////////////////////////////////////////////////////////
1096 75 unneback
// LFSR counter
1097
module vl_cnt_lfsr_ce (
1098
 cke, zq, rst, clk);
1099
   parameter length = 4;
1100
   input cke;
1101
   output reg zq;
1102
   input rst;
1103
   input clk;
1104
   parameter clear_value = 0;
1105
   parameter set_value = 1;
1106
   parameter wrap_value = 0;
1107
   parameter level1_value = 15;
1108
   reg  [length:1] qi;
1109
   reg lfsr_fb;
1110
   wire [length:1] q_next;
1111
   reg [32:1] polynom;
1112
   integer i;
1113
   always @ (qi)
1114
   begin
1115
        case (length)
1116
         2: polynom = 32'b11;                               // 0x3
1117
         3: polynom = 32'b110;                              // 0x6
1118
         4: polynom = 32'b1100;                             // 0xC
1119
         5: polynom = 32'b10100;                            // 0x14
1120
         6: polynom = 32'b110000;                           // 0x30
1121
         7: polynom = 32'b1100000;                          // 0x60
1122
         8: polynom = 32'b10111000;                         // 0xb8
1123
         9: polynom = 32'b100010000;                        // 0x110
1124
        10: polynom = 32'b1001000000;                       // 0x240
1125
        11: polynom = 32'b10100000000;                      // 0x500
1126
        12: polynom = 32'b100000101001;                     // 0x829
1127
        13: polynom = 32'b1000000001100;                    // 0x100C
1128
        14: polynom = 32'b10000000010101;                   // 0x2015
1129
        15: polynom = 32'b110000000000000;                  // 0x6000
1130
        16: polynom = 32'b1101000000001000;                 // 0xD008
1131
        17: polynom = 32'b10010000000000000;                // 0x12000
1132
        18: polynom = 32'b100000010000000000;               // 0x20400
1133
        19: polynom = 32'b1000000000000100011;              // 0x40023
1134
        20: polynom = 32'b10010000000000000000;             // 0x90000
1135
        21: polynom = 32'b101000000000000000000;            // 0x140000
1136
        22: polynom = 32'b1100000000000000000000;           // 0x300000
1137
        23: polynom = 32'b10000100000000000000000;          // 0x420000
1138
        24: polynom = 32'b111000010000000000000000;         // 0xE10000
1139
        25: polynom = 32'b1001000000000000000000000;        // 0x1200000
1140
        26: polynom = 32'b10000000000000000000100011;       // 0x2000023
1141
        27: polynom = 32'b100000000000000000000010011;      // 0x4000013
1142
        28: polynom = 32'b1100100000000000000000000000;     // 0xC800000
1143
        29: polynom = 32'b10100000000000000000000000000;    // 0x14000000
1144
        30: polynom = 32'b100000000000000000000000101001;   // 0x20000029
1145
        31: polynom = 32'b1001000000000000000000000000000;  // 0x48000000
1146
        32: polynom = 32'b10000000001000000000000000000011; // 0x80200003
1147
        default: polynom = 32'b0;
1148
        endcase
1149
        lfsr_fb = qi[length];
1150
        for (i=length-1; i>=1; i=i-1) begin
1151
            if (polynom[i])
1152
                lfsr_fb = lfsr_fb  ~^ qi[i];
1153
        end
1154
    end
1155
   assign q_next = (qi == wrap_value) ? {length{1'b0}} :{qi[length-1:1],lfsr_fb};
1156
   always @ (posedge clk or posedge rst)
1157
     if (rst)
1158
       qi <= {length{1'b0}};
1159
     else
1160
     if (cke)
1161
       qi <= q_next;
1162
   always @ (posedge clk or posedge rst)
1163
     if (rst)
1164
       zq <= 1'b1;
1165
     else
1166
     if (cke)
1167
       zq <= q_next == {length{1'b0}};
1168
endmodule
1169
//////////////////////////////////////////////////////////////////////
1170
////                                                              ////
1171
////  Versatile counter                                           ////
1172
////                                                              ////
1173
////  Description                                                 ////
1174
////  Versatile counter, a reconfigurable binary, gray or LFSR    ////
1175
////  counter                                                     ////
1176
////                                                              ////
1177
////  To Do:                                                      ////
1178
////   - add LFSR with more taps                                  ////
1179
////                                                              ////
1180
////  Author(s):                                                  ////
1181
////      - Michael Unneback, unneback@opencores.org              ////
1182
////        ORSoC AB                                              ////
1183
////                                                              ////
1184
//////////////////////////////////////////////////////////////////////
1185
////                                                              ////
1186
//// Copyright (C) 2009 Authors and OPENCORES.ORG                 ////
1187
////                                                              ////
1188
//// This source file may be used and distributed without         ////
1189
//// restriction provided that this copyright statement is not    ////
1190
//// removed from the file and that any derivative work contains  ////
1191
//// the original copyright notice and the associated disclaimer. ////
1192
////                                                              ////
1193
//// This source file is free software; you can redistribute it   ////
1194
//// and/or modify it under the terms of the GNU Lesser General   ////
1195
//// Public License as published by the Free Software Foundation; ////
1196
//// either version 2.1 of the License, or (at your option) any   ////
1197
//// later version.                                               ////
1198
////                                                              ////
1199
//// This source is distributed in the hope that it will be       ////
1200
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1201
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1202
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1203
//// details.                                                     ////
1204
////                                                              ////
1205
//// You should have received a copy of the GNU Lesser General    ////
1206
//// Public License along with this source; if not, download it   ////
1207
//// from http://www.opencores.org/lgpl.shtml                     ////
1208
////                                                              ////
1209
//////////////////////////////////////////////////////////////////////
1210 6 unneback
// GRAY counter
1211 40 unneback
module vl_cnt_gray_ce_bin (
1212
 cke, q, q_bin, rst, clk);
1213 6 unneback
   parameter length = 4;
1214
   input cke;
1215
   output reg [length:1] q;
1216
   output [length:1] q_bin;
1217
   input rst;
1218
   input clk;
1219
   parameter clear_value = 0;
1220
   parameter set_value = 1;
1221
   parameter wrap_value = 8;
1222
   parameter level1_value = 15;
1223
   reg  [length:1] qi;
1224
   wire [length:1] q_next;
1225
   assign q_next = qi + {{length-1{1'b0}},1'b1};
1226
   always @ (posedge clk or posedge rst)
1227
     if (rst)
1228
       qi <= {length{1'b0}};
1229
     else
1230
     if (cke)
1231
       qi <= q_next;
1232
   always @ (posedge clk or posedge rst)
1233
     if (rst)
1234
       q <= {length{1'b0}};
1235
     else
1236
       if (cke)
1237
         q <= (q_next>>1) ^ q_next;
1238
   assign q_bin = qi;
1239
endmodule
1240
//////////////////////////////////////////////////////////////////////
1241
////                                                              ////
1242
////  Versatile library, counters                                 ////
1243
////                                                              ////
1244
////  Description                                                 ////
1245
////  counters                                                    ////
1246
////                                                              ////
1247
////                                                              ////
1248
////  To Do:                                                      ////
1249
////   - add more counters                                        ////
1250
////                                                              ////
1251
////  Author(s):                                                  ////
1252
////      - Michael Unneback, unneback@opencores.org              ////
1253
////        ORSoC AB                                              ////
1254
////                                                              ////
1255
//////////////////////////////////////////////////////////////////////
1256
////                                                              ////
1257
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1258
////                                                              ////
1259
//// This source file may be used and distributed without         ////
1260
//// restriction provided that this copyright statement is not    ////
1261
//// removed from the file and that any derivative work contains  ////
1262
//// the original copyright notice and the associated disclaimer. ////
1263
////                                                              ////
1264
//// This source file is free software; you can redistribute it   ////
1265
//// and/or modify it under the terms of the GNU Lesser General   ////
1266
//// Public License as published by the Free Software Foundation; ////
1267
//// either version 2.1 of the License, or (at your option) any   ////
1268
//// later version.                                               ////
1269
////                                                              ////
1270
//// This source is distributed in the hope that it will be       ////
1271
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1272
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1273
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1274
//// details.                                                     ////
1275
////                                                              ////
1276
//// You should have received a copy of the GNU Lesser General    ////
1277
//// Public License along with this source; if not, download it   ////
1278
//// from http://www.opencores.org/lgpl.shtml                     ////
1279
////                                                              ////
1280
//////////////////////////////////////////////////////////////////////
1281 18 unneback
module vl_cnt_shreg_wrap ( q, rst, clk);
1282 6 unneback
   parameter length = 4;
1283
   output reg [0:length-1] q;
1284
   input rst;
1285
   input clk;
1286
    always @ (posedge clk or posedge rst)
1287
    if (rst)
1288
        q <= {1'b1,{length-1{1'b0}}};
1289
    else
1290
        q <= {q[length-1],q[0:length-2]};
1291
endmodule
1292 18 unneback
module vl_cnt_shreg_ce_wrap ( cke, q, rst, clk);
1293 6 unneback
   parameter length = 4;
1294
   input cke;
1295
   output reg [0:length-1] q;
1296
   input rst;
1297
   input clk;
1298
    always @ (posedge clk or posedge rst)
1299
    if (rst)
1300
        q <= {1'b1,{length-1{1'b0}}};
1301
    else
1302
        if (cke)
1303
            q <= {q[length-1],q[0:length-2]};
1304
endmodule
1305 18 unneback
module vl_cnt_shreg_ce_clear ( cke, clear, q, rst, clk);
1306 6 unneback
   parameter length = 4;
1307
   input cke, clear;
1308
   output reg [0:length-1] q;
1309
   input rst;
1310
   input clk;
1311
    always @ (posedge clk or posedge rst)
1312
    if (rst)
1313
        q <= {1'b1,{length-1{1'b0}}};
1314
    else
1315
        if (cke)
1316
            if (clear)
1317
                q <= {1'b1,{length-1{1'b0}}};
1318
            else
1319
                q <= q >> 1;
1320
endmodule
1321 18 unneback
module vl_cnt_shreg_ce_clear_wrap ( cke, clear, q, rst, clk);
1322 6 unneback
   parameter length = 4;
1323
   input cke, clear;
1324
   output reg [0:length-1] q;
1325
   input rst;
1326
   input clk;
1327
    always @ (posedge clk or posedge rst)
1328
    if (rst)
1329
        q <= {1'b1,{length-1{1'b0}}};
1330
    else
1331
        if (cke)
1332
            if (clear)
1333
                q <= {1'b1,{length-1{1'b0}}};
1334
            else
1335
            q <= {q[length-1],q[0:length-2]};
1336
endmodule
1337
//////////////////////////////////////////////////////////////////////
1338
////                                                              ////
1339
////  Versatile library, memories                                 ////
1340
////                                                              ////
1341
////  Description                                                 ////
1342
////  memories                                                    ////
1343
////                                                              ////
1344
////                                                              ////
1345
////  To Do:                                                      ////
1346
////   - add more memory types                                    ////
1347
////                                                              ////
1348
////  Author(s):                                                  ////
1349
////      - Michael Unneback, unneback@opencores.org              ////
1350
////        ORSoC AB                                              ////
1351
////                                                              ////
1352
//////////////////////////////////////////////////////////////////////
1353
////                                                              ////
1354
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
1355
////                                                              ////
1356
//// This source file may be used and distributed without         ////
1357
//// restriction provided that this copyright statement is not    ////
1358
//// removed from the file and that any derivative work contains  ////
1359
//// the original copyright notice and the associated disclaimer. ////
1360
////                                                              ////
1361
//// This source file is free software; you can redistribute it   ////
1362
//// and/or modify it under the terms of the GNU Lesser General   ////
1363
//// Public License as published by the Free Software Foundation; ////
1364
//// either version 2.1 of the License, or (at your option) any   ////
1365
//// later version.                                               ////
1366
////                                                              ////
1367
//// This source is distributed in the hope that it will be       ////
1368
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
1369
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
1370
//// PURPOSE.  See the GNU Lesser General Public License for more ////
1371
//// details.                                                     ////
1372
////                                                              ////
1373
//// You should have received a copy of the GNU Lesser General    ////
1374
//// Public License along with this source; if not, download it   ////
1375
//// from http://www.opencores.org/lgpl.shtml                     ////
1376
////                                                              ////
1377
//////////////////////////////////////////////////////////////////////
1378
/// ROM
1379 7 unneback
module vl_rom_init ( adr, q, clk);
1380
   parameter data_width = 32;
1381
   parameter addr_width = 8;
1382 75 unneback
   parameter mem_size = 1<<addr_width;
1383 7 unneback
   input [(addr_width-1):0]       adr;
1384
   output reg [(data_width-1):0] q;
1385
   input                         clk;
1386 75 unneback
   reg [data_width-1:0] rom [mem_size-1:0];
1387 7 unneback
   parameter memory_file = "vl_rom.vmem";
1388
   initial
1389
     begin
1390
        $readmemh(memory_file, rom);
1391
     end
1392
   always @ (posedge clk)
1393
     q <= rom[adr];
1394
endmodule
1395 6 unneback
// Single port RAM
1396
module vl_ram ( d, adr, we, q, clk);
1397
   parameter data_width = 32;
1398
   parameter addr_width = 8;
1399 75 unneback
   parameter mem_size = 1<<addr_width;
1400 6 unneback
   input [(data_width-1):0]      d;
1401
   input [(addr_width-1):0]       adr;
1402
   input                         we;
1403 7 unneback
   output reg [(data_width-1):0] q;
1404 6 unneback
   input                         clk;
1405 98 unneback
   reg [data_width-1:0] ram [mem_size-1:0];
1406 7 unneback
   parameter init = 0;
1407
   parameter memory_file = "vl_ram.vmem";
1408
   generate if (init) begin : init_mem
1409
   initial
1410
     begin
1411
        $readmemh(memory_file, ram);
1412
     end
1413
   end
1414
   endgenerate
1415 6 unneback
   always @ (posedge clk)
1416
   begin
1417
   if (we)
1418
     ram[adr] <= d;
1419
   q <= ram[adr];
1420
   end
1421
endmodule
1422 91 unneback
module vl_ram_be ( d, adr, be, we, q, clk);
1423 7 unneback
   parameter data_width = 32;
1424 72 unneback
   parameter addr_width = 6;
1425 75 unneback
   parameter mem_size = 1<<addr_width;
1426 7 unneback
   input [(data_width-1):0]      d;
1427
   input [(addr_width-1):0]       adr;
1428 73 unneback
   input [(data_width/8)-1:0]    be;
1429 7 unneback
   input                         we;
1430
   output reg [(data_width-1):0] q;
1431
   input                         clk;
1432 65 unneback
`ifdef SYSTEMVERILOG
1433 95 unneback
    // use a multi-dimensional packed array
1434
    //t o model individual bytes within the word
1435
    logic [data_width/8-1:0][7:0] ram [0:mem_size-1];// # words = 1 << address width
1436 65 unneback
`else
1437 85 unneback
    reg [data_width-1:0] ram [mem_size-1:0];
1438
    wire [data_width/8-1:0] cke;
1439 65 unneback
`endif
1440 60 unneback
   parameter memory_init = 0;
1441 7 unneback
   parameter memory_file = "vl_ram.vmem";
1442 60 unneback
   generate if (memory_init) begin : init_mem
1443 7 unneback
   initial
1444
     begin
1445
        $readmemh(memory_file, ram);
1446
     end
1447
   end
1448
   endgenerate
1449 60 unneback
`ifdef SYSTEMVERILOG
1450
always_ff@(posedge clk)
1451
begin
1452 95 unneback
    if(we) begin
1453 86 unneback
        if(be[3]) ram[adr][3] <= d[31:24];
1454
        if(be[2]) ram[adr][2] <= d[23:16];
1455
        if(be[1]) ram[adr][1] <= d[15:8];
1456
        if(be[0]) ram[adr][0] <= d[7:0];
1457 60 unneback
    end
1458 90 unneback
        q <= ram[adr];
1459 60 unneback
end
1460
`else
1461 85 unneback
assign cke = {data_width/8{we}} & be;
1462 7 unneback
   genvar i;
1463 85 unneback
   generate for (i=0;i<data_width/8;i=i+1) begin : be_ram
1464 7 unneback
      always @ (posedge clk)
1465 85 unneback
      if (cke[i])
1466 7 unneback
        ram[adr][(i+1)*8-1:i*8] <= d[(i+1)*8-1:i*8];
1467
   end
1468
   endgenerate
1469
   always @ (posedge clk)
1470
      q <= ram[adr];
1471 60 unneback
`endif
1472 93 unneback
`ifdef verilator
1473 85 unneback
   // Function to access RAM (for use by Verilator).
1474
   function [31:0] get_mem;
1475
      // verilator public
1476 90 unneback
      input [addr_width-1:0]             addr;
1477 85 unneback
      get_mem = ram[addr];
1478
   endfunction // get_mem
1479
   // Function to write RAM (for use by Verilator).
1480
   function set_mem;
1481
      // verilator public
1482 90 unneback
      input [addr_width-1:0]             addr;
1483
      input [data_width-1:0]             data;
1484 85 unneback
      ram[addr] = data;
1485
   endfunction // set_mem
1486 93 unneback
`endif
1487 7 unneback
endmodule
1488
module vl_dpram_1r1w ( d_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1489 6 unneback
   parameter data_width = 32;
1490
   parameter addr_width = 8;
1491 75 unneback
   parameter mem_size = 1<<addr_width;
1492 6 unneback
   input [(data_width-1):0]      d_a;
1493
   input [(addr_width-1):0]       adr_a;
1494
   input [(addr_width-1):0]       adr_b;
1495
   input                         we_a;
1496
   output [(data_width-1):0]      q_b;
1497
   input                         clk_a, clk_b;
1498
   reg [(addr_width-1):0]         adr_b_reg;
1499 75 unneback
   reg [data_width-1:0] ram [mem_szie-1:0] ;
1500 7 unneback
   parameter init = 0;
1501
   parameter memory_file = "vl_ram.vmem";
1502
   generate if (init) begin : init_mem
1503
   initial
1504
     begin
1505
        $readmemh(memory_file, ram);
1506
     end
1507
   end
1508
   endgenerate
1509 6 unneback
   always @ (posedge clk_a)
1510
   if (we_a)
1511
     ram[adr_a] <= d_a;
1512
   always @ (posedge clk_b)
1513
   adr_b_reg <= adr_b;
1514
   assign q_b = ram[adr_b_reg];
1515
endmodule
1516 7 unneback
module vl_dpram_2r1w ( d_a, q_a, adr_a, we_a, clk_a, q_b, adr_b, clk_b );
1517 6 unneback
   parameter data_width = 32;
1518
   parameter addr_width = 8;
1519 75 unneback
   parameter mem_size = 1<<addr_width;
1520 6 unneback
   input [(data_width-1):0]      d_a;
1521
   input [(addr_width-1):0]       adr_a;
1522
   input [(addr_width-1):0]       adr_b;
1523
   input                         we_a;
1524
   output [(data_width-1):0]      q_b;
1525
   output reg [(data_width-1):0] q_a;
1526
   input                         clk_a, clk_b;
1527
   reg [(data_width-1):0]         q_b;
1528 75 unneback
   reg [data_width-1:0] ram [mem_szie-1:0] ;
1529 7 unneback
   parameter init = 0;
1530
   parameter memory_file = "vl_ram.vmem";
1531
   generate if (init) begin : init_mem
1532
   initial
1533
     begin
1534
        $readmemh(memory_file, ram);
1535
     end
1536
   end
1537
   endgenerate
1538 6 unneback
   always @ (posedge clk_a)
1539
     begin
1540
        q_a <= ram[adr_a];
1541
        if (we_a)
1542
             ram[adr_a] <= d_a;
1543
     end
1544
   always @ (posedge clk_b)
1545
          q_b <= ram[adr_b];
1546
endmodule
1547 7 unneback
module vl_dpram_2r2w ( d_a, q_a, adr_a, we_a, clk_a, d_b, q_b, adr_b, we_b, clk_b );
1548 6 unneback
   parameter data_width = 32;
1549
   parameter addr_width = 8;
1550 75 unneback
   parameter mem_size = 1<<addr_width;
1551 6 unneback
   input [(data_width-1):0]      d_a;
1552
   input [(addr_width-1):0]       adr_a;
1553
   input [(addr_width-1):0]       adr_b;
1554
   input                         we_a;
1555
   output [(data_width-1):0]      q_b;
1556
   input [(data_width-1):0]       d_b;
1557
   output reg [(data_width-1):0] q_a;
1558
   input                         we_b;
1559
   input                         clk_a, clk_b;
1560
   reg [(data_width-1):0]         q_b;
1561 75 unneback
   reg [data_width-1:0] ram [mem_size-1:0] ;
1562 7 unneback
   parameter init = 0;
1563
   parameter memory_file = "vl_ram.vmem";
1564
   generate if (init) begin : init_mem
1565
   initial
1566
     begin
1567
        $readmemh(memory_file, ram);
1568
     end
1569
   end
1570
   endgenerate
1571 6 unneback
   always @ (posedge clk_a)
1572
     begin
1573
        q_a <= ram[adr_a];
1574
        if (we_a)
1575
             ram[adr_a] <= d_a;
1576
     end
1577
   always @ (posedge clk_b)
1578
     begin
1579
        q_b <= ram[adr_b];
1580
        if (we_b)
1581
          ram[adr_b] <= d_b;
1582
     end
1583
endmodule
1584 92 unneback
module vl_dpram_be_2r2w ( d_a, q_a, adr_a, be_a, we_a, clk_a, d_b, q_b, adr_b, be_b, we_b, clk_b );
1585 75 unneback
   parameter a_data_width = 32;
1586
   parameter a_addr_width = 8;
1587 95 unneback
   parameter b_data_width = 64; //a_data_width;
1588 91 unneback
   localparam b_addr_width = a_data_width * a_addr_width / b_data_width;
1589 95 unneback
   localparam ratio = (a_addr_width>b_addr_width) ? (a_addr_width/b_addr_width) : (b_addr_width/a_addr_width);
1590
   parameter mem_size = (a_addr_width>b_addr_width) ? (1<<b_addr_width) : (1<<a_addr_width);
1591
   parameter init = 0;
1592
   parameter memory_file = "vl_ram.vmem";
1593 75 unneback
   input [(a_data_width-1):0]      d_a;
1594 91 unneback
   input [(a_addr_width-1):0]       adr_a;
1595
   input [(a_data_width/8-1):0]    be_a;
1596
   input                           we_a;
1597 75 unneback
   output reg [(a_data_width-1):0] q_a;
1598 91 unneback
   input [(b_data_width-1):0]       d_b;
1599
   input [(b_addr_width-1):0]       adr_b;
1600 92 unneback
   input [(b_data_width/8-1):0]    be_b;
1601
   input                           we_b;
1602
   output reg [(b_data_width-1):0]          q_b;
1603 91 unneback
   input                           clk_a, clk_b;
1604
`ifdef SYSTEMVERILOG
1605
// use a multi-dimensional packed array
1606
//to model individual bytes within the word
1607 75 unneback
generate
1608 91 unneback
if (a_data_width==32 & b_data_width==32) begin : dpram_3232
1609 98 unneback
    logic [0:3][7:0] ram [0:mem_size-1] ;
1610 95 unneback
    initial
1611
        if (init)
1612
            $readmemh(memory_file, ram);
1613 91 unneback
    always_ff@(posedge clk_a)
1614
    begin
1615
        if(we_a) begin
1616
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
1617
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
1618
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
1619
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
1620
        end
1621
    end
1622 92 unneback
    always@(posedge clk_a)
1623
        q_a = ram[adr_a];
1624 91 unneback
    always_ff@(posedge clk_b)
1625 92 unneback
    begin
1626
        if(we_b) begin
1627
            if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
1628
            if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
1629
            if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
1630
            if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
1631
        end
1632
    end
1633
    always@(posedge clk_b)
1634
        q_b = ram[adr_b];
1635 75 unneback
end
1636
endgenerate
1637 95 unneback
generate
1638
if (a_data_width==64 & b_data_width==64) begin : dpram_6464
1639 98 unneback
    logic [0:7][7:0] ram [0:mem_size-1] ;
1640 95 unneback
    initial
1641
        if (init)
1642
            $readmemh(memory_file, ram);
1643
    always_ff@(posedge clk_a)
1644
    begin
1645
        if(we_a) begin
1646
            if(be_a[7]) ram[adr_a][7] <= d_a[63:56];
1647
            if(be_a[6]) ram[adr_a][6] <= d_a[55:48];
1648
            if(be_a[5]) ram[adr_a][5] <= d_a[47:40];
1649
            if(be_a[4]) ram[adr_a][4] <= d_a[39:32];
1650
            if(be_a[3]) ram[adr_a][3] <= d_a[31:24];
1651
            if(be_a[2]) ram[adr_a][2] <= d_a[23:16];
1652
            if(be_a[1]) ram[adr_a][1] <= d_a[15:8];
1653
            if(be_a[0]) ram[adr_a][0] <= d_a[7:0];
1654
        end
1655
    end
1656
    always@(posedge clk_a)
1657
        q_a = ram[adr_a];
1658
    always_ff@(posedge clk_b)
1659
    begin
1660
        if(we_b) begin
1661
            if(be_b[7]) ram[adr_b][7] <= d_b[63:56];
1662
            if(be_b[6]) ram[adr_b][6] <= d_b[55:48];
1663
            if(be_b[5]) ram[adr_b][5] <= d_b[47:40];
1664
            if(be_b[4]) ram[adr_b][4] <= d_b[39:32];
1665
            if(be_b[3]) ram[adr_b][3] <= d_b[31:24];
1666
            if(be_b[2]) ram[adr_b][2] <= d_b[23:16];
1667
            if(be_b[1]) ram[adr_b][1] <= d_b[15:8];
1668
            if(be_b[0]) ram[adr_b][0] <= d_b[7:0];
1669
        end
1670
    end
1671
    always@(posedge clk_b)
1672
        q_b = ram[adr_b];
1673
end
1674
endgenerate
1675
generate
1676
if (a_data_width==32 & b_data_width==16) begin : dpram_3216
1677
logic [31:0] temp;
1678
vl_dpram_be_2r2w # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .init(init), .memory_file(memory_file))
1679
dpram6464 (
1680
    .d_a(d_a),
1681
    .q_a(q_a),
1682
    .adr_a(adr_a),
1683
    .be_a(be_a),
1684
    .we_a(we_a),
1685
    .clk_a(clk_a),
1686
    .d_b({d_b,d_b}),
1687
    .q_b(temp),
1688
    .adr_b(adr_b),
1689
    .be_b({be_b,be_b} & {{2{adr_b[0]}},{2{!adr_b[0]}}}),
1690
    .we_b(we_b),
1691
    .clk_b(clk_b)
1692
);
1693
always_comb
1694
    if (adr_b[0])
1695
        q_b = temp[31:16];
1696
    else
1697
        q_b = temp[15:0];
1698
end
1699
endgenerate
1700
generate
1701
if (a_data_width==32 & b_data_width==64) begin : dpram_3264
1702
logic [63:0] temp;
1703
vl_dpram_be_2r2w # (.a_data_width(64), .b_data_width(64), .a_addr_width(a_addr_width), .mem_size(mem_size), .init(init), .memory_file(memory_file))
1704
dpram6464 (
1705
    .d_a({d_a,d_a}),
1706
    .q_a(temp),
1707
    .adr_a(adr_a[a_addr_width-1:1]),
1708
    .be_a({be_a,be_a} & {{4{adr_a[0]}},{4{!adr_a[0]}}}),
1709
    .we_a(we_a),
1710
    .clk_a(clk_a),
1711
    .d_b(d_b),
1712
    .q_b(q_b),
1713
    .adr_b(adr_b),
1714
    .be_b(be_b),
1715
    .we_b(we_b),
1716
    .clk_b(clk_b)
1717
);
1718
always_comb
1719
    if (adr_a[0])
1720
        q_a = temp[63:32];
1721
    else
1722
        q_a = temp[31:0];
1723
end
1724
endgenerate
1725 91 unneback
`else
1726 92 unneback
    // This modules requires SystemVerilog
1727 98 unneback
    // at this point anyway
1728 91 unneback
`endif
1729 75 unneback
endmodule
1730 6 unneback
// FIFO
1731 25 unneback
module vl_fifo_1r1w_fill_level_sync (
1732
    d, wr, fifo_full,
1733
    q, rd, fifo_empty,
1734
    fill_level,
1735
    clk, rst
1736
    );
1737
parameter data_width = 18;
1738
parameter addr_width = 4;
1739
// write side
1740
input  [data_width-1:0] d;
1741
input                   wr;
1742
output                  fifo_full;
1743
// read side
1744
output [data_width-1:0] q;
1745
input                   rd;
1746
output                  fifo_empty;
1747
// common
1748
output [addr_width:0]   fill_level;
1749
input rst, clk;
1750
wire [addr_width:1] wadr, radr;
1751
vl_cnt_bin_ce
1752
    # ( .length(addr_width))
1753
    fifo_wr_adr( .cke(wr), .q(wadr), .rst(rst), .clk(clk));
1754
vl_cnt_bin_ce
1755
    # (.length(addr_width))
1756
    fifo_rd_adr( .cke(rd), .q(radr), .rst(rst), .clk(clk));
1757
vl_dpram_1r1w
1758
    # (.data_width(data_width), .addr_width(addr_width))
1759
    dpram ( .d_a(d), .adr_a(wadr), .we_a(wr), .clk_a(clk), .q_b(q), .adr_b(radr), .clk_b(clk));
1760 31 unneback
vl_cnt_bin_ce_rew_q_zq_l1
1761 27 unneback
    # (.length(addr_width+1), .level1_value(1<<addr_width))
1762 25 unneback
    fill_level_cnt( .cke(rd ^ wr), .rew(rd), .q(fill_level), .zq(fifo_empty), .level1(fifo_full), .rst(rst), .clk(clk));
1763
endmodule
1764 27 unneback
// Intended use is two small FIFOs (RX and TX typically) in one FPGA RAM resource
1765
// RAM is supposed to be larger than the two FIFOs
1766
// LFSR counters used adr pointers
1767
module vl_fifo_2r2w_sync_simplex (
1768
    // a side
1769
    a_d, a_wr, a_fifo_full,
1770
    a_q, a_rd, a_fifo_empty,
1771
    a_fill_level,
1772
    // b side
1773
    b_d, b_wr, b_fifo_full,
1774
    b_q, b_rd, b_fifo_empty,
1775
    b_fill_level,
1776
    // common
1777
    clk, rst
1778
    );
1779
parameter data_width = 8;
1780
parameter addr_width = 5;
1781
parameter fifo_full_level = (1<<addr_width)-1;
1782
// a side
1783
input  [data_width-1:0] a_d;
1784
input                   a_wr;
1785
output                  a_fifo_full;
1786
output [data_width-1:0] a_q;
1787
input                   a_rd;
1788
output                  a_fifo_empty;
1789
output [addr_width-1:0] a_fill_level;
1790
// b side
1791
input  [data_width-1:0] b_d;
1792
input                   b_wr;
1793
output                  b_fifo_full;
1794
output [data_width-1:0] b_q;
1795
input                   b_rd;
1796
output                  b_fifo_empty;
1797
output [addr_width-1:0] b_fill_level;
1798
input                   clk;
1799
input                   rst;
1800
// adr_gen
1801
wire [addr_width:1] a_wadr, a_radr;
1802
wire [addr_width:1] b_wadr, b_radr;
1803
// dpram
1804
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
1805
vl_cnt_lfsr_ce
1806
    # ( .length(addr_width))
1807
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .rst(rst), .clk(clk));
1808
vl_cnt_lfsr_ce
1809
    # (.length(addr_width))
1810
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .rst(rst), .clk(clk));
1811
vl_cnt_lfsr_ce
1812
    # ( .length(addr_width))
1813
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .rst(rst), .clk(clk));
1814
vl_cnt_lfsr_ce
1815
    # (.length(addr_width))
1816
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .rst(rst), .clk(clk));
1817
// mux read or write adr to DPRAM
1818
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr} : {1'b1,a_radr};
1819
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr} : {1'b0,b_radr};
1820
vl_dpram_2r2w
1821
    # (.data_width(data_width), .addr_width(addr_width+1))
1822
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
1823
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
1824
vl_cnt_bin_ce_rew_zq_l1
1825 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
1826 27 unneback
    a_fill_level_cnt( .cke(a_rd ^ a_wr), .rew(a_rd), .q(a_fill_level), .zq(a_fifo_empty), .level1(a_fifo_full), .rst(rst), .clk(clk));
1827
vl_cnt_bin_ce_rew_zq_l1
1828 28 unneback
    # (.length(addr_width), .level1_value(fifo_full_level))
1829 27 unneback
    b_fill_level_cnt( .cke(b_rd ^ b_wr), .rew(b_rd), .q(b_fill_level), .zq(b_fifo_empty), .level1(b_fifo_full), .rst(rst), .clk(clk));
1830
endmodule
1831 6 unneback
module vl_fifo_cmp_async ( wptr, rptr, fifo_empty, fifo_full, wclk, rclk, rst );
1832 11 unneback
   parameter addr_width = 4;
1833
   parameter N = addr_width-1;
1834 6 unneback
   parameter Q1 = 2'b00;
1835
   parameter Q2 = 2'b01;
1836
   parameter Q3 = 2'b11;
1837
   parameter Q4 = 2'b10;
1838
   parameter going_empty = 1'b0;
1839
   parameter going_full  = 1'b1;
1840
   input [N:0]  wptr, rptr;
1841 14 unneback
   output       fifo_empty;
1842 6 unneback
   output       fifo_full;
1843
   input        wclk, rclk, rst;
1844
   wire direction;
1845
   reg  direction_set, direction_clr;
1846
   wire async_empty, async_full;
1847
   wire fifo_full2;
1848 14 unneback
   wire fifo_empty2;
1849 6 unneback
   // direction_set
1850
   always @ (wptr[N:N-1] or rptr[N:N-1])
1851
     case ({wptr[N:N-1],rptr[N:N-1]})
1852
       {Q1,Q2} : direction_set <= 1'b1;
1853
       {Q2,Q3} : direction_set <= 1'b1;
1854
       {Q3,Q4} : direction_set <= 1'b1;
1855
       {Q4,Q1} : direction_set <= 1'b1;
1856
       default : direction_set <= 1'b0;
1857
     endcase
1858
   // direction_clear
1859
   always @ (wptr[N:N-1] or rptr[N:N-1] or rst)
1860
     if (rst)
1861
       direction_clr <= 1'b1;
1862
     else
1863
       case ({wptr[N:N-1],rptr[N:N-1]})
1864
         {Q2,Q1} : direction_clr <= 1'b1;
1865
         {Q3,Q2} : direction_clr <= 1'b1;
1866
         {Q4,Q3} : direction_clr <= 1'b1;
1867
         {Q1,Q4} : direction_clr <= 1'b1;
1868
         default : direction_clr <= 1'b0;
1869
       endcase
1870 18 unneback
    vl_dff_sr dff_sr_dir( .aclr(direction_clr), .aset(direction_set), .clock(1'b1), .data(1'b1), .q(direction));
1871 6 unneback
   assign async_empty = (wptr == rptr) && (direction==going_empty);
1872
   assign async_full  = (wptr == rptr) && (direction==going_full);
1873 18 unneback
    vl_dff_sr dff_sr_empty0( .aclr(rst), .aset(async_full), .clock(wclk), .data(async_full), .q(fifo_full2));
1874
    vl_dff_sr dff_sr_empty1( .aclr(rst), .aset(async_full), .clock(wclk), .data(fifo_full2), .q(fifo_full));
1875 6 unneback
/*
1876
   always @ (posedge wclk or posedge rst or posedge async_full)
1877
     if (rst)
1878
       {fifo_full, fifo_full2} <= 2'b00;
1879
     else if (async_full)
1880
       {fifo_full, fifo_full2} <= 2'b11;
1881
     else
1882
       {fifo_full, fifo_full2} <= {fifo_full2, async_full};
1883
*/
1884 14 unneback
/*   always @ (posedge rclk or posedge async_empty)
1885 6 unneback
     if (async_empty)
1886
       {fifo_empty, fifo_empty2} <= 2'b11;
1887
     else
1888 14 unneback
       {fifo_empty,fifo_empty2} <= {fifo_empty2,async_empty}; */
1889 18 unneback
    vl_dff # ( .reset_value(1'b1)) dff0 ( .d(async_empty), .q(fifo_empty2), .clk(rclk), .rst(async_empty));
1890
    vl_dff # ( .reset_value(1'b1)) dff1 ( .d(fifo_empty2), .q(fifo_empty),  .clk(rclk), .rst(async_empty));
1891 27 unneback
endmodule // async_compb
1892 6 unneback
module vl_fifo_1r1w_async (
1893
    d, wr, fifo_full, wr_clk, wr_rst,
1894
    q, rd, fifo_empty, rd_clk, rd_rst
1895
    );
1896
parameter data_width = 18;
1897
parameter addr_width = 4;
1898
// write side
1899
input  [data_width-1:0] d;
1900
input                   wr;
1901
output                  fifo_full;
1902
input                   wr_clk;
1903
input                   wr_rst;
1904
// read side
1905
output [data_width-1:0] q;
1906
input                   rd;
1907
output                  fifo_empty;
1908
input                   rd_clk;
1909
input                   rd_rst;
1910
wire [addr_width:1] wadr, wadr_bin, radr, radr_bin;
1911 18 unneback
vl_cnt_gray_ce_bin
1912 6 unneback
    # ( .length(addr_width))
1913
    fifo_wr_adr( .cke(wr), .q(wadr), .q_bin(wadr_bin), .rst(wr_rst), .clk(wr_clk));
1914 18 unneback
vl_cnt_gray_ce_bin
1915 6 unneback
    # (.length(addr_width))
1916 23 unneback
    fifo_rd_adr( .cke(rd), .q(radr), .q_bin(radr_bin), .rst(rd_rst), .clk(rd_clk));
1917 7 unneback
vl_dpram_1r1w
1918 6 unneback
    # (.data_width(data_width), .addr_width(addr_width))
1919
    dpram ( .d_a(d), .adr_a(wadr_bin), .we_a(wr), .clk_a(wr_clk), .q_b(q), .adr_b(radr_bin), .clk_b(rd_clk));
1920
vl_fifo_cmp_async
1921
    # (.addr_width(addr_width))
1922
    cmp ( .wptr(wadr), .rptr(radr), .fifo_empty(fifo_empty), .fifo_full(fifo_full), .wclk(wr_clk), .rclk(rd_clk), .rst(wr_rst) );
1923
endmodule
1924 8 unneback
module vl_fifo_2r2w_async (
1925 6 unneback
    // a side
1926
    a_d, a_wr, a_fifo_full,
1927
    a_q, a_rd, a_fifo_empty,
1928
    a_clk, a_rst,
1929
    // b side
1930
    b_d, b_wr, b_fifo_full,
1931
    b_q, b_rd, b_fifo_empty,
1932
    b_clk, b_rst
1933
    );
1934
parameter data_width = 18;
1935
parameter addr_width = 4;
1936
// a side
1937
input  [data_width-1:0] a_d;
1938
input                   a_wr;
1939
output                  a_fifo_full;
1940
output [data_width-1:0] a_q;
1941
input                   a_rd;
1942
output                  a_fifo_empty;
1943
input                   a_clk;
1944
input                   a_rst;
1945
// b side
1946
input  [data_width-1:0] b_d;
1947
input                   b_wr;
1948
output                  b_fifo_full;
1949
output [data_width-1:0] b_q;
1950
input                   b_rd;
1951
output                  b_fifo_empty;
1952
input                   b_clk;
1953
input                   b_rst;
1954
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1955
vl_fifo_1r1w_async_a (
1956
    .d(a_d), .wr(a_wr), .fifo_full(a_fifo_full), .wr_clk(a_clk), .wr_rst(a_rst),
1957
    .q(b_q), .rd(b_rd), .fifo_empty(b_fifo_empty), .rd_clk(b_clk), .rd_rst(b_rst)
1958
    );
1959
vl_fifo_1r1w_async # (.data_width(data_width), .addr_width(addr_width))
1960
vl_fifo_1r1w_async_b (
1961
    .d(b_d), .wr(b_wr), .fifo_full(b_fifo_full), .wr_clk(b_clk), .wr_rst(b_rst),
1962
    .q(a_q), .rd(a_rd), .fifo_empty(a_fifo_empty), .rd_clk(a_clk), .rd_rst(a_rst)
1963
    );
1964
endmodule
1965 8 unneback
module vl_fifo_2r2w_async_simplex (
1966 6 unneback
    // a side
1967
    a_d, a_wr, a_fifo_full,
1968
    a_q, a_rd, a_fifo_empty,
1969
    a_clk, a_rst,
1970
    // b side
1971
    b_d, b_wr, b_fifo_full,
1972
    b_q, b_rd, b_fifo_empty,
1973
    b_clk, b_rst
1974
    );
1975
parameter data_width = 18;
1976
parameter addr_width = 4;
1977
// a side
1978
input  [data_width-1:0] a_d;
1979
input                   a_wr;
1980
output                  a_fifo_full;
1981
output [data_width-1:0] a_q;
1982
input                   a_rd;
1983
output                  a_fifo_empty;
1984
input                   a_clk;
1985
input                   a_rst;
1986
// b side
1987
input  [data_width-1:0] b_d;
1988
input                   b_wr;
1989
output                  b_fifo_full;
1990
output [data_width-1:0] b_q;
1991
input                   b_rd;
1992
output                  b_fifo_empty;
1993
input                   b_clk;
1994
input                   b_rst;
1995
// adr_gen
1996
wire [addr_width:1] a_wadr, a_wadr_bin, a_radr, a_radr_bin;
1997
wire [addr_width:1] b_wadr, b_wadr_bin, b_radr, b_radr_bin;
1998
// dpram
1999
wire [addr_width:0] a_dpram_adr, b_dpram_adr;
2000 18 unneback
vl_cnt_gray_ce_bin
2001 6 unneback
    # ( .length(addr_width))
2002
    fifo_a_wr_adr( .cke(a_wr), .q(a_wadr), .q_bin(a_wadr_bin), .rst(a_rst), .clk(a_clk));
2003 18 unneback
vl_cnt_gray_ce_bin
2004 6 unneback
    # (.length(addr_width))
2005
    fifo_a_rd_adr( .cke(a_rd), .q(a_radr), .q_bin(a_radr_bin), .rst(a_rst), .clk(a_clk));
2006 18 unneback
vl_cnt_gray_ce_bin
2007 6 unneback
    # ( .length(addr_width))
2008
    fifo_b_wr_adr( .cke(b_wr), .q(b_wadr), .q_bin(b_wadr_bin), .rst(b_rst), .clk(b_clk));
2009 18 unneback
vl_cnt_gray_ce_bin
2010 6 unneback
    # (.length(addr_width))
2011
    fifo_b_rd_adr( .cke(b_rd), .q(b_radr), .q_bin(b_radr_bin), .rst(b_rst), .clk(b_clk));
2012
// mux read or write adr to DPRAM
2013
assign a_dpram_adr = (a_wr) ? {1'b0,a_wadr_bin} : {1'b1,a_radr_bin};
2014
assign b_dpram_adr = (b_wr) ? {1'b1,b_wadr_bin} : {1'b0,b_radr_bin};
2015 11 unneback
vl_dpram_2r2w
2016 6 unneback
    # (.data_width(data_width), .addr_width(addr_width+1))
2017
    dpram ( .d_a(a_d), .q_a(a_q), .adr_a(a_dpram_adr), .we_a(a_wr), .clk_a(a_clk),
2018
            .d_b(b_d), .q_b(b_q), .adr_b(b_dpram_adr), .we_b(b_wr), .clk_b(b_clk));
2019 11 unneback
vl_fifo_cmp_async
2020 6 unneback
    # (.addr_width(addr_width))
2021
    cmp1 ( .wptr(a_wadr), .rptr(b_radr), .fifo_empty(b_fifo_empty), .fifo_full(a_fifo_full), .wclk(a_clk), .rclk(b_clk), .rst(a_rst) );
2022 11 unneback
vl_fifo_cmp_async
2023 6 unneback
    # (.addr_width(addr_width))
2024
    cmp2 ( .wptr(b_wadr), .rptr(a_radr), .fifo_empty(a_fifo_empty), .fifo_full(b_fifo_full), .wclk(b_clk), .rclk(a_clk), .rst(b_rst) );
2025
endmodule
2026 48 unneback
module vl_reg_file (
2027
    a1, a2, a3, wd3, we3, rd1, rd2, clk
2028
);
2029
parameter data_width = 32;
2030
parameter addr_width = 5;
2031
input [addr_width-1:0] a1, a2, a3;
2032
input [data_width-1:0] wd3;
2033
input we3;
2034
output [data_width-1:0] rd1, rd2;
2035
input clk;
2036
vl_dpram_1r1w
2037
    # ( .data_width(data_width), .addr_width(addr_width))
2038
    ram1 (
2039
        .d_a(wd3),
2040
        .adr_a(a3),
2041
        .we_a(we3),
2042
        .clk_a(clk),
2043
        .q_b(rd1),
2044
        .adr_b(a1),
2045
        .clk_b(clk) );
2046
vl_dpram_1r1w
2047
    # ( .data_width(data_width), .addr_width(addr_width))
2048
    ram2 (
2049
        .d_a(wd3),
2050
        .adr_a(a3),
2051
        .we_a(we3),
2052
        .clk_a(clk),
2053
        .q_b(rd2),
2054
        .adr_b(a2),
2055
        .clk_b(clk) );
2056
endmodule
2057 12 unneback
//////////////////////////////////////////////////////////////////////
2058
////                                                              ////
2059
////  Versatile library, wishbone stuff                           ////
2060
////                                                              ////
2061
////  Description                                                 ////
2062
////  Wishbone compliant modules                                  ////
2063
////                                                              ////
2064
////                                                              ////
2065
////  To Do:                                                      ////
2066
////   -                                                          ////
2067
////                                                              ////
2068
////  Author(s):                                                  ////
2069
////      - Michael Unneback, unneback@opencores.org              ////
2070
////        ORSoC AB                                              ////
2071
////                                                              ////
2072
//////////////////////////////////////////////////////////////////////
2073
////                                                              ////
2074
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
2075
////                                                              ////
2076
//// This source file may be used and distributed without         ////
2077
//// restriction provided that this copyright statement is not    ////
2078
//// removed from the file and that any derivative work contains  ////
2079
//// the original copyright notice and the associated disclaimer. ////
2080
////                                                              ////
2081
//// This source file is free software; you can redistribute it   ////
2082
//// and/or modify it under the terms of the GNU Lesser General   ////
2083
//// Public License as published by the Free Software Foundation; ////
2084
//// either version 2.1 of the License, or (at your option) any   ////
2085
//// later version.                                               ////
2086
////                                                              ////
2087
//// This source is distributed in the hope that it will be       ////
2088
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
2089
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
2090
//// PURPOSE.  See the GNU Lesser General Public License for more ////
2091
//// details.                                                     ////
2092
////                                                              ////
2093
//// You should have received a copy of the GNU Lesser General    ////
2094
//// Public License along with this source; if not, download it   ////
2095
//// from http://www.opencores.org/lgpl.shtml                     ////
2096
////                                                              ////
2097
//////////////////////////////////////////////////////////////////////
2098
// async wb3 - wb3 bridge
2099
`timescale 1ns/1ns
2100 85 unneback
module vl_wb_adr_inc ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
2101 83 unneback
parameter adr_width = 10;
2102
parameter max_burst_width = 4;
2103 85 unneback
input cyc_i, stb_i, we_i;
2104 83 unneback
input [2:0] cti_i;
2105
input [1:0] bte_i;
2106
input [adr_width-1:0] adr_i;
2107
output [adr_width-1:0] adr_o;
2108
output ack_o;
2109
input clk, rst;
2110
reg [adr_width-1:0] adr;
2111 90 unneback
wire [max_burst_width-1:0] to_adr;
2112 91 unneback
reg [max_burst_width-1:0] last_adr;
2113 92 unneback
reg last_cycle;
2114
localparam idle_or_eoc = 1'b0;
2115
localparam cyc_or_ws   = 1'b1;
2116 91 unneback
always @ (posedge clk or posedge rst)
2117
if (rst)
2118
    last_adr <= {max_burst_width{1'b0}};
2119
else
2120
    if (stb_i)
2121 92 unneback
        last_adr <=adr_o[max_burst_width-1:0];
2122 83 unneback
generate
2123
if (max_burst_width==0) begin : inst_0
2124 97 unneback
        reg ack_o;
2125
        assign adr_o = adr_i;
2126
        always @ (posedge clk or posedge rst)
2127
        if (rst)
2128
            ack_o <= 1'b0;
2129
        else
2130
            ack_o <= cyc_i & stb_i & !ack_o;
2131 83 unneback
end else begin
2132
    always @ (posedge clk or posedge rst)
2133
    if (rst)
2134 92 unneback
        last_cycle <= idle_or_eoc;
2135 83 unneback
    else
2136 92 unneback
        last_cycle <= (!cyc_i) ? idle_or_eoc : //idle
2137
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? idle_or_eoc : // eoc
2138
                      (cyc_i & !stb_i) ? cyc_or_ws : //ws
2139
                      cyc_or_ws; // cyc
2140
    assign to_adr = (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
2141 85 unneback
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
2142 91 unneback
                                        (!stb_i) ? last_adr :
2143 92 unneback
                                        (last_cycle==idle_or_eoc) ? adr_i[max_burst_width-1:0] :
2144 85 unneback
                                        adr[max_burst_width-1:0];
2145 92 unneback
    assign ack_o = (last_cycle==cyc_or_ws) & stb_i;
2146 83 unneback
end
2147
endgenerate
2148
generate
2149
if (max_burst_width==2) begin : inst_2
2150
    always @ (posedge clk or posedge rst)
2151
    if (rst)
2152
        adr <= 2'h0;
2153
    else
2154
        if (cyc_i & stb_i)
2155
            adr[1:0] <= to_adr[1:0] + 2'd1;
2156
        else
2157
            adr <= to_adr[1:0];
2158
end
2159
endgenerate
2160
generate
2161
if (max_burst_width==3) begin : inst_3
2162
    always @ (posedge clk or posedge rst)
2163
    if (rst)
2164
        adr <= 3'h0;
2165
    else
2166
        if (cyc_i & stb_i)
2167
            case (bte_i)
2168
            2'b01: adr[2:0] <= {to_adr[2],to_adr[1:0] + 2'd1};
2169
            default: adr[3:0] <= to_adr[2:0] + 3'd1;
2170
            endcase
2171
        else
2172
            adr <= to_adr[2:0];
2173
end
2174
endgenerate
2175
generate
2176
if (max_burst_width==4) begin : inst_4
2177
    always @ (posedge clk or posedge rst)
2178
    if (rst)
2179
        adr <= 4'h0;
2180
    else
2181 91 unneback
        if (stb_i) // | (!stb_i & last_cycle!=ws)) // for !stb_i restart with adr_i +1, only inc once
2182 83 unneback
            case (bte_i)
2183
            2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
2184
            2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
2185
            default: adr[3:0] <= to_adr + 4'd1;
2186
            endcase
2187
        else
2188
            adr <= to_adr[3:0];
2189
end
2190
endgenerate
2191
generate
2192
if (adr_width > max_burst_width) begin : pass_through
2193
    assign adr_o[adr_width-1:max_burst_width] = adr_i[adr_width-1:max_burst_width];
2194
end
2195
endgenerate
2196
endmodule
2197
// async wb3 - wb3 bridge
2198
`timescale 1ns/1ns
2199 18 unneback
module vl_wb3wb3_bridge (
2200 12 unneback
        // wishbone slave side
2201
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
2202
        // wishbone master side
2203
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
2204 95 unneback
parameter style = "FIFO"; // valid: simple, FIFO
2205
parameter addr_width = 4;
2206 12 unneback
input [31:0] wbs_dat_i;
2207
input [31:2] wbs_adr_i;
2208
input [3:0]  wbs_sel_i;
2209
input [1:0]  wbs_bte_i;
2210
input [2:0]  wbs_cti_i;
2211
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
2212
output [31:0] wbs_dat_o;
2213 14 unneback
output wbs_ack_o;
2214 12 unneback
input wbs_clk, wbs_rst;
2215
output [31:0] wbm_dat_o;
2216
output reg [31:2] wbm_adr_o;
2217
output [3:0]  wbm_sel_o;
2218
output reg [1:0]  wbm_bte_o;
2219
output reg [2:0]  wbm_cti_o;
2220 14 unneback
output reg wbm_we_o;
2221
output wbm_cyc_o;
2222 12 unneback
output wbm_stb_o;
2223
input [31:0]  wbm_dat_i;
2224
input wbm_ack_i;
2225
input wbm_clk, wbm_rst;
2226
// bte
2227
parameter linear       = 2'b00;
2228
parameter wrap4        = 2'b01;
2229
parameter wrap8        = 2'b10;
2230
parameter wrap16       = 2'b11;
2231
// cti
2232
parameter classic      = 3'b000;
2233
parameter incburst     = 3'b010;
2234
parameter endofburst   = 3'b111;
2235 95 unneback
localparam wbs_adr  = 1'b0;
2236
localparam wbs_data = 1'b1;
2237
localparam wbm_adr0      = 2'b00;
2238
localparam wbm_adr1      = 2'b01;
2239
localparam wbm_data      = 2'b10;
2240
localparam wbm_data_wait = 2'b11;
2241 12 unneback
reg [1:0] wbs_bte_reg;
2242
reg wbs;
2243
wire wbs_eoc_alert, wbm_eoc_alert;
2244
reg wbs_eoc, wbm_eoc;
2245
reg [1:0] wbm;
2246 14 unneback
wire [1:16] wbs_count, wbm_count;
2247 12 unneback
wire [35:0] a_d, a_q, b_d, b_q;
2248
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
2249
reg a_rd_reg;
2250
wire b_rd_adr, b_rd_data;
2251 14 unneback
wire b_rd_data_reg;
2252
wire [35:0] temp;
2253 12 unneback
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
2254
always @ (posedge wbs_clk or posedge wbs_rst)
2255
if (wbs_rst)
2256
        wbs_eoc <= 1'b0;
2257
else
2258
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
2259 78 unneback
                wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111);
2260 12 unneback
        else if (wbs_eoc_alert & (a_rd | a_wr))
2261
                wbs_eoc <= 1'b1;
2262 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
2263 12 unneback
    cnt0 (
2264
        .cke(wbs_ack_o),
2265
        .clear(wbs_eoc),
2266
        .q(wbs_count),
2267
        .rst(wbs_rst),
2268
        .clk(wbs_clk));
2269
always @ (posedge wbs_clk or posedge wbs_rst)
2270
if (wbs_rst)
2271
        wbs <= wbs_adr;
2272
else
2273 75 unneback
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)
2274 12 unneback
                wbs <= wbs_data;
2275
        else if (wbs_eoc & wbs_ack_o)
2276
                wbs <= wbs_adr;
2277
// wbs FIFO
2278 75 unneback
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};
2279
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :
2280 12 unneback
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
2281
              1'b0;
2282
assign a_rd = !a_fifo_empty;
2283
always @ (posedge wbs_clk or posedge wbs_rst)
2284
if (wbs_rst)
2285
        a_rd_reg <= 1'b0;
2286
else
2287
        a_rd_reg <= a_rd;
2288
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
2289
assign wbs_dat_o = a_q[35:4];
2290
always @ (posedge wbs_clk or posedge wbs_rst)
2291
if (wbs_rst)
2292 13 unneback
        wbs_bte_reg <= 2'b00;
2293 12 unneback
else
2294 13 unneback
        wbs_bte_reg <= wbs_bte_i;
2295 12 unneback
// wbm FIFO
2296
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
2297
always @ (posedge wbm_clk or posedge wbm_rst)
2298
if (wbm_rst)
2299
        wbm_eoc <= 1'b0;
2300
else
2301
        if (wbm==wbm_adr0 & !b_fifo_empty)
2302
                wbm_eoc <= b_q[4:3] == linear;
2303
        else if (wbm_eoc_alert & wbm_ack_i)
2304
                wbm_eoc <= 1'b1;
2305
always @ (posedge wbm_clk or posedge wbm_rst)
2306
if (wbm_rst)
2307
        wbm <= wbm_adr0;
2308
else
2309 33 unneback
/*
2310 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
2311
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
2312
        (wbm==wbm_adr1 & !wbm_we_o) |
2313
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
2314
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
2315 33 unneback
*/
2316
    case (wbm)
2317
    wbm_adr0:
2318
        if (!b_fifo_empty)
2319
            wbm <= wbm_adr1;
2320
    wbm_adr1:
2321
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
2322
            wbm <= wbm_data;
2323
    wbm_data:
2324
        if (wbm_ack_i & wbm_eoc)
2325
            wbm <= wbm_adr0;
2326
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
2327
            wbm <= wbm_data_wait;
2328
    wbm_data_wait:
2329
        if (!b_fifo_empty)
2330
            wbm <= wbm_data;
2331
    endcase
2332 12 unneback
assign b_d = {wbm_dat_i,4'b1111};
2333
assign b_wr = !wbm_we_o & wbm_ack_i;
2334
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
2335
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
2336
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
2337 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
2338 12 unneback
                   1'b0;
2339
assign b_rd = b_rd_adr | b_rd_data;
2340 18 unneback
vl_dff dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
2341
vl_dff_ce # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
2342 12 unneback
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
2343 18 unneback
vl_cnt_shreg_ce_clear # ( .length(16))
2344 12 unneback
    cnt1 (
2345
        .cke(wbm_ack_i),
2346
        .clear(wbm_eoc),
2347
        .q(wbm_count),
2348
        .rst(wbm_rst),
2349
        .clk(wbm_clk));
2350 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
2351
assign wbm_stb_o = (wbm==wbm_data);
2352 12 unneback
always @ (posedge wbm_clk or posedge wbm_rst)
2353
if (wbm_rst)
2354
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
2355
else begin
2356
        if (wbm==wbm_adr0 & !b_fifo_empty)
2357
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
2358
        else if (wbm_eoc_alert & wbm_ack_i)
2359
                wbm_cti_o <= endofburst;
2360
end
2361
//async_fifo_dw_simplex_top
2362
vl_fifo_2r2w_async_simplex
2363
# ( .data_width(36), .addr_width(addr_width))
2364
fifo (
2365
    // a side
2366
    .a_d(a_d),
2367
    .a_wr(a_wr),
2368
    .a_fifo_full(a_fifo_full),
2369
    .a_q(a_q),
2370
    .a_rd(a_rd),
2371
    .a_fifo_empty(a_fifo_empty),
2372
    .a_clk(wbs_clk),
2373
    .a_rst(wbs_rst),
2374
    // b side
2375
    .b_d(b_d),
2376
    .b_wr(b_wr),
2377
    .b_fifo_full(b_fifo_full),
2378
    .b_q(b_q),
2379
    .b_rd(b_rd),
2380
    .b_fifo_empty(b_fifo_empty),
2381
    .b_clk(wbm_clk),
2382
    .b_rst(wbm_rst)
2383
    );
2384
endmodule
2385 75 unneback
module vl_wb3avalon_bridge (
2386
        // wishbone slave side
2387
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
2388 77 unneback
        // avalon master side
2389 75 unneback
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
2390 85 unneback
parameter linewrapburst = 1'b0;
2391 75 unneback
input [31:0] wbs_dat_i;
2392
input [31:2] wbs_adr_i;
2393
input [3:0]  wbs_sel_i;
2394
input [1:0]  wbs_bte_i;
2395
input [2:0]  wbs_cti_i;
2396 83 unneback
input wbs_we_i;
2397
input wbs_cyc_i;
2398
input wbs_stb_i;
2399 75 unneback
output [31:0] wbs_dat_o;
2400
output wbs_ack_o;
2401
input wbs_clk, wbs_rst;
2402
input [31:0] readdata;
2403
output [31:0] writedata;
2404
output [