OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [wb.v] - Blame information for rev 75

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 12 unneback
//////////////////////////////////////////////////////////////////////
2
////                                                              ////
3
////  Versatile library, wishbone stuff                           ////
4
////                                                              ////
5
////  Description                                                 ////
6
////  Wishbone compliant modules                                  ////
7
////                                                              ////
8
////                                                              ////
9
////  To Do:                                                      ////
10
////   -                                                          ////
11
////                                                              ////
12
////  Author(s):                                                  ////
13
////      - Michael Unneback, unneback@opencores.org              ////
14
////        ORSoC AB                                              ////
15
////                                                              ////
16
//////////////////////////////////////////////////////////////////////
17
////                                                              ////
18
//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
19
////                                                              ////
20
//// This source file may be used and distributed without         ////
21
//// restriction provided that this copyright statement is not    ////
22
//// removed from the file and that any derivative work contains  ////
23
//// the original copyright notice and the associated disclaimer. ////
24
////                                                              ////
25
//// This source file is free software; you can redistribute it   ////
26
//// and/or modify it under the terms of the GNU Lesser General   ////
27
//// Public License as published by the Free Software Foundation; ////
28
//// either version 2.1 of the License, or (at your option) any   ////
29
//// later version.                                               ////
30
////                                                              ////
31
//// This source is distributed in the hope that it will be       ////
32
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
33
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
34
//// PURPOSE.  See the GNU Lesser General Public License for more ////
35
//// details.                                                     ////
36
////                                                              ////
37
//// You should have received a copy of the GNU Lesser General    ////
38
//// Public License along with this source; if not, download it   ////
39
//// from http://www.opencores.org/lgpl.shtml                     ////
40
////                                                              ////
41
//////////////////////////////////////////////////////////////////////
42
 
43 75 unneback
`ifdef WB_ADR_INC
44
// async wb3 - wb3 bridge
45
`timescale 1ns/1ns
46
`define MODULE wb_adr_inc
47
module `BASE`MODULE (
48
`undef MODULE
49
 
50
    always @ (posedge clk or posedge rst)
51
        if (rst)
52
           col_reg <= {col_reg_width{1'b0}};
53
        else
54
            case (state)
55
            `FSM_IDLE:
56
               col_reg <= col[col_reg_width-1:0];
57
            `FSM_RW:
58
               if (~stall)
59
                  case (bte_i)
60
`ifdef SDR_BEAT4
61
                        beat4:  col_reg[2:0] <= col_reg[2:0] + 3'd1;
62
`endif
63
`ifdef SDR_BEAT8
64
                        beat8:  col_reg[3:0] <= col_reg[3:0] + 4'd1;
65
`endif
66
`ifdef SDR_BEAT16
67
                        beat16: col_reg[4:0] <= col_reg[4:0] + 5'd1;
68
`endif
69
                  endcase
70
            endcase
71
`endif
72
 
73 40 unneback
`ifdef WB3WB3_BRIDGE
74 12 unneback
// async wb3 - wb3 bridge
75
`timescale 1ns/1ns
76 40 unneback
`define MODULE wb3wb3_bridge
77
module `BASE`MODULE (
78
`undef MODULE
79 12 unneback
        // wishbone slave side
80
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
81
        // wishbone master side
82
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
83
 
84
input [31:0] wbs_dat_i;
85
input [31:2] wbs_adr_i;
86
input [3:0]  wbs_sel_i;
87
input [1:0]  wbs_bte_i;
88
input [2:0]  wbs_cti_i;
89
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
90
output [31:0] wbs_dat_o;
91 14 unneback
output wbs_ack_o;
92 12 unneback
input wbs_clk, wbs_rst;
93
 
94
output [31:0] wbm_dat_o;
95
output reg [31:2] wbm_adr_o;
96
output [3:0]  wbm_sel_o;
97
output reg [1:0]  wbm_bte_o;
98
output reg [2:0]  wbm_cti_o;
99 14 unneback
output reg wbm_we_o;
100
output wbm_cyc_o;
101 12 unneback
output wbm_stb_o;
102
input [31:0]  wbm_dat_i;
103
input wbm_ack_i;
104
input wbm_clk, wbm_rst;
105
 
106
parameter addr_width = 4;
107
 
108
// bte
109
parameter linear       = 2'b00;
110
parameter wrap4        = 2'b01;
111
parameter wrap8        = 2'b10;
112
parameter wrap16       = 2'b11;
113
// cti
114
parameter classic      = 3'b000;
115
parameter incburst     = 3'b010;
116
parameter endofburst   = 3'b111;
117
 
118
parameter wbs_adr  = 1'b0;
119
parameter wbs_data = 1'b1;
120
 
121 33 unneback
parameter wbm_adr0      = 2'b00;
122
parameter wbm_adr1      = 2'b01;
123
parameter wbm_data      = 2'b10;
124
parameter wbm_data_wait = 2'b11;
125 12 unneback
 
126
reg [1:0] wbs_bte_reg;
127
reg wbs;
128
wire wbs_eoc_alert, wbm_eoc_alert;
129
reg wbs_eoc, wbm_eoc;
130
reg [1:0] wbm;
131
 
132 14 unneback
wire [1:16] wbs_count, wbm_count;
133 12 unneback
 
134
wire [35:0] a_d, a_q, b_d, b_q;
135
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
136
reg a_rd_reg;
137
wire b_rd_adr, b_rd_data;
138 14 unneback
wire b_rd_data_reg;
139
wire [35:0] temp;
140 12 unneback
 
141
`define WE 5
142
`define BTE 4:3
143
`define CTI 2:0
144
 
145
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
146
always @ (posedge wbs_clk or posedge wbs_rst)
147
if (wbs_rst)
148
        wbs_eoc <= 1'b0;
149
else
150
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
151
                wbs_eoc <= wbs_bte_i==linear;
152
        else if (wbs_eoc_alert & (a_rd | a_wr))
153
                wbs_eoc <= 1'b1;
154
 
155 40 unneback
`define MODULE cnt_shreg_ce_clear
156
`BASE`MODULE # ( .length(16))
157
`undef MODULE
158 12 unneback
    cnt0 (
159
        .cke(wbs_ack_o),
160
        .clear(wbs_eoc),
161
        .q(wbs_count),
162
        .rst(wbs_rst),
163
        .clk(wbs_clk));
164
 
165
always @ (posedge wbs_clk or posedge wbs_rst)
166
if (wbs_rst)
167
        wbs <= wbs_adr;
168
else
169 75 unneback
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)
170 12 unneback
                wbs <= wbs_data;
171
        else if (wbs_eoc & wbs_ack_o)
172
                wbs <= wbs_adr;
173
 
174
// wbs FIFO
175 75 unneback
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};
176
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :
177 12 unneback
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
178
              1'b0;
179
assign a_rd = !a_fifo_empty;
180
always @ (posedge wbs_clk or posedge wbs_rst)
181
if (wbs_rst)
182
        a_rd_reg <= 1'b0;
183
else
184
        a_rd_reg <= a_rd;
185
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
186
 
187
assign wbs_dat_o = a_q[35:4];
188
 
189
always @ (posedge wbs_clk or posedge wbs_rst)
190
if (wbs_rst)
191 13 unneback
        wbs_bte_reg <= 2'b00;
192 12 unneback
else
193 13 unneback
        wbs_bte_reg <= wbs_bte_i;
194 12 unneback
 
195
// wbm FIFO
196
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
197
always @ (posedge wbm_clk or posedge wbm_rst)
198
if (wbm_rst)
199
        wbm_eoc <= 1'b0;
200
else
201
        if (wbm==wbm_adr0 & !b_fifo_empty)
202
                wbm_eoc <= b_q[`BTE] == linear;
203
        else if (wbm_eoc_alert & wbm_ack_i)
204
                wbm_eoc <= 1'b1;
205
 
206
always @ (posedge wbm_clk or posedge wbm_rst)
207
if (wbm_rst)
208
        wbm <= wbm_adr0;
209
else
210 33 unneback
/*
211 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
212
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
213
        (wbm==wbm_adr1 & !wbm_we_o) |
214
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
215
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
216 33 unneback
*/
217
    case (wbm)
218
    wbm_adr0:
219
        if (!b_fifo_empty)
220
            wbm <= wbm_adr1;
221
    wbm_adr1:
222
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
223
            wbm <= wbm_data;
224
    wbm_data:
225
        if (wbm_ack_i & wbm_eoc)
226
            wbm <= wbm_adr0;
227
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
228
            wbm <= wbm_data_wait;
229
    wbm_data_wait:
230
        if (!b_fifo_empty)
231
            wbm <= wbm_data;
232
    endcase
233 12 unneback
 
234
assign b_d = {wbm_dat_i,4'b1111};
235
assign b_wr = !wbm_we_o & wbm_ack_i;
236
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
237
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
238
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
239 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
240 12 unneback
                   1'b0;
241
assign b_rd = b_rd_adr | b_rd_data;
242
 
243 40 unneback
`define MODULE dff
244
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
245
`undef MODULE
246
`define MODULE dff_ce
247
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
248
`undef MODULE
249 12 unneback
 
250
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
251
 
252 40 unneback
`define MODULE cnt_shreg_ce_clear
253 42 unneback
`BASE`MODULE # ( .length(16))
254 40 unneback
`undef MODULE
255 12 unneback
    cnt1 (
256
        .cke(wbm_ack_i),
257
        .clear(wbm_eoc),
258
        .q(wbm_count),
259
        .rst(wbm_rst),
260
        .clk(wbm_clk));
261
 
262 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
263
assign wbm_stb_o = (wbm==wbm_data);
264 12 unneback
 
265
always @ (posedge wbm_clk or posedge wbm_rst)
266
if (wbm_rst)
267
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
268
else begin
269
        if (wbm==wbm_adr0 & !b_fifo_empty)
270
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
271
        else if (wbm_eoc_alert & wbm_ack_i)
272
                wbm_cti_o <= endofburst;
273
end
274
 
275
//async_fifo_dw_simplex_top
276 40 unneback
`define MODULE fifo_2r2w_async_simplex
277
`BASE`MODULE
278
`undef MODULE
279 12 unneback
# ( .data_width(36), .addr_width(addr_width))
280
fifo (
281
    // a side
282
    .a_d(a_d),
283
    .a_wr(a_wr),
284
    .a_fifo_full(a_fifo_full),
285
    .a_q(a_q),
286
    .a_rd(a_rd),
287
    .a_fifo_empty(a_fifo_empty),
288
    .a_clk(wbs_clk),
289
    .a_rst(wbs_rst),
290
    // b side
291
    .b_d(b_d),
292
    .b_wr(b_wr),
293
    .b_fifo_full(b_fifo_full),
294
    .b_q(b_q),
295
    .b_rd(b_rd),
296
    .b_fifo_empty(b_fifo_empty),
297
    .b_clk(wbm_clk),
298
    .b_rst(wbm_rst)
299
    );
300
 
301
endmodule
302 40 unneback
`undef WE
303
`undef BTE
304
`undef CTI
305
`endif
306 17 unneback
 
307 75 unneback
`ifdef WB3AVALON_BRIDGE
308
`define MODULE wb3avalon_bridge
309
module `BASE`MODULE (
310
`undef MODULE
311
        // wishbone slave side
312
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
313
        // wishbone master side
314
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
315
 
316
input [31:0] wbs_dat_i;
317
input [31:2] wbs_adr_i;
318
input [3:0]  wbs_sel_i;
319
input [1:0]  wbs_bte_i;
320
input [2:0]  wbs_cti_i;
321
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
322
output [31:0] wbs_dat_o;
323
output wbs_ack_o;
324
input wbs_clk, wbs_rst;
325
 
326
input [31:0] readdata;
327
output [31:0] writedata;
328
output [31:2] address;
329
output [3:0]  be;
330
output write;
331
output read;
332
output beginbursttransfer;
333
output [3:0] burstcount;
334
input readdatavalid;
335
input waitrequest;
336
input clk;
337
input rst;
338
 
339
wire [1:0] wbm_bte_o;
340
wire [2:0] wbm_cti_o;
341
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
342
reg last_cyc;
343
 
344
always @ (posedge clk or posedge rst)
345
if (rst)
346
    last_cyc <= 1'b0;
347
else
348
    last_cyc <= wbm_cyc_o;
349
 
350
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
351
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
352
                    (wbm_bte_o==2'b10) ? 4'd8 :
353
                    4'd16;
354
assign write = wbm_cyc_o & wbm_stb_o &  wbm_we_o;
355
assign read  = wbm_cyc_o & wbm_stb_o & !wbm_we_o;
356
assign wbm_ack_i = (readdatavalid & !waitrequest) | (write & !waitrequest);
357
 
358
`define MODULE wb3wb3_bridge
359
`BASE`MODULE (
360
`undef MODULE
361
    // wishbone slave side
362
    .wbs_dat_i(wbs_dat_i),
363
    .wbs_adr_i(wbs_adr_i),
364
    .wbs_sel_i(wbs_sel_i),
365
    .wbs_bte_i(wbs_bte_i),
366
    .wbs_cti_i(wbs_cti_i),
367
    .wbs_we_i(wbs_we_i),
368
    .wbs_cyc_i(wbs_cyc_i),
369
    .wbs_stb_i(wbs_stb_i),
370
    .wbs_dat_o(wbs_dat_o),
371
    .wbs_ack_o(wbs_ack_o),
372
    .wbs_clk(wbs_clk),
373
    .wbs_rst(wbs_rst),
374
    // wishbone master side
375
    .wbm_dat_o(writedata),
376
    .wbm_adr_o(adress),
377
    .wbm_sel_o(be),
378
    .wbm_bte_o(wbm_bte_o),
379
    .wbm_cti_o(wbm_cti_o),
380
    .wbm_we_o(wbm_we_o),
381
    .wbm_cyc_o(wbm_cyc_o),
382
    .wbm_stb_o(wbm_stb_o),
383
    .wbm_dat_i(readdata),
384
    .wbm_ack_i(wbm_ack_i),
385
    .wbm_clk(clk),
386
    .wbm_rst(rst));
387
 
388
 
389
endmodule
390
`endif
391
 
392 40 unneback
`ifdef WB3_ARBITER_TYPE1
393
`define MODULE wb3_arbiter_type1
394 42 unneback
module `BASE`MODULE (
395 40 unneback
`undef MODULE
396 39 unneback
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
397
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
398
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
399
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
400
    wb_clk, wb_rst
401
);
402
 
403
parameter nr_of_ports = 3;
404
parameter adr_size = 26;
405
parameter adr_lo   = 2;
406
parameter dat_size = 32;
407
parameter sel_size = dat_size/8;
408
 
409
localparam aw = (adr_size - adr_lo) * nr_of_ports;
410
localparam dw = dat_size * nr_of_ports;
411
localparam sw = sel_size * nr_of_ports;
412
localparam cw = 3 * nr_of_ports;
413
localparam bw = 2 * nr_of_ports;
414
 
415
input  [dw-1:0] wbm_dat_o;
416
input  [aw-1:0] wbm_adr_o;
417
input  [sw-1:0] wbm_sel_o;
418
input  [cw-1:0] wbm_cti_o;
419
input  [bw-1:0] wbm_bte_o;
420
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
421
output [dw-1:0] wbm_dat_i;
422
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
423
 
424
output [dat_size-1:0] wbs_dat_i;
425
output [adr_size-1:adr_lo] wbs_adr_i;
426
output [sel_size-1:0] wbs_sel_i;
427
output [2:0] wbs_cti_i;
428
output [1:0] wbs_bte_i;
429
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
430
input  [dat_size-1:0] wbs_dat_o;
431
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
432
 
433
input wb_clk, wb_rst;
434
 
435 44 unneback
reg  [nr_of_ports-1:0] select;
436 39 unneback
wire [nr_of_ports-1:0] state;
437
wire [nr_of_ports-1:0] eoc; // end-of-cycle
438
wire [nr_of_ports-1:0] sel;
439
wire idle;
440
 
441
genvar i;
442
 
443
assign idle = !(|state);
444
 
445
generate
446
if (nr_of_ports == 2) begin
447
 
448
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
449
 
450
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
451
 
452 44 unneback
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
453
 
454
    always @ (idle or wbm_cyc_o)
455
    if (idle)
456
        casex (wbm_cyc_o)
457
        2'b1x : select = 2'b10;
458
        2'b01 : select = 2'b01;
459
        default : select = {nr_of_ports{1'b0}};
460
        endcase
461
    else
462
        select = {nr_of_ports{1'b0}};
463
 
464 39 unneback
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
465
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
466
 
467
end
468
endgenerate
469
 
470
generate
471
if (nr_of_ports == 3) begin
472
 
473
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
474
 
475
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
476
 
477 44 unneback
    always @ (idle or wbm_cyc_o)
478
    if (idle)
479
        casex (wbm_cyc_o)
480
        3'b1xx : select = 3'b100;
481
        3'b01x : select = 3'b010;
482
        3'b001 : select = 3'b001;
483
        default : select = {nr_of_ports{1'b0}};
484
        endcase
485
    else
486
        select = {nr_of_ports{1'b0}};
487
 
488
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
489 39 unneback
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
490
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
491
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
492
 
493
end
494
endgenerate
495
 
496
generate
497 44 unneback
if (nr_of_ports == 4) begin
498
 
499
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
500
 
501
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
502
 
503
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
504
 
505
    always @ (idle or wbm_cyc_o)
506
    if (idle)
507
        casex (wbm_cyc_o)
508
        4'b1xxx : select = 4'b1000;
509
        4'b01xx : select = 4'b0100;
510
        4'b001x : select = 4'b0010;
511
        4'b0001 : select = 4'b0001;
512
        default : select = {nr_of_ports{1'b0}};
513
        endcase
514
    else
515
        select = {nr_of_ports{1'b0}};
516
 
517
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
518
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
519
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
520
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
521
 
522
end
523
endgenerate
524
 
525
generate
526
if (nr_of_ports == 5) begin
527
 
528
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
529
 
530
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
531
 
532
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
533
 
534
    always @ (idle or wbm_cyc_o)
535
    if (idle)
536
        casex (wbm_cyc_o)
537
        5'b1xxxx : select = 5'b10000;
538
        5'b01xxx : select = 5'b01000;
539
        5'b001xx : select = 5'b00100;
540
        5'b0001x : select = 5'b00010;
541
        5'b00001 : select = 5'b00001;
542
        default : select = {nr_of_ports{1'b0}};
543
        endcase
544
    else
545
        select = {nr_of_ports{1'b0}};
546
 
547
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
548
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
549
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
550
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
551
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
552
 
553
end
554
endgenerate
555
 
556
generate
557 67 unneback
if (nr_of_ports == 6) begin
558
 
559
    wire [2:0] wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
560
 
561
    assign {wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
562
 
563
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
564
 
565
    always @ (idle or wbm_cyc_o)
566
    if (idle)
567
        casex (wbm_cyc_o)
568
        6'b1xxxxx : select = 6'b100000;
569
        6'b01xxxx : select = 6'b010000;
570
        6'b001xxx : select = 6'b001000;
571
        6'b0001xx : select = 6'b000100;
572
        6'b00001x : select = 6'b000010;
573
        6'b000001 : select = 6'b000001;
574
        default : select = {nr_of_ports{1'b0}};
575
        endcase
576
    else
577
        select = {nr_of_ports{1'b0}};
578
 
579
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
580
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
581
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
582
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
583
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
584
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
585
 
586
end
587
endgenerate
588
 
589
generate
590
if (nr_of_ports == 7) begin
591
 
592
    wire [2:0] wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
593
 
594
    assign {wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
595
 
596
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
597
 
598
    always @ (idle or wbm_cyc_o)
599
    if (idle)
600
        casex (wbm_cyc_o)
601
        7'b1xxxxxx : select = 7'b1000000;
602
        7'b01xxxxx : select = 7'b0100000;
603
        7'b001xxxx : select = 7'b0010000;
604
        7'b0001xxx : select = 7'b0001000;
605
        7'b00001xx : select = 7'b0000100;
606
        7'b000001x : select = 7'b0000010;
607
        7'b0000001 : select = 7'b0000001;
608
        default : select = {nr_of_ports{1'b0}};
609
        endcase
610
    else
611
        select = {nr_of_ports{1'b0}};
612
 
613
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
614
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
615
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
616
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
617
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
618
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
619
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
620
 
621
end
622
endgenerate
623
 
624
generate
625
if (nr_of_ports == 8) begin
626
 
627
    wire [2:0] wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
628
 
629
    assign {wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
630
 
631
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
632
 
633
    always @ (idle or wbm_cyc_o)
634
    if (idle)
635
        casex (wbm_cyc_o)
636
        8'b1xxxxxxx : select = 8'b10000000;
637
        8'b01xxxxxx : select = 8'b01000000;
638
        8'b001xxxxx : select = 8'b00100000;
639
        8'b0001xxxx : select = 8'b00010000;
640
        8'b00001xxx : select = 8'b00001000;
641
        8'b000001xx : select = 8'b00000100;
642
        8'b0000001x : select = 8'b00000010;
643
        8'b00000001 : select = 8'b00000001;
644
        default : select = {nr_of_ports{1'b0}};
645
        endcase
646
    else
647
        select = {nr_of_ports{1'b0}};
648
 
649
    assign eoc[7] = (wbm_ack_i[7] & (wbm7_cti_o == 3'b000 | wbm7_cti_o == 3'b111)) | !wbm_cyc_o[7];
650
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
651
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
652
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
653
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
654
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
655
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
656
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
657
 
658
end
659
endgenerate
660
 
661
generate
662 63 unneback
for (i=0;i<nr_of_ports;i=i+1) begin : spr0
663 42 unneback
`define MODULE spr
664
    `BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
665
`undef MODULE
666 39 unneback
end
667
endgenerate
668
 
669
    assign sel = select | state;
670
 
671 40 unneback
`define MODULE mux_andor
672
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
673
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
674
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
675
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
676
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
677
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
678
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
679
`undef MODULE
680 39 unneback
    assign wbs_cyc_i = |sel;
681
 
682
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
683
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
684
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
685
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
686
 
687
endmodule
688 40 unneback
`endif
689 39 unneback
 
690 60 unneback
`ifdef WB_B3_RAM_BE
691 49 unneback
// WB RAM with byte enable
692 59 unneback
`define MODULE wb_b3_ram_be
693
module `BASE`MODULE (
694
`undef MODULE
695 69 unneback
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
696
    wbs_dat_o, wbs_ack_o, wb_clk, wb_rst);
697 59 unneback
 
698 68 unneback
parameter adr_size = 16;
699 60 unneback
parameter adr_lo   = 2;
700 68 unneback
parameter mem_size = 1<<16;
701 60 unneback
parameter dat_size = 32;
702
parameter memory_init = 1;
703
parameter memory_file = "vl_ram.vmem";
704 59 unneback
 
705 69 unneback
localparam aw = (adr_size - adr_lo);
706
localparam dw = dat_size;
707
localparam sw = dat_size/8;
708
localparam cw = 3;
709
localparam bw = 2;
710 60 unneback
 
711 70 unneback
input [dw-1:0] wbs_dat_i;
712
input [aw-1:0] wbs_adr_i;
713
input [cw-1:0] wbs_cti_i;
714
input [bw-1:0] wbs_bte_i;
715
input [sw-1:0] wbs_sel_i;
716
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
717
output [dw-1:0] wbs_dat_o;
718
output wbs_ack_o;
719 71 unneback
input wb_clk, wb_rst;
720 59 unneback
 
721 60 unneback
wire [sw-1:0] cke;
722 59 unneback
 
723 60 unneback
reg wbs_ack_o;
724
 
725
`define MODULE ram_be
726
`BASE`MODULE # (
727
    .data_width(dat_size),
728 72 unneback
    .addr_width(adr_size-2),
729 69 unneback
    .mem_size(mem_size),
730 68 unneback
    .memory_init(memory_init),
731
    .memory_file(memory_file))
732 60 unneback
ram0(
733
`undef MODULE
734
    .d(wbs_dat_i),
735
    .adr(wbs_adr_i[adr_size-1:2]),
736
    .be(wbs_sel_i),
737
    .we(wbs_we_i),
738
    .q(wbs_dat_o),
739
    .clk(wb_clk)
740
);
741
 
742 59 unneback
always @ (posedge wb_clk or posedge wb_rst)
743
if (wb_rst)
744 60 unneback
    wbs_ack_o <= 1'b0;
745 59 unneback
else
746 60 unneback
    if (wbs_cti_i==3'b000 | wbs_cti_i==3'b111)
747
        wbs_ack_o <= wbs_stb_i & wbs_cyc_i & !wbs_ack_o;
748 59 unneback
    else
749 60 unneback
        wbs_ack_o <= wbs_stb_i & wbs_cyc_i;
750
 
751 59 unneback
endmodule
752
`endif
753
 
754
`ifdef WB_B4_RAM_BE
755
// WB RAM with byte enable
756 49 unneback
`define MODULE wb_b4_ram_be
757
module `BASE`MODULE (
758
`undef MODULE
759
    wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
760 52 unneback
    wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
761 49 unneback
 
762
    parameter dat_width = 32;
763
    parameter adr_width = 8;
764
 
765
input [dat_width-1:0] wb_dat_i;
766
input [adr_width-1:0] wb_adr_i;
767
input [dat_width/8-1:0] wb_sel_i;
768
input wb_we_i, wb_stb_i, wb_cyc_i;
769
output [dat_width-1:0] wb_dat_o;
770 51 unneback
reg [dat_width-1:0] wb_dat_o;
771 52 unneback
output wb_stall_o;
772 49 unneback
output wb_ack_o;
773
reg wb_ack_o;
774
input wb_clk, wb_rst;
775
 
776 56 unneback
wire [dat_width/8-1:0] cke;
777
 
778 49 unneback
generate
779
if (dat_width==32) begin
780 51 unneback
reg [7:0] ram3 [1<<(adr_width-2)-1:0];
781
reg [7:0] ram2 [1<<(adr_width-2)-1:0];
782
reg [7:0] ram1 [1<<(adr_width-2)-1:0];
783
reg [7:0] ram0 [1<<(adr_width-2)-1:0];
784 56 unneback
assign cke = wb_sel_i & {(dat_width/8){wb_we_i}};
785 49 unneback
    always @ (posedge wb_clk)
786
    begin
787 56 unneback
        if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
788
        if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
789
        if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
790
        if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
791 49 unneback
    end
792 59 unneback
    always @ (posedge wb_clk or posedge wb_rst)
793
    begin
794
        if (wb_rst)
795
            wb_dat_o <= 32'h0;
796
        else
797
            wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
798
    end
799 49 unneback
end
800
endgenerate
801
 
802 52 unneback
always @ (posedge wb_clk or posedge wb_rst)
803 55 unneback
if (wb_rst)
804 52 unneback
    wb_ack_o <= 1'b0;
805
else
806 54 unneback
    wb_ack_o <= wb_stb_i & wb_cyc_i;
807 52 unneback
 
808
assign wb_stall_o = 1'b0;
809
 
810 49 unneback
endmodule
811
`endif
812
 
813 48 unneback
`ifdef WB_B4_ROM
814
// WB ROM
815
`define MODULE wb_b4_rom
816
module `BASE`MODULE (
817
`undef MODULE
818
    wb_adr_i, wb_stb_i, wb_cyc_i,
819
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
820
 
821
    parameter dat_width = 32;
822
    parameter dat_default = 32'h15000000;
823
    parameter adr_width = 32;
824
 
825
/*
826
//E2_ifndef ROM
827
//E2_define ROM "rom.v"
828
//E2_endif
829
*/
830
    input [adr_width-1:2]   wb_adr_i;
831
    input                   wb_stb_i;
832
    input                   wb_cyc_i;
833
    output [dat_width-1:0]  wb_dat_o;
834
    reg [dat_width-1:0]     wb_dat_o;
835
    output                  wb_ack_o;
836
    reg                     wb_ack_o;
837
    output                  stall_o;
838
    input                   wb_clk;
839
    input                   wb_rst;
840
 
841
always @ (posedge wb_clk or posedge wb_rst)
842
    if (wb_rst)
843
        wb_dat_o <= {dat_width{1'b0}};
844
    else
845
         case (wb_adr_i[adr_width-1:2])
846
//E2_ifdef ROM
847
//E2_include `ROM
848
//E2_endif
849
           default:
850
             wb_dat_o <= dat_default;
851
 
852
         endcase // case (wb_adr_i)
853
 
854
 
855
always @ (posedge wb_clk or posedge wb_rst)
856
    if (wb_rst)
857
        wb_ack_o <= 1'b0;
858
    else
859
        wb_ack_o <= wb_stb_i & wb_cyc_i;
860
 
861
assign stall_o = 1'b0;
862
 
863
endmodule
864
`endif
865
 
866
 
867 40 unneback
`ifdef WB_BOOT_ROM
868 17 unneback
// WB ROM
869 40 unneback
`define MODULE wb_boot_rom
870
module `BASE`MODULE (
871
`undef MODULE
872 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
873 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
874 17 unneback
 
875 18 unneback
    parameter adr_hi = 31;
876
    parameter adr_lo = 28;
877
    parameter adr_sel = 4'hf;
878
    parameter addr_width = 5;
879 33 unneback
/*
880 17 unneback
//E2_ifndef BOOT_ROM
881
//E2_define BOOT_ROM "boot_rom.v"
882
//E2_endif
883 33 unneback
*/
884 18 unneback
    input [adr_hi:2]    wb_adr_i;
885
    input               wb_stb_i;
886
    input               wb_cyc_i;
887
    output [31:0]        wb_dat_o;
888
    output              wb_ack_o;
889
    output              hit_o;
890
    input               wb_clk;
891
    input               wb_rst;
892
 
893
    wire hit;
894
    reg [31:0] wb_dat;
895
    reg wb_ack;
896
 
897
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
898 17 unneback
 
899
always @ (posedge wb_clk or posedge wb_rst)
900
    if (wb_rst)
901 18 unneback
        wb_dat <= 32'h15000000;
902 17 unneback
    else
903 18 unneback
         case (wb_adr_i[addr_width-1:2])
904 33 unneback
//E2_ifdef BOOT_ROM
905 17 unneback
//E2_include `BOOT_ROM
906 33 unneback
//E2_endif
907 17 unneback
           /*
908
            // Zero r0 and jump to 0x00000100
909 18 unneback
 
910
            1 : wb_dat <= 32'hA8200000;
911
            2 : wb_dat <= 32'hA8C00100;
912
            3 : wb_dat <= 32'h44003000;
913
            4 : wb_dat <= 32'h15000000;
914 17 unneback
            */
915
           default:
916 18 unneback
             wb_dat <= 32'h00000000;
917 17 unneback
 
918
         endcase // case (wb_adr_i)
919
 
920
 
921
always @ (posedge wb_clk or posedge wb_rst)
922
    if (wb_rst)
923 18 unneback
        wb_ack <= 1'b0;
924 17 unneback
    else
925 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
926 17 unneback
 
927 18 unneback
assign hit_o = hit;
928
assign wb_dat_o = wb_dat & {32{wb_ack}};
929
assign wb_ack_o = wb_ack;
930
 
931 17 unneback
endmodule
932 40 unneback
`endif
933 32 unneback
 
934 40 unneback
`ifdef WB_DPRAM
935
`define MODULE wb_dpram
936
module `BASE`MODULE (
937
`undef MODULE
938 32 unneback
        // wishbone slave side a
939
        wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
940
        wbsa_clk, wbsa_rst,
941
        // wishbone slave side a
942
        wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
943
        wbsb_clk, wbsb_rst);
944
 
945
parameter data_width = 32;
946
parameter addr_width = 8;
947
 
948
parameter dat_o_mask_a = 1;
949
parameter dat_o_mask_b = 1;
950
 
951
input [31:0] wbsa_dat_i;
952
input [addr_width-1:2] wbsa_adr_i;
953
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
954
output [31:0] wbsa_dat_o;
955
output wbsa_ack_o;
956
input wbsa_clk, wbsa_rst;
957
 
958
input [31:0] wbsb_dat_i;
959
input [addr_width-1:2] wbsb_adr_i;
960
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
961
output [31:0] wbsb_dat_o;
962
output wbsb_ack_o;
963
input wbsb_clk, wbsb_rst;
964
 
965
wire wbsa_dat_tmp, wbsb_dat_tmp;
966
 
967 40 unneback
`define MODULE dpram_2r2w
968
`BASE`MODULE # (
969
`undef MODULE
970 33 unneback
    .data_width(data_width), .addr_width(addr_width) )
971 32 unneback
dpram0(
972
    .d_a(wbsa_dat_i),
973
    .q_a(wbsa_dat_tmp),
974
    .adr_a(wbsa_adr_i),
975
    .we_a(wbsa_we_i),
976
    .clk_a(wbsa_clk),
977
    .d_b(wbsb_dat_i),
978
    .q_b(wbsb_dat_tmp),
979
    .adr_b(wbsb_adr_i),
980
    .we_b(wbsb_we_i),
981
    .clk_b(wbsb_clk) );
982
 
983 33 unneback
generate if (dat_o_mask_a==1)
984 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
985
endgenerate
986 33 unneback
generate if (dat_o_mask_a==0)
987 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp;
988
endgenerate
989
 
990 33 unneback
generate if (dat_o_mask_b==1)
991 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
992
endgenerate
993 33 unneback
generate if (dat_o_mask_b==0)
994 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp;
995
endgenerate
996
 
997 40 unneback
`define MODULE spr
998
`BASE`MODULE ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
999
`BASE`MODULE ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
1000
`undef MODULE
1001 32 unneback
 
1002
endmodule
1003 40 unneback
`endif

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.