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1 12 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Versatile library, wishbone stuff                           ////
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////                                                              ////
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////  Description                                                 ////
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////  Wishbone compliant modules                                  ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   -                                                          ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42
 
43 75 unneback
`ifdef WB_ADR_INC
44
// async wb3 - wb3 bridge
45
`timescale 1ns/1ns
46
`define MODULE wb_adr_inc
47
module `BASE`MODULE (
48
`undef MODULE
49
 
50
    always @ (posedge clk or posedge rst)
51
        if (rst)
52
           col_reg <= {col_reg_width{1'b0}};
53
        else
54
            case (state)
55
            `FSM_IDLE:
56
               col_reg <= col[col_reg_width-1:0];
57
            `FSM_RW:
58
               if (~stall)
59
                  case (bte_i)
60
`ifdef SDR_BEAT4
61
                        beat4:  col_reg[2:0] <= col_reg[2:0] + 3'd1;
62
`endif
63
`ifdef SDR_BEAT8
64
                        beat8:  col_reg[3:0] <= col_reg[3:0] + 4'd1;
65
`endif
66
`ifdef SDR_BEAT16
67
                        beat16: col_reg[4:0] <= col_reg[4:0] + 5'd1;
68
`endif
69
                  endcase
70
            endcase
71
`endif
72
 
73 40 unneback
`ifdef WB3WB3_BRIDGE
74 12 unneback
// async wb3 - wb3 bridge
75
`timescale 1ns/1ns
76 40 unneback
`define MODULE wb3wb3_bridge
77
module `BASE`MODULE (
78
`undef MODULE
79 12 unneback
        // wishbone slave side
80
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
81
        // wishbone master side
82
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
83
 
84
input [31:0] wbs_dat_i;
85
input [31:2] wbs_adr_i;
86
input [3:0]  wbs_sel_i;
87
input [1:0]  wbs_bte_i;
88
input [2:0]  wbs_cti_i;
89
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
90
output [31:0] wbs_dat_o;
91 14 unneback
output wbs_ack_o;
92 12 unneback
input wbs_clk, wbs_rst;
93
 
94
output [31:0] wbm_dat_o;
95
output reg [31:2] wbm_adr_o;
96
output [3:0]  wbm_sel_o;
97
output reg [1:0]  wbm_bte_o;
98
output reg [2:0]  wbm_cti_o;
99 14 unneback
output reg wbm_we_o;
100
output wbm_cyc_o;
101 12 unneback
output wbm_stb_o;
102
input [31:0]  wbm_dat_i;
103
input wbm_ack_i;
104
input wbm_clk, wbm_rst;
105
 
106
parameter addr_width = 4;
107
 
108
// bte
109
parameter linear       = 2'b00;
110
parameter wrap4        = 2'b01;
111
parameter wrap8        = 2'b10;
112
parameter wrap16       = 2'b11;
113
// cti
114
parameter classic      = 3'b000;
115
parameter incburst     = 3'b010;
116
parameter endofburst   = 3'b111;
117
 
118
parameter wbs_adr  = 1'b0;
119
parameter wbs_data = 1'b1;
120
 
121 33 unneback
parameter wbm_adr0      = 2'b00;
122
parameter wbm_adr1      = 2'b01;
123
parameter wbm_data      = 2'b10;
124
parameter wbm_data_wait = 2'b11;
125 12 unneback
 
126
reg [1:0] wbs_bte_reg;
127
reg wbs;
128
wire wbs_eoc_alert, wbm_eoc_alert;
129
reg wbs_eoc, wbm_eoc;
130
reg [1:0] wbm;
131
 
132 14 unneback
wire [1:16] wbs_count, wbm_count;
133 12 unneback
 
134
wire [35:0] a_d, a_q, b_d, b_q;
135
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
136
reg a_rd_reg;
137
wire b_rd_adr, b_rd_data;
138 14 unneback
wire b_rd_data_reg;
139
wire [35:0] temp;
140 12 unneback
 
141
`define WE 5
142
`define BTE 4:3
143
`define CTI 2:0
144
 
145
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
146
always @ (posedge wbs_clk or posedge wbs_rst)
147
if (wbs_rst)
148
        wbs_eoc <= 1'b0;
149
else
150
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
151 78 unneback
                wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111);
152 12 unneback
        else if (wbs_eoc_alert & (a_rd | a_wr))
153
                wbs_eoc <= 1'b1;
154
 
155 40 unneback
`define MODULE cnt_shreg_ce_clear
156
`BASE`MODULE # ( .length(16))
157
`undef MODULE
158 12 unneback
    cnt0 (
159
        .cke(wbs_ack_o),
160
        .clear(wbs_eoc),
161
        .q(wbs_count),
162
        .rst(wbs_rst),
163
        .clk(wbs_clk));
164
 
165
always @ (posedge wbs_clk or posedge wbs_rst)
166
if (wbs_rst)
167
        wbs <= wbs_adr;
168
else
169 75 unneback
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)
170 12 unneback
                wbs <= wbs_data;
171
        else if (wbs_eoc & wbs_ack_o)
172
                wbs <= wbs_adr;
173
 
174
// wbs FIFO
175 75 unneback
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};
176
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :
177 12 unneback
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
178
              1'b0;
179
assign a_rd = !a_fifo_empty;
180
always @ (posedge wbs_clk or posedge wbs_rst)
181
if (wbs_rst)
182
        a_rd_reg <= 1'b0;
183
else
184
        a_rd_reg <= a_rd;
185
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
186
 
187
assign wbs_dat_o = a_q[35:4];
188
 
189
always @ (posedge wbs_clk or posedge wbs_rst)
190
if (wbs_rst)
191 13 unneback
        wbs_bte_reg <= 2'b00;
192 12 unneback
else
193 13 unneback
        wbs_bte_reg <= wbs_bte_i;
194 12 unneback
 
195
// wbm FIFO
196
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
197
always @ (posedge wbm_clk or posedge wbm_rst)
198
if (wbm_rst)
199
        wbm_eoc <= 1'b0;
200
else
201
        if (wbm==wbm_adr0 & !b_fifo_empty)
202
                wbm_eoc <= b_q[`BTE] == linear;
203
        else if (wbm_eoc_alert & wbm_ack_i)
204
                wbm_eoc <= 1'b1;
205
 
206
always @ (posedge wbm_clk or posedge wbm_rst)
207
if (wbm_rst)
208
        wbm <= wbm_adr0;
209
else
210 33 unneback
/*
211 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
212
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
213
        (wbm==wbm_adr1 & !wbm_we_o) |
214
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
215
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
216 33 unneback
*/
217
    case (wbm)
218
    wbm_adr0:
219
        if (!b_fifo_empty)
220
            wbm <= wbm_adr1;
221
    wbm_adr1:
222
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
223
            wbm <= wbm_data;
224
    wbm_data:
225
        if (wbm_ack_i & wbm_eoc)
226
            wbm <= wbm_adr0;
227
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
228
            wbm <= wbm_data_wait;
229
    wbm_data_wait:
230
        if (!b_fifo_empty)
231
            wbm <= wbm_data;
232
    endcase
233 12 unneback
 
234
assign b_d = {wbm_dat_i,4'b1111};
235
assign b_wr = !wbm_we_o & wbm_ack_i;
236
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
237
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
238
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
239 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
240 12 unneback
                   1'b0;
241
assign b_rd = b_rd_adr | b_rd_data;
242
 
243 40 unneback
`define MODULE dff
244
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
245
`undef MODULE
246
`define MODULE dff_ce
247
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
248
`undef MODULE
249 12 unneback
 
250
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
251
 
252 40 unneback
`define MODULE cnt_shreg_ce_clear
253 42 unneback
`BASE`MODULE # ( .length(16))
254 40 unneback
`undef MODULE
255 12 unneback
    cnt1 (
256
        .cke(wbm_ack_i),
257
        .clear(wbm_eoc),
258
        .q(wbm_count),
259
        .rst(wbm_rst),
260
        .clk(wbm_clk));
261
 
262 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
263
assign wbm_stb_o = (wbm==wbm_data);
264 12 unneback
 
265
always @ (posedge wbm_clk or posedge wbm_rst)
266
if (wbm_rst)
267
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
268
else begin
269
        if (wbm==wbm_adr0 & !b_fifo_empty)
270
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
271
        else if (wbm_eoc_alert & wbm_ack_i)
272
                wbm_cti_o <= endofburst;
273
end
274
 
275
//async_fifo_dw_simplex_top
276 40 unneback
`define MODULE fifo_2r2w_async_simplex
277
`BASE`MODULE
278
`undef MODULE
279 12 unneback
# ( .data_width(36), .addr_width(addr_width))
280
fifo (
281
    // a side
282
    .a_d(a_d),
283
    .a_wr(a_wr),
284
    .a_fifo_full(a_fifo_full),
285
    .a_q(a_q),
286
    .a_rd(a_rd),
287
    .a_fifo_empty(a_fifo_empty),
288
    .a_clk(wbs_clk),
289
    .a_rst(wbs_rst),
290
    // b side
291
    .b_d(b_d),
292
    .b_wr(b_wr),
293
    .b_fifo_full(b_fifo_full),
294
    .b_q(b_q),
295
    .b_rd(b_rd),
296
    .b_fifo_empty(b_fifo_empty),
297
    .b_clk(wbm_clk),
298
    .b_rst(wbm_rst)
299
    );
300
 
301
endmodule
302 40 unneback
`undef WE
303
`undef BTE
304
`undef CTI
305
`endif
306 17 unneback
 
307 75 unneback
`ifdef WB3AVALON_BRIDGE
308
`define MODULE wb3avalon_bridge
309
module `BASE`MODULE (
310
`undef MODULE
311
        // wishbone slave side
312
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
313 77 unneback
        // avalon master side
314 75 unneback
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
315
 
316
input [31:0] wbs_dat_i;
317
input [31:2] wbs_adr_i;
318
input [3:0]  wbs_sel_i;
319
input [1:0]  wbs_bte_i;
320
input [2:0]  wbs_cti_i;
321
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
322
output [31:0] wbs_dat_o;
323
output wbs_ack_o;
324
input wbs_clk, wbs_rst;
325
 
326
input [31:0] readdata;
327
output [31:0] writedata;
328
output [31:2] address;
329
output [3:0]  be;
330
output write;
331 81 unneback
output read;
332 75 unneback
output beginbursttransfer;
333
output [3:0] burstcount;
334
input readdatavalid;
335
input waitrequest;
336
input clk;
337
input rst;
338
 
339
wire [1:0] wbm_bte_o;
340
wire [2:0] wbm_cti_o;
341
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
342
reg last_cyc;
343 79 unneback
reg [3:0] counter;
344 82 unneback
reg read_busy;
345 75 unneback
 
346
always @ (posedge clk or posedge rst)
347
if (rst)
348
    last_cyc <= 1'b0;
349
else
350
    last_cyc <= wbm_cyc_o;
351
 
352 79 unneback
always @ (posedge clk or posedge rst)
353
if (rst)
354 82 unneback
    read_busy <= 1'b0;
355 79 unneback
else
356 82 unneback
    if (read & !waitrequest)
357
        read_busy <= 1'b1;
358
    else if (wbm_ack_i & wbm_cti_o!=3'b010)
359
        read_busy <= 1'b0;
360
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;
361 81 unneback
 
362 75 unneback
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
363
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
364
                    (wbm_bte_o==2'b10) ? 4'd8 :
365 78 unneback
                    (wbm_bte_o==2'b11) ? 4'd16:
366
                    4'd1;
367 82 unneback
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);
368 75 unneback
 
369 79 unneback
always @ (posedge clk or posedge rst)
370
if (rst) begin
371
    counter <= 4'd0;
372
end else
373 80 unneback
    if (wbm_we_o) begin
374
        if (!waitrequest & !last_cyc & wbm_cyc_o) begin
375
            counter <= burstcount -1;
376
        end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
377
            counter <= burstcount;
378
        end else if (!waitrequest & wbm_stb_o) begin
379
            counter <= counter - 4'd1;
380
        end
381 82 unneback
    end
382 81 unneback
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
383 79 unneback
 
384 75 unneback
`define MODULE wb3wb3_bridge
385 77 unneback
`BASE`MODULE wbwb3inst (
386 75 unneback
`undef MODULE
387
    // wishbone slave side
388
    .wbs_dat_i(wbs_dat_i),
389
    .wbs_adr_i(wbs_adr_i),
390
    .wbs_sel_i(wbs_sel_i),
391
    .wbs_bte_i(wbs_bte_i),
392
    .wbs_cti_i(wbs_cti_i),
393
    .wbs_we_i(wbs_we_i),
394
    .wbs_cyc_i(wbs_cyc_i),
395
    .wbs_stb_i(wbs_stb_i),
396
    .wbs_dat_o(wbs_dat_o),
397
    .wbs_ack_o(wbs_ack_o),
398
    .wbs_clk(wbs_clk),
399
    .wbs_rst(wbs_rst),
400
    // wishbone master side
401
    .wbm_dat_o(writedata),
402 78 unneback
    .wbm_adr_o(address),
403 75 unneback
    .wbm_sel_o(be),
404
    .wbm_bte_o(wbm_bte_o),
405
    .wbm_cti_o(wbm_cti_o),
406
    .wbm_we_o(wbm_we_o),
407
    .wbm_cyc_o(wbm_cyc_o),
408
    .wbm_stb_o(wbm_stb_o),
409
    .wbm_dat_i(readdata),
410
    .wbm_ack_i(wbm_ack_i),
411
    .wbm_clk(clk),
412
    .wbm_rst(rst));
413
 
414
 
415
endmodule
416
`endif
417
 
418 40 unneback
`ifdef WB3_ARBITER_TYPE1
419
`define MODULE wb3_arbiter_type1
420 42 unneback
module `BASE`MODULE (
421 40 unneback
`undef MODULE
422 39 unneback
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
423
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
424
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
425
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
426
    wb_clk, wb_rst
427
);
428
 
429
parameter nr_of_ports = 3;
430
parameter adr_size = 26;
431
parameter adr_lo   = 2;
432
parameter dat_size = 32;
433
parameter sel_size = dat_size/8;
434
 
435
localparam aw = (adr_size - adr_lo) * nr_of_ports;
436
localparam dw = dat_size * nr_of_ports;
437
localparam sw = sel_size * nr_of_ports;
438
localparam cw = 3 * nr_of_ports;
439
localparam bw = 2 * nr_of_ports;
440
 
441
input  [dw-1:0] wbm_dat_o;
442
input  [aw-1:0] wbm_adr_o;
443
input  [sw-1:0] wbm_sel_o;
444
input  [cw-1:0] wbm_cti_o;
445
input  [bw-1:0] wbm_bte_o;
446
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
447
output [dw-1:0] wbm_dat_i;
448
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
449
 
450
output [dat_size-1:0] wbs_dat_i;
451
output [adr_size-1:adr_lo] wbs_adr_i;
452
output [sel_size-1:0] wbs_sel_i;
453
output [2:0] wbs_cti_i;
454
output [1:0] wbs_bte_i;
455
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
456
input  [dat_size-1:0] wbs_dat_o;
457
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
458
 
459
input wb_clk, wb_rst;
460
 
461 44 unneback
reg  [nr_of_ports-1:0] select;
462 39 unneback
wire [nr_of_ports-1:0] state;
463
wire [nr_of_ports-1:0] eoc; // end-of-cycle
464
wire [nr_of_ports-1:0] sel;
465
wire idle;
466
 
467
genvar i;
468
 
469
assign idle = !(|state);
470
 
471
generate
472
if (nr_of_ports == 2) begin
473
 
474
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
475
 
476
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
477
 
478 44 unneback
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
479
 
480
    always @ (idle or wbm_cyc_o)
481
    if (idle)
482
        casex (wbm_cyc_o)
483
        2'b1x : select = 2'b10;
484
        2'b01 : select = 2'b01;
485
        default : select = {nr_of_ports{1'b0}};
486
        endcase
487
    else
488
        select = {nr_of_ports{1'b0}};
489
 
490 39 unneback
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
491
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
492
 
493
end
494
endgenerate
495
 
496
generate
497
if (nr_of_ports == 3) begin
498
 
499
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
500
 
501
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
502
 
503 44 unneback
    always @ (idle or wbm_cyc_o)
504
    if (idle)
505
        casex (wbm_cyc_o)
506
        3'b1xx : select = 3'b100;
507
        3'b01x : select = 3'b010;
508
        3'b001 : select = 3'b001;
509
        default : select = {nr_of_ports{1'b0}};
510
        endcase
511
    else
512
        select = {nr_of_ports{1'b0}};
513
 
514
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
515 39 unneback
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
516
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
517
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
518
 
519
end
520
endgenerate
521
 
522
generate
523 44 unneback
if (nr_of_ports == 4) begin
524
 
525
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
526
 
527
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
528
 
529
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
530
 
531
    always @ (idle or wbm_cyc_o)
532
    if (idle)
533
        casex (wbm_cyc_o)
534
        4'b1xxx : select = 4'b1000;
535
        4'b01xx : select = 4'b0100;
536
        4'b001x : select = 4'b0010;
537
        4'b0001 : select = 4'b0001;
538
        default : select = {nr_of_ports{1'b0}};
539
        endcase
540
    else
541
        select = {nr_of_ports{1'b0}};
542
 
543
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
544
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
545
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
546
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
547
 
548
end
549
endgenerate
550
 
551
generate
552
if (nr_of_ports == 5) begin
553
 
554
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
555
 
556
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
557
 
558
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
559
 
560
    always @ (idle or wbm_cyc_o)
561
    if (idle)
562
        casex (wbm_cyc_o)
563
        5'b1xxxx : select = 5'b10000;
564
        5'b01xxx : select = 5'b01000;
565
        5'b001xx : select = 5'b00100;
566
        5'b0001x : select = 5'b00010;
567
        5'b00001 : select = 5'b00001;
568
        default : select = {nr_of_ports{1'b0}};
569
        endcase
570
    else
571
        select = {nr_of_ports{1'b0}};
572
 
573
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
574
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
575
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
576
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
577
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
578
 
579
end
580
endgenerate
581
 
582
generate
583 67 unneback
if (nr_of_ports == 6) begin
584
 
585
    wire [2:0] wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
586
 
587
    assign {wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
588
 
589
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
590
 
591
    always @ (idle or wbm_cyc_o)
592
    if (idle)
593
        casex (wbm_cyc_o)
594
        6'b1xxxxx : select = 6'b100000;
595
        6'b01xxxx : select = 6'b010000;
596
        6'b001xxx : select = 6'b001000;
597
        6'b0001xx : select = 6'b000100;
598
        6'b00001x : select = 6'b000010;
599
        6'b000001 : select = 6'b000001;
600
        default : select = {nr_of_ports{1'b0}};
601
        endcase
602
    else
603
        select = {nr_of_ports{1'b0}};
604
 
605
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
606
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
607
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
608
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
609
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
610
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
611
 
612
end
613
endgenerate
614
 
615
generate
616
if (nr_of_ports == 7) begin
617
 
618
    wire [2:0] wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
619
 
620
    assign {wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
621
 
622
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
623
 
624
    always @ (idle or wbm_cyc_o)
625
    if (idle)
626
        casex (wbm_cyc_o)
627
        7'b1xxxxxx : select = 7'b1000000;
628
        7'b01xxxxx : select = 7'b0100000;
629
        7'b001xxxx : select = 7'b0010000;
630
        7'b0001xxx : select = 7'b0001000;
631
        7'b00001xx : select = 7'b0000100;
632
        7'b000001x : select = 7'b0000010;
633
        7'b0000001 : select = 7'b0000001;
634
        default : select = {nr_of_ports{1'b0}};
635
        endcase
636
    else
637
        select = {nr_of_ports{1'b0}};
638
 
639
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
640
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
641
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
642
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
643
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
644
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
645
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
646
 
647
end
648
endgenerate
649
 
650
generate
651
if (nr_of_ports == 8) begin
652
 
653
    wire [2:0] wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
654
 
655
    assign {wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
656
 
657
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
658
 
659
    always @ (idle or wbm_cyc_o)
660
    if (idle)
661
        casex (wbm_cyc_o)
662
        8'b1xxxxxxx : select = 8'b10000000;
663
        8'b01xxxxxx : select = 8'b01000000;
664
        8'b001xxxxx : select = 8'b00100000;
665
        8'b0001xxxx : select = 8'b00010000;
666
        8'b00001xxx : select = 8'b00001000;
667
        8'b000001xx : select = 8'b00000100;
668
        8'b0000001x : select = 8'b00000010;
669
        8'b00000001 : select = 8'b00000001;
670
        default : select = {nr_of_ports{1'b0}};
671
        endcase
672
    else
673
        select = {nr_of_ports{1'b0}};
674
 
675
    assign eoc[7] = (wbm_ack_i[7] & (wbm7_cti_o == 3'b000 | wbm7_cti_o == 3'b111)) | !wbm_cyc_o[7];
676
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
677
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
678
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
679
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
680
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
681
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
682
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
683
 
684
end
685
endgenerate
686
 
687
generate
688 63 unneback
for (i=0;i<nr_of_ports;i=i+1) begin : spr0
689 42 unneback
`define MODULE spr
690
    `BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
691
`undef MODULE
692 39 unneback
end
693
endgenerate
694
 
695
    assign sel = select | state;
696
 
697 40 unneback
`define MODULE mux_andor
698
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
699
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
700
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
701
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
702
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
703
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
704
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
705
`undef MODULE
706 39 unneback
    assign wbs_cyc_i = |sel;
707
 
708
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
709
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
710
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
711
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
712
 
713
endmodule
714 40 unneback
`endif
715 39 unneback
 
716 60 unneback
`ifdef WB_B3_RAM_BE
717 49 unneback
// WB RAM with byte enable
718 59 unneback
`define MODULE wb_b3_ram_be
719
module `BASE`MODULE (
720
`undef MODULE
721 69 unneback
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
722
    wbs_dat_o, wbs_ack_o, wb_clk, wb_rst);
723 59 unneback
 
724 68 unneback
parameter adr_size = 16;
725 60 unneback
parameter adr_lo   = 2;
726 68 unneback
parameter mem_size = 1<<16;
727 60 unneback
parameter dat_size = 32;
728
parameter memory_init = 1;
729
parameter memory_file = "vl_ram.vmem";
730 59 unneback
 
731 69 unneback
localparam aw = (adr_size - adr_lo);
732
localparam dw = dat_size;
733
localparam sw = dat_size/8;
734
localparam cw = 3;
735
localparam bw = 2;
736 60 unneback
 
737 70 unneback
input [dw-1:0] wbs_dat_i;
738
input [aw-1:0] wbs_adr_i;
739
input [cw-1:0] wbs_cti_i;
740
input [bw-1:0] wbs_bte_i;
741
input [sw-1:0] wbs_sel_i;
742
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
743
output [dw-1:0] wbs_dat_o;
744
output wbs_ack_o;
745 71 unneback
input wb_clk, wb_rst;
746 59 unneback
 
747 60 unneback
wire [sw-1:0] cke;
748 59 unneback
 
749 60 unneback
reg wbs_ack_o;
750
 
751
`define MODULE ram_be
752
`BASE`MODULE # (
753
    .data_width(dat_size),
754 72 unneback
    .addr_width(adr_size-2),
755 69 unneback
    .mem_size(mem_size),
756 68 unneback
    .memory_init(memory_init),
757
    .memory_file(memory_file))
758 60 unneback
ram0(
759
`undef MODULE
760
    .d(wbs_dat_i),
761
    .adr(wbs_adr_i[adr_size-1:2]),
762
    .be(wbs_sel_i),
763
    .we(wbs_we_i),
764
    .q(wbs_dat_o),
765
    .clk(wb_clk)
766
);
767
 
768 59 unneback
always @ (posedge wb_clk or posedge wb_rst)
769
if (wb_rst)
770 60 unneback
    wbs_ack_o <= 1'b0;
771 59 unneback
else
772 60 unneback
    if (wbs_cti_i==3'b000 | wbs_cti_i==3'b111)
773
        wbs_ack_o <= wbs_stb_i & wbs_cyc_i & !wbs_ack_o;
774 59 unneback
    else
775 60 unneback
        wbs_ack_o <= wbs_stb_i & wbs_cyc_i;
776
 
777 59 unneback
endmodule
778
`endif
779
 
780
`ifdef WB_B4_RAM_BE
781
// WB RAM with byte enable
782 49 unneback
`define MODULE wb_b4_ram_be
783
module `BASE`MODULE (
784
`undef MODULE
785
    wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
786 52 unneback
    wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
787 49 unneback
 
788
    parameter dat_width = 32;
789
    parameter adr_width = 8;
790
 
791
input [dat_width-1:0] wb_dat_i;
792
input [adr_width-1:0] wb_adr_i;
793
input [dat_width/8-1:0] wb_sel_i;
794
input wb_we_i, wb_stb_i, wb_cyc_i;
795
output [dat_width-1:0] wb_dat_o;
796 51 unneback
reg [dat_width-1:0] wb_dat_o;
797 52 unneback
output wb_stall_o;
798 49 unneback
output wb_ack_o;
799
reg wb_ack_o;
800
input wb_clk, wb_rst;
801
 
802 56 unneback
wire [dat_width/8-1:0] cke;
803
 
804 49 unneback
generate
805
if (dat_width==32) begin
806 51 unneback
reg [7:0] ram3 [1<<(adr_width-2)-1:0];
807
reg [7:0] ram2 [1<<(adr_width-2)-1:0];
808
reg [7:0] ram1 [1<<(adr_width-2)-1:0];
809
reg [7:0] ram0 [1<<(adr_width-2)-1:0];
810 56 unneback
assign cke = wb_sel_i & {(dat_width/8){wb_we_i}};
811 49 unneback
    always @ (posedge wb_clk)
812
    begin
813 56 unneback
        if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
814
        if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
815
        if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
816
        if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
817 49 unneback
    end
818 59 unneback
    always @ (posedge wb_clk or posedge wb_rst)
819
    begin
820
        if (wb_rst)
821
            wb_dat_o <= 32'h0;
822
        else
823
            wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
824
    end
825 49 unneback
end
826
endgenerate
827
 
828 52 unneback
always @ (posedge wb_clk or posedge wb_rst)
829 55 unneback
if (wb_rst)
830 52 unneback
    wb_ack_o <= 1'b0;
831
else
832 54 unneback
    wb_ack_o <= wb_stb_i & wb_cyc_i;
833 52 unneback
 
834
assign wb_stall_o = 1'b0;
835
 
836 49 unneback
endmodule
837
`endif
838
 
839 48 unneback
`ifdef WB_B4_ROM
840
// WB ROM
841
`define MODULE wb_b4_rom
842
module `BASE`MODULE (
843
`undef MODULE
844
    wb_adr_i, wb_stb_i, wb_cyc_i,
845
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
846
 
847
    parameter dat_width = 32;
848
    parameter dat_default = 32'h15000000;
849
    parameter adr_width = 32;
850
 
851
/*
852
//E2_ifndef ROM
853
//E2_define ROM "rom.v"
854
//E2_endif
855
*/
856
    input [adr_width-1:2]   wb_adr_i;
857
    input                   wb_stb_i;
858
    input                   wb_cyc_i;
859
    output [dat_width-1:0]  wb_dat_o;
860
    reg [dat_width-1:0]     wb_dat_o;
861
    output                  wb_ack_o;
862
    reg                     wb_ack_o;
863
    output                  stall_o;
864
    input                   wb_clk;
865
    input                   wb_rst;
866
 
867
always @ (posedge wb_clk or posedge wb_rst)
868
    if (wb_rst)
869
        wb_dat_o <= {dat_width{1'b0}};
870
    else
871
         case (wb_adr_i[adr_width-1:2])
872
//E2_ifdef ROM
873
//E2_include `ROM
874
//E2_endif
875
           default:
876
             wb_dat_o <= dat_default;
877
 
878
         endcase // case (wb_adr_i)
879
 
880
 
881
always @ (posedge wb_clk or posedge wb_rst)
882
    if (wb_rst)
883
        wb_ack_o <= 1'b0;
884
    else
885
        wb_ack_o <= wb_stb_i & wb_cyc_i;
886
 
887
assign stall_o = 1'b0;
888
 
889
endmodule
890
`endif
891
 
892
 
893 40 unneback
`ifdef WB_BOOT_ROM
894 17 unneback
// WB ROM
895 40 unneback
`define MODULE wb_boot_rom
896
module `BASE`MODULE (
897
`undef MODULE
898 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
899 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
900 17 unneback
 
901 18 unneback
    parameter adr_hi = 31;
902
    parameter adr_lo = 28;
903
    parameter adr_sel = 4'hf;
904
    parameter addr_width = 5;
905 33 unneback
/*
906 17 unneback
//E2_ifndef BOOT_ROM
907
//E2_define BOOT_ROM "boot_rom.v"
908
//E2_endif
909 33 unneback
*/
910 18 unneback
    input [adr_hi:2]    wb_adr_i;
911
    input               wb_stb_i;
912
    input               wb_cyc_i;
913
    output [31:0]        wb_dat_o;
914
    output              wb_ack_o;
915
    output              hit_o;
916
    input               wb_clk;
917
    input               wb_rst;
918
 
919
    wire hit;
920
    reg [31:0] wb_dat;
921
    reg wb_ack;
922
 
923
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
924 17 unneback
 
925
always @ (posedge wb_clk or posedge wb_rst)
926
    if (wb_rst)
927 18 unneback
        wb_dat <= 32'h15000000;
928 17 unneback
    else
929 18 unneback
         case (wb_adr_i[addr_width-1:2])
930 33 unneback
//E2_ifdef BOOT_ROM
931 17 unneback
//E2_include `BOOT_ROM
932 33 unneback
//E2_endif
933 17 unneback
           /*
934
            // Zero r0 and jump to 0x00000100
935 18 unneback
 
936
            1 : wb_dat <= 32'hA8200000;
937
            2 : wb_dat <= 32'hA8C00100;
938
            3 : wb_dat <= 32'h44003000;
939
            4 : wb_dat <= 32'h15000000;
940 17 unneback
            */
941
           default:
942 18 unneback
             wb_dat <= 32'h00000000;
943 17 unneback
 
944
         endcase // case (wb_adr_i)
945
 
946
 
947
always @ (posedge wb_clk or posedge wb_rst)
948
    if (wb_rst)
949 18 unneback
        wb_ack <= 1'b0;
950 17 unneback
    else
951 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
952 17 unneback
 
953 18 unneback
assign hit_o = hit;
954
assign wb_dat_o = wb_dat & {32{wb_ack}};
955
assign wb_ack_o = wb_ack;
956
 
957 17 unneback
endmodule
958 40 unneback
`endif
959 32 unneback
 
960 40 unneback
`ifdef WB_DPRAM
961
`define MODULE wb_dpram
962
module `BASE`MODULE (
963
`undef MODULE
964 32 unneback
        // wishbone slave side a
965
        wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
966
        wbsa_clk, wbsa_rst,
967
        // wishbone slave side a
968
        wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
969
        wbsb_clk, wbsb_rst);
970
 
971
parameter data_width = 32;
972
parameter addr_width = 8;
973
 
974
parameter dat_o_mask_a = 1;
975
parameter dat_o_mask_b = 1;
976
 
977
input [31:0] wbsa_dat_i;
978
input [addr_width-1:2] wbsa_adr_i;
979
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
980
output [31:0] wbsa_dat_o;
981
output wbsa_ack_o;
982
input wbsa_clk, wbsa_rst;
983
 
984
input [31:0] wbsb_dat_i;
985
input [addr_width-1:2] wbsb_adr_i;
986
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
987
output [31:0] wbsb_dat_o;
988
output wbsb_ack_o;
989
input wbsb_clk, wbsb_rst;
990
 
991
wire wbsa_dat_tmp, wbsb_dat_tmp;
992
 
993 40 unneback
`define MODULE dpram_2r2w
994
`BASE`MODULE # (
995
`undef MODULE
996 33 unneback
    .data_width(data_width), .addr_width(addr_width) )
997 32 unneback
dpram0(
998
    .d_a(wbsa_dat_i),
999
    .q_a(wbsa_dat_tmp),
1000
    .adr_a(wbsa_adr_i),
1001
    .we_a(wbsa_we_i),
1002
    .clk_a(wbsa_clk),
1003
    .d_b(wbsb_dat_i),
1004
    .q_b(wbsb_dat_tmp),
1005
    .adr_b(wbsb_adr_i),
1006
    .we_b(wbsb_we_i),
1007
    .clk_b(wbsb_clk) );
1008
 
1009 33 unneback
generate if (dat_o_mask_a==1)
1010 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
1011
endgenerate
1012 33 unneback
generate if (dat_o_mask_a==0)
1013 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp;
1014
endgenerate
1015
 
1016 33 unneback
generate if (dat_o_mask_b==1)
1017 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
1018
endgenerate
1019 33 unneback
generate if (dat_o_mask_b==0)
1020 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp;
1021
endgenerate
1022
 
1023 40 unneback
`define MODULE spr
1024
`BASE`MODULE ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
1025
`BASE`MODULE ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
1026
`undef MODULE
1027 32 unneback
 
1028
endmodule
1029 40 unneback
`endif

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