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1 12 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Versatile library, wishbone stuff                           ////
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////                                                              ////
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////  Description                                                 ////
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////  Wishbone compliant modules                                  ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   -                                                          ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42
 
43 75 unneback
`ifdef WB_ADR_INC
44
// async wb3 - wb3 bridge
45
`timescale 1ns/1ns
46
`define MODULE wb_adr_inc
47 83 unneback
module `BASE`MODULE ( cyc_i, stb_i, cti_i, bte_i, adr_i, ack_o, adr_o, clk, rst);
48 75 unneback
`undef MODULE
49 83 unneback
parameter adr_width = 10;
50
parameter max_burst_width = 4;
51
input cyc_i, stb_i;
52
input [2:0] cti_i;
53
input [1:0] bte_i;
54
input [adr_width-1:0] adr_i;
55
output [adr_width-1:0] adr_o;
56
output ack_o;
57
input clk, rst;
58 75 unneback
 
59 83 unneback
reg [adr_width-1:0] adr;
60
 
61
generate
62
if (max_burst_width==0) begin : inst_0
63
    reg ack_o;
64
    assign adr_o = adr_i;
65 75 unneback
    always @ (posedge clk or posedge rst)
66 83 unneback
    if (rst)
67
        ack_o <= 1'b0;
68
    else
69
        ack_o <= cyc_i & stb_i & !ack_o;
70
end else begin
71
 
72
    wire [max_burst_width-1:0] to_adr;
73
 
74
    reg [1:0] last_cycle;
75
    localparam idle = 2'b00;
76
    localparam cyc  = 2'b01;
77
    localparam ws   = 2'b10;
78
    localparam eoc  = 2'b11;
79
    always @ (posedge clk or posedge rst)
80
    if (rst)
81
        last_cycle <= idle;
82
    else
83
        last_cycle <= (!cyc_i) ? idle :
84
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? eoc :
85
                      (cyc_i & !stb_i) ? ws :
86
                      cyc;
87
    assign to_adr = (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
88
    assign adr_o[max_burst_width-1:0] = (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
89
    assign ack_o = last_cycle == cyc;
90
end
91
endgenerate
92
 
93
generate
94
if (max_burst_width==2) begin : inst_2
95
    always @ (posedge clk or posedge rst)
96
    if (rst)
97
        adr <= 2'h0;
98
    else
99
        if (cyc_i & stb_i)
100
            adr[1:0] <= to_adr[1:0] + 2'd1;
101 75 unneback
        else
102 83 unneback
            adr <= to_adr[1:0];
103
end
104
endgenerate
105
 
106
generate
107
if (max_burst_width==3) begin : inst_3
108
    always @ (posedge clk or posedge rst)
109
    if (rst)
110
        adr <= 3'h0;
111
    else
112
        if (cyc_i & stb_i)
113
            case (bte_i)
114
            2'b01: adr[2:0] <= {to_adr[2],to_adr[1:0] + 2'd1};
115
            default: adr[3:0] <= to_adr[2:0] + 3'd1;
116 75 unneback
            endcase
117 83 unneback
        else
118
            adr <= to_adr[2:0];
119
end
120
endgenerate
121
 
122
generate
123
if (max_burst_width==4) begin : inst_4
124
    always @ (posedge clk or posedge rst)
125
    if (rst)
126
        adr <= 4'h0;
127
    else
128
        if (cyc_i & stb_i)
129
            case (bte_i)
130
            2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
131
            2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
132
            default: adr[3:0] <= to_adr + 4'd1;
133
            endcase
134
        else
135
            adr <= to_adr[3:0];
136
end
137
endgenerate
138
 
139
generate
140
if (adr_width > max_burst_width) begin : pass_through
141
    assign adr_o[adr_width-1:max_burst_width] = adr_i[adr_width-1:max_burst_width];
142
end
143
endgenerate
144
 
145
endmodule
146 75 unneback
`endif
147
 
148 40 unneback
`ifdef WB3WB3_BRIDGE
149 12 unneback
// async wb3 - wb3 bridge
150
`timescale 1ns/1ns
151 40 unneback
`define MODULE wb3wb3_bridge
152
module `BASE`MODULE (
153
`undef MODULE
154 12 unneback
        // wishbone slave side
155
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
156
        // wishbone master side
157
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
158
 
159
input [31:0] wbs_dat_i;
160
input [31:2] wbs_adr_i;
161
input [3:0]  wbs_sel_i;
162
input [1:0]  wbs_bte_i;
163
input [2:0]  wbs_cti_i;
164
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
165
output [31:0] wbs_dat_o;
166 14 unneback
output wbs_ack_o;
167 12 unneback
input wbs_clk, wbs_rst;
168
 
169
output [31:0] wbm_dat_o;
170
output reg [31:2] wbm_adr_o;
171
output [3:0]  wbm_sel_o;
172
output reg [1:0]  wbm_bte_o;
173
output reg [2:0]  wbm_cti_o;
174 14 unneback
output reg wbm_we_o;
175
output wbm_cyc_o;
176 12 unneback
output wbm_stb_o;
177
input [31:0]  wbm_dat_i;
178
input wbm_ack_i;
179
input wbm_clk, wbm_rst;
180
 
181
parameter addr_width = 4;
182
 
183
// bte
184
parameter linear       = 2'b00;
185
parameter wrap4        = 2'b01;
186
parameter wrap8        = 2'b10;
187
parameter wrap16       = 2'b11;
188
// cti
189
parameter classic      = 3'b000;
190
parameter incburst     = 3'b010;
191
parameter endofburst   = 3'b111;
192
 
193
parameter wbs_adr  = 1'b0;
194
parameter wbs_data = 1'b1;
195
 
196 33 unneback
parameter wbm_adr0      = 2'b00;
197
parameter wbm_adr1      = 2'b01;
198
parameter wbm_data      = 2'b10;
199
parameter wbm_data_wait = 2'b11;
200 12 unneback
 
201
reg [1:0] wbs_bte_reg;
202
reg wbs;
203
wire wbs_eoc_alert, wbm_eoc_alert;
204
reg wbs_eoc, wbm_eoc;
205
reg [1:0] wbm;
206
 
207 14 unneback
wire [1:16] wbs_count, wbm_count;
208 12 unneback
 
209
wire [35:0] a_d, a_q, b_d, b_q;
210
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
211
reg a_rd_reg;
212
wire b_rd_adr, b_rd_data;
213 14 unneback
wire b_rd_data_reg;
214
wire [35:0] temp;
215 12 unneback
 
216
`define WE 5
217
`define BTE 4:3
218
`define CTI 2:0
219
 
220
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
221
always @ (posedge wbs_clk or posedge wbs_rst)
222
if (wbs_rst)
223
        wbs_eoc <= 1'b0;
224
else
225
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
226 78 unneback
                wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111);
227 12 unneback
        else if (wbs_eoc_alert & (a_rd | a_wr))
228
                wbs_eoc <= 1'b1;
229
 
230 40 unneback
`define MODULE cnt_shreg_ce_clear
231
`BASE`MODULE # ( .length(16))
232
`undef MODULE
233 12 unneback
    cnt0 (
234
        .cke(wbs_ack_o),
235
        .clear(wbs_eoc),
236
        .q(wbs_count),
237
        .rst(wbs_rst),
238
        .clk(wbs_clk));
239
 
240
always @ (posedge wbs_clk or posedge wbs_rst)
241
if (wbs_rst)
242
        wbs <= wbs_adr;
243
else
244 75 unneback
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)
245 12 unneback
                wbs <= wbs_data;
246
        else if (wbs_eoc & wbs_ack_o)
247
                wbs <= wbs_adr;
248
 
249
// wbs FIFO
250 75 unneback
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};
251
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :
252 12 unneback
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
253
              1'b0;
254
assign a_rd = !a_fifo_empty;
255
always @ (posedge wbs_clk or posedge wbs_rst)
256
if (wbs_rst)
257
        a_rd_reg <= 1'b0;
258
else
259
        a_rd_reg <= a_rd;
260
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
261
 
262
assign wbs_dat_o = a_q[35:4];
263
 
264
always @ (posedge wbs_clk or posedge wbs_rst)
265
if (wbs_rst)
266 13 unneback
        wbs_bte_reg <= 2'b00;
267 12 unneback
else
268 13 unneback
        wbs_bte_reg <= wbs_bte_i;
269 12 unneback
 
270
// wbm FIFO
271
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
272
always @ (posedge wbm_clk or posedge wbm_rst)
273
if (wbm_rst)
274
        wbm_eoc <= 1'b0;
275
else
276
        if (wbm==wbm_adr0 & !b_fifo_empty)
277
                wbm_eoc <= b_q[`BTE] == linear;
278
        else if (wbm_eoc_alert & wbm_ack_i)
279
                wbm_eoc <= 1'b1;
280
 
281
always @ (posedge wbm_clk or posedge wbm_rst)
282
if (wbm_rst)
283
        wbm <= wbm_adr0;
284
else
285 33 unneback
/*
286 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
287
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
288
        (wbm==wbm_adr1 & !wbm_we_o) |
289
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
290
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
291 33 unneback
*/
292
    case (wbm)
293
    wbm_adr0:
294
        if (!b_fifo_empty)
295
            wbm <= wbm_adr1;
296
    wbm_adr1:
297
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
298
            wbm <= wbm_data;
299
    wbm_data:
300
        if (wbm_ack_i & wbm_eoc)
301
            wbm <= wbm_adr0;
302
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
303
            wbm <= wbm_data_wait;
304
    wbm_data_wait:
305
        if (!b_fifo_empty)
306
            wbm <= wbm_data;
307
    endcase
308 12 unneback
 
309
assign b_d = {wbm_dat_i,4'b1111};
310
assign b_wr = !wbm_we_o & wbm_ack_i;
311
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
312
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
313
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
314 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
315 12 unneback
                   1'b0;
316
assign b_rd = b_rd_adr | b_rd_data;
317
 
318 40 unneback
`define MODULE dff
319
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
320
`undef MODULE
321
`define MODULE dff_ce
322
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
323
`undef MODULE
324 12 unneback
 
325
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
326
 
327 40 unneback
`define MODULE cnt_shreg_ce_clear
328 42 unneback
`BASE`MODULE # ( .length(16))
329 40 unneback
`undef MODULE
330 12 unneback
    cnt1 (
331
        .cke(wbm_ack_i),
332
        .clear(wbm_eoc),
333
        .q(wbm_count),
334
        .rst(wbm_rst),
335
        .clk(wbm_clk));
336
 
337 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
338
assign wbm_stb_o = (wbm==wbm_data);
339 12 unneback
 
340
always @ (posedge wbm_clk or posedge wbm_rst)
341
if (wbm_rst)
342
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
343
else begin
344
        if (wbm==wbm_adr0 & !b_fifo_empty)
345
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
346
        else if (wbm_eoc_alert & wbm_ack_i)
347
                wbm_cti_o <= endofburst;
348
end
349
 
350
//async_fifo_dw_simplex_top
351 40 unneback
`define MODULE fifo_2r2w_async_simplex
352
`BASE`MODULE
353
`undef MODULE
354 12 unneback
# ( .data_width(36), .addr_width(addr_width))
355
fifo (
356
    // a side
357
    .a_d(a_d),
358
    .a_wr(a_wr),
359
    .a_fifo_full(a_fifo_full),
360
    .a_q(a_q),
361
    .a_rd(a_rd),
362
    .a_fifo_empty(a_fifo_empty),
363
    .a_clk(wbs_clk),
364
    .a_rst(wbs_rst),
365
    // b side
366
    .b_d(b_d),
367
    .b_wr(b_wr),
368
    .b_fifo_full(b_fifo_full),
369
    .b_q(b_q),
370
    .b_rd(b_rd),
371
    .b_fifo_empty(b_fifo_empty),
372
    .b_clk(wbm_clk),
373
    .b_rst(wbm_rst)
374
    );
375
 
376
endmodule
377 40 unneback
`undef WE
378
`undef BTE
379
`undef CTI
380
`endif
381 17 unneback
 
382 75 unneback
`ifdef WB3AVALON_BRIDGE
383
`define MODULE wb3avalon_bridge
384
module `BASE`MODULE (
385
`undef MODULE
386
        // wishbone slave side
387
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
388 77 unneback
        // avalon master side
389 75 unneback
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
390
 
391
input [31:0] wbs_dat_i;
392
input [31:2] wbs_adr_i;
393
input [3:0]  wbs_sel_i;
394
input [1:0]  wbs_bte_i;
395
input [2:0]  wbs_cti_i;
396 83 unneback
input wbs_we_i;
397
input wbs_cyc_i;
398
input wbs_stb_i;
399 75 unneback
output [31:0] wbs_dat_o;
400
output wbs_ack_o;
401
input wbs_clk, wbs_rst;
402
 
403
input [31:0] readdata;
404
output [31:0] writedata;
405
output [31:2] address;
406
output [3:0]  be;
407
output write;
408 81 unneback
output read;
409 75 unneback
output beginbursttransfer;
410
output [3:0] burstcount;
411
input readdatavalid;
412
input waitrequest;
413
input clk;
414
input rst;
415
 
416
wire [1:0] wbm_bte_o;
417
wire [2:0] wbm_cti_o;
418
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
419
reg last_cyc;
420 79 unneback
reg [3:0] counter;
421 82 unneback
reg read_busy;
422 75 unneback
 
423
always @ (posedge clk or posedge rst)
424
if (rst)
425
    last_cyc <= 1'b0;
426
else
427
    last_cyc <= wbm_cyc_o;
428
 
429 79 unneback
always @ (posedge clk or posedge rst)
430
if (rst)
431 82 unneback
    read_busy <= 1'b0;
432 79 unneback
else
433 82 unneback
    if (read & !waitrequest)
434
        read_busy <= 1'b1;
435
    else if (wbm_ack_i & wbm_cti_o!=3'b010)
436
        read_busy <= 1'b0;
437
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;
438 81 unneback
 
439 75 unneback
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
440
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
441
                    (wbm_bte_o==2'b10) ? 4'd8 :
442 78 unneback
                    (wbm_bte_o==2'b11) ? 4'd16:
443
                    4'd1;
444 82 unneback
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);
445 75 unneback
 
446 79 unneback
always @ (posedge clk or posedge rst)
447
if (rst) begin
448
    counter <= 4'd0;
449
end else
450 80 unneback
    if (wbm_we_o) begin
451
        if (!waitrequest & !last_cyc & wbm_cyc_o) begin
452
            counter <= burstcount -1;
453
        end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
454
            counter <= burstcount;
455
        end else if (!waitrequest & wbm_stb_o) begin
456
            counter <= counter - 4'd1;
457
        end
458 82 unneback
    end
459 81 unneback
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
460 79 unneback
 
461 75 unneback
`define MODULE wb3wb3_bridge
462 77 unneback
`BASE`MODULE wbwb3inst (
463 75 unneback
`undef MODULE
464
    // wishbone slave side
465
    .wbs_dat_i(wbs_dat_i),
466
    .wbs_adr_i(wbs_adr_i),
467
    .wbs_sel_i(wbs_sel_i),
468
    .wbs_bte_i(wbs_bte_i),
469
    .wbs_cti_i(wbs_cti_i),
470
    .wbs_we_i(wbs_we_i),
471
    .wbs_cyc_i(wbs_cyc_i),
472
    .wbs_stb_i(wbs_stb_i),
473
    .wbs_dat_o(wbs_dat_o),
474
    .wbs_ack_o(wbs_ack_o),
475
    .wbs_clk(wbs_clk),
476
    .wbs_rst(wbs_rst),
477
    // wishbone master side
478
    .wbm_dat_o(writedata),
479 78 unneback
    .wbm_adr_o(address),
480 75 unneback
    .wbm_sel_o(be),
481
    .wbm_bte_o(wbm_bte_o),
482
    .wbm_cti_o(wbm_cti_o),
483
    .wbm_we_o(wbm_we_o),
484
    .wbm_cyc_o(wbm_cyc_o),
485
    .wbm_stb_o(wbm_stb_o),
486
    .wbm_dat_i(readdata),
487
    .wbm_ack_i(wbm_ack_i),
488
    .wbm_clk(clk),
489
    .wbm_rst(rst));
490
 
491
 
492
endmodule
493
`endif
494
 
495 40 unneback
`ifdef WB3_ARBITER_TYPE1
496
`define MODULE wb3_arbiter_type1
497 42 unneback
module `BASE`MODULE (
498 40 unneback
`undef MODULE
499 39 unneback
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
500
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
501
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
502
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
503
    wb_clk, wb_rst
504
);
505
 
506
parameter nr_of_ports = 3;
507
parameter adr_size = 26;
508
parameter adr_lo   = 2;
509
parameter dat_size = 32;
510
parameter sel_size = dat_size/8;
511
 
512
localparam aw = (adr_size - adr_lo) * nr_of_ports;
513
localparam dw = dat_size * nr_of_ports;
514
localparam sw = sel_size * nr_of_ports;
515
localparam cw = 3 * nr_of_ports;
516
localparam bw = 2 * nr_of_ports;
517
 
518
input  [dw-1:0] wbm_dat_o;
519
input  [aw-1:0] wbm_adr_o;
520
input  [sw-1:0] wbm_sel_o;
521
input  [cw-1:0] wbm_cti_o;
522
input  [bw-1:0] wbm_bte_o;
523
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
524
output [dw-1:0] wbm_dat_i;
525
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
526
 
527
output [dat_size-1:0] wbs_dat_i;
528
output [adr_size-1:adr_lo] wbs_adr_i;
529
output [sel_size-1:0] wbs_sel_i;
530
output [2:0] wbs_cti_i;
531
output [1:0] wbs_bte_i;
532
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
533
input  [dat_size-1:0] wbs_dat_o;
534
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
535
 
536
input wb_clk, wb_rst;
537
 
538 44 unneback
reg  [nr_of_ports-1:0] select;
539 39 unneback
wire [nr_of_ports-1:0] state;
540
wire [nr_of_ports-1:0] eoc; // end-of-cycle
541
wire [nr_of_ports-1:0] sel;
542
wire idle;
543
 
544
genvar i;
545
 
546
assign idle = !(|state);
547
 
548
generate
549
if (nr_of_ports == 2) begin
550
 
551
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
552
 
553
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
554
 
555 44 unneback
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
556
 
557
    always @ (idle or wbm_cyc_o)
558
    if (idle)
559
        casex (wbm_cyc_o)
560
        2'b1x : select = 2'b10;
561
        2'b01 : select = 2'b01;
562
        default : select = {nr_of_ports{1'b0}};
563
        endcase
564
    else
565
        select = {nr_of_ports{1'b0}};
566
 
567 39 unneback
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
568
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
569
 
570
end
571
endgenerate
572
 
573
generate
574
if (nr_of_ports == 3) begin
575
 
576
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
577
 
578
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
579
 
580 44 unneback
    always @ (idle or wbm_cyc_o)
581
    if (idle)
582
        casex (wbm_cyc_o)
583
        3'b1xx : select = 3'b100;
584
        3'b01x : select = 3'b010;
585
        3'b001 : select = 3'b001;
586
        default : select = {nr_of_ports{1'b0}};
587
        endcase
588
    else
589
        select = {nr_of_ports{1'b0}};
590
 
591
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
592 39 unneback
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
593
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
594
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
595
 
596
end
597
endgenerate
598
 
599
generate
600 44 unneback
if (nr_of_ports == 4) begin
601
 
602
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
603
 
604
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
605
 
606
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
607
 
608
    always @ (idle or wbm_cyc_o)
609
    if (idle)
610
        casex (wbm_cyc_o)
611
        4'b1xxx : select = 4'b1000;
612
        4'b01xx : select = 4'b0100;
613
        4'b001x : select = 4'b0010;
614
        4'b0001 : select = 4'b0001;
615
        default : select = {nr_of_ports{1'b0}};
616
        endcase
617
    else
618
        select = {nr_of_ports{1'b0}};
619
 
620
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
621
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
622
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
623
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
624
 
625
end
626
endgenerate
627
 
628
generate
629
if (nr_of_ports == 5) begin
630
 
631
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
632
 
633
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
634
 
635
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
636
 
637
    always @ (idle or wbm_cyc_o)
638
    if (idle)
639
        casex (wbm_cyc_o)
640
        5'b1xxxx : select = 5'b10000;
641
        5'b01xxx : select = 5'b01000;
642
        5'b001xx : select = 5'b00100;
643
        5'b0001x : select = 5'b00010;
644
        5'b00001 : select = 5'b00001;
645
        default : select = {nr_of_ports{1'b0}};
646
        endcase
647
    else
648
        select = {nr_of_ports{1'b0}};
649
 
650
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
651
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
652
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
653
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
654
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
655
 
656
end
657
endgenerate
658
 
659
generate
660 67 unneback
if (nr_of_ports == 6) begin
661
 
662
    wire [2:0] wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
663
 
664
    assign {wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
665
 
666
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
667
 
668
    always @ (idle or wbm_cyc_o)
669
    if (idle)
670
        casex (wbm_cyc_o)
671
        6'b1xxxxx : select = 6'b100000;
672
        6'b01xxxx : select = 6'b010000;
673
        6'b001xxx : select = 6'b001000;
674
        6'b0001xx : select = 6'b000100;
675
        6'b00001x : select = 6'b000010;
676
        6'b000001 : select = 6'b000001;
677
        default : select = {nr_of_ports{1'b0}};
678
        endcase
679
    else
680
        select = {nr_of_ports{1'b0}};
681
 
682
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
683
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
684
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
685
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
686
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
687
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
688
 
689
end
690
endgenerate
691
 
692
generate
693
if (nr_of_ports == 7) begin
694
 
695
    wire [2:0] wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
696
 
697
    assign {wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
698
 
699
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
700
 
701
    always @ (idle or wbm_cyc_o)
702
    if (idle)
703
        casex (wbm_cyc_o)
704
        7'b1xxxxxx : select = 7'b1000000;
705
        7'b01xxxxx : select = 7'b0100000;
706
        7'b001xxxx : select = 7'b0010000;
707
        7'b0001xxx : select = 7'b0001000;
708
        7'b00001xx : select = 7'b0000100;
709
        7'b000001x : select = 7'b0000010;
710
        7'b0000001 : select = 7'b0000001;
711
        default : select = {nr_of_ports{1'b0}};
712
        endcase
713
    else
714
        select = {nr_of_ports{1'b0}};
715
 
716
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
717
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
718
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
719
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
720
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
721
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
722
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
723
 
724
end
725
endgenerate
726
 
727
generate
728
if (nr_of_ports == 8) begin
729
 
730
    wire [2:0] wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
731
 
732
    assign {wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
733
 
734
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
735
 
736
    always @ (idle or wbm_cyc_o)
737
    if (idle)
738
        casex (wbm_cyc_o)
739
        8'b1xxxxxxx : select = 8'b10000000;
740
        8'b01xxxxxx : select = 8'b01000000;
741
        8'b001xxxxx : select = 8'b00100000;
742
        8'b0001xxxx : select = 8'b00010000;
743
        8'b00001xxx : select = 8'b00001000;
744
        8'b000001xx : select = 8'b00000100;
745
        8'b0000001x : select = 8'b00000010;
746
        8'b00000001 : select = 8'b00000001;
747
        default : select = {nr_of_ports{1'b0}};
748
        endcase
749
    else
750
        select = {nr_of_ports{1'b0}};
751
 
752
    assign eoc[7] = (wbm_ack_i[7] & (wbm7_cti_o == 3'b000 | wbm7_cti_o == 3'b111)) | !wbm_cyc_o[7];
753
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
754
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
755
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
756
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
757
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
758
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
759
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
760
 
761
end
762
endgenerate
763
 
764
generate
765 63 unneback
for (i=0;i<nr_of_ports;i=i+1) begin : spr0
766 42 unneback
`define MODULE spr
767
    `BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
768
`undef MODULE
769 39 unneback
end
770
endgenerate
771
 
772
    assign sel = select | state;
773
 
774 40 unneback
`define MODULE mux_andor
775
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
776
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
777
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
778
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
779
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
780
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
781
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
782
`undef MODULE
783 39 unneback
    assign wbs_cyc_i = |sel;
784
 
785
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
786
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
787
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
788
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
789
 
790
endmodule
791 40 unneback
`endif
792 39 unneback
 
793 60 unneback
`ifdef WB_B3_RAM_BE
794 49 unneback
// WB RAM with byte enable
795 59 unneback
`define MODULE wb_b3_ram_be
796
module `BASE`MODULE (
797
`undef MODULE
798 69 unneback
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
799
    wbs_dat_o, wbs_ack_o, wb_clk, wb_rst);
800 59 unneback
 
801 68 unneback
parameter adr_size = 16;
802 60 unneback
parameter adr_lo   = 2;
803 68 unneback
parameter mem_size = 1<<16;
804 60 unneback
parameter dat_size = 32;
805 83 unneback
parameter max_burst_width = 4;
806 60 unneback
parameter memory_init = 1;
807
parameter memory_file = "vl_ram.vmem";
808 59 unneback
 
809 69 unneback
localparam aw = (adr_size - adr_lo);
810
localparam dw = dat_size;
811
localparam sw = dat_size/8;
812
localparam cw = 3;
813
localparam bw = 2;
814 60 unneback
 
815 70 unneback
input [dw-1:0] wbs_dat_i;
816
input [aw-1:0] wbs_adr_i;
817
input [cw-1:0] wbs_cti_i;
818
input [bw-1:0] wbs_bte_i;
819
input [sw-1:0] wbs_sel_i;
820
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
821
output [dw-1:0] wbs_dat_o;
822
output wbs_ack_o;
823 71 unneback
input wb_clk, wb_rst;
824 83 unneback
reg wbs_ack_o;
825 59 unneback
 
826 83 unneback
wire [aw-1:0] adr;
827 59 unneback
 
828 60 unneback
`define MODULE ram_be
829
`BASE`MODULE # (
830
    .data_width(dat_size),
831 83 unneback
    .addr_width(aw),
832 69 unneback
    .mem_size(mem_size),
833 68 unneback
    .memory_init(memory_init),
834
    .memory_file(memory_file))
835 60 unneback
ram0(
836
`undef MODULE
837
    .d(wbs_dat_i),
838 83 unneback
    .adr(adr),
839 60 unneback
    .be(wbs_sel_i),
840
    .we(wbs_we_i),
841
    .q(wbs_dat_o),
842
    .clk(wb_clk)
843
);
844
 
845 83 unneback
`define MODULE wb_adr_inc
846
`BASE`MODULE # ( .adr_width(aw), .max_burst_width(max_burst_width)) adr_inc0 (
847
    .cyc_i(wbs_cyc_i),
848
    .stb_i(wbs_stb_i),
849
    .cti_i(wbs_cti_i),
850
    .bte_i(wbs_bte_i),
851
    .adr_i(wbs_adr_i),
852
    .ack_o(wbs_ack_o),
853
    .adr_o(adr),
854
    .clk(wb_clk),
855
    .rst(wb_rst));
856
`undef MODULE
857 60 unneback
 
858 59 unneback
endmodule
859
`endif
860
 
861
`ifdef WB_B4_RAM_BE
862
// WB RAM with byte enable
863 49 unneback
`define MODULE wb_b4_ram_be
864
module `BASE`MODULE (
865
`undef MODULE
866
    wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
867 52 unneback
    wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
868 49 unneback
 
869
    parameter dat_width = 32;
870
    parameter adr_width = 8;
871
 
872
input [dat_width-1:0] wb_dat_i;
873
input [adr_width-1:0] wb_adr_i;
874
input [dat_width/8-1:0] wb_sel_i;
875
input wb_we_i, wb_stb_i, wb_cyc_i;
876
output [dat_width-1:0] wb_dat_o;
877 51 unneback
reg [dat_width-1:0] wb_dat_o;
878 52 unneback
output wb_stall_o;
879 49 unneback
output wb_ack_o;
880
reg wb_ack_o;
881
input wb_clk, wb_rst;
882
 
883 56 unneback
wire [dat_width/8-1:0] cke;
884
 
885 49 unneback
generate
886
if (dat_width==32) begin
887 51 unneback
reg [7:0] ram3 [1<<(adr_width-2)-1:0];
888
reg [7:0] ram2 [1<<(adr_width-2)-1:0];
889
reg [7:0] ram1 [1<<(adr_width-2)-1:0];
890
reg [7:0] ram0 [1<<(adr_width-2)-1:0];
891 56 unneback
assign cke = wb_sel_i & {(dat_width/8){wb_we_i}};
892 49 unneback
    always @ (posedge wb_clk)
893
    begin
894 56 unneback
        if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
895
        if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
896
        if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
897
        if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
898 49 unneback
    end
899 59 unneback
    always @ (posedge wb_clk or posedge wb_rst)
900
    begin
901
        if (wb_rst)
902
            wb_dat_o <= 32'h0;
903
        else
904
            wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
905
    end
906 49 unneback
end
907
endgenerate
908
 
909 52 unneback
always @ (posedge wb_clk or posedge wb_rst)
910 55 unneback
if (wb_rst)
911 52 unneback
    wb_ack_o <= 1'b0;
912
else
913 54 unneback
    wb_ack_o <= wb_stb_i & wb_cyc_i;
914 52 unneback
 
915
assign wb_stall_o = 1'b0;
916
 
917 49 unneback
endmodule
918
`endif
919
 
920 48 unneback
`ifdef WB_B4_ROM
921
// WB ROM
922
`define MODULE wb_b4_rom
923
module `BASE`MODULE (
924
`undef MODULE
925
    wb_adr_i, wb_stb_i, wb_cyc_i,
926
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
927
 
928
    parameter dat_width = 32;
929
    parameter dat_default = 32'h15000000;
930
    parameter adr_width = 32;
931
 
932
/*
933
//E2_ifndef ROM
934
//E2_define ROM "rom.v"
935
//E2_endif
936
*/
937
    input [adr_width-1:2]   wb_adr_i;
938
    input                   wb_stb_i;
939
    input                   wb_cyc_i;
940
    output [dat_width-1:0]  wb_dat_o;
941
    reg [dat_width-1:0]     wb_dat_o;
942
    output                  wb_ack_o;
943
    reg                     wb_ack_o;
944
    output                  stall_o;
945
    input                   wb_clk;
946
    input                   wb_rst;
947
 
948
always @ (posedge wb_clk or posedge wb_rst)
949
    if (wb_rst)
950
        wb_dat_o <= {dat_width{1'b0}};
951
    else
952
         case (wb_adr_i[adr_width-1:2])
953
//E2_ifdef ROM
954
//E2_include `ROM
955
//E2_endif
956
           default:
957
             wb_dat_o <= dat_default;
958
 
959
         endcase // case (wb_adr_i)
960
 
961
 
962
always @ (posedge wb_clk or posedge wb_rst)
963
    if (wb_rst)
964
        wb_ack_o <= 1'b0;
965
    else
966
        wb_ack_o <= wb_stb_i & wb_cyc_i;
967
 
968
assign stall_o = 1'b0;
969
 
970
endmodule
971
`endif
972
 
973
 
974 40 unneback
`ifdef WB_BOOT_ROM
975 17 unneback
// WB ROM
976 40 unneback
`define MODULE wb_boot_rom
977
module `BASE`MODULE (
978
`undef MODULE
979 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
980 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
981 17 unneback
 
982 18 unneback
    parameter adr_hi = 31;
983
    parameter adr_lo = 28;
984
    parameter adr_sel = 4'hf;
985
    parameter addr_width = 5;
986 33 unneback
/*
987 17 unneback
//E2_ifndef BOOT_ROM
988
//E2_define BOOT_ROM "boot_rom.v"
989
//E2_endif
990 33 unneback
*/
991 18 unneback
    input [adr_hi:2]    wb_adr_i;
992
    input               wb_stb_i;
993
    input               wb_cyc_i;
994
    output [31:0]        wb_dat_o;
995
    output              wb_ack_o;
996
    output              hit_o;
997
    input               wb_clk;
998
    input               wb_rst;
999
 
1000
    wire hit;
1001
    reg [31:0] wb_dat;
1002
    reg wb_ack;
1003
 
1004
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
1005 17 unneback
 
1006
always @ (posedge wb_clk or posedge wb_rst)
1007
    if (wb_rst)
1008 18 unneback
        wb_dat <= 32'h15000000;
1009 17 unneback
    else
1010 18 unneback
         case (wb_adr_i[addr_width-1:2])
1011 33 unneback
//E2_ifdef BOOT_ROM
1012 17 unneback
//E2_include `BOOT_ROM
1013 33 unneback
//E2_endif
1014 17 unneback
           /*
1015
            // Zero r0 and jump to 0x00000100
1016 18 unneback
 
1017
            1 : wb_dat <= 32'hA8200000;
1018
            2 : wb_dat <= 32'hA8C00100;
1019
            3 : wb_dat <= 32'h44003000;
1020
            4 : wb_dat <= 32'h15000000;
1021 17 unneback
            */
1022
           default:
1023 18 unneback
             wb_dat <= 32'h00000000;
1024 17 unneback
 
1025
         endcase // case (wb_adr_i)
1026
 
1027
 
1028
always @ (posedge wb_clk or posedge wb_rst)
1029
    if (wb_rst)
1030 18 unneback
        wb_ack <= 1'b0;
1031 17 unneback
    else
1032 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
1033 17 unneback
 
1034 18 unneback
assign hit_o = hit;
1035
assign wb_dat_o = wb_dat & {32{wb_ack}};
1036
assign wb_ack_o = wb_ack;
1037
 
1038 17 unneback
endmodule
1039 40 unneback
`endif
1040 32 unneback
 
1041 40 unneback
`ifdef WB_DPRAM
1042
`define MODULE wb_dpram
1043
module `BASE`MODULE (
1044
`undef MODULE
1045 32 unneback
        // wishbone slave side a
1046
        wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
1047
        wbsa_clk, wbsa_rst,
1048
        // wishbone slave side a
1049
        wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
1050
        wbsb_clk, wbsb_rst);
1051
 
1052
parameter data_width = 32;
1053
parameter addr_width = 8;
1054
 
1055
parameter dat_o_mask_a = 1;
1056
parameter dat_o_mask_b = 1;
1057
 
1058
input [31:0] wbsa_dat_i;
1059
input [addr_width-1:2] wbsa_adr_i;
1060
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
1061
output [31:0] wbsa_dat_o;
1062
output wbsa_ack_o;
1063
input wbsa_clk, wbsa_rst;
1064
 
1065
input [31:0] wbsb_dat_i;
1066
input [addr_width-1:2] wbsb_adr_i;
1067
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
1068
output [31:0] wbsb_dat_o;
1069
output wbsb_ack_o;
1070
input wbsb_clk, wbsb_rst;
1071
 
1072
wire wbsa_dat_tmp, wbsb_dat_tmp;
1073
 
1074 40 unneback
`define MODULE dpram_2r2w
1075
`BASE`MODULE # (
1076
`undef MODULE
1077 33 unneback
    .data_width(data_width), .addr_width(addr_width) )
1078 32 unneback
dpram0(
1079
    .d_a(wbsa_dat_i),
1080
    .q_a(wbsa_dat_tmp),
1081
    .adr_a(wbsa_adr_i),
1082
    .we_a(wbsa_we_i),
1083
    .clk_a(wbsa_clk),
1084
    .d_b(wbsb_dat_i),
1085
    .q_b(wbsb_dat_tmp),
1086
    .adr_b(wbsb_adr_i),
1087
    .we_b(wbsb_we_i),
1088
    .clk_b(wbsb_clk) );
1089
 
1090 33 unneback
generate if (dat_o_mask_a==1)
1091 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
1092
endgenerate
1093 33 unneback
generate if (dat_o_mask_a==0)
1094 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp;
1095
endgenerate
1096
 
1097 33 unneback
generate if (dat_o_mask_b==1)
1098 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
1099
endgenerate
1100 33 unneback
generate if (dat_o_mask_b==0)
1101 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp;
1102
endgenerate
1103
 
1104 40 unneback
`define MODULE spr
1105
`BASE`MODULE ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
1106
`BASE`MODULE ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
1107
`undef MODULE
1108 32 unneback
 
1109
endmodule
1110 40 unneback
`endif

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