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1 12 unneback
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////  Versatile library, wishbone stuff                           ////
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////                                                              ////
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////  Description                                                 ////
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////  Wishbone compliant modules                                  ////
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////                                                              ////
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////                                                              ////
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////  To Do:                                                      ////
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////   -                                                          ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Michael Unneback, unneback@opencores.org              ////
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////        ORSoC AB                                              ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2010 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
42
 
43 75 unneback
`ifdef WB_ADR_INC
44
// async wb3 - wb3 bridge
45
`timescale 1ns/1ns
46
`define MODULE wb_adr_inc
47 84 unneback
module `BASE`MODULE ( cyc_i, stb_i, cti_i, bte_i, adr_i, we_i, ack_o, adr_o, clk, rst);
48 75 unneback
`undef MODULE
49 83 unneback
parameter adr_width = 10;
50
parameter max_burst_width = 4;
51 84 unneback
input cyc_i, stb_i, we_i;
52 83 unneback
input [2:0] cti_i;
53
input [1:0] bte_i;
54
input [adr_width-1:0] adr_i;
55
output [adr_width-1:0] adr_o;
56
output ack_o;
57
input clk, rst;
58 75 unneback
 
59 83 unneback
reg [adr_width-1:0] adr;
60
 
61
generate
62
if (max_burst_width==0) begin : inst_0
63
    reg ack_o;
64
    assign adr_o = adr_i;
65 75 unneback
    always @ (posedge clk or posedge rst)
66 83 unneback
    if (rst)
67
        ack_o <= 1'b0;
68
    else
69
        ack_o <= cyc_i & stb_i & !ack_o;
70
end else begin
71
 
72
    wire [max_burst_width-1:0] to_adr;
73
 
74
    reg [1:0] last_cycle;
75
    localparam idle = 2'b00;
76
    localparam cyc  = 2'b01;
77
    localparam ws   = 2'b10;
78
    localparam eoc  = 2'b11;
79
    always @ (posedge clk or posedge rst)
80
    if (rst)
81
        last_cycle <= idle;
82
    else
83
        last_cycle <= (!cyc_i) ? idle :
84
                      (cyc_i & ack_o & (cti_i==3'b000 | cti_i==3'b111)) ? eoc :
85
                      (cyc_i & !stb_i) ? ws :
86
                      cyc;
87
    assign to_adr = (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] : adr[max_burst_width-1:0];
88 84 unneback
    assign adr_o[max_burst_width-1:0] = (we_i) ? adr_i[max_burst_width-1:0] :
89
                                        (last_cycle==idle | last_cycle==eoc) ? adr_i[max_burst_width-1:0] :
90
                                        adr[max_burst_width-1:0];
91 83 unneback
    assign ack_o = last_cycle == cyc;
92
end
93
endgenerate
94
 
95
generate
96
if (max_burst_width==2) begin : inst_2
97
    always @ (posedge clk or posedge rst)
98
    if (rst)
99
        adr <= 2'h0;
100
    else
101
        if (cyc_i & stb_i)
102
            adr[1:0] <= to_adr[1:0] + 2'd1;
103 75 unneback
        else
104 83 unneback
            adr <= to_adr[1:0];
105
end
106
endgenerate
107
 
108
generate
109
if (max_burst_width==3) begin : inst_3
110
    always @ (posedge clk or posedge rst)
111
    if (rst)
112
        adr <= 3'h0;
113
    else
114
        if (cyc_i & stb_i)
115
            case (bte_i)
116
            2'b01: adr[2:0] <= {to_adr[2],to_adr[1:0] + 2'd1};
117
            default: adr[3:0] <= to_adr[2:0] + 3'd1;
118 75 unneback
            endcase
119 83 unneback
        else
120
            adr <= to_adr[2:0];
121
end
122
endgenerate
123
 
124
generate
125
if (max_burst_width==4) begin : inst_4
126
    always @ (posedge clk or posedge rst)
127
    if (rst)
128
        adr <= 4'h0;
129
    else
130
        if (cyc_i & stb_i)
131
            case (bte_i)
132
            2'b01: adr[3:0] <= {to_adr[3:2],to_adr[1:0] + 2'd1};
133
            2'b10: adr[3:0] <= {to_adr[3],to_adr[2:0] + 3'd1};
134
            default: adr[3:0] <= to_adr + 4'd1;
135
            endcase
136
        else
137
            adr <= to_adr[3:0];
138
end
139
endgenerate
140
 
141
generate
142
if (adr_width > max_burst_width) begin : pass_through
143
    assign adr_o[adr_width-1:max_burst_width] = adr_i[adr_width-1:max_burst_width];
144
end
145
endgenerate
146
 
147
endmodule
148 75 unneback
`endif
149
 
150 40 unneback
`ifdef WB3WB3_BRIDGE
151 12 unneback
// async wb3 - wb3 bridge
152
`timescale 1ns/1ns
153 40 unneback
`define MODULE wb3wb3_bridge
154
module `BASE`MODULE (
155
`undef MODULE
156 12 unneback
        // wishbone slave side
157
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
158
        // wishbone master side
159
        wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_bte_o, wbm_cti_o, wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_dat_i, wbm_ack_i, wbm_clk, wbm_rst);
160
 
161
input [31:0] wbs_dat_i;
162
input [31:2] wbs_adr_i;
163
input [3:0]  wbs_sel_i;
164
input [1:0]  wbs_bte_i;
165
input [2:0]  wbs_cti_i;
166
input wbs_we_i, wbs_cyc_i, wbs_stb_i;
167
output [31:0] wbs_dat_o;
168 14 unneback
output wbs_ack_o;
169 12 unneback
input wbs_clk, wbs_rst;
170
 
171
output [31:0] wbm_dat_o;
172
output reg [31:2] wbm_adr_o;
173
output [3:0]  wbm_sel_o;
174
output reg [1:0]  wbm_bte_o;
175
output reg [2:0]  wbm_cti_o;
176 14 unneback
output reg wbm_we_o;
177
output wbm_cyc_o;
178 12 unneback
output wbm_stb_o;
179
input [31:0]  wbm_dat_i;
180
input wbm_ack_i;
181
input wbm_clk, wbm_rst;
182
 
183
parameter addr_width = 4;
184
 
185
// bte
186
parameter linear       = 2'b00;
187
parameter wrap4        = 2'b01;
188
parameter wrap8        = 2'b10;
189
parameter wrap16       = 2'b11;
190
// cti
191
parameter classic      = 3'b000;
192
parameter incburst     = 3'b010;
193
parameter endofburst   = 3'b111;
194
 
195
parameter wbs_adr  = 1'b0;
196
parameter wbs_data = 1'b1;
197
 
198 33 unneback
parameter wbm_adr0      = 2'b00;
199
parameter wbm_adr1      = 2'b01;
200
parameter wbm_data      = 2'b10;
201
parameter wbm_data_wait = 2'b11;
202 12 unneback
 
203
reg [1:0] wbs_bte_reg;
204
reg wbs;
205
wire wbs_eoc_alert, wbm_eoc_alert;
206
reg wbs_eoc, wbm_eoc;
207
reg [1:0] wbm;
208
 
209 14 unneback
wire [1:16] wbs_count, wbm_count;
210 12 unneback
 
211
wire [35:0] a_d, a_q, b_d, b_q;
212
wire a_wr, a_rd, a_fifo_full, a_fifo_empty, b_wr, b_rd, b_fifo_full, b_fifo_empty;
213
reg a_rd_reg;
214
wire b_rd_adr, b_rd_data;
215 14 unneback
wire b_rd_data_reg;
216
wire [35:0] temp;
217 12 unneback
 
218
`define WE 5
219
`define BTE 4:3
220
`define CTI 2:0
221
 
222
assign wbs_eoc_alert = (wbs_bte_reg==wrap4 & wbs_count[3]) | (wbs_bte_reg==wrap8 & wbs_count[7]) | (wbs_bte_reg==wrap16 & wbs_count[15]);
223
always @ (posedge wbs_clk or posedge wbs_rst)
224
if (wbs_rst)
225
        wbs_eoc <= 1'b0;
226
else
227
        if (wbs==wbs_adr & wbs_stb_i & !a_fifo_full)
228 78 unneback
                wbs_eoc <= (wbs_bte_i==linear) | (wbs_cti_i==3'b111);
229 12 unneback
        else if (wbs_eoc_alert & (a_rd | a_wr))
230
                wbs_eoc <= 1'b1;
231
 
232 40 unneback
`define MODULE cnt_shreg_ce_clear
233
`BASE`MODULE # ( .length(16))
234
`undef MODULE
235 12 unneback
    cnt0 (
236
        .cke(wbs_ack_o),
237
        .clear(wbs_eoc),
238
        .q(wbs_count),
239
        .rst(wbs_rst),
240
        .clk(wbs_clk));
241
 
242
always @ (posedge wbs_clk or posedge wbs_rst)
243
if (wbs_rst)
244
        wbs <= wbs_adr;
245
else
246 75 unneback
        if ((wbs==wbs_adr) & wbs_cyc_i & wbs_stb_i & a_fifo_empty)
247 12 unneback
                wbs <= wbs_data;
248
        else if (wbs_eoc & wbs_ack_o)
249
                wbs <= wbs_adr;
250
 
251
// wbs FIFO
252 75 unneback
assign a_d = (wbs==wbs_adr) ? {wbs_adr_i[31:2],wbs_we_i,((wbs_cti_i==3'b111) ? {2'b00,3'b000} : {wbs_bte_i,wbs_cti_i})} : {wbs_dat_i,wbs_sel_i};
253
assign a_wr = (wbs==wbs_adr)  ? wbs_cyc_i & wbs_stb_i & a_fifo_empty :
254 12 unneback
              (wbs==wbs_data) ? wbs_we_i  & wbs_stb_i & !a_fifo_full :
255
              1'b0;
256
assign a_rd = !a_fifo_empty;
257
always @ (posedge wbs_clk or posedge wbs_rst)
258
if (wbs_rst)
259
        a_rd_reg <= 1'b0;
260
else
261
        a_rd_reg <= a_rd;
262
assign wbs_ack_o = a_rd_reg | (a_wr & wbs==wbs_data);
263
 
264
assign wbs_dat_o = a_q[35:4];
265
 
266
always @ (posedge wbs_clk or posedge wbs_rst)
267
if (wbs_rst)
268 13 unneback
        wbs_bte_reg <= 2'b00;
269 12 unneback
else
270 13 unneback
        wbs_bte_reg <= wbs_bte_i;
271 12 unneback
 
272
// wbm FIFO
273
assign wbm_eoc_alert = (wbm_bte_o==wrap4 & wbm_count[3]) | (wbm_bte_o==wrap8 & wbm_count[7]) | (wbm_bte_o==wrap16 & wbm_count[15]);
274
always @ (posedge wbm_clk or posedge wbm_rst)
275
if (wbm_rst)
276
        wbm_eoc <= 1'b0;
277
else
278
        if (wbm==wbm_adr0 & !b_fifo_empty)
279
                wbm_eoc <= b_q[`BTE] == linear;
280
        else if (wbm_eoc_alert & wbm_ack_i)
281
                wbm_eoc <= 1'b1;
282
 
283
always @ (posedge wbm_clk or posedge wbm_rst)
284
if (wbm_rst)
285
        wbm <= wbm_adr0;
286
else
287 33 unneback
/*
288 12 unneback
    if ((wbm==wbm_adr0 & !b_fifo_empty) |
289
        (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) |
290
        (wbm==wbm_adr1 & !wbm_we_o) |
291
        (wbm==wbm_data & wbm_ack_i & wbm_eoc))
292
        wbm <= {wbm[0],!(wbm[1] ^ wbm[0])};  // count sequence 00,01,10
293 33 unneback
*/
294
    case (wbm)
295
    wbm_adr0:
296
        if (!b_fifo_empty)
297
            wbm <= wbm_adr1;
298
    wbm_adr1:
299
        if (!wbm_we_o | (!b_fifo_empty & wbm_we_o))
300
            wbm <= wbm_data;
301
    wbm_data:
302
        if (wbm_ack_i & wbm_eoc)
303
            wbm <= wbm_adr0;
304
        else if (b_fifo_empty & wbm_we_o & wbm_ack_i)
305
            wbm <= wbm_data_wait;
306
    wbm_data_wait:
307
        if (!b_fifo_empty)
308
            wbm <= wbm_data;
309
    endcase
310 12 unneback
 
311
assign b_d = {wbm_dat_i,4'b1111};
312
assign b_wr = !wbm_we_o & wbm_ack_i;
313
assign b_rd_adr  = (wbm==wbm_adr0 & !b_fifo_empty);
314
assign b_rd_data = (wbm==wbm_adr1 & !b_fifo_empty & wbm_we_o) ? 1'b1 : // b_q[`WE]
315
                   (wbm==wbm_data & !b_fifo_empty & wbm_we_o & wbm_ack_i & !wbm_eoc) ? 1'b1 :
316 33 unneback
                   (wbm==wbm_data_wait & !b_fifo_empty) ? 1'b1 :
317 12 unneback
                   1'b0;
318
assign b_rd = b_rd_adr | b_rd_data;
319
 
320 40 unneback
`define MODULE dff
321
`BASE`MODULE dff1 ( .d(b_rd_data), .q(b_rd_data_reg), .clk(wbm_clk), .rst(wbm_rst));
322
`undef MODULE
323
`define MODULE dff_ce
324
`BASE`MODULE # ( .width(36)) dff2 ( .d(b_q), .ce(b_rd_data_reg), .q(temp), .clk(wbm_clk), .rst(wbm_rst));
325
`undef MODULE
326 12 unneback
 
327
assign {wbm_dat_o,wbm_sel_o} = (b_rd_data_reg) ? b_q : temp;
328
 
329 40 unneback
`define MODULE cnt_shreg_ce_clear
330 42 unneback
`BASE`MODULE # ( .length(16))
331 40 unneback
`undef MODULE
332 12 unneback
    cnt1 (
333
        .cke(wbm_ack_i),
334
        .clear(wbm_eoc),
335
        .q(wbm_count),
336
        .rst(wbm_rst),
337
        .clk(wbm_clk));
338
 
339 33 unneback
assign wbm_cyc_o = (wbm==wbm_data | wbm==wbm_data_wait);
340
assign wbm_stb_o = (wbm==wbm_data);
341 12 unneback
 
342
always @ (posedge wbm_clk or posedge wbm_rst)
343
if (wbm_rst)
344
        {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= {30'h0,1'b0,linear,classic};
345
else begin
346
        if (wbm==wbm_adr0 & !b_fifo_empty)
347
                {wbm_adr_o,wbm_we_o,wbm_bte_o,wbm_cti_o} <= b_q;
348
        else if (wbm_eoc_alert & wbm_ack_i)
349
                wbm_cti_o <= endofburst;
350
end
351
 
352
//async_fifo_dw_simplex_top
353 40 unneback
`define MODULE fifo_2r2w_async_simplex
354
`BASE`MODULE
355
`undef MODULE
356 12 unneback
# ( .data_width(36), .addr_width(addr_width))
357
fifo (
358
    // a side
359
    .a_d(a_d),
360
    .a_wr(a_wr),
361
    .a_fifo_full(a_fifo_full),
362
    .a_q(a_q),
363
    .a_rd(a_rd),
364
    .a_fifo_empty(a_fifo_empty),
365
    .a_clk(wbs_clk),
366
    .a_rst(wbs_rst),
367
    // b side
368
    .b_d(b_d),
369
    .b_wr(b_wr),
370
    .b_fifo_full(b_fifo_full),
371
    .b_q(b_q),
372
    .b_rd(b_rd),
373
    .b_fifo_empty(b_fifo_empty),
374
    .b_clk(wbm_clk),
375
    .b_rst(wbm_rst)
376
    );
377
 
378
endmodule
379 40 unneback
`undef WE
380
`undef BTE
381
`undef CTI
382
`endif
383 17 unneback
 
384 75 unneback
`ifdef WB3AVALON_BRIDGE
385
`define MODULE wb3avalon_bridge
386
module `BASE`MODULE (
387
`undef MODULE
388
        // wishbone slave side
389
        wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_bte_i, wbs_cti_i, wbs_we_i, wbs_cyc_i, wbs_stb_i, wbs_dat_o, wbs_ack_o, wbs_clk, wbs_rst,
390 77 unneback
        // avalon master side
391 75 unneback
        readdata, readdatavalid, address, read, be, write, burstcount, writedata, waitrequest, beginbursttransfer, clk, rst);
392
 
393 84 unneback
parameter linewrapburst = 1'b0;
394
 
395 75 unneback
input [31:0] wbs_dat_i;
396
input [31:2] wbs_adr_i;
397
input [3:0]  wbs_sel_i;
398
input [1:0]  wbs_bte_i;
399
input [2:0]  wbs_cti_i;
400 83 unneback
input wbs_we_i;
401
input wbs_cyc_i;
402
input wbs_stb_i;
403 75 unneback
output [31:0] wbs_dat_o;
404
output wbs_ack_o;
405
input wbs_clk, wbs_rst;
406
 
407
input [31:0] readdata;
408
output [31:0] writedata;
409
output [31:2] address;
410
output [3:0]  be;
411
output write;
412 81 unneback
output read;
413 75 unneback
output beginbursttransfer;
414
output [3:0] burstcount;
415
input readdatavalid;
416
input waitrequest;
417
input clk;
418
input rst;
419
 
420
wire [1:0] wbm_bte_o;
421
wire [2:0] wbm_cti_o;
422
wire wbm_we_o, wbm_cyc_o, wbm_stb_o, wbm_ack_i;
423
reg last_cyc;
424 79 unneback
reg [3:0] counter;
425 82 unneback
reg read_busy;
426 75 unneback
 
427
always @ (posedge clk or posedge rst)
428
if (rst)
429
    last_cyc <= 1'b0;
430
else
431
    last_cyc <= wbm_cyc_o;
432
 
433 79 unneback
always @ (posedge clk or posedge rst)
434
if (rst)
435 82 unneback
    read_busy <= 1'b0;
436 79 unneback
else
437 82 unneback
    if (read & !waitrequest)
438
        read_busy <= 1'b1;
439
    else if (wbm_ack_i & wbm_cti_o!=3'b010)
440
        read_busy <= 1'b0;
441
assign read = wbm_cyc_o & wbm_stb_o & !wbm_we_o & !read_busy;
442 81 unneback
 
443 75 unneback
assign beginbursttransfer = (!last_cyc & wbm_cyc_o) & wbm_cti_o==3'b010;
444
assign burstcount = (wbm_bte_o==2'b01) ? 4'd4 :
445
                    (wbm_bte_o==2'b10) ? 4'd8 :
446 78 unneback
                    (wbm_bte_o==2'b11) ? 4'd16:
447
                    4'd1;
448 82 unneback
assign wbm_ack_i = (readdatavalid) | (write & !waitrequest);
449 75 unneback
 
450 79 unneback
always @ (posedge clk or posedge rst)
451
if (rst) begin
452
    counter <= 4'd0;
453
end else
454 80 unneback
    if (wbm_we_o) begin
455
        if (!waitrequest & !last_cyc & wbm_cyc_o) begin
456 84 unneback
            counter <= burstcount -4'd1;
457 80 unneback
        end else if (waitrequest & !last_cyc & wbm_cyc_o) begin
458
            counter <= burstcount;
459
        end else if (!waitrequest & wbm_stb_o) begin
460
            counter <= counter - 4'd1;
461
        end
462 82 unneback
    end
463 81 unneback
assign write = wbm_cyc_o & wbm_stb_o & wbm_we_o & counter!=4'd0;
464 79 unneback
 
465 75 unneback
`define MODULE wb3wb3_bridge
466 77 unneback
`BASE`MODULE wbwb3inst (
467 75 unneback
`undef MODULE
468
    // wishbone slave side
469
    .wbs_dat_i(wbs_dat_i),
470
    .wbs_adr_i(wbs_adr_i),
471
    .wbs_sel_i(wbs_sel_i),
472
    .wbs_bte_i(wbs_bte_i),
473
    .wbs_cti_i(wbs_cti_i),
474
    .wbs_we_i(wbs_we_i),
475
    .wbs_cyc_i(wbs_cyc_i),
476
    .wbs_stb_i(wbs_stb_i),
477
    .wbs_dat_o(wbs_dat_o),
478
    .wbs_ack_o(wbs_ack_o),
479
    .wbs_clk(wbs_clk),
480
    .wbs_rst(wbs_rst),
481
    // wishbone master side
482
    .wbm_dat_o(writedata),
483 78 unneback
    .wbm_adr_o(address),
484 75 unneback
    .wbm_sel_o(be),
485
    .wbm_bte_o(wbm_bte_o),
486
    .wbm_cti_o(wbm_cti_o),
487
    .wbm_we_o(wbm_we_o),
488
    .wbm_cyc_o(wbm_cyc_o),
489
    .wbm_stb_o(wbm_stb_o),
490
    .wbm_dat_i(readdata),
491
    .wbm_ack_i(wbm_ack_i),
492
    .wbm_clk(clk),
493
    .wbm_rst(rst));
494
 
495
 
496
endmodule
497
`endif
498
 
499 40 unneback
`ifdef WB3_ARBITER_TYPE1
500
`define MODULE wb3_arbiter_type1
501 42 unneback
module `BASE`MODULE (
502 40 unneback
`undef MODULE
503 39 unneback
    wbm_dat_o, wbm_adr_o, wbm_sel_o, wbm_cti_o, wbm_bte_o, wbm_we_o, wbm_stb_o, wbm_cyc_o,
504
    wbm_dat_i, wbm_ack_i, wbm_err_i, wbm_rty_i,
505
    wbs_dat_i, wbs_adr_i, wbs_sel_i, wbs_cti_i, wbs_bte_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
506
    wbs_dat_o, wbs_ack_o, wbs_err_o, wbs_rty_o,
507
    wb_clk, wb_rst
508
);
509
 
510
parameter nr_of_ports = 3;
511
parameter adr_size = 26;
512
parameter adr_lo   = 2;
513
parameter dat_size = 32;
514
parameter sel_size = dat_size/8;
515
 
516
localparam aw = (adr_size - adr_lo) * nr_of_ports;
517
localparam dw = dat_size * nr_of_ports;
518
localparam sw = sel_size * nr_of_ports;
519
localparam cw = 3 * nr_of_ports;
520
localparam bw = 2 * nr_of_ports;
521
 
522
input  [dw-1:0] wbm_dat_o;
523
input  [aw-1:0] wbm_adr_o;
524
input  [sw-1:0] wbm_sel_o;
525
input  [cw-1:0] wbm_cti_o;
526
input  [bw-1:0] wbm_bte_o;
527
input  [nr_of_ports-1:0] wbm_we_o, wbm_stb_o, wbm_cyc_o;
528
output [dw-1:0] wbm_dat_i;
529
output [nr_of_ports-1:0] wbm_ack_i, wbm_err_i, wbm_rty_i;
530
 
531
output [dat_size-1:0] wbs_dat_i;
532
output [adr_size-1:adr_lo] wbs_adr_i;
533
output [sel_size-1:0] wbs_sel_i;
534
output [2:0] wbs_cti_i;
535
output [1:0] wbs_bte_i;
536
output wbs_we_i, wbs_stb_i, wbs_cyc_i;
537
input  [dat_size-1:0] wbs_dat_o;
538
input  wbs_ack_o, wbs_err_o, wbs_rty_o;
539
 
540
input wb_clk, wb_rst;
541
 
542 44 unneback
reg  [nr_of_ports-1:0] select;
543 39 unneback
wire [nr_of_ports-1:0] state;
544
wire [nr_of_ports-1:0] eoc; // end-of-cycle
545
wire [nr_of_ports-1:0] sel;
546
wire idle;
547
 
548
genvar i;
549
 
550
assign idle = !(|state);
551
 
552
generate
553
if (nr_of_ports == 2) begin
554
 
555
    wire [2:0] wbm1_cti_o, wbm0_cti_o;
556
 
557
    assign {wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
558
 
559 44 unneback
    //assign select = (idle) ? {wbm_cyc_o[1],!wbm_cyc_o[1] & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
560
 
561
    always @ (idle or wbm_cyc_o)
562
    if (idle)
563
        casex (wbm_cyc_o)
564
        2'b1x : select = 2'b10;
565
        2'b01 : select = 2'b01;
566
        default : select = {nr_of_ports{1'b0}};
567
        endcase
568
    else
569
        select = {nr_of_ports{1'b0}};
570
 
571 39 unneback
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
572
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
573
 
574
end
575
endgenerate
576
 
577
generate
578
if (nr_of_ports == 3) begin
579
 
580
    wire [2:0] wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
581
 
582
    assign {wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
583
 
584 44 unneback
    always @ (idle or wbm_cyc_o)
585
    if (idle)
586
        casex (wbm_cyc_o)
587
        3'b1xx : select = 3'b100;
588
        3'b01x : select = 3'b010;
589
        3'b001 : select = 3'b001;
590
        default : select = {nr_of_ports{1'b0}};
591
        endcase
592
    else
593
        select = {nr_of_ports{1'b0}};
594
 
595
//    assign select = (idle) ? {wbm_cyc_o[2],!wbm_cyc_o[2] & wbm_cyc_o[1],wbm_cyc_o[2:1]==2'b00 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
596 39 unneback
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
597
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
598
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
599
 
600
end
601
endgenerate
602
 
603
generate
604 44 unneback
if (nr_of_ports == 4) begin
605
 
606
    wire [2:0] wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
607
 
608
    assign {wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
609
 
610
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
611
 
612
    always @ (idle or wbm_cyc_o)
613
    if (idle)
614
        casex (wbm_cyc_o)
615
        4'b1xxx : select = 4'b1000;
616
        4'b01xx : select = 4'b0100;
617
        4'b001x : select = 4'b0010;
618
        4'b0001 : select = 4'b0001;
619
        default : select = {nr_of_ports{1'b0}};
620
        endcase
621
    else
622
        select = {nr_of_ports{1'b0}};
623
 
624
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
625
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
626
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
627
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
628
 
629
end
630
endgenerate
631
 
632
generate
633
if (nr_of_ports == 5) begin
634
 
635
    wire [2:0] wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
636
 
637
    assign {wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
638
 
639
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
640
 
641
    always @ (idle or wbm_cyc_o)
642
    if (idle)
643
        casex (wbm_cyc_o)
644
        5'b1xxxx : select = 5'b10000;
645
        5'b01xxx : select = 5'b01000;
646
        5'b001xx : select = 5'b00100;
647
        5'b0001x : select = 5'b00010;
648
        5'b00001 : select = 5'b00001;
649
        default : select = {nr_of_ports{1'b0}};
650
        endcase
651
    else
652
        select = {nr_of_ports{1'b0}};
653
 
654
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
655
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
656
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
657
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
658
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
659
 
660
end
661
endgenerate
662
 
663
generate
664 67 unneback
if (nr_of_ports == 6) begin
665
 
666
    wire [2:0] wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
667
 
668
    assign {wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
669
 
670
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
671
 
672
    always @ (idle or wbm_cyc_o)
673
    if (idle)
674
        casex (wbm_cyc_o)
675
        6'b1xxxxx : select = 6'b100000;
676
        6'b01xxxx : select = 6'b010000;
677
        6'b001xxx : select = 6'b001000;
678
        6'b0001xx : select = 6'b000100;
679
        6'b00001x : select = 6'b000010;
680
        6'b000001 : select = 6'b000001;
681
        default : select = {nr_of_ports{1'b0}};
682
        endcase
683
    else
684
        select = {nr_of_ports{1'b0}};
685
 
686
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
687
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
688
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
689
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
690
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
691
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
692
 
693
end
694
endgenerate
695
 
696
generate
697
if (nr_of_ports == 7) begin
698
 
699
    wire [2:0] wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
700
 
701
    assign {wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
702
 
703
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
704
 
705
    always @ (idle or wbm_cyc_o)
706
    if (idle)
707
        casex (wbm_cyc_o)
708
        7'b1xxxxxx : select = 7'b1000000;
709
        7'b01xxxxx : select = 7'b0100000;
710
        7'b001xxxx : select = 7'b0010000;
711
        7'b0001xxx : select = 7'b0001000;
712
        7'b00001xx : select = 7'b0000100;
713
        7'b000001x : select = 7'b0000010;
714
        7'b0000001 : select = 7'b0000001;
715
        default : select = {nr_of_ports{1'b0}};
716
        endcase
717
    else
718
        select = {nr_of_ports{1'b0}};
719
 
720
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
721
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
722
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
723
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
724
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
725
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
726
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
727
 
728
end
729
endgenerate
730
 
731
generate
732
if (nr_of_ports == 8) begin
733
 
734
    wire [2:0] wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o, wbm1_cti_o, wbm0_cti_o;
735
 
736
    assign {wbm7_cti_o, wbm6_cti_o, wbm5_cti_o, wbm4_cti_o, wbm3_cti_o, wbm2_cti_o,wbm1_cti_o,wbm0_cti_o} = wbm_cti_o;
737
 
738
    //assign select = (idle) ? {wbm_cyc_o[3],!wbm_cyc_o[3] & wbm_cyc_o[2],wbm_cyc_o[3:2]==2'b00 & wbm_cyc_o[1],wbm_cyc_o[3:1]==3'b000 & wbm_cyc_o[0]} : {nr_of_ports{1'b0}};
739
 
740
    always @ (idle or wbm_cyc_o)
741
    if (idle)
742
        casex (wbm_cyc_o)
743
        8'b1xxxxxxx : select = 8'b10000000;
744
        8'b01xxxxxx : select = 8'b01000000;
745
        8'b001xxxxx : select = 8'b00100000;
746
        8'b0001xxxx : select = 8'b00010000;
747
        8'b00001xxx : select = 8'b00001000;
748
        8'b000001xx : select = 8'b00000100;
749
        8'b0000001x : select = 8'b00000010;
750
        8'b00000001 : select = 8'b00000001;
751
        default : select = {nr_of_ports{1'b0}};
752
        endcase
753
    else
754
        select = {nr_of_ports{1'b0}};
755
 
756
    assign eoc[7] = (wbm_ack_i[7] & (wbm7_cti_o == 3'b000 | wbm7_cti_o == 3'b111)) | !wbm_cyc_o[7];
757
    assign eoc[6] = (wbm_ack_i[6] & (wbm6_cti_o == 3'b000 | wbm6_cti_o == 3'b111)) | !wbm_cyc_o[6];
758
    assign eoc[5] = (wbm_ack_i[5] & (wbm5_cti_o == 3'b000 | wbm5_cti_o == 3'b111)) | !wbm_cyc_o[5];
759
    assign eoc[4] = (wbm_ack_i[4] & (wbm4_cti_o == 3'b000 | wbm4_cti_o == 3'b111)) | !wbm_cyc_o[4];
760
    assign eoc[3] = (wbm_ack_i[3] & (wbm3_cti_o == 3'b000 | wbm3_cti_o == 3'b111)) | !wbm_cyc_o[3];
761
    assign eoc[2] = (wbm_ack_i[2] & (wbm2_cti_o == 3'b000 | wbm2_cti_o == 3'b111)) | !wbm_cyc_o[2];
762
    assign eoc[1] = (wbm_ack_i[1] & (wbm1_cti_o == 3'b000 | wbm1_cti_o == 3'b111)) | !wbm_cyc_o[1];
763
    assign eoc[0] = (wbm_ack_i[0] & (wbm0_cti_o == 3'b000 | wbm0_cti_o == 3'b111)) | !wbm_cyc_o[0];
764
 
765
end
766
endgenerate
767
 
768
generate
769 63 unneback
for (i=0;i<nr_of_ports;i=i+1) begin : spr0
770 42 unneback
`define MODULE spr
771
    `BASE`MODULE sr0( .sp(select[i]), .r(eoc[i]), .q(state[i]), .clk(wb_clk), .rst(wb_rst));
772
`undef MODULE
773 39 unneback
end
774
endgenerate
775
 
776
    assign sel = select | state;
777
 
778 40 unneback
`define MODULE mux_andor
779
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(32)) mux0 ( .a(wbm_dat_o), .sel(sel), .dout(wbs_dat_i));
780
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(adr_size-adr_lo)) mux1 ( .a(wbm_adr_o), .sel(sel), .dout(wbs_adr_i));
781
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(sel_size)) mux2 ( .a(wbm_sel_o), .sel(sel), .dout(wbs_sel_i));
782
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(3)) mux3 ( .a(wbm_cti_o), .sel(sel), .dout(wbs_cti_i));
783
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(2)) mux4 ( .a(wbm_bte_o), .sel(sel), .dout(wbs_bte_i));
784
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux5 ( .a(wbm_we_o), .sel(sel), .dout(wbs_we_i));
785
    `BASE`MODULE # ( .nr_of_ports(nr_of_ports), .width(1)) mux6 ( .a(wbm_stb_o), .sel(sel), .dout(wbs_stb_i));
786
`undef MODULE
787 39 unneback
    assign wbs_cyc_i = |sel;
788
 
789
    assign wbm_dat_i = {nr_of_ports{wbs_dat_o}};
790
    assign wbm_ack_i = {nr_of_ports{wbs_ack_o}} & sel;
791
    assign wbm_err_i = {nr_of_ports{wbs_err_o}} & sel;
792
    assign wbm_rty_i = {nr_of_ports{wbs_rty_o}} & sel;
793
 
794
endmodule
795 40 unneback
`endif
796 39 unneback
 
797 60 unneback
`ifdef WB_B3_RAM_BE
798 49 unneback
// WB RAM with byte enable
799 59 unneback
`define MODULE wb_b3_ram_be
800
module `BASE`MODULE (
801
`undef MODULE
802 69 unneback
    wbs_dat_i, wbs_adr_i, wbs_cti_i, wbs_bte_i, wbs_sel_i, wbs_we_i, wbs_stb_i, wbs_cyc_i,
803
    wbs_dat_o, wbs_ack_o, wb_clk, wb_rst);
804 59 unneback
 
805 68 unneback
parameter adr_size = 16;
806 84 unneback
parameter mem_size = 1<<adr_size;
807 60 unneback
parameter dat_size = 32;
808 83 unneback
parameter max_burst_width = 4;
809 60 unneback
parameter memory_init = 1;
810
parameter memory_file = "vl_ram.vmem";
811 59 unneback
 
812 84 unneback
localparam aw = (adr_size);
813 69 unneback
localparam dw = dat_size;
814
localparam sw = dat_size/8;
815
localparam cw = 3;
816
localparam bw = 2;
817 60 unneback
 
818 70 unneback
input [dw-1:0] wbs_dat_i;
819
input [aw-1:0] wbs_adr_i;
820
input [cw-1:0] wbs_cti_i;
821
input [bw-1:0] wbs_bte_i;
822
input [sw-1:0] wbs_sel_i;
823
input wbs_we_i, wbs_stb_i, wbs_cyc_i;
824
output [dw-1:0] wbs_dat_o;
825
output wbs_ack_o;
826 71 unneback
input wb_clk, wb_rst;
827 59 unneback
 
828 83 unneback
wire [aw-1:0] adr;
829 59 unneback
 
830 60 unneback
`define MODULE ram_be
831
`BASE`MODULE # (
832
    .data_width(dat_size),
833 83 unneback
    .addr_width(aw),
834 69 unneback
    .mem_size(mem_size),
835 68 unneback
    .memory_init(memory_init),
836
    .memory_file(memory_file))
837 60 unneback
ram0(
838
`undef MODULE
839
    .d(wbs_dat_i),
840 83 unneback
    .adr(adr),
841 60 unneback
    .be(wbs_sel_i),
842 86 unneback
    .we(wbs_we_i & wbs_ack_o),
843 60 unneback
    .q(wbs_dat_o),
844
    .clk(wb_clk)
845
);
846
 
847 83 unneback
`define MODULE wb_adr_inc
848
`BASE`MODULE # ( .adr_width(aw), .max_burst_width(max_burst_width)) adr_inc0 (
849
    .cyc_i(wbs_cyc_i),
850
    .stb_i(wbs_stb_i),
851
    .cti_i(wbs_cti_i),
852
    .bte_i(wbs_bte_i),
853
    .adr_i(wbs_adr_i),
854 84 unneback
    .we_i(wbs_we_i),
855 83 unneback
    .ack_o(wbs_ack_o),
856
    .adr_o(adr),
857
    .clk(wb_clk),
858
    .rst(wb_rst));
859
`undef MODULE
860 60 unneback
 
861 59 unneback
endmodule
862
`endif
863
 
864
`ifdef WB_B4_RAM_BE
865
// WB RAM with byte enable
866 49 unneback
`define MODULE wb_b4_ram_be
867
module `BASE`MODULE (
868
`undef MODULE
869
    wb_dat_i, wb_adr_i, wb_sel_i, wb_we_i, wb_stb_i, wb_cyc_i,
870 52 unneback
    wb_dat_o, wb_stall_o, wb_ack_o, wb_clk, wb_rst);
871 49 unneback
 
872
    parameter dat_width = 32;
873
    parameter adr_width = 8;
874
 
875
input [dat_width-1:0] wb_dat_i;
876
input [adr_width-1:0] wb_adr_i;
877
input [dat_width/8-1:0] wb_sel_i;
878
input wb_we_i, wb_stb_i, wb_cyc_i;
879
output [dat_width-1:0] wb_dat_o;
880 51 unneback
reg [dat_width-1:0] wb_dat_o;
881 52 unneback
output wb_stall_o;
882 49 unneback
output wb_ack_o;
883
reg wb_ack_o;
884
input wb_clk, wb_rst;
885
 
886 56 unneback
wire [dat_width/8-1:0] cke;
887
 
888 49 unneback
generate
889
if (dat_width==32) begin
890 51 unneback
reg [7:0] ram3 [1<<(adr_width-2)-1:0];
891
reg [7:0] ram2 [1<<(adr_width-2)-1:0];
892
reg [7:0] ram1 [1<<(adr_width-2)-1:0];
893
reg [7:0] ram0 [1<<(adr_width-2)-1:0];
894 56 unneback
assign cke = wb_sel_i & {(dat_width/8){wb_we_i}};
895 49 unneback
    always @ (posedge wb_clk)
896
    begin
897 56 unneback
        if (cke[3]) ram3[wb_adr_i[adr_width-1:2]] <= wb_dat_i[31:24];
898
        if (cke[2]) ram2[wb_adr_i[adr_width-1:2]] <= wb_dat_i[23:16];
899
        if (cke[1]) ram1[wb_adr_i[adr_width-1:2]] <= wb_dat_i[15:8];
900
        if (cke[0]) ram0[wb_adr_i[adr_width-1:2]] <= wb_dat_i[7:0];
901 49 unneback
    end
902 59 unneback
    always @ (posedge wb_clk or posedge wb_rst)
903
    begin
904
        if (wb_rst)
905
            wb_dat_o <= 32'h0;
906
        else
907
            wb_dat_o <= {ram3[wb_adr_i[adr_width-1:2]],ram2[wb_adr_i[adr_width-1:2]],ram1[wb_adr_i[adr_width-1:2]],ram0[wb_adr_i[adr_width-1:2]]};
908
    end
909 49 unneback
end
910
endgenerate
911
 
912 52 unneback
always @ (posedge wb_clk or posedge wb_rst)
913 55 unneback
if (wb_rst)
914 52 unneback
    wb_ack_o <= 1'b0;
915
else
916 54 unneback
    wb_ack_o <= wb_stb_i & wb_cyc_i;
917 52 unneback
 
918
assign wb_stall_o = 1'b0;
919
 
920 49 unneback
endmodule
921
`endif
922
 
923 48 unneback
`ifdef WB_B4_ROM
924
// WB ROM
925
`define MODULE wb_b4_rom
926
module `BASE`MODULE (
927
`undef MODULE
928
    wb_adr_i, wb_stb_i, wb_cyc_i,
929
    wb_dat_o, stall_o, wb_ack_o, wb_clk, wb_rst);
930
 
931
    parameter dat_width = 32;
932
    parameter dat_default = 32'h15000000;
933
    parameter adr_width = 32;
934
 
935
/*
936
//E2_ifndef ROM
937
//E2_define ROM "rom.v"
938
//E2_endif
939
*/
940
    input [adr_width-1:2]   wb_adr_i;
941
    input                   wb_stb_i;
942
    input                   wb_cyc_i;
943
    output [dat_width-1:0]  wb_dat_o;
944
    reg [dat_width-1:0]     wb_dat_o;
945
    output                  wb_ack_o;
946
    reg                     wb_ack_o;
947
    output                  stall_o;
948
    input                   wb_clk;
949
    input                   wb_rst;
950
 
951
always @ (posedge wb_clk or posedge wb_rst)
952
    if (wb_rst)
953
        wb_dat_o <= {dat_width{1'b0}};
954
    else
955
         case (wb_adr_i[adr_width-1:2])
956
//E2_ifdef ROM
957
//E2_include `ROM
958
//E2_endif
959
           default:
960
             wb_dat_o <= dat_default;
961
 
962
         endcase // case (wb_adr_i)
963
 
964
 
965
always @ (posedge wb_clk or posedge wb_rst)
966
    if (wb_rst)
967
        wb_ack_o <= 1'b0;
968
    else
969
        wb_ack_o <= wb_stb_i & wb_cyc_i;
970
 
971
assign stall_o = 1'b0;
972
 
973
endmodule
974
`endif
975
 
976
 
977 40 unneback
`ifdef WB_BOOT_ROM
978 17 unneback
// WB ROM
979 40 unneback
`define MODULE wb_boot_rom
980
module `BASE`MODULE (
981
`undef MODULE
982 17 unneback
    wb_adr_i, wb_stb_i, wb_cyc_i,
983 18 unneback
    wb_dat_o, wb_ack_o, hit_o, wb_clk, wb_rst);
984 17 unneback
 
985 18 unneback
    parameter adr_hi = 31;
986
    parameter adr_lo = 28;
987
    parameter adr_sel = 4'hf;
988
    parameter addr_width = 5;
989 33 unneback
/*
990 17 unneback
//E2_ifndef BOOT_ROM
991
//E2_define BOOT_ROM "boot_rom.v"
992
//E2_endif
993 33 unneback
*/
994 18 unneback
    input [adr_hi:2]    wb_adr_i;
995
    input               wb_stb_i;
996
    input               wb_cyc_i;
997
    output [31:0]        wb_dat_o;
998
    output              wb_ack_o;
999
    output              hit_o;
1000
    input               wb_clk;
1001
    input               wb_rst;
1002
 
1003
    wire hit;
1004
    reg [31:0] wb_dat;
1005
    reg wb_ack;
1006
 
1007
assign hit = wb_adr_i[adr_hi:adr_lo] == adr_sel;
1008 17 unneback
 
1009
always @ (posedge wb_clk or posedge wb_rst)
1010
    if (wb_rst)
1011 18 unneback
        wb_dat <= 32'h15000000;
1012 17 unneback
    else
1013 18 unneback
         case (wb_adr_i[addr_width-1:2])
1014 33 unneback
//E2_ifdef BOOT_ROM
1015 17 unneback
//E2_include `BOOT_ROM
1016 33 unneback
//E2_endif
1017 17 unneback
           /*
1018
            // Zero r0 and jump to 0x00000100
1019 18 unneback
 
1020
            1 : wb_dat <= 32'hA8200000;
1021
            2 : wb_dat <= 32'hA8C00100;
1022
            3 : wb_dat <= 32'h44003000;
1023
            4 : wb_dat <= 32'h15000000;
1024 17 unneback
            */
1025
           default:
1026 18 unneback
             wb_dat <= 32'h00000000;
1027 17 unneback
 
1028
         endcase // case (wb_adr_i)
1029
 
1030
 
1031
always @ (posedge wb_clk or posedge wb_rst)
1032
    if (wb_rst)
1033 18 unneback
        wb_ack <= 1'b0;
1034 17 unneback
    else
1035 18 unneback
        wb_ack <= wb_stb_i & wb_cyc_i & hit & !wb_ack;
1036 17 unneback
 
1037 18 unneback
assign hit_o = hit;
1038
assign wb_dat_o = wb_dat & {32{wb_ack}};
1039
assign wb_ack_o = wb_ack;
1040
 
1041 17 unneback
endmodule
1042 40 unneback
`endif
1043 32 unneback
 
1044 40 unneback
`ifdef WB_DPRAM
1045
`define MODULE wb_dpram
1046
module `BASE`MODULE (
1047
`undef MODULE
1048 32 unneback
        // wishbone slave side a
1049
        wbsa_dat_i, wbsa_adr_i, wbsa_we_i, wbsa_cyc_i, wbsa_stb_i, wbsa_dat_o, wbsa_ack_o,
1050
        wbsa_clk, wbsa_rst,
1051
        // wishbone slave side a
1052
        wbsb_dat_i, wbsb_adr_i, wbsb_we_i, wbsb_cyc_i, wbsb_stb_i, wbsb_dat_o, wbsb_ack_o,
1053
        wbsb_clk, wbsb_rst);
1054
 
1055
parameter data_width = 32;
1056
parameter addr_width = 8;
1057
 
1058
parameter dat_o_mask_a = 1;
1059
parameter dat_o_mask_b = 1;
1060
 
1061
input [31:0] wbsa_dat_i;
1062
input [addr_width-1:2] wbsa_adr_i;
1063
input wbsa_we_i, wbsa_cyc_i, wbsa_stb_i;
1064
output [31:0] wbsa_dat_o;
1065
output wbsa_ack_o;
1066
input wbsa_clk, wbsa_rst;
1067
 
1068
input [31:0] wbsb_dat_i;
1069
input [addr_width-1:2] wbsb_adr_i;
1070
input wbsb_we_i, wbsb_cyc_i, wbsb_stb_i;
1071
output [31:0] wbsb_dat_o;
1072
output wbsb_ack_o;
1073
input wbsb_clk, wbsb_rst;
1074
 
1075
wire wbsa_dat_tmp, wbsb_dat_tmp;
1076
 
1077 40 unneback
`define MODULE dpram_2r2w
1078
`BASE`MODULE # (
1079
`undef MODULE
1080 33 unneback
    .data_width(data_width), .addr_width(addr_width) )
1081 32 unneback
dpram0(
1082
    .d_a(wbsa_dat_i),
1083
    .q_a(wbsa_dat_tmp),
1084
    .adr_a(wbsa_adr_i),
1085
    .we_a(wbsa_we_i),
1086
    .clk_a(wbsa_clk),
1087
    .d_b(wbsb_dat_i),
1088
    .q_b(wbsb_dat_tmp),
1089
    .adr_b(wbsb_adr_i),
1090
    .we_b(wbsb_we_i),
1091
    .clk_b(wbsb_clk) );
1092
 
1093 33 unneback
generate if (dat_o_mask_a==1)
1094 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp & {data_width{wbsa_ack_o}};
1095
endgenerate
1096 33 unneback
generate if (dat_o_mask_a==0)
1097 32 unneback
    assign wbsa_dat_o = wbsa_dat_tmp;
1098
endgenerate
1099
 
1100 33 unneback
generate if (dat_o_mask_b==1)
1101 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp & {data_width{wbsb_ack_o}};
1102
endgenerate
1103 33 unneback
generate if (dat_o_mask_b==0)
1104 32 unneback
    assign wbsb_dat_o = wbsb_dat_tmp;
1105
endgenerate
1106
 
1107 40 unneback
`define MODULE spr
1108
`BASE`MODULE ack_a( .sp(wbsa_cyc_i & wbsa_stb_i & !wbsa_ack_o), .r(1'b1), .q(wbsa_ack_o), .clk(wbsa_clk), .rst(wbsa_rst));
1109
`BASE`MODULE ack_b( .sp(wbsb_cyc_i & wbsb_stb_i & !wbsb_ack_o), .r(1'b1), .q(wbsb_ack_o), .clk(wbsb_clk), .rst(wbsb_rst));
1110
`undef MODULE
1111 32 unneback
 
1112
endmodule
1113 40 unneback
`endif

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