URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [sim/] [rtl_sim/] [run/] [Makefile] - Blame information for rev 88

Line No.	Rev	Author	Line
1	88	unneback	`VERILOG_FILES = ./../../../rtl/verilog/versatile_library.v`
2
3			`wb_b3_ram_be.v:`
4			`vppreproc --noline --noblank +define+SYSTEMVERILOG +define+WB_B3_RAM_BE $(VERILOG_FILES) > wb_b3_ram_be.v`