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[/] [versatile_library/] [trunk/] [sim/] [rtl_sim/] [run/] [Makefile] - Blame information for rev 88

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Line No. Rev Author Line
1 88 unneback
VERILOG_FILES = ./../../../rtl/verilog/versatile_library.v
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wb_b3_ram_be.v:
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        vppreproc --noline --noblank +define+SYSTEMVERILOG +define+WB_B3_RAM_BE $(VERILOG_FILES) > wb_b3_ram_be.v

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