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[/] [vhdl_wb_tb/] [trunk/] [bench/] [vhdl/] [tb_top.vhd] - Blame information for rev 18

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---------------------------------------------------------------------- 
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----                                                              ---- 
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----  VHDL Wishbone TESTBENCH                                     ---- 
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----                                                              ---- 
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----  This file is part of the vhdl_wb_tb project                 ---- 
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----  https://opencores.org/project/vhdl_wb_tb                    ---- 
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----                                                              ---- 
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----  This file contains the highest (top) module for simulation. ----
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----  Like tb_top it instantiates the core_top module and         ----
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----  provides parameters/generics. Where the top module provides ---- 
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----  parameters for synthesis this file provides parameters for  ----
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----  simulation.                                                 ----
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----                                                              ---- 
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----  It instantiates the design under test (DUT), instantiates   ----
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----  the stimulator module for test vector generation,           ----
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----  instantiates the verifier module for result comparison,     ----
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----  instantiates the test case top (testcase_top) bfm,          ----
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----  interconnects all three components, generates DUT-external  ----
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----  clocks and resets.                                          ----
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----                                                              ---- 
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----  To Do:                                                      ---- 
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----   -                                                          ---- 
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----                                                              ---- 
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----  Author(s):                                                  ---- 
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----      - Sinx, sinx@opencores.org                              ---- 
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----                                                              ---- 
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----------------------------------------------------------------------
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----    SVN information
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----
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----      $URL: file:///svn/vhdl_wb_tb/vhdl_wb_tb/trunk/bench/vhdl/tb_top.vhd $
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---- $Revision: 18 $
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----     $Date: 2018-08-01 11:56:15 +0200 (Wed, 01 Aug 2018) $
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----   $Author: sinx $
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----       $Id: tb_top.vhd 18 2018-08-01 09:56:15Z sinx $
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---------------------------------------------------------------------- 
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----                                                              ---- 
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---- Copyright (C) 2018 Authors and OPENCORES.ORG                 ---- 
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----                                                              ---- 
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---- This source file may be used and distributed without         ---- 
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---- restriction provided that this copyright statement is not    ---- 
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---- removed from the file and that any derivative work contains  ---- 
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---- the original copyright notice and the associated disclaimer. ---- 
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----                                                              ---- 
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---- This source file is free software; you can redistribute it   ---- 
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---- and/or modify it under the terms of the GNU Lesser General   ---- 
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---- Public License as published by the Free Software Foundation; ---- 
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---- either version 2.1 of the License, or (at your option) any   ---- 
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---- later version.                                               ---- 
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----                                                              ---- 
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---- This source is distributed in the hope that it will be       ---- 
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---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
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---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
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---- details.                                                     ---- 
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----                                                              ---- 
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---- You should have received a copy of the GNU Lesser General    ---- 
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---- Public License along with this source; if not, download it   ---- 
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---- from http://www.opencores.org/lgpl.shtml                     ---- 
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----                                                              ---- 
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----------------------------------------------------------------------
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-- library -----------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.convert_pkg.all;
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use work.wishbone_pkg.all;
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use work.wishbone_bfm_pkg.all;
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-- entity ------------------------------------------------------------
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entity tb_top is
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  -- empty entity, since this is the simulation top and all test cases are defined
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  -- in the tc_xxx files.
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end entity tb_top;
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-- architecture ------------------------------------------------------
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architecture rtl of tb_top is
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  -----------------------------------------------------------------------------
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  constant  wb_clock_period_g               : time     := 20.0 ns;   -- 50 mhz
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  -----------------------------------------------------------------------------
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  signal wb_bfm_out_s                 : wishbone_bfm_master_out_t; -- from testcase_top
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  signal wb_bfm_in_s                  : wishbone_bfm_master_in_t;  -- to testcase_top
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  signal wb_master_out_s              : wishbone_master_out_t;    -- from wb_decoder
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  signal wb_master_in_s               : wishbone_master_in_t;    -- to wb_decoder
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  constant number_of_wb_slaves_c      : integer := 2;
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  signal wb_slaves_in_s               : wishbone_slave_in_array_t (number_of_wb_slaves_c-1 downto 0);
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  signal wb_slaves_out_s              : wishbone_slave_out_array_t (number_of_wb_slaves_c-1 downto 0);
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  signal wb_clock_s                   : std_logic := '0';
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  signal wb_clock_locked_s            : std_logic := '0';
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  signal wb_reset_p1_s                : std_logic := '1';
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  signal wb_reset_p2_s                : std_logic := '1';
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  signal wb_reset_s                   : std_logic := '1';
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  constant number_of_stimulus_signals_c : integer := 8;
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  constant number_of_verify_signals_c   : integer := 8;
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  signal stimulus_s                   : std_logic_vector(number_of_stimulus_signals_c-1 downto 0);
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  signal verify_s                     : std_logic_vector(number_of_verify_signals_c-1 downto 0);
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  -----------------------------------------------------------------------------
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begin
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  -----------------------------------------------------------------------------
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  --clocks---------------------------------------------------------------------
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  wb_clock_generator : process -- required for test bench wb bus; 50mhz is standard
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  begin
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    wb_clock_s        <= '0';
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    wait for wb_clock_period_g/2;
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    wb_clock_s        <= '1';
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    wait for wb_clock_period_g/2;
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    wb_clock_locked_s <= '1';
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  end process;
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  -----------------------------------------------------------------------------
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  synchronize_reset_proc : process(all)
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  begin
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    if (wb_clock_locked_s = '0') then
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      wb_reset_p1_s <= '1';
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      wb_reset_p2_s <= '1';
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    elsif (rising_edge(wb_clock_s)) then
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      wb_reset_p1_s <= '0'; -- or tc_reset_s;
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      wb_reset_p2_s <= wb_reset_p1_s;
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    end if;
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  end process;
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  wb_reset_s   <= wb_reset_p2_s;
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  -----------------------------------------------------------------------------
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  -- instance of test case "player"; runs tc_xxxx modules
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  tc_top_inst : entity work.tc_top
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    port map (
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      wb_o                => wb_bfm_out_s,
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      wb_i                => wb_bfm_in_s
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      );
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  -----------------------------------------------------------------------------
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  -- splits the test case wb bus for all stimulation and verifier modules.
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  -- decodes the given bits (decoded_address_msb_g:decoded_address_lsb_g) and#
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  -- compares them to 0..n, with n=(number_of_ports_g-1)
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  proc_readdata_decoder  : process (all)
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    begin
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      wb_bfm_in_s.dat <= (others => 'U');
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      wb_bfm_in_s.ack <= '1';
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      wb_bfm_in_s.clk <= wb_clock_s;
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      wb_bfm_in_s.int <= '0';
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      wb_bfm_in_s.rst <= wb_reset_s;
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      wb_bfm_in_s.tgd <= (others => '0');
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      wb_bfm_in_s.err <= '0';
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      wb_bfm_in_s.rty <= '0';
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      for I in number_of_wb_slaves_c-1 downto 0 loop
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        wb_slaves_in_s(I) <= work.wishbone_pkg.wb_master_out_idle_c; -- default values are init (idle) values
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        wb_slaves_in_s(I).clk <= wb_clock_s;
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        wb_slaves_in_s(I).rst <= wb_reset_s OR wb_bfm_out_s.rst;
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        if ( wb_bfm_out_s.adr(31 downto 28) = to_std_logic_vector(I,4)) then -- decode the upper nibble for module decoding
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          wb_bfm_in_s.dat <= wb_slaves_out_s(I).dat;
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          wb_bfm_in_s.ack <= wb_slaves_out_s(I).ack;
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          wb_bfm_in_s.tgd <= wb_slaves_out_s(I).tgd;
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          wb_bfm_in_s.err <= wb_slaves_out_s(I).err;
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          wb_bfm_in_s.rty <= wb_slaves_out_s(I).rty;
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          wb_slaves_in_s(I).dat <= wb_bfm_out_s.dat;
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          wb_slaves_in_s(I).tgd  <= wb_bfm_out_s.tgd;
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          wb_slaves_in_s(I).adr  <= wb_bfm_out_s.adr;
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          wb_slaves_in_s(I).cyc  <= wb_bfm_out_s.cyc;
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          wb_slaves_in_s(I).lock <= wb_bfm_out_s.lock;
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          wb_slaves_in_s(I).sel  <= wb_bfm_out_s.sel;
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          wb_slaves_in_s(I).stb  <= wb_bfm_out_s.stb;
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          wb_slaves_in_s(I).tga  <= wb_bfm_out_s.tga;
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          wb_slaves_in_s(I).tgc  <= wb_bfm_out_s.tgc;
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          wb_slaves_in_s(I).we   <= wb_bfm_out_s.we;
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        end if;
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      end loop;
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  end process;
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  -----------------------------------------------------------------------------
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  -- instance of design under test
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  core_top_inst : entity work.core_top
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    generic map(
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      number_of_in_signals_g              => number_of_stimulus_signals_c,
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      number_of_out_signals_g             => number_of_verify_signals_c
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      )
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    port map(
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      clock_i                             => wb_clock_s,
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      reset_i                             => wb_reset_s,
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      signals_i                           => stimulus_s,
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      signals_o                           => verify_s
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      );
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  -----------------------------------------------------------------------------
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  -- instance of stimulator
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  stimulator_inst : entity work.stimulator
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    generic map(
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      number_of_signals_g                 => number_of_stimulus_signals_c
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      )
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    port map(
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      wb_i                                => wb_slaves_in_s(0),
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      wb_o                                => wb_slaves_out_s(0),
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      signals_o                           => stimulus_s
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      );
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  -----------------------------------------------------------------------------
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  -- instance of stimulator
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  verifier_inst : entity work.verifier
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    generic map(
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      number_of_signals_g                 => number_of_verify_signals_c
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      )
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    port map(
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      wb_i                                => wb_slaves_in_s(1),
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      wb_o                                => wb_slaves_out_s(1),
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      signals_i                           => verify_s
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      );
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  -----------------------------------------------------------------------------
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end rtl;
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----------------------------------------------------------------------
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---- end of file                                                  ---- 
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----------------------------------------------------------------------

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