OpenCores
URL https://opencores.org/ocsvn/vhdl_wb_tb/vhdl_wb_tb/trunk

Subversion Repositories vhdl_wb_tb

[/] [vhdl_wb_tb/] [trunk/] [bench/] [vhdl/] [tc_top.vhd] - Blame information for rev 4

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 4 sinx
---------------------------------------------------------------------- 
2
----                                                              ---- 
3
----  VHDL Wishbone TESTBENCH                                     ---- 
4
----                                                              ---- 
5
----  This file is part of the vhdl_wb_tb project                 ---- 
6
----  http://www.opencores.org/cores/vhdl_wb_tb/                  ---- 
7
----                                                              ---- 
8
----  This file contains the top of the test case module.         ----
9
----  It contains only an entity whereas the architecture is      ----
10
----  located in several tc_xxxx files.                           ----  
11
----  Every test case shall have its own tc_xxxx file. Every      ----
12
----  tc_xxxx file needs to be compiled into the work library and ----
13
----  simulated independently. Use a script to run all tc_xxx     ----
14
----  files automatically.                                        ----
15
----                                                              ---- 
16
----  To Do:                                                      ---- 
17
----   -                                                          ---- 
18
----                                                              ---- 
19
----  Author(s):                                                  ---- 
20
----      - Sinx, sinx@opencores.org                              ---- 
21
----                                                              ---- 
22
---------------------------------------------------------------------- 
23
----    SVN information
24
----
25
----      $URL:  $
26
---- $Revision:  $
27
----     $Date:  $
28
----   $Author:  $
29
----       $Id:  $
30
---------------------------------------------------------------------- 
31
----                                                              ---- 
32
---- Copyright (C) 2018 Authors and OPENCORES.ORG                 ---- 
33
----                                                              ---- 
34
---- This source file may be used and distributed without         ---- 
35
---- restriction provided that this copyright statement is not    ---- 
36
---- removed from the file and that any derivative work contains  ---- 
37
---- the original copyright notice and the associated disclaimer. ---- 
38
----                                                              ---- 
39
---- This source file is free software; you can redistribute it   ---- 
40
---- and/or modify it under the terms of the GNU Lesser General   ---- 
41
---- Public License as published by the Free Software Foundation; ---- 
42
---- either version 2.1 of the License, or (at your option) any   ---- 
43
---- later version.                                               ---- 
44
----                                                              ---- 
45
---- This source is distributed in the hope that it will be       ---- 
46
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
47
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
48
---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
49
---- details.                                                     ---- 
50
----                                                              ---- 
51
---- You should have received a copy of the GNU Lesser General    ---- 
52
---- Public License along with this source; if not, download it   ---- 
53
---- from http://www.opencores.org/lgpl.shtml                     ---- 
54
----                                                              ---- 
55
----------------------------------------------------------------------
56
 
57
-- library -----------------------------------------------------------
58
library ieee;
59
use ieee.std_logic_1164.all;
60
use ieee.numeric_std.all;
61
library work;
62
use work.convert_pkg.all;
63
use work.my_project_pkg.all;
64
use work.wishbone_pkg.all;
65
use work.wishbone_bfm_pkg.all;
66
 
67
-- entity ------------------------------------------------------------
68
entity tc_top is
69
  port (
70
    wb_o           : out wishbone_bfm_master_out_t;
71
    wb_i           : in  wishbone_bfm_master_in_t
72
    );
73
end entity tc_top;
74
----------------------------------------------------------------------
75
---- end of file                                                  ---- 
76
----------------------------------------------------------------------

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.