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---- ----
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---- VHDL Wishbone TESTBENCH ----
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---- ----
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---- This file is part of the vhdl_wb_tb project ----
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---- http://www.opencores.org/cores/vhdl_wb_tb/ ----
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---- ----
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---- This file contains the top functional module of the design ----
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---- under test. The top functional module will be enclosed by ----
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---- the top module for synthesis or the tb_top for simulation. ----
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---- The top module can contain some synthesis specific code, ----
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---- where the tb_top contains simulation specific code. ----
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---- ----
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---- To Do: ----
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---- - ----
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---- ----
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---- Author(s): ----
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---- - Sinx, email@opencores.org ----
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---- ----
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----------------------------------------------------------------------
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-- SVN information
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--
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-- $URL: $
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-- $Revision: $
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-- $Date: $
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-- $Author: $
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-- $Id: $
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--
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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-- library -----------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.convert_pkg.all;
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use work.wishbone_pkg.all;
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use work.my_project_pkg.all;
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use work.wishbone_bfm_pkg.all;
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-- entity ------------------------------------------------------------
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entity verifier is
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generic(
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g_number_of_signals : natural := 1
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);
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port(
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wb_i : in wishbone_slave_in_t;
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wb_o : out wishbone_slave_out_t;
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signals_i : in std_logic_vector(g_number_of_signals-1 downto 0)
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);
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end verifier;
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--=architecture===============================================================
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architecture rtl of verifier is
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--============================================================================
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-- signal declaration
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--============================================================================
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signal s_register0 : std_logic_vector(31 downto 0);
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signal s_register1 : std_logic_vector(31 downto 0);
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--============================================================================
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begin
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------------------------------------------------------------------------------
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wb_o.ack <= '1';
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wb_o.err <= '0';
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wb_o.rty <= '0';
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wb_o.int <= '0';
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wb_o.tgd <= (others => '0');
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-- read data multiplexer
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proc_read_data_mux : process (all)
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begin
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case wb_i.adr(27 downto 0) is
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when 28X"000_0000" =>
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wb_o.dat <= s_register0;
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when 28X"000_0004" =>
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wb_o.dat <= s_register1;
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when 28X"000_0008" =>
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wb_o.dat <= zero_c(wb_o.dat'left downto signals_i'left+1) & signals_i;
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when others =>
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wb_o.dat <= (others =>'U');
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end case;
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end process;
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------------------------------------------------------------------------------
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-- write signals to control the verifier
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proc_avalon_write_data : process (all)
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begin
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if (wb_i.rst = '1') then
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s_register0 <= (others => '0');
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s_register1 <= (others => '0');
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elsif (rising_edge(wb_i.clk)) then
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if (wb_i.we = '1' AND wb_i.stb = '1' AND wb_i.sel = X"F" AND wb_i.cyc = '1') then
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case wb_i.adr(27 downto 0) is
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when 28X"000_0000" =>
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s_register0 <= wb_i.dat;
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when 28X"000_0004" =>
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s_register1 <= wb_i.dat;
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when others =>
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end case;
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end if;
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end if;
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end process;
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------------------------------------------------------------------------------
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--============================================================================
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end rtl; --verifier
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--============================================================================
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-- end of file
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--============================================================================
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