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---------------------------------------------------------------------- 
----                                                              ---- 
----  VHDL Wishbone TESTBENCH                                     ---- 
----                                                              ---- 
----  This file is part of the vhdl_wb_tb project                 ---- 
----  http://www.opencores.org/cores/vhdl_wb_tb/                  ---- 
----                                                              ---- 
----  This file contains the verifier module which monitors the   ----
----  DUTs responses. It is controlled via a wishbone interface   ----
----  by the tc_xxxx files.                                       ---- 
----  It can check the signals by itself or forward information   ----
----  To the tc_xxxx files.                                       ----
----                                                              ---- 
----  To Do:                                                      ---- 
----   -                                                          ---- 
----                                                              ---- 
----  Author(s):                                                  ---- 
----      - Sinx, sinx@opencores.org                              ---- 
----                                                              ---- 
---------------------------------------------------------------------- 
----    SVN information
----
----      $URL:  $
---- $Revision:  $
----     $Date:  $
----   $Author:  $
----       $Id:  $
---------------------------------------------------------------------- 
----                                                              ---- 
---- Copyright (C) 2018 Authors and OPENCORES.ORG                 ---- 
----                                                              ---- 
---- This source file may be used and distributed without         ---- 
---- restriction provided that this copyright statement is not    ---- 
---- removed from the file and that any derivative work contains  ---- 
---- the original copyright notice and the associated disclaimer. ---- 
----                                                              ---- 
---- This source file is free software; you can redistribute it   ---- 
---- and/or modify it under the terms of the GNU Lesser General   ---- 
---- Public License as published by the Free Software Foundation; ---- 
---- either version 2.1 of the License, or (at your option) any   ---- 
---- later version.                                               ---- 
----                                                              ---- 
---- This source is distributed in the hope that it will be       ---- 
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
---- details.                                                     ---- 
----                                                              ---- 
---- You should have received a copy of the GNU Lesser General    ---- 
---- Public License along with this source; if not, download it   ---- 
---- from http://www.opencores.org/lgpl.shtml                     ---- 
----                                                              ---- 
----------------------------------------------------------------------
 
-- library -----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.convert_pkg.all;
use work.wishbone_pkg.all;
use work.my_project_pkg.all;
use work.wishbone_bfm_pkg.all;
 
-- entity ------------------------------------------------------------
entity verifier is
  generic(
    number_of_signals_g             : natural := 1
    );
  port(
    wb_i                            : in wishbone_slave_in_t;
    wb_o                            : out wishbone_slave_out_t;
 
    signals_i                       : in std_logic_vector(number_of_signals_g-1 downto 0)
    );
end verifier;
 
-- architecture ----------------------------------------------------------------
architecture rtl of verifier is
  ------------------------------------------------------------------------------
  -- signal declaration
  ------------------------------------------------------------------------------
  signal  register0_s                    : std_logic_vector(31 downto 0);
  signal  register1_s                    : std_logic_vector(31 downto 0);
  ------------------------------------------------------------------------------
begin
  ------------------------------------------------------------------------------
  wb_o.ack <= '1';
  wb_o.err <= '0';
  wb_o.rty <= '0';
  wb_o.int <= '0';
  wb_o.tgd <= (others => '0');
 
  -- read data multiplexer
  proc_read_data_mux : process (all)
    begin
      case wb_i.adr(27 downto 0) is
        when 28X"000_0000" =>
          wb_o.dat <= register0_s;
        when 28X"000_0004" =>
          wb_o.dat <= register1_s;
        when 28X"000_0008" =>
          wb_o.dat <= zero_c(wb_o.dat'left downto signals_i'left+1) & signals_i;
        when others =>
          wb_o.dat <= (others =>'U');
      end case;
    end process;
  ------------------------------------------------------------------------------
  -- write signals to control the verifier
  proc_avalon_write_data  : process (all)
    begin
      if (wb_i.rst = '1') then
        register0_s        <= (others => '0');
        register1_s        <= (others => '0');
      elsif (rising_edge(wb_i.clk)) then
        if (wb_i.we = '1' AND wb_i.stb = '1' AND wb_i.sel = X"F" AND wb_i.cyc = '1') then
          case wb_i.adr(27 downto 0) is
            when 28X"000_0000" =>
              register0_s        <= wb_i.dat;
            when 28X"000_0004" =>
              register1_s        <= wb_i.dat;
            when others =>
          end case;
        end if;
      end if;
    end process;
 
  ------------------------------------------------------------------------------
end rtl; --verifier
----------------------------------------------------------------------
---- end of file                                                  ---- 
----------------------------------------------------------------------

Line No.	Rev	Author	Line
1	2	sinx	`----------------------------------------------------------------------`
2			`---- ----`
3			`---- VHDL Wishbone TESTBENCH ----`
4			`---- ----`
5			`---- This file is part of the vhdl_wb_tb project ----`
6			`---- http://www.opencores.org/cores/vhdl_wb_tb/ ----`
7			`---- ----`
8	4	sinx	`---- This file contains the verifier module which monitors the ----`
9			`---- DUTs responses. It is controlled via a wishbone interface ----`
10			`---- by the tc_xxxx files. ----`
11			`---- It can check the signals by itself or forward information ----`
12			`---- To the tc_xxxx files. ----`
13	2	sinx	`---- ----`
14			`---- To Do: ----`
15			`---- - ----`
16			`---- ----`
17			`---- Author(s): ----`
18	4	sinx	`---- - Sinx, sinx@opencores.org ----`
19	2	sinx	`---- ----`
20			`----------------------------------------------------------------------`
21	4	sinx	`---- SVN information`
22			`----`
23			`---- $URL: $`
24			`---- $Revision: $`
25			`---- $Date: $`
26			`---- $Author: $`
27			`---- $Id: $`
28			`----------------------------------------------------------------------`
29	2	sinx	`---- ----`
30			`---- Copyright (C) 2018 Authors and OPENCORES.ORG ----`
31			`---- ----`
32			`---- This source file may be used and distributed without ----`
33			`---- restriction provided that this copyright statement is not ----`
34			`---- removed from the file and that any derivative work contains ----`
35			`---- the original copyright notice and the associated disclaimer. ----`
36			`---- ----`
37			`---- This source file is free software; you can redistribute it ----`
38			`---- and/or modify it under the terms of the GNU Lesser General ----`
39			`---- Public License as published by the Free Software Foundation; ----`
40			`---- either version 2.1 of the License, or (at your option) any ----`
41			`---- later version. ----`
42			`---- ----`
43			`---- This source is distributed in the hope that it will be ----`
44			`---- useful, but WITHOUT ANY WARRANTY; without even the implied ----`
45			`---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----`
46			`---- PURPOSE. See the GNU Lesser General Public License for more ----`
47			`---- details. ----`
48			`---- ----`
49			`---- You should have received a copy of the GNU Lesser General ----`
50			`---- Public License along with this source; if not, download it ----`
51			`---- from http://www.opencores.org/lgpl.shtml ----`
52			`---- ----`
53			`----------------------------------------------------------------------`
54
55			`-- library -----------------------------------------------------------`
56			`library ieee;`
57			`use ieee.std_logic_1164.all;`
58			`use ieee.numeric_std.all;`
59			`library work;`
60			`use work.convert_pkg.all;`
61			`use work.wishbone_pkg.all;`
62			`use work.my_project_pkg.all;`
63			`use work.wishbone_bfm_pkg.all;`
64
65			`-- entity ------------------------------------------------------------`
66			`entity verifier is`
67			`generic(`
68	5	sinx	`number_of_signals_g : natural := 1`
69	2	sinx	`);`
70			`port(`
71			`wb_i : in wishbone_slave_in_t;`
72			`wb_o : out wishbone_slave_out_t;`
73
74	5	sinx	`signals_i : in std_logic_vector(number_of_signals_g-1 downto 0)`
75	2	sinx	`);`
76			`end verifier;`
77
78	4	sinx	`-- architecture ----------------------------------------------------------------`
79	2	sinx	`architecture rtl of verifier is`
80	4	sinx	`------------------------------------------------------------------------------`
81	2	sinx	`-- signal declaration`
82	4	sinx	`------------------------------------------------------------------------------`
83	5	sinx	`signal register0_s : std_logic_vector(31 downto 0);`
84			`signal register1_s : std_logic_vector(31 downto 0);`
85	4	sinx	`------------------------------------------------------------------------------`
86	2	sinx	`begin`
87			`------------------------------------------------------------------------------`
88			`wb_o.ack <= '1';`
89			`wb_o.err <= '0';`
90			`wb_o.rty <= '0';`
91			`wb_o.int <= '0';`
92			`wb_o.tgd <= (others => '0');`
93
94			`-- read data multiplexer`
95			`proc_read_data_mux : process (all)`
96			`begin`
97			`case wb_i.adr(27 downto 0) is`
98			`when 28X"000_0000" =>`
99	5	sinx	`wb_o.dat <= register0_s;`
100	2	sinx	`when 28X"000_0004" =>`
101	5	sinx	`wb_o.dat <= register1_s;`
102	2	sinx	`when 28X"000_0008" =>`
103			`wb_o.dat <= zero_c(wb_o.dat'left downto signals_i'left+1) & signals_i;`
104			`when others =>`
105			`wb_o.dat <= (others =>'U');`
106			`end case;`
107			`end process;`
108			`------------------------------------------------------------------------------`
109			`-- write signals to control the verifier`
110			`proc_avalon_write_data : process (all)`
111			`begin`
112			`if (wb_i.rst = '1') then`
113	5	sinx	`register0_s <= (others => '0');`
114			`register1_s <= (others => '0');`
115	2	sinx	`elsif (rising_edge(wb_i.clk)) then`
116			`if (wb_i.we = '1' AND wb_i.stb = '1' AND wb_i.sel = X"F" AND wb_i.cyc = '1') then`
117			`case wb_i.adr(27 downto 0) is`
118			`when 28X"000_0000" =>`
119	5	sinx	`register0_s <= wb_i.dat;`
120	2	sinx	`when 28X"000_0004" =>`
121	5	sinx	`register1_s <= wb_i.dat;`
122	2	sinx	`when others =>`
123			`end case;`
124			`end if;`
125			`end if;`
126			`end process;`
127
128			`------------------------------------------------------------------------------`
129			`end rtl; --verifier`
130	4	sinx	`----------------------------------------------------------------------`
131			`---- end of file ----`
132			`----------------------------------------------------------------------`

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[/] [vhdl_wb_tb/] [trunk/] [bench/] [vhdl/] [verifier.vhd] - Blame information for rev 5