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---- ----
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---- VHDL Wishbone TESTBENCH ----
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---- ----
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---- This file is part of the vhdl_wb_tb project ----
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---- http://www.opencores.org/cores/vhdl_wb_tb/ ----
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---- ----
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---- This file contains the wishbone_bfm_pkg package and defines ----
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---- wishbone transaction processes functions for simulation. ----
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---- ----
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---- To Do: ----
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---- - ----
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---- ----
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---- Author(s): ----
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---- - Sinx, email@opencores.org ----
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---- ----
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----------------------------------------------------------------------
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-- SVN information
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--
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-- $URL: $
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-- $Revision: $
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-- $Date: $
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-- $Author: $
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-- $Id: $
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--
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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-- library -----------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.my_project_pkg.all;
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use work.wishbone_pkg.all;
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use work.convert_pkg.all;
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-- package -----------------------------------------------------------
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package wishbone_bfm_pkg is
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-- defines output signals of wb bfm (simulation only)
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type wishbone_bfm_master_out_t is record
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-- 2.2.2 Signals Common to MASTER and SLAVE Interfaces
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dat : wishbone_data_t; -- data []
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rst : std_logic; -- reset [mandatory RULE 3.40]
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tgd : wishbone_tag_data_t; -- data tag []
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-- 2.2.3 MASTER Signals
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adr : wishbone_address_t; -- address [optional]
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cyc : std_logic; -- cycle [mandatory RULE 3.40]
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lock: std_logic; -- lock []
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sel : wishbone_byte_select_t;
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stb : std_logic; -- strobe [mandatory RULE 3.40]
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tga : wishbone_tag_address_t; -- address tag []
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tgc : wishbone_tag_cycle_t; -- cycle tag []
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we : std_logic; -- write enable []
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end record wishbone_bfm_master_out_t;
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-- defines input signals of wb bfm (simulation only)
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type wishbone_bfm_master_in_t is record
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-- 2.2.2 Signals Common to MASTER and SLAVE Interfaces
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rst : std_logic; -- reset [mandatory RULE 3.40]
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clk : std_logic; -- clock [mandatory RULE 3.40]
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dat : wishbone_data_t; -- read data []
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tgd : wishbone_tag_data_t; -- read data tag []
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-- 2.2.4 SLAVE Signals
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ack : std_logic; -- acknowledge [mandatory RULE 3.40]
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err : std_logic; -- error [optional PERMISSION 3.20]
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rty : std_logic; -- retry [optional PERMISSION 3.25]
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--stall : std_logic;
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int : std_logic; -- interrupt [non WB signal]
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end record wishbone_bfm_master_in_t;
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-- define the idle state of wb bus
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constant wb_bfm_master_out_idle_c : wishbone_bfm_master_out_t := (
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dat => wishbone_data_of_unused_address_c,
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rst => '0',
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tgd => (others=>'0'),
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adr => (others=>'U'),
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cyc => '0',
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lock => '0',
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sel => (others=>'0'),
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stb => '0',
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tga => (others=>'0'),
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tgc => (others=>'0'),
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we => '0'
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);
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----------------------------------------------------------------------
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-- BUS FUNCTIONS -----------------------------------------------------
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----------------------------------------------------------------------
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-- generate single write cycle
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PROCEDURE wb_write(
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address_i : IN integer; -- address to write to
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data_i : IN integer; -- data value to be written
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SIGNAL i : IN wishbone_bfm_master_in_t; -- incoming wb signals
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SIGNAL o : OUT wishbone_bfm_master_out_t; -- incoming wb signals
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display_error_message_i : IN integer range 0 to 2 := 1; -- verbose mode; 0=no output, 1=error only, 2= all
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additional_error_message_i : IN string := ""
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);
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-- generate single read cycle and verify read word with expected_data_i
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PROCEDURE wb_read(
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address_i : IN INTEGER;
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expected_data_i : IN INTEGER;
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SIGNAL i : IN wishbone_bfm_master_in_t;
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SIGNAL o : OUT wishbone_bfm_master_out_t;
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display_error_message_i : IN integer range 0 to 4 := 1; -- verbose mode; 0=no output, 1=error only, 2= all, 3=use expected_data_mask_i, 4=show difference read to exp.
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additional_error_message_i : IN STRING := "";
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expected_data_mask_i : IN INTEGER := 0
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);
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-- generate single read cycle and return read data via read_data_o
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PROCEDURE wb_read(
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address_i : IN INTEGER;
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read_data_o : OUT STD_LOGIC_VECTOR (wishbone_address_width_c-1 DOWNTO 0);
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SIGNAL i : IN wishbone_bfm_master_in_t;
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SIGNAL o : OUT wishbone_bfm_master_out_t
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);
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----------------------------------------------------------------------
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end;
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-- package body ------------------------------------------------------
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package body wishbone_bfm_pkg is
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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PROCEDURE wb_write(
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address_i : IN integer;
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data_i : IN integer;
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SIGNAL i : IN wishbone_bfm_master_in_t;
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SIGNAL o : OUT wishbone_bfm_master_out_t;
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display_error_message_i : IN integer range 0 to 2 := 1;
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additional_error_message_i : IN string := ""
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) IS
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----------------------------------------------------------------------
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BEGIN
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o.adr <= to_std_logic_vector(address_i, wishbone_address_width_c);
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o.dat <= to_std_logic_vector(data_i, wishbone_address_width_c);
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o.we <= '1';
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o.rst <= '0';
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o.tgd <= (others => '0');
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o.cyc <= '1';
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o.lock <= '1';
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o.sel <= (others => '1');
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o.stb <= '1';
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o.tga <= (others => '0');
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o.tgc <= (others => '0');
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IF (display_error_message_i = 2) THEN
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REPORT "Writing :" & to_string(data_i, 16, wishbone_address_width_c/4) & " to: " & to_string(address_i, 16, wishbone_address_width_c/4) &
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additional_error_message_i;
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END IF;
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WAIT UNTIL falling_edge(i.clk);
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-- wait for ack
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WHILE i.ack = '0' LOOP
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WAIT UNTIL falling_edge(i.clk);
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END LOOP;
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WAIT UNTIL rising_edge(i.clk);
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o <= wb_bfm_master_out_idle_c; -- reset bus
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END wb_write;
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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PROCEDURE wb_read(
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address_i : IN INTEGER;
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read_data_o : OUT STD_LOGIC_VECTOR (wishbone_address_width_c-1 DOWNTO 0);
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SIGNAL i : IN wishbone_bfm_master_in_t;
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SIGNAL o : OUT wishbone_bfm_master_out_t
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) IS
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----------------------------------------------------------------------
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BEGIN
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o.adr <= to_std_logic_vector(address_i, wishbone_address_width_c);
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o.dat <= (others => 'U');
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o.we <= '0';
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o.rst <= '0';
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o.tgd <= (others => '0');
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o.cyc <= '1';
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o.lock <= '1';
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o.sel <= (others => '1');
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o.stb <= '1';
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o.tga <= (others => '0');
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o.tgc <= (others => '0');
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WAIT UNTIL falling_edge(i.clk);
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-- ack handling
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WHILE (i.ack = '0') LOOP
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WAIT UNTIL falling_edge(i.clk);
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END LOOP;
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read_data_o := i.dat;
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WAIT UNTIL rising_edge(i.clk);
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o <= wb_bfm_master_out_idle_c; -- reset bus
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END wb_read;
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------------------------------------------------------------------------
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------------------------------------------------------------------------
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PROCEDURE wb_read(
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address_i : IN INTEGER;
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expected_data_i : IN INTEGER;
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SIGNAL i : IN wishbone_bfm_master_in_t;
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SIGNAL o : OUT wishbone_bfm_master_out_t;
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display_error_message_i : IN integer range 0 to 4 := 1;
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additional_error_message_i : IN STRING := "";
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expected_data_mask_i : IN INTEGER := 0
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) IS
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----------------------------------------------------------------------
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VARIABLE readdata_v : STD_LOGIC_VECTOR (31 DOWNTO 0);
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VARIABLE diff_v : INTEGER;
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----------------------------------------------------------------------
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BEGIN
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wb_read(address_i,readdata_v,i,o); -- read from bus
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diff_v := to_integer(readdata_v) - expected_data_i;
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IF (display_error_message_i = 1) THEN -- output errors only
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IF (readdata_v /= to_std_logic_vector(expected_data_i, wishbone_address_width_c)) THEN
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REPORT "ERROR" & additional_error_message_i & ": Expected data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
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" was: 0x" & to_string(expected_data_i, 16, wishbone_address_width_c/4) & " but read: 0x" & to_string(readdata_v,16,wishbone_address_width_c/4)
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SEVERITY error;
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END IF;
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ELSIF (display_error_message_i = 2) THEN -- Output all
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REPORT additional_error_message_i & ": Read data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
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" was: 0x" & to_string(readdata_v, 16, wishbone_address_width_c/4)
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SEVERITY note;
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ELSIF (display_error_message_i = 3) THEN -- Output Filter
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IF ((readdata_v AND to_std_logic_vector(expected_data_mask_i, wishbone_address_width_c)) /=
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to_std_logic_vector(expected_data_i, wishbone_address_width_c)) THEN
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REPORT additional_error_message_i & ": Read data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
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" was: 0x" & to_string(readdata_v, 16, wishbone_address_width_c/4)
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SEVERITY note;
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END IF;
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ELSIF display_error_message_i = 4 THEN
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IF (readdata_v /= to_std_logic_vector(expected_data_i, wishbone_address_width_c)) THEN
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REPORT "ERROR" & additional_error_message_i & ": Expected data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
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" was: 0x" & to_string(expected_data_i, 16, wishbone_address_width_c/4) & " but read: 0x" & to_string(readdata_v,16,wishbone_address_width_c/4) & " Diff: " & to_string(readdata_v,16,wishbone_address_width_c/4)
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SEVERITY error;
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END IF;
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END IF;
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END wb_read;
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--------------------------------------------------------------------
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end package body;
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----------------------------------------------------------------------
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---- end of file ----
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----------------------------------------------------------------------
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