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sinx |
----------------------------------------------------------------------
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---- ----
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---- VHDL Wishbone TESTBENCH ----
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---- ----
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---- This file is part of the vhdl_wb_tb project ----
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---- http://www.opencores.org/cores/vhdl_wb_tb/ ----
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---- ----
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---- This file contains the wishbone_bfm_pkg package and defines ----
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---- wishbone transaction processes functions for simulation. ----
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---- ----
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---- To Do: ----
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---- - ----
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---- ----
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---- Author(s): ----
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4 |
sinx |
---- - Sinx, sinx@opencores.org ----
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2 |
sinx |
---- ----
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----------------------------------------------------------------------
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4 |
sinx |
---- SVN information
|
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----
|
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14 |
sinx |
---- $URL: file:///svn/vhdl_wb_tb/vhdl_wb_tb/trunk/bench/vhdl/wishbone_bfm_pkg.vhd $
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---- $Revision: 27 $
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---- $Date: 2019-09-21 17:20:11 +0200 (Sat, 21 Sep 2019) $
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---- $Author: sinx $
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---- $Id: wishbone_bfm_pkg.vhd 27 2019-09-21 15:20:11Z sinx $
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25 |
4 |
sinx |
----------------------------------------------------------------------
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2 |
sinx |
---- ----
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27 |
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---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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46 |
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---- You should have received a copy of the GNU Lesser General ----
|
47 |
|
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---- Public License along with this source; if not, download it ----
|
48 |
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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50 |
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----------------------------------------------------------------------
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52 |
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-- library -----------------------------------------------------------
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53 |
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library ieee;
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54 |
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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56 |
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57 |
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library work;
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58 |
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use work.my_project_pkg.all;
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59 |
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use work.wishbone_pkg.all;
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60 |
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use work.convert_pkg.all;
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61 |
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62 |
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-- package -----------------------------------------------------------
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63 |
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package wishbone_bfm_pkg is
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64 |
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-- defines output signals of wb bfm (simulation only)
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65 |
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type wishbone_bfm_master_out_t is record
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66 |
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-- 2.2.2 Signals Common to MASTER and SLAVE Interfaces
|
67 |
|
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dat : wishbone_data_t; -- data []
|
68 |
|
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rst : std_logic; -- reset [mandatory RULE 3.40]
|
69 |
|
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tgd : wishbone_tag_data_t; -- data tag []
|
70 |
|
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-- 2.2.3 MASTER Signals
|
71 |
|
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adr : wishbone_address_t; -- address [optional]
|
72 |
|
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cyc : std_logic; -- cycle [mandatory RULE 3.40]
|
73 |
|
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lock: std_logic; -- lock []
|
74 |
|
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sel : wishbone_byte_select_t;
|
75 |
|
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stb : std_logic; -- strobe [mandatory RULE 3.40]
|
76 |
|
|
tga : wishbone_tag_address_t; -- address tag []
|
77 |
|
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tgc : wishbone_tag_cycle_t; -- cycle tag []
|
78 |
|
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we : std_logic; -- write enable []
|
79 |
|
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end record wishbone_bfm_master_out_t;
|
80 |
|
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|
81 |
|
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-- defines input signals of wb bfm (simulation only)
|
82 |
|
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type wishbone_bfm_master_in_t is record
|
83 |
|
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-- 2.2.2 Signals Common to MASTER and SLAVE Interfaces
|
84 |
|
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rst : std_logic; -- reset [mandatory RULE 3.40]
|
85 |
|
|
clk : std_logic; -- clock [mandatory RULE 3.40]
|
86 |
|
|
dat : wishbone_data_t; -- read data []
|
87 |
|
|
tgd : wishbone_tag_data_t; -- read data tag []
|
88 |
|
|
-- 2.2.4 SLAVE Signals
|
89 |
|
|
ack : std_logic; -- acknowledge [mandatory RULE 3.40]
|
90 |
|
|
err : std_logic; -- error [optional PERMISSION 3.20]
|
91 |
|
|
rty : std_logic; -- retry [optional PERMISSION 3.25]
|
92 |
|
|
--stall : std_logic;
|
93 |
|
|
int : std_logic; -- interrupt [non WB signal]
|
94 |
|
|
end record wishbone_bfm_master_in_t;
|
95 |
|
|
|
96 |
|
|
-- define the idle state of wb bus
|
97 |
|
|
constant wb_bfm_master_out_idle_c : wishbone_bfm_master_out_t := (
|
98 |
20 |
sinx |
dat => wishbone_data_of_unused_address_c,
|
99 |
|
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rst => '0',
|
100 |
|
|
tgd => (others=>'0'),
|
101 |
|
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adr => (others=>'U'),
|
102 |
|
|
cyc => '0',
|
103 |
|
|
lock => '0',
|
104 |
|
|
sel => (others=>'0'),
|
105 |
|
|
stb => '0',
|
106 |
|
|
tga => (others=>'0'),
|
107 |
|
|
tgc => (others=>'0'),
|
108 |
|
|
we => '0'
|
109 |
|
|
);
|
110 |
2 |
sinx |
-- BUS FUNCTIONS -----------------------------------------------------
|
111 |
|
|
----------------------------------------------------------------------
|
112 |
4 |
sinx |
----------------------------------------------------------------------
|
113 |
2 |
sinx |
-- generate single write cycle
|
114 |
4 |
sinx |
procedure wb_write(
|
115 |
23 |
sinx |
address_i : in integer; -- address to write to
|
116 |
|
|
data_i : in integer; -- data value to be written
|
117 |
|
|
signal i : in wishbone_bfm_master_in_t; -- incoming wb signals
|
118 |
|
|
signal o : out wishbone_bfm_master_out_t; -- incoming wb signals
|
119 |
|
|
verbose_mode_i : in integer range 0 to 2 := 1; -- verbose mode; 2= print all activities; others: print nothing
|
120 |
|
|
message_prolog_i : in string := "" -- string to be added in front of generated message
|
121 |
2 |
sinx |
);
|
122 |
|
|
|
123 |
|
|
-- generate single read cycle and verify read word with expected_data_i
|
124 |
4 |
sinx |
procedure wb_read(
|
125 |
23 |
sinx |
address_i : in integer; -- address to read from
|
126 |
|
|
expected_data_i : in integer; -- data to be compared to read data; if different an error message is generated
|
127 |
|
|
signal i : in wishbone_bfm_master_in_t; -- incoming wb signals
|
128 |
|
|
signal o : out wishbone_bfm_master_out_t; -- outgoing wb signals
|
129 |
|
|
verbose_mode_i : in integer range 0 to 4 := 1; -- verbose mode; 0=no output, 1=error only, 2= all, 3=use expected_data_mask_i, 4=show difference read to exp.
|
130 |
|
|
message_prolog_i : in string := ""; -- string to be added in front of generated message
|
131 |
|
|
expected_data_mask_i : in integer := 0 -- bit mask for expected_data_i; 0: bis is not compared; 1: bit is compared
|
132 |
2 |
sinx |
);
|
133 |
|
|
|
134 |
|
|
-- generate single read cycle and return read data via read_data_o
|
135 |
4 |
sinx |
procedure wb_read(
|
136 |
23 |
sinx |
address_i : in integer; -- address to read from
|
137 |
|
|
read_data_o : out std_logic_vector (wishbone_data_width_c-1 downto 0); -- read data output
|
138 |
|
|
signal i : in wishbone_bfm_master_in_t; -- incoming wb signals
|
139 |
|
|
signal o : out wishbone_bfm_master_out_t; -- outgoing wb signals
|
140 |
|
|
verbose_mode_i : in integer range 0 to 4 := 0; -- verbose mode; 2 = output read data; others: no output
|
141 |
|
|
message_prolog_i : in string := "" -- string to be added in front of generated message
|
142 |
2 |
sinx |
);
|
143 |
|
|
----------------------------------------------------------------------
|
144 |
|
|
end;
|
145 |
|
|
|
146 |
|
|
-- package body ------------------------------------------------------
|
147 |
|
|
package body wishbone_bfm_pkg is
|
148 |
|
|
----------------------------------------------------------------------
|
149 |
|
|
----------------------------------------------------------------------
|
150 |
4 |
sinx |
procedure wb_write(
|
151 |
23 |
sinx |
address_i : in integer; -- address to write to
|
152 |
|
|
data_i : in integer; -- data value to be written
|
153 |
|
|
signal i : in wishbone_bfm_master_in_t; -- incoming wb signals
|
154 |
|
|
signal o : out wishbone_bfm_master_out_t; -- outgoing wb signals
|
155 |
|
|
verbose_mode_i : in integer range 0 to 2 := 1; -- verbose mode; 0=no output, 1=error only, 2= all
|
156 |
|
|
message_prolog_i : in string := "" -- string to be added in front of generated message
|
157 |
4 |
sinx |
) is
|
158 |
2 |
sinx |
----------------------------------------------------------------------
|
159 |
4 |
sinx |
begin
|
160 |
2 |
sinx |
o.adr <= to_std_logic_vector(address_i, wishbone_address_width_c);
|
161 |
20 |
sinx |
o.dat <= to_std_logic_vector(data_i, wishbone_data_width_c);
|
162 |
2 |
sinx |
o.we <= '1';
|
163 |
|
|
o.rst <= '0';
|
164 |
|
|
o.tgd <= (others => '0');
|
165 |
|
|
o.cyc <= '1';
|
166 |
|
|
o.lock <= '1';
|
167 |
|
|
o.sel <= (others => '1');
|
168 |
|
|
o.stb <= '1';
|
169 |
|
|
o.tga <= (others => '0');
|
170 |
|
|
o.tgc <= (others => '0');
|
171 |
23 |
sinx |
if (verbose_mode_i = 2) then
|
172 |
|
|
report message_prolog_i & " writing :" & to_string(data_i, 16, wishbone_data_width_c/4) & " to: " & to_string(address_i, 16, wishbone_address_width_c/4);
|
173 |
4 |
sinx |
end if;
|
174 |
2 |
sinx |
|
175 |
20 |
sinx |
-- ack handling
|
176 |
|
|
loop
|
177 |
|
|
wait until rising_edge(i.clk);
|
178 |
|
|
if (i.ack = '1') then
|
179 |
|
|
exit;
|
180 |
|
|
end if;
|
181 |
4 |
sinx |
end loop;
|
182 |
2 |
sinx |
o <= wb_bfm_master_out_idle_c; -- reset bus
|
183 |
4 |
sinx |
end wb_write;
|
184 |
2 |
sinx |
----------------------------------------------------------------------
|
185 |
|
|
----------------------------------------------------------------------
|
186 |
4 |
sinx |
procedure wb_read(
|
187 |
23 |
sinx |
address_i : in integer; -- address to read from
|
188 |
|
|
read_data_o : out std_logic_vector (wishbone_data_width_c-1 downto 0);-- read data output
|
189 |
|
|
signal i : in wishbone_bfm_master_in_t; -- incoming wb signals
|
190 |
|
|
signal o : out wishbone_bfm_master_out_t; -- outgoing wb signals
|
191 |
|
|
verbose_mode_i : in integer range 0 to 4 := 0; -- verbose mode; 2 = output read data; others: no output
|
192 |
|
|
message_prolog_i : in string := "" -- string to be added in front of generated message
|
193 |
4 |
sinx |
) is
|
194 |
2 |
sinx |
----------------------------------------------------------------------
|
195 |
4 |
sinx |
begin
|
196 |
2 |
sinx |
o.adr <= to_std_logic_vector(address_i, wishbone_address_width_c);
|
197 |
|
|
o.dat <= (others => 'U');
|
198 |
|
|
o.we <= '0';
|
199 |
|
|
o.rst <= '0';
|
200 |
|
|
o.tgd <= (others => '0');
|
201 |
|
|
o.cyc <= '1';
|
202 |
|
|
o.lock <= '1';
|
203 |
|
|
o.sel <= (others => '1');
|
204 |
|
|
o.stb <= '1';
|
205 |
|
|
o.tga <= (others => '0');
|
206 |
|
|
o.tgc <= (others => '0');
|
207 |
|
|
-- ack handling
|
208 |
20 |
sinx |
loop
|
209 |
|
|
wait until rising_edge(i.clk);
|
210 |
|
|
read_data_o := i.dat;
|
211 |
|
|
if (i.ack = '1') then
|
212 |
|
|
exit;
|
213 |
|
|
end if;
|
214 |
4 |
sinx |
end loop;
|
215 |
2 |
sinx |
o <= wb_bfm_master_out_idle_c; -- reset bus
|
216 |
23 |
sinx |
|
217 |
|
|
if (verbose_mode_i = 2) then -- output all
|
218 |
|
|
report message_prolog_i & ": read data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
|
219 |
27 |
sinx |
" was: 0x" & to_string(read_data_o, 16, wishbone_data_width_c/4)
|
220 |
23 |
sinx |
severity note;
|
221 |
27 |
sinx |
end if;
|
222 |
4 |
sinx |
end wb_read;
|
223 |
2 |
sinx |
------------------------------------------------------------------------
|
224 |
|
|
------------------------------------------------------------------------
|
225 |
4 |
sinx |
procedure wb_read(
|
226 |
23 |
sinx |
address_i : in integer; -- address to read from
|
227 |
|
|
expected_data_i : in integer; -- data to be compared to read data; if different an error message is generated
|
228 |
|
|
signal i : in wishbone_bfm_master_in_t; -- incoming wb signals
|
229 |
|
|
signal o : out wishbone_bfm_master_out_t; -- outgoing wb signals
|
230 |
|
|
verbose_mode_i : in integer range 0 to 4 := 1; -- verbose mode; 0=no output, 1=error only, 2= all, 3=use expected_data_mask_i, 4=show difference read to exp.
|
231 |
|
|
message_prolog_i : in string := ""; -- string to be added in front of generated message
|
232 |
|
|
expected_data_mask_i : in integer := 0 -- bit mask for expected_data_i; 0: bis is not compared; 1: bit is compared
|
233 |
4 |
sinx |
) is
|
234 |
2 |
sinx |
----------------------------------------------------------------------
|
235 |
4 |
sinx |
variable readdata_v : std_logic_vector (31 downto 0);
|
236 |
|
|
variable diff_v : integer;
|
237 |
2 |
sinx |
----------------------------------------------------------------------
|
238 |
4 |
sinx |
begin
|
239 |
2 |
sinx |
wb_read(address_i,readdata_v,i,o); -- read from bus
|
240 |
20 |
sinx |
|
241 |
2 |
sinx |
diff_v := to_integer(readdata_v) - expected_data_i;
|
242 |
|
|
|
243 |
23 |
sinx |
if (verbose_mode_i = 1) then -- output errors only
|
244 |
20 |
sinx |
if (readdata_v /= to_std_logic_vector(expected_data_i, wishbone_data_width_c)) then
|
245 |
23 |
sinx |
report "error" & message_prolog_i & ": expected data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
|
246 |
20 |
sinx |
" was: 0x" & to_string(expected_data_i, 16, wishbone_data_width_c/4) & " but read: 0x" & to_string(readdata_v,16,wishbone_data_width_c/4)
|
247 |
4 |
sinx |
severity error;
|
248 |
|
|
end if;
|
249 |
23 |
sinx |
elsif (verbose_mode_i = 2) then -- output all
|
250 |
|
|
report message_prolog_i & ": read data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
|
251 |
20 |
sinx |
" was: 0x" & to_string(readdata_v, 16, wishbone_data_width_c/4)
|
252 |
4 |
sinx |
severity note;
|
253 |
23 |
sinx |
elsif (verbose_mode_i = 3) then -- output filter
|
254 |
20 |
sinx |
if ((readdata_v and to_std_logic_vector(expected_data_mask_i, wishbone_data_width_c)) /=
|
255 |
|
|
to_std_logic_vector(expected_data_i, wishbone_data_width_c)) then
|
256 |
23 |
sinx |
report message_prolog_i & ": read data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
|
257 |
20 |
sinx |
" was: 0x" & to_string(readdata_v, 16, wishbone_data_width_c/4)
|
258 |
4 |
sinx |
severity note;
|
259 |
|
|
end if;
|
260 |
23 |
sinx |
elsif verbose_mode_i = 4 then
|
261 |
20 |
sinx |
if (readdata_v /= to_std_logic_vector(expected_data_i, wishbone_data_width_c)) then
|
262 |
23 |
sinx |
report "error" & message_prolog_i & ": expected data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
|
263 |
20 |
sinx |
" was: 0x" & to_string(expected_data_i, 16, wishbone_data_width_c/4) & " but read: 0x" & to_string(readdata_v,16,wishbone_data_width_c/4) & " diff: " & to_string(readdata_v,16,wishbone_address_width_c/4)
|
264 |
4 |
sinx |
severity error;
|
265 |
|
|
end if;
|
266 |
|
|
end if;
|
267 |
|
|
end wb_read;
|
268 |
2 |
sinx |
--------------------------------------------------------------------
|
269 |
|
|
end package body;
|
270 |
|
|
----------------------------------------------------------------------
|
271 |
|
|
---- end of file ----
|
272 |
|
|
----------------------------------------------------------------------
|