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[/] [vhdl_wb_tb/] [trunk/] [bench/] [vhdl/] [wishbone_bfm_pkg.vhd] - Blame information for rev 27

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1 2 sinx
---------------------------------------------------------------------- 
2
----                                                              ---- 
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----  VHDL Wishbone TESTBENCH                                     ---- 
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----                                                              ---- 
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----  This file is part of the vhdl_wb_tb project                 ---- 
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----  http://www.opencores.org/cores/vhdl_wb_tb/                  ---- 
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----                                                              ---- 
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----  This file contains the wishbone_bfm_pkg package and defines ----
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----  wishbone transaction processes functions for simulation.    ---- 
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----                                                              ---- 
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----  To Do:                                                      ---- 
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----   -                                                          ---- 
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----                                                              ---- 
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----  Author(s):                                                  ---- 
15 4 sinx
----      - Sinx, sinx@opencores.org                              ---- 
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----                                                              ---- 
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---------------------------------------------------------------------- 
18 4 sinx
----    SVN information
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----
20 14 sinx
----      $URL: file:///svn/vhdl_wb_tb/vhdl_wb_tb/trunk/bench/vhdl/wishbone_bfm_pkg.vhd $
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---- $Revision: 27 $
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----     $Date: 2019-09-21 17:20:11 +0200 (Sat, 21 Sep 2019) $
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----   $Author: sinx $
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----       $Id: wishbone_bfm_pkg.vhd 27 2019-09-21 15:20:11Z sinx $
25 4 sinx
---------------------------------------------------------------------- 
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----                                                              ---- 
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---- Copyright (C) 2018 Authors and OPENCORES.ORG                 ---- 
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----                                                              ---- 
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---- This source file may be used and distributed without         ---- 
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---- restriction provided that this copyright statement is not    ---- 
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---- removed from the file and that any derivative work contains  ---- 
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---- the original copyright notice and the associated disclaimer. ---- 
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----                                                              ---- 
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---- This source file is free software; you can redistribute it   ---- 
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---- and/or modify it under the terms of the GNU Lesser General   ---- 
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---- Public License as published by the Free Software Foundation; ---- 
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---- either version 2.1 of the License, or (at your option) any   ---- 
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---- later version.                                               ---- 
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----                                                              ---- 
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---- This source is distributed in the hope that it will be       ---- 
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---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
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---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
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---- details.                                                     ---- 
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----                                                              ---- 
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---- You should have received a copy of the GNU Lesser General    ---- 
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---- Public License along with this source; if not, download it   ---- 
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---- from http://www.opencores.org/lgpl.shtml                     ---- 
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----                                                              ---- 
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----------------------------------------------------------------------
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52
-- library -----------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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57
library work;
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use work.my_project_pkg.all;
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use work.wishbone_pkg.all;
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use work.convert_pkg.all;
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-- package -----------------------------------------------------------
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package wishbone_bfm_pkg is
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  -- defines output signals of wb bfm (simulation only)
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  type wishbone_bfm_master_out_t is record
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    -- 2.2.2 Signals Common to MASTER and SLAVE Interfaces 
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    dat : wishbone_data_t; -- data []
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    rst : std_logic; -- reset [mandatory RULE 3.40]
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    tgd : wishbone_tag_data_t; -- data tag []
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    -- 2.2.3 MASTER Signals
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    adr : wishbone_address_t; -- address [optional]
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    cyc : std_logic; -- cycle [mandatory RULE 3.40]
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    lock: std_logic; -- lock []
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    sel : wishbone_byte_select_t;
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    stb : std_logic; -- strobe [mandatory RULE 3.40]
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    tga : wishbone_tag_address_t; -- address tag []
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    tgc : wishbone_tag_cycle_t; -- cycle tag []
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    we  : std_logic; -- write enable []
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  end record wishbone_bfm_master_out_t;
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81
  -- defines input signals of wb bfm (simulation only)
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  type wishbone_bfm_master_in_t is record
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    -- 2.2.2 Signals Common to MASTER and SLAVE Interfaces 
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    rst : std_logic; -- reset [mandatory RULE 3.40]
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    clk : std_logic; -- clock [mandatory RULE 3.40]
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    dat : wishbone_data_t; -- read data []
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    tgd : wishbone_tag_data_t; -- read data tag []
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    -- 2.2.4 SLAVE Signals 
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    ack : std_logic; -- acknowledge [mandatory RULE 3.40]
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    err : std_logic; -- error [optional PERMISSION 3.20]
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    rty : std_logic; -- retry [optional PERMISSION 3.25]
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    --stall : std_logic;
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    int   : std_logic; -- interrupt [non WB signal]
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  end record wishbone_bfm_master_in_t;
95
 
96
  -- define the idle state of wb bus
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  constant wb_bfm_master_out_idle_c : wishbone_bfm_master_out_t := (
98 20 sinx
    dat  =>  wishbone_data_of_unused_address_c,
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    rst  =>  '0',
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    tgd  =>  (others=>'0'),
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    adr  =>  (others=>'U'),
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    cyc  =>  '0',
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    lock =>  '0',
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    sel  =>  (others=>'0'),
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    stb  =>  '0',
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    tga  =>  (others=>'0'),
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    tgc  =>  (others=>'0'),
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    we   =>  '0'
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    );
110 2 sinx
  -- BUS FUNCTIONS -----------------------------------------------------
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  ---------------------------------------------------------------------- 
112 4 sinx
  ---------------------------------------------------------------------- 
113 2 sinx
  -- generate single write cycle
114 4 sinx
  procedure wb_write(
115 23 sinx
    address_i                   : in  integer; -- address to write to
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    data_i                      : in  integer; -- data value to be written
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    signal i                    : in  wishbone_bfm_master_in_t; -- incoming wb signals
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    signal o                    : out wishbone_bfm_master_out_t; -- incoming wb signals
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    verbose_mode_i              : in  integer range 0 to 2 := 1; -- verbose mode; 2= print all activities; others: print nothing
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    message_prolog_i            : in  string  := "" -- string to be added in front of generated message
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    );
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  -- generate single read cycle and verify read word with expected_data_i
124 4 sinx
  procedure wb_read(
125 23 sinx
    address_i                   : in  integer; -- address to read from
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    expected_data_i             : in  integer; -- data to be compared to read data; if different an error message is generated
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    signal i                    : in  wishbone_bfm_master_in_t;  -- incoming wb signals
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    signal o                    : out wishbone_bfm_master_out_t; -- outgoing wb signals
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    verbose_mode_i              : in  integer range 0 to 4 := 1; -- verbose mode; 0=no output, 1=error only, 2= all, 3=use expected_data_mask_i, 4=show difference read to exp.
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    message_prolog_i            : in  string  := ""; -- string to be added in front of generated message
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    expected_data_mask_i        : in  integer := 0 -- bit mask for expected_data_i; 0: bis is not compared; 1: bit is compared
132 2 sinx
    );
133
 
134
  -- generate single read cycle and return read data via read_data_o
135 4 sinx
  procedure wb_read(
136 23 sinx
    address_i                   : in  integer; -- address to read from
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    read_data_o                 : out std_logic_vector (wishbone_data_width_c-1 downto 0); -- read data output
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    signal i                    : in  wishbone_bfm_master_in_t; -- incoming wb signals
139
    signal o                    : out wishbone_bfm_master_out_t;  -- outgoing wb signals
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    verbose_mode_i              : in  integer range 0 to 4 := 0; -- verbose mode; 2 = output read data; others: no output
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    message_prolog_i            : in  string  := "" -- string to be added in front of generated message
142 2 sinx
    );
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  ---------------------------------------------------------------------- 
144
end;
145
 
146
-- package body ------------------------------------------------------
147
package body wishbone_bfm_pkg is
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  ---------------------------------------------------------------------- 
149
  ---------------------------------------------------------------------- 
150 4 sinx
  procedure wb_write(
151 23 sinx
    address_i                   : in  integer; -- address to write to
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    data_i                      : in  integer; -- data value to be written
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    signal i                    : in  wishbone_bfm_master_in_t; -- incoming wb signals
154
    signal o                    : out wishbone_bfm_master_out_t; -- outgoing wb signals
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    verbose_mode_i              : in  integer range 0 to 2 := 1; -- verbose mode; 0=no output, 1=error only, 2= all
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    message_prolog_i            : in  string  := "" -- string to be added in front of generated message
157 4 sinx
    ) is
158 2 sinx
    ---------------------------------------------------------------------- 
159 4 sinx
  begin
160 2 sinx
    o.adr       <= to_std_logic_vector(address_i, wishbone_address_width_c);
161 20 sinx
    o.dat       <= to_std_logic_vector(data_i, wishbone_data_width_c);
162 2 sinx
    o.we        <= '1';
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    o.rst       <= '0';
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    o.tgd       <= (others => '0');
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    o.cyc       <= '1';
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    o.lock      <= '1';
167
    o.sel       <= (others => '1');
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    o.stb       <= '1';
169
    o.tga       <= (others => '0');
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    o.tgc       <= (others => '0');
171 23 sinx
    if (verbose_mode_i = 2) then
172
      report message_prolog_i & " writing :" & to_string(data_i, 16, wishbone_data_width_c/4) & " to: " & to_string(address_i, 16, wishbone_address_width_c/4);
173 4 sinx
    end if;
174 2 sinx
 
175 20 sinx
    -- ack handling
176
    loop
177
      wait until rising_edge(i.clk);
178
      if (i.ack = '1') then
179
        exit;
180
      end if;
181 4 sinx
    end loop;
182 2 sinx
    o           <= wb_bfm_master_out_idle_c; -- reset bus
183 4 sinx
  end wb_write;
184 2 sinx
  ----------------------------------------------------------------------
185
  ----------------------------------------------------------------------
186 4 sinx
  procedure wb_read(
187 23 sinx
    address_i               : in  integer;   -- address to read from
188
    read_data_o             : out std_logic_vector (wishbone_data_width_c-1 downto 0);-- read data output
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    signal i                : in  wishbone_bfm_master_in_t;  -- incoming wb signals
190
    signal o                : out wishbone_bfm_master_out_t;  -- outgoing wb signals
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    verbose_mode_i          : in  integer range 0 to 4 := 0; -- verbose mode; 2 = output read data; others: no output
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    message_prolog_i        : in  string  := "" -- string to be added in front of generated message
193 4 sinx
    ) is
194 2 sinx
    ----------------------------------------------------------------------
195 4 sinx
  begin
196 2 sinx
    o.adr       <= to_std_logic_vector(address_i, wishbone_address_width_c);
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    o.dat       <= (others => 'U');
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    o.we        <= '0';
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    o.rst       <= '0';
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    o.tgd       <= (others => '0');
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    o.cyc       <= '1';
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    o.lock      <= '1';
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    o.sel       <= (others => '1');
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    o.stb       <= '1';
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    o.tga       <= (others => '0');
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    o.tgc       <= (others => '0');
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    -- ack handling
208 20 sinx
    loop
209
      wait until rising_edge(i.clk);
210
      read_data_o := i.dat;
211
      if (i.ack = '1') then
212
        exit;
213
      end if;
214 4 sinx
    end loop;
215 2 sinx
    o           <= wb_bfm_master_out_idle_c; -- reset bus
216 23 sinx
 
217
    if (verbose_mode_i = 2) then  -- output all
218
      report message_prolog_i & ": read data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
219 27 sinx
        " was: 0x" & to_string(read_data_o, 16, wishbone_data_width_c/4)
220 23 sinx
        severity note;
221 27 sinx
     end if;
222 4 sinx
  end wb_read;
223 2 sinx
  ------------------------------------------------------------------------
224
  ------------------------------------------------------------------------
225 4 sinx
  procedure wb_read(
226 23 sinx
    address_i                   : in  integer; -- address to read from
227
    expected_data_i             : in  integer; -- data to be compared to read data; if different an error message is generated
228
    signal i                    : in  wishbone_bfm_master_in_t; -- incoming wb signals
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    signal o                    : out wishbone_bfm_master_out_t; -- outgoing wb signals
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    verbose_mode_i              : in  integer range 0 to 4 := 1; -- verbose mode; 0=no output, 1=error only, 2= all, 3=use expected_data_mask_i, 4=show difference read to exp.
231
    message_prolog_i            : in  string  := ""; -- string to be added in front of generated message
232
    expected_data_mask_i        : in  integer := 0 -- bit mask for expected_data_i; 0: bis is not compared; 1: bit is compared
233 4 sinx
    ) is
234 2 sinx
    ----------------------------------------------------------------------
235 4 sinx
    variable readdata_v : std_logic_vector (31 downto 0);
236
    variable diff_v     : integer;
237 2 sinx
    ----------------------------------------------------------------------
238 4 sinx
  begin
239 2 sinx
    wb_read(address_i,readdata_v,i,o); -- read from bus
240 20 sinx
 
241 2 sinx
    diff_v     := to_integer(readdata_v) - expected_data_i;
242
 
243 23 sinx
    if (verbose_mode_i = 1) then -- output errors only
244 20 sinx
      if (readdata_v /= to_std_logic_vector(expected_data_i, wishbone_data_width_c)) then
245 23 sinx
        report "error" & message_prolog_i & ": expected data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
246 20 sinx
          " was: 0x" & to_string(expected_data_i, 16, wishbone_data_width_c/4) & " but read: 0x" & to_string(readdata_v,16,wishbone_data_width_c/4)
247 4 sinx
          severity error;
248
      end if;
249 23 sinx
    elsif (verbose_mode_i = 2) then  -- output all
250
      report message_prolog_i & ": read data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
251 20 sinx
        " was: 0x" & to_string(readdata_v, 16, wishbone_data_width_c/4)
252 4 sinx
        severity note;
253 23 sinx
    elsif (verbose_mode_i = 3) then  -- output filter
254 20 sinx
      if ((readdata_v and to_std_logic_vector(expected_data_mask_i, wishbone_data_width_c)) /=
255
          to_std_logic_vector(expected_data_i, wishbone_data_width_c)) then
256 23 sinx
        report message_prolog_i & ": read data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
257 20 sinx
          " was: 0x" & to_string(readdata_v, 16, wishbone_data_width_c/4)
258 4 sinx
          severity note;
259
      end if;
260 23 sinx
    elsif verbose_mode_i = 4 then
261 20 sinx
      if (readdata_v /= to_std_logic_vector(expected_data_i, wishbone_data_width_c)) then
262 23 sinx
        report "error" & message_prolog_i & ": expected data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
263 20 sinx
          " was: 0x" & to_string(expected_data_i, 16, wishbone_data_width_c/4) & " but read: 0x" & to_string(readdata_v,16,wishbone_data_width_c/4) & " diff: " & to_string(readdata_v,16,wishbone_address_width_c/4)
264 4 sinx
          severity error;
265
      end if;
266
    end if;
267
  end wb_read;
268 2 sinx
  --------------------------------------------------------------------
269
end package body;
270
----------------------------------------------------------------------
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---- end of file                                                  ---- 
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----------------------------------------------------------------------

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