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[/] [vhdl_wb_tb/] [trunk/] [bench/] [vhdl/] [wishbone_bfm_pkg.vhd] - Blame information for rev 4

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1 2 sinx
---------------------------------------------------------------------- 
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----                                                              ---- 
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----  VHDL Wishbone TESTBENCH                                     ---- 
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----                                                              ---- 
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----  This file is part of the vhdl_wb_tb project                 ---- 
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----  http://www.opencores.org/cores/vhdl_wb_tb/                  ---- 
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----                                                              ---- 
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----  This file contains the wishbone_bfm_pkg package and defines ----
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----  wishbone transaction processes functions for simulation.    ---- 
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----                                                              ---- 
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----  To Do:                                                      ---- 
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----   -                                                          ---- 
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----                                                              ---- 
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----  Author(s):                                                  ---- 
15 4 sinx
----      - Sinx, sinx@opencores.org                              ---- 
16 2 sinx
----                                                              ---- 
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---------------------------------------------------------------------- 
18 4 sinx
----    SVN information
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----
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----      $URL:  $
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---- $Revision:  $
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----     $Date:  $
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----   $Author:  $
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----       $Id:  $
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---------------------------------------------------------------------- 
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----                                                              ---- 
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---- Copyright (C) 2018 Authors and OPENCORES.ORG                 ---- 
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----                                                              ---- 
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---- This source file may be used and distributed without         ---- 
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---- restriction provided that this copyright statement is not    ---- 
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---- removed from the file and that any derivative work contains  ---- 
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---- the original copyright notice and the associated disclaimer. ---- 
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----                                                              ---- 
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---- This source file is free software; you can redistribute it   ---- 
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---- and/or modify it under the terms of the GNU Lesser General   ---- 
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---- Public License as published by the Free Software Foundation; ---- 
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---- either version 2.1 of the License, or (at your option) any   ---- 
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---- later version.                                               ---- 
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----                                                              ---- 
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---- This source is distributed in the hope that it will be       ---- 
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---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
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---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
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---- details.                                                     ---- 
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----                                                              ---- 
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---- You should have received a copy of the GNU Lesser General    ---- 
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---- Public License along with this source; if not, download it   ---- 
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---- from http://www.opencores.org/lgpl.shtml                     ---- 
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----                                                              ---- 
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----------------------------------------------------------------------
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-- library -----------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.my_project_pkg.all;
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use work.wishbone_pkg.all;
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use work.convert_pkg.all;
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-- package -----------------------------------------------------------
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package wishbone_bfm_pkg is
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  -- defines output signals of wb bfm (simulation only)
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  type wishbone_bfm_master_out_t is record
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    -- 2.2.2 Signals Common to MASTER and SLAVE Interfaces 
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    dat : wishbone_data_t; -- data []
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    rst : std_logic; -- reset [mandatory RULE 3.40]
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    tgd : wishbone_tag_data_t; -- data tag []
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    -- 2.2.3 MASTER Signals
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    adr : wishbone_address_t; -- address [optional]
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    cyc : std_logic; -- cycle [mandatory RULE 3.40]
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    lock: std_logic; -- lock []
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    sel : wishbone_byte_select_t;
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    stb : std_logic; -- strobe [mandatory RULE 3.40]
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    tga : wishbone_tag_address_t; -- address tag []
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    tgc : wishbone_tag_cycle_t; -- cycle tag []
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    we  : std_logic; -- write enable []
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  end record wishbone_bfm_master_out_t;
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  -- defines input signals of wb bfm (simulation only)
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  type wishbone_bfm_master_in_t is record
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    -- 2.2.2 Signals Common to MASTER and SLAVE Interfaces 
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    rst : std_logic; -- reset [mandatory RULE 3.40]
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    clk : std_logic; -- clock [mandatory RULE 3.40]
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    dat : wishbone_data_t; -- read data []
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    tgd : wishbone_tag_data_t; -- read data tag []
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    -- 2.2.4 SLAVE Signals 
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    ack : std_logic; -- acknowledge [mandatory RULE 3.40]
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    err : std_logic; -- error [optional PERMISSION 3.20]
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    rty : std_logic; -- retry [optional PERMISSION 3.25]
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    --stall : std_logic;
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    int   : std_logic; -- interrupt [non WB signal]
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  end record wishbone_bfm_master_in_t;
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  -- define the idle state of wb bus
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  constant wb_bfm_master_out_idle_c : wishbone_bfm_master_out_t := (
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                                                          dat  =>  wishbone_data_of_unused_address_c,
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                                                          rst  =>  '0',
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                                                          tgd  =>  (others=>'0'),
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                                                          adr  =>  (others=>'U'),
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                                                          cyc  =>  '0',
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                                                          lock =>  '0',
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                                                          sel  =>  (others=>'0'),
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                                                          stb  =>  '0',
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                                                          tga  =>  (others=>'0'),
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                                                          tgc  =>  (others=>'0'),
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                                                          we   =>  '0'
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                                                          );
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  -- BUS FUNCTIONS -----------------------------------------------------
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  ---------------------------------------------------------------------- 
112 4 sinx
  ---------------------------------------------------------------------- 
113 2 sinx
  -- generate single write cycle
114 4 sinx
  procedure wb_write(
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    address_i                  : in  integer; -- address to write to
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    data_i                     : in  integer; -- data value to be written
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    signal i                   : in  wishbone_bfm_master_in_t; -- incoming wb signals
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    signal o                   : out wishbone_bfm_master_out_t; -- incoming wb signals
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    display_error_message_i    : in  integer range 0 to 2 := 1; -- verbose mode; 0=no output, 1=error only, 2= all
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    additional_error_message_i : in  string  := ""
121 2 sinx
    );
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  -- generate single read cycle and verify read word with expected_data_i
124 4 sinx
  procedure wb_read(
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    address_i                  : in  integer;
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    expected_data_i            : in  integer;
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    signal i                   : in  wishbone_bfm_master_in_t;
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    signal o                   : out wishbone_bfm_master_out_t;
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    display_error_message_i    : in  integer range 0 to 4 := 1; -- verbose mode; 0=no output, 1=error only, 2= all, 3=use expected_data_mask_i, 4=show difference read to exp.
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    additional_error_message_i : in  string  := "";
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    expected_data_mask_i       : in  integer := 0
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    );
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  -- generate single read cycle and return read data via read_data_o
135 4 sinx
  procedure wb_read(
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    address_i                  : in  integer;
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    read_data_o                : out std_logic_vector (wishbone_address_width_c-1 downto 0);
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    signal i                   : in  wishbone_bfm_master_in_t;
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    signal o                   : out wishbone_bfm_master_out_t
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    );
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  ---------------------------------------------------------------------- 
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end;
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-- package body ------------------------------------------------------
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package body wishbone_bfm_pkg is
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  ---------------------------------------------------------------------- 
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  ---------------------------------------------------------------------- 
148 4 sinx
  procedure wb_write(
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    address_i                  : in  integer;
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    data_i                     : in  integer;
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    signal i                   : in  wishbone_bfm_master_in_t;
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    signal o                   : out wishbone_bfm_master_out_t;
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    display_error_message_i    : in  integer range 0 to 2 := 1;
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    additional_error_message_i : in  string  := ""
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    ) is
156 2 sinx
    ---------------------------------------------------------------------- 
157 4 sinx
  begin
158 2 sinx
    o.adr       <= to_std_logic_vector(address_i, wishbone_address_width_c);
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    o.dat       <= to_std_logic_vector(data_i, wishbone_address_width_c);
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    o.we        <= '1';
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    o.rst       <= '0';
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    o.tgd       <= (others => '0');
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    o.cyc       <= '1';
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    o.lock      <= '1';
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    o.sel       <= (others => '1');
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    o.stb       <= '1';
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    o.tga       <= (others => '0');
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    o.tgc       <= (others => '0');
169 4 sinx
    if (display_error_message_i = 2) then
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      report "writing :" & to_string(data_i, 16, wishbone_address_width_c/4) & " to: " & to_string(address_i, 16, wishbone_address_width_c/4) &
171 2 sinx
        additional_error_message_i;
172 4 sinx
    end if;
173 2 sinx
 
174 4 sinx
    wait until falling_edge(i.clk);
175 2 sinx
    -- wait for ack
176 4 sinx
    while i.ack = '0' loop
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      wait until falling_edge(i.clk);
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    end loop;
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    wait until rising_edge(i.clk);
180 2 sinx
    o           <= wb_bfm_master_out_idle_c; -- reset bus
181 4 sinx
  end wb_write;
182 2 sinx
  ----------------------------------------------------------------------
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  ----------------------------------------------------------------------
184 4 sinx
  procedure wb_read(
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    address_i   : in  integer;
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    read_data_o : out std_logic_vector (wishbone_address_width_c-1 downto 0);
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    signal i    : in  wishbone_bfm_master_in_t;
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    signal o    : out wishbone_bfm_master_out_t
189
    ) is
190 2 sinx
    ----------------------------------------------------------------------
191 4 sinx
  begin
192 2 sinx
    o.adr       <= to_std_logic_vector(address_i, wishbone_address_width_c);
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    o.dat       <= (others => 'U');
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    o.we        <= '0';
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    o.rst       <= '0';
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    o.tgd       <= (others => '0');
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    o.cyc       <= '1';
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    o.lock      <= '1';
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    o.sel       <= (others => '1');
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    o.stb       <= '1';
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    o.tga       <= (others => '0');
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    o.tgc       <= (others => '0');
203 4 sinx
    wait until falling_edge(i.clk);
204 2 sinx
    -- ack handling
205 4 sinx
    while (i.ack = '0') loop
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      wait until falling_edge(i.clk);
207
    end loop;
208 2 sinx
    read_data_o := i.dat;
209 4 sinx
    wait until rising_edge(i.clk);
210 2 sinx
    o           <= wb_bfm_master_out_idle_c; -- reset bus
211 4 sinx
  end wb_read;
212 2 sinx
  ------------------------------------------------------------------------
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  ------------------------------------------------------------------------
214 4 sinx
  procedure wb_read(
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    address_i                  : in  integer;
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    expected_data_i            : in  integer;
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    signal i                   : in  wishbone_bfm_master_in_t;
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    signal o                   : out wishbone_bfm_master_out_t;
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    display_error_message_i    : in  integer range 0 to 4 := 1;
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    additional_error_message_i : in  string  := "";
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    expected_data_mask_i       : in  integer := 0
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    ) is
223 2 sinx
    ----------------------------------------------------------------------
224 4 sinx
    variable readdata_v : std_logic_vector (31 downto 0);
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    variable diff_v     : integer;
226 2 sinx
    ----------------------------------------------------------------------
227 4 sinx
  begin
228 2 sinx
    wb_read(address_i,readdata_v,i,o); -- read from bus
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    diff_v     := to_integer(readdata_v) - expected_data_i;
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232 4 sinx
    if (display_error_message_i = 1) then -- output errors only
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      if (readdata_v /= to_std_logic_vector(expected_data_i, wishbone_address_width_c)) then
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        report "error" & additional_error_message_i & ": expected data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
235 2 sinx
          " was: 0x" & to_string(expected_data_i, 16, wishbone_address_width_c/4) & " but read: 0x" & to_string(readdata_v,16,wishbone_address_width_c/4)
236 4 sinx
          severity error;
237
      end if;
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    elsif (display_error_message_i = 2) then  -- output all
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      report additional_error_message_i & ": read data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
240 2 sinx
        " was: 0x" & to_string(readdata_v, 16, wishbone_address_width_c/4)
241 4 sinx
        severity note;
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    elsif (display_error_message_i = 3) then  -- output filter
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      if ((readdata_v and to_std_logic_vector(expected_data_mask_i, wishbone_address_width_c)) /=
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          to_std_logic_vector(expected_data_i, wishbone_address_width_c)) then
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        report additional_error_message_i & ": read data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
246 2 sinx
          " was: 0x" & to_string(readdata_v, 16, wishbone_address_width_c/4)
247 4 sinx
          severity note;
248
      end if;
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    elsif display_error_message_i = 4 then
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      if (readdata_v /= to_std_logic_vector(expected_data_i, wishbone_address_width_c)) then
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        report "error" & additional_error_message_i & ": expected data at address 0x" & to_string(address_i, 16, wishbone_address_width_c/4) &
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          " was: 0x" & to_string(expected_data_i, 16, wishbone_address_width_c/4) & " but read: 0x" & to_string(readdata_v,16,wishbone_address_width_c/4) & " diff: " & to_string(readdata_v,16,wishbone_address_width_c/4)
253
          severity error;
254
      end if;
255
    end if;
256
  end wb_read;
257 2 sinx
  --------------------------------------------------------------------
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end package body;
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----------------------------------------------------------------------
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---- end of file                                                  ---- 
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----------------------------------------------------------------------

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