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[/] [vhdl_wb_tb/] [trunk/] [rtl/] [vhdl/] [core_top.vhd] - Blame information for rev 4

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---------------------------------------------------------------------- 
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----                                                              ---- 
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----  VHDL Wishbone TESTBENCH                                     ---- 
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----                                                              ---- 
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----  This file is part of the vhdl_wb_tb project                 ---- 
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----  http://www.opencores.org/cores/vhdl_wb_tb/                  ---- 
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----                                                              ---- 
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----  This file contains the top functional module of the design  ----
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----  under test. The top functional module will be enclosed by   ----
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----  the top module for synthesis or the tb_top for simulation.  ---- 
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----  The top module can contain some synthesis specific code,    ----
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----  where the tb_top contains simulation specific code.          ----
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----                                                              ---- 
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----  To Do:                                                      ---- 
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----   -                                                          ---- 
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----                                                              ---- 
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----  Author(s):                                                  ---- 
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----      - Sinx, sinx@opencores.org                              ---- 
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----                                                              ---- 
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---------------------------------------------------------------------- 
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----    SVN information
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----
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----      $URL:  $
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---- $Revision:  $
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----     $Date:  $
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----   $Author:  $
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----       $Id:  $
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---------------------------------------------------------------------- 
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----                                                              ---- 
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---- Copyright (C) 2018 Authors and OPENCORES.ORG                 ---- 
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----                                                              ---- 
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---- This source file may be used and distributed without         ---- 
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---- restriction provided that this copyright statement is not    ---- 
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---- removed from the file and that any derivative work contains  ---- 
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---- the original copyright notice and the associated disclaimer. ---- 
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----                                                              ---- 
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---- This source file is free software; you can redistribute it   ---- 
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---- and/or modify it under the terms of the GNU Lesser General   ---- 
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---- Public License as published by the Free Software Foundation; ---- 
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---- either version 2.1 of the License, or (at your option) any   ---- 
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---- later version.                                               ---- 
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----                                                              ---- 
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---- This source is distributed in the hope that it will be       ---- 
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---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
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---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
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---- details.                                                     ---- 
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----                                                              ---- 
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---- You should have received a copy of the GNU Lesser General    ---- 
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---- Public License along with this source; if not, download it   ---- 
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---- from http://www.opencores.org/lgpl.shtml                     ---- 
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----                                                              ---- 
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----------------------------------------------------------------------
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-- library -----------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.convert_pkg.all;
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use work.wishbone_pkg.all;
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-- entity ------------------------------------------------------------
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entity core_top is
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  generic(
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    g_number_of_in_signals          : natural := 1;
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    g_number_of_out_signals         : natural := 1
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    );
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  port(
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    clock_i                         : in std_logic;
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    reset_i                         : in std_logic;
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    signals_i                       : in std_logic_vector(g_number_of_in_signals-1 downto 0);
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    signals_o                       : out std_logic_vector(g_number_of_out_signals-1 downto 0)
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    );
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end core_top;
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-- architecture ------------------------------------------------------
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architecture rtl of core_top is
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  ------------------------------------------------------------------------------
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  -- signal declaration
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  ------------------------------------------------------------------------------
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  signal    shift_register_r   : std_logic_vector (g_number_of_out_signals-1 downto 0);
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  signal    old_shift_clock_r  : std_logic := '0';
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  ------------------------------------------------------------------------------
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begin
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  ------------------------------------------------------------------------------
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  -- module instantiation
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  ------------------------------------------------------------------------------
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  proc_shift_register : process (all)
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    begin
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      if (reset_i = '1' ) then
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        shift_register_r <= (others => '0');
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      elsif (rising_edge(clock_i)) then
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        old_shift_clock_r <= signals_i(1);
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        if (signals_i(1) = '1' AND old_shift_clock_r= '0') then
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          shift_register_r        <= shift_register_r(shift_register_r'left-1 downto 0) & signals_i(0);
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        end if;
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      end if;
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    end process;
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  ------------------------------------------------------------------------------
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  signals_o <= shift_register_r;
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  ------------------------------------------------------------------------------
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end rtl;
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----------------------------------------------------------------------
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---- end of file                                                  ---- 
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----------------------------------------------------------------------

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