OpenCores
URL https://opencores.org/ocsvn/vhdl_wb_tb/vhdl_wb_tb/trunk

Subversion Repositories vhdl_wb_tb

[/] [vhdl_wb_tb/] [trunk/] [rtl/] [vhdl/] [packages/] [my_project_pkg.vhd] - Blame information for rev 2

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 sinx
---------------------------------------------------------------------- 
2
----                                                              ---- 
3
----  WISHBONE XXX IP Core                                        ---- 
4
----                                                              ---- 
5
----  This file is part of the XXX project                        ---- 
6
----  http://www.opencores.org/cores/xxx/                         ---- 
7
----                                                              ---- 
8
----  Description                                                 ---- 
9
----  Implementation of XXX IP core according to                  ---- 
10
----  XXX IP core specification document.                         ---- 
11
----                                                              ---- 
12
----  To Do:                                                      ---- 
13
----   - Adjust and rename this package for your project          ---- 
14
----   - remove these comments                                    ---- 
15
----                                                              ---- 
16
----  Author(s):                                                  ---- 
17
----      - First & Last Name, email@opencores.org                ---- 
18
----                                                              ---- 
19
----------------------------------------------------------------------
20
--    SVN information
21
--
22
--      $URL:  $
23
-- $Revision:  $
24
--     $Date:  $
25
--   $Author:  $
26
--       $Id:  $
27
--
28
---------------------------------------------------------------------- 
29
----                                                              ---- 
30
---- Copyright (C) 2018 Authors and OPENCORES.ORG                 ---- 
31
----                                                              ---- 
32
---- This source file may be used and distributed without         ---- 
33
---- restriction provided that this copyright statement is not    ---- 
34
---- removed from the file and that any derivative work contains  ---- 
35
---- the original copyright notice and the associated disclaimer. ---- 
36
----                                                              ---- 
37
---- This source file is free software; you can redistribute it   ---- 
38
---- and/or modify it under the terms of the GNU Lesser General   ---- 
39
---- Public License as published by the Free Software Foundation; ---- 
40
---- either version 2.1 of the License, or (at your option) any   ---- 
41
---- later version.                                               ---- 
42
----                                                              ---- 
43
---- This source is distributed in the hope that it will be       ---- 
44
---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
45
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
46
---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
47
---- details.                                                     ---- 
48
----                                                              ---- 
49
---- You should have received a copy of the GNU Lesser General    ---- 
50
---- Public License along with this source; if not, download it   ---- 
51
---- from http://www.opencores.org/lgpl.shtml                     ---- 
52
----                                                              ---- 
53
----------------------------------------------------------------------
54
 
55
library ieee;
56
use ieee.std_logic_1164.all;
57
use ieee.numeric_std.all;
58
 
59
library work;
60
 
61
package my_project_pkg is
62
 
63
  constant wishbone_address_width_c : integer := 32;
64
  constant wishbone_data_width_c    : integer := 32;
65
  constant wishbone_data_of_unused_address_c : std_logic_vector(wishbone_data_width_c-1 DOWNTO 0) := X"DEADDEAD"; -- "X" might lead to less resources. Meaningful value might ease debugging
66
  constant wishbone_data_of_unused_address_p : std_logic_vector(wishbone_data_width_c-1 DOWNTO 0) := X"DEADBEEF"; -- "X" might lead to less resources. Meaningful value might ease debugging
67
 
68
  subtype wishbone_tag_data_t is std_logic_vector(1 downto 0);
69
  subtype wishbone_tag_address_t is std_logic_vector(1 downto 0);
70
  subtype wishbone_tag_cycle_t is std_logic_vector(1 downto 0);
71
 
72
  --type t_wishbone_interface_mode is (CLASSIC, PIPELINED);
73
  --type t_wishbone_address_granularity is (BYTE, WORD);
74
  constant zero_c : std_logic_vector(511 downto 0) := (others => '0');
75
end my_project_pkg;
76
 
77
package body my_project_pkg is
78
end my_project_pkg;
79
 

powered by: WebSVN 2.1.0

© copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.