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Subversion Repositories vhdl_wb_tb

[/] [vhdl_wb_tb/] [trunk/] [rtl/] [vhdl/] [packages/] [my_project_pkg.vhd] - Blame information for rev 27

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---------------------------------------------------------------------- 
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----                                                              ---- 
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----  VHDL Wishbone TESTBENCH                                     ---- 
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----                                                              ---- 
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----  This file is part of the vhdl_wb_tb project                 ---- 
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----  http://www.opencores.org/cores/vhdl_wb_tb/                  ---- 
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----                                                              ---- 
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----  This file contains the project specific defines             ----
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----                                                              ---- 
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----  To Do:                                                      ---- 
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----   -                                                          ---- 
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----                                                              ---- 
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----  Author(s):                                                  ---- 
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----      - Sinx, sinx@opencores.org                              ---- 
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----                                                              ---- 
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---------------------------------------------------------------------- 
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----    SVN information
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----
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----      $URL: file:///svn/vhdl_wb_tb/vhdl_wb_tb/trunk/rtl/vhdl/packages/my_project_pkg.vhd $
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---- $Revision: 27 $
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----     $Date: 2019-09-21 17:20:11 +0200 (Sat, 21 Sep 2019) $
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----   $Author: sinx $
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----       $Id: my_project_pkg.vhd 27 2019-09-21 15:20:11Z sinx $
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---------------------------------------------------------------------- 
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----                                                              ---- 
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---- Copyright (C) 2018 Authors and OPENCORES.ORG                 ---- 
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----                                                              ---- 
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---- This source file may be used and distributed without         ---- 
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---- restriction provided that this copyright statement is not    ---- 
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---- removed from the file and that any derivative work contains  ---- 
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---- the original copyright notice and the associated disclaimer. ---- 
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----                                                              ---- 
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---- This source file is free software; you can redistribute it   ---- 
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---- and/or modify it under the terms of the GNU Lesser General   ---- 
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---- Public License as published by the Free Software Foundation; ---- 
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---- either version 2.1 of the License, or (at your option) any   ---- 
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---- later version.                                               ---- 
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----                                                              ---- 
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---- This source is distributed in the hope that it will be       ---- 
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---- useful, but WITHOUT ANY WARRANTY; without even the implied   ---- 
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ---- 
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---- PURPOSE.  See the GNU Lesser General Public License for more ---- 
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---- details.                                                     ---- 
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----                                                              ---- 
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---- You should have received a copy of the GNU Lesser General    ---- 
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---- Public License along with this source; if not, download it   ---- 
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---- from http://www.opencores.org/lgpl.shtml                     ---- 
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----                                                              ---- 
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----------------------------------------------------------------------
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-- library -----------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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-- package -----------------------------------------------------------
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package my_project_pkg is
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  constant wishbone_address_width_c : integer := 32;
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  constant wishbone_unused_address_c : std_logic_vector(wishbone_address_width_c-1 DOWNTO 0) := X"DEADDEAD"; -- "X" might lead to less resources. Meaningful value might ease debugging
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  constant wishbone_data_width_c    : integer := 32;
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  constant wishbone_data_of_unused_address_c : std_logic_vector(wishbone_data_width_c-1 DOWNTO 0) := X"DEADDEAD"; -- "X" might lead to less resources. Meaningful value might ease debugging
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  constant exit_simulator_at_tc_end_c        : std_logic_vector := "0"; -- "1": exit simulator at end of tc_xxxx file. used for scripted simulation runs; 
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                                                                        -- "0": just pause simulator at end of tc_xxx file. used for manual simulation runs.
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  subtype wishbone_tag_data_t is std_logic_vector(1 downto 0);
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  subtype wishbone_tag_address_t is std_logic_vector(1 downto 0);
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  subtype wishbone_tag_cycle_t is std_logic_vector(1 downto 0);
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  --type wishbone_interface_mode_t is (CLASSIC, PIPELINED);
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  --type wishbone_address_granularity_t is (BYTE, WORD);
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  constant zero_c : std_logic_vector(511 downto 0) := (others => '0');
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end my_project_pkg;
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-- package body ------------------------------------------------------
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package body my_project_pkg is
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end my_project_pkg;
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----------------------------------------------------------------------
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---- end of file                                                  ---- 
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----------------------------------------------------------------------

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