| 1 |
2 |
sinx |
----------------------------------------------------------------------
|
| 2 |
|
|
---- ----
|
| 3 |
|
|
---- VHDL Wishbone TESTBENCH ----
|
| 4 |
|
|
---- ----
|
| 5 |
|
|
---- This file is part of the vhdl_wb_tb project ----
|
| 6 |
4 |
sinx |
---- https://opencores.org/project/vhdl_wb_tb ----
|
| 7 |
2 |
sinx |
---- ----
|
| 8 |
4 |
sinx |
---- This file contains the highest (top) module for synthesis. ----
|
| 9 |
|
|
---- Like tb_top it instantiates the core_top module and ----
|
| 10 |
|
|
---- provides parameters/generics. Where the tb_top module ----
|
| 11 |
|
|
---- provides parameters for simulation this file provides ----
|
| 12 |
|
|
---- parameters for synthesis. ----
|
| 13 |
2 |
sinx |
---- ----
|
| 14 |
|
|
---- To Do: ----
|
| 15 |
|
|
---- - ----
|
| 16 |
|
|
---- ----
|
| 17 |
|
|
---- Author(s): ----
|
| 18 |
4 |
sinx |
---- - Sinx, sinx@opencores.org ----
|
| 19 |
2 |
sinx |
---- ----
|
| 20 |
|
|
----------------------------------------------------------------------
|
| 21 |
4 |
sinx |
---- SVN information
|
| 22 |
|
|
----
|
| 23 |
13 |
sinx |
---- $URL: file:///svn/vhdl_wb_tb/vhdl_wb_tb/trunk/rtl/vhdl/top.vhd $
|
| 24 |
|
|
---- $Revision: 13 $
|
| 25 |
|
|
---- $Date: 2018-07-22 16:23:45 +0200 (Sun, 22 Jul 2018) $
|
| 26 |
|
|
---- $Author: sinx $
|
| 27 |
|
|
---- $Id: top.vhd 13 2018-07-22 14:23:45Z sinx $
|
| 28 |
4 |
sinx |
----------------------------------------------------------------------
|
| 29 |
2 |
sinx |
---- ----
|
| 30 |
|
|
---- Copyright (C) 2018 Authors and OPENCORES.ORG ----
|
| 31 |
|
|
---- ----
|
| 32 |
|
|
---- This source file may be used and distributed without ----
|
| 33 |
|
|
---- restriction provided that this copyright statement is not ----
|
| 34 |
|
|
---- removed from the file and that any derivative work contains ----
|
| 35 |
|
|
---- the original copyright notice and the associated disclaimer. ----
|
| 36 |
|
|
---- ----
|
| 37 |
|
|
---- This source file is free software; you can redistribute it ----
|
| 38 |
|
|
---- and/or modify it under the terms of the GNU Lesser General ----
|
| 39 |
|
|
---- Public License as published by the Free Software Foundation; ----
|
| 40 |
|
|
---- either version 2.1 of the License, or (at your option) any ----
|
| 41 |
|
|
---- later version. ----
|
| 42 |
|
|
---- ----
|
| 43 |
|
|
---- This source is distributed in the hope that it will be ----
|
| 44 |
|
|
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
|
| 45 |
|
|
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
|
| 46 |
|
|
---- PURPOSE. See the GNU Lesser General Public License for more ----
|
| 47 |
|
|
---- details. ----
|
| 48 |
|
|
---- ----
|
| 49 |
|
|
---- You should have received a copy of the GNU Lesser General ----
|
| 50 |
|
|
---- Public License along with this source; if not, download it ----
|
| 51 |
|
|
---- from http://www.opencores.org/lgpl.shtml ----
|
| 52 |
|
|
---- ----
|
| 53 |
|
|
----------------------------------------------------------------------
|
| 54 |
|
|
|
| 55 |
|
|
-- library -----------------------------------------------------------
|
| 56 |
|
|
library ieee;
|
| 57 |
|
|
use ieee.std_logic_1164.all;
|
| 58 |
|
|
use ieee.numeric_std.all;
|
| 59 |
|
|
library work;
|
| 60 |
|
|
use work.convert_pkg.all;
|
| 61 |
|
|
use work.wishbone_pkg.all;
|
| 62 |
|
|
|
| 63 |
|
|
-- entity ------------------------------------------------------------
|
| 64 |
|
|
entity top is
|
| 65 |
|
|
port(
|
| 66 |
|
|
clock_i : in std_logic;
|
| 67 |
|
|
signals_i : in std_logic_vector(7 downto 0);
|
| 68 |
|
|
signals_o : out std_logic_vector(7 downto 0)
|
| 69 |
|
|
);
|
| 70 |
|
|
end entity top;
|
| 71 |
|
|
|
| 72 |
4 |
sinx |
-- architecture ------------------------------------------------------
|
| 73 |
2 |
sinx |
architecture rtl of top is
|
| 74 |
4 |
sinx |
-----------------------------------------------------------------------------
|
| 75 |
2 |
sinx |
-- constant number_of_stimulus_signals_c : integer := 8;
|
| 76 |
5 |
sinx |
-- signal verify_s : std_logic_vector(number_of_verify_signals_c-1 downto 0);
|
| 77 |
2 |
sinx |
-----------------------------------------------------------------------------
|
| 78 |
|
|
begin
|
| 79 |
4 |
sinx |
-----------------------------------------------------------------------------
|
| 80 |
2 |
sinx |
-- instance of design
|
| 81 |
|
|
core_top_inst : entity work.core_top
|
| 82 |
|
|
generic map(
|
| 83 |
5 |
sinx |
number_of_in_signals_g => 8,
|
| 84 |
|
|
number_of_out_signals_g => 8
|
| 85 |
2 |
sinx |
)
|
| 86 |
|
|
port map(
|
| 87 |
|
|
clock_i => clock_i,
|
| 88 |
|
|
reset_i => '0',
|
| 89 |
|
|
signals_i => signals_i,
|
| 90 |
|
|
signals_o => signals_o
|
| 91 |
|
|
);
|
| 92 |
|
|
-----------------------------------------------------------------------------
|
| 93 |
|
|
end rtl;
|
| 94 |
4 |
sinx |
----------------------------------------------------------------------
|
| 95 |
|
|
---- end of file ----
|
| 96 |
|
|
----------------------------------------------------------------------
|
