OpenCores
URL https://opencores.org/ocsvn/vhdl_wb_tb/vhdl_wb_tb/trunk

Subversion Repositories vhdl_wb_tb

[/] [vhdl_wb_tb/] [trunk/] [rtl_sim/] [run/] [sim.mpf] - Blame information for rev 4

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Line No. Rev Author Line
1 2 sinx
; Copyright 1991-2009 Mentor Graphics Corporation
2
;
3
; All Rights Reserved.
4
;
5
; THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS THE PROPERTY OF
6
; MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS SUBJECT TO LICENSE TERMS.
7
;
8
 
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[Library]
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others = $MODEL_TECH/../modelsim.ini
11
 
12
; Altera Primitive libraries
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;
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; VHDL Section
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;
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;
17
; Verilog Section
18
;
19
 
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work = work
21
[vcom]
22
; VHDL93 variable selects language version as the default.
23
; Default is VHDL-2002.
24
; Value of 0 or 1987 for VHDL-1987.
25
; Value of 1 or 1993 for VHDL-1993.
26
; Default or value of 2 or 2002 for VHDL-2002.
27
; Default or value of 3 or 2008 for VHDL-2008.
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VHDL93 = 2008
29
 
30
; Show source line containing error. Default is off.
31
; Show_source = 1
32
 
33
; Turn off unbound-component warnings. Default is on.
34
; Show_Warning1 = 0
35
 
36
; Turn off process-without-a-wait-statement warnings. Default is on.
37
; Show_Warning2 = 0
38
 
39
; Turn off null-range warnings. Default is on.
40
; Show_Warning3 = 0
41
 
42
; Turn off no-space-in-time-literal warnings. Default is on.
43
; Show_Warning4 = 0
44
 
45
; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
46
; Show_Warning5 = 0
47
 
48
; Turn off optimization for IEEE std_logic_1164 package. Default is on.
49
; Optimize_1164 = 0
50
 
51
; Turn on resolving of ambiguous function overloading in favor of the
52
; "explicit" function declaration (not the one automatically created by
53
; the compiler for each type declaration). Default is off.
54
; The .ini file has Explicit enabled so that std_logic_signed/unsigned
55
; will match the behavior of synthesis tools.
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Explicit = 1
57
 
58
; Turn off acceleration of the VITAL packages. Default is to accelerate.
59
; NoVital = 1
60
 
61
; Turn off VITAL compliance checking. Default is checking on.
62
; NoVitalCheck = 1
63
 
64
; Ignore VITAL compliance checking errors. Default is to not ignore.
65
; IgnoreVitalErrors = 1
66
 
67
; Turn off VITAL compliance checking warnings. Default is to show warnings.
68
; Show_VitalChecksWarnings = 0
69
 
70
; Keep silent about case statement static warnings.
71
; Default is to give a warning.
72
; NoCaseStaticError = 1
73
 
74
; Keep silent about warnings caused by aggregates that are not locally static.
75
; Default is to give a warning.
76
; NoOthersStaticError = 1
77
 
78
; Turn off inclusion of debugging info within design units.
79
; Default is to include debugging info.
80
; NoDebug = 1
81
 
82
; Turn off "Loading..." messages. Default is messages on.
83
; Quiet = 1
84
 
85
; Turn on some limited synthesis rule compliance checking. Checks only:
86
;    -- signals used (read) by a process must be in the sensitivity list
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; CheckSynthesis = 1
88
 
89
; Activate optimizations on expressions that do not involve signals,
90
; waits, or function/procedure/task invocations. Default is off.
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; ScalarOpts = 1
92
 
93
; Require the user to specify a configuration for all bindings,
94
; and do not generate a compile time default binding for the
95
; component. This will result in an elaboration error of
96
; 'component not bound' if the user fails to do so. Avoids the rare
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; issue of a false dependency upon the unused default binding.
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; RequireConfigForAllDefaultBinding = 1
99
 
100
; Inhibit range checking on subscripts of arrays. Range checking on
101
; scalars defined with subtypes is inhibited by default.
102
; NoIndexCheck = 1
103
 
104
; Inhibit range checks on all (implicit and explicit) assignments to
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; scalar objects defined with subtypes.
106
; NoRangeCheck = 1
107
 
108
[vlog]
109
 
110
; Turn off inclusion of debugging info within design units.
111
; Default is to include debugging info.
112
; NoDebug = 1
113
 
114
; Turn off "loading..." messages. Default is messages on.
115
; Quiet = 1
116
 
117
; Turn on Verilog hazard checking (order-dependent accessing of global vars).
118
; Default is off.
119
; Hazard = 1
120
 
121
; Turn on converting regular Verilog identifiers to uppercase. Allows case
122
; insensitivity for module names. Default is no conversion.
123
; UpCase = 1
124
 
125
; Turn on incremental compilation of modules. Default is off.
126
; Incremental = 1
127
 
128
; Turns on lint-style checking.
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; Show_Lint = 1
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131
[vsim]
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; Simulator resolution
133
; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
134
Resolution = ps
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136
; User time unit for run commands
137
; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
138
; unit specified for Resolution. For example, if Resolution is 100ps,
139
; then UserTimeUnit defaults to ps.
140
; Should generally be set to default.
141
UserTimeUnit = default
142
 
143
; Default run length
144
RunLength = 120 us
145
 
146
; Maximum iterations that can be run without advancing simulation time
147
IterationLimit = 5000
148
 
149
; Directive to license manager:
150
; vhdl          Immediately reserve a VHDL license
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; vlog          Immediately reserve a Verilog license
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; plus          Immediately reserve a VHDL and Verilog license
153
; nomgc         Do not look for Mentor Graphics Licenses
154
; nomti         Do not look for Model Technology Licenses
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; noqueue       Do not wait in the license queue when a license isn't available
156
; viewsim       Try for viewer license but accept simulator license(s) instead
157
;               of queuing for viewer license
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; License = plus
159
 
160
; Stop the simulator after a VHDL/Verilog assertion message
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; 0 = Note  1 = Warning  2 = Error  3 = Failure  4 = Fatal
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BreakOnAssertion = 3
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164
; Assertion Message Format
165
; %S - Severity Level
166
; %R - Report Message
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; %T - Time of assertion
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; %D - Delta
169
; %I - Instance or Region pathname (if available)
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; %% - print '%' character
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; AssertionFormat = "** %S: %R\n   Time: %T  Iteration: %D%I\n"
172 4 sinx
AssertionFormat = "** [%I] %T %S %R\n"
173 2 sinx
 
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; Assertion File - alternate file for storing VHDL/Verilog assertion messages
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; AssertFile = assert.log
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177
; Default radix for all windows and commands...
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; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
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DefaultRadix = hexadecimal
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181
; VSIM Startup command
182
; Startup = do startup.do
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184
; File for saving command transcript
185
;TranscriptFile = transcript.log
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187
; File for saving command history
188
;CommandHistory = cmdhist.log
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190
; Specify whether paths in simulator commands should be described
191
; in VHDL or Verilog format.
192
; For VHDL, PathSeparator = /
193
; For Verilog, PathSeparator = .
194
; Must not be the same character as DatasetSeparator.
195
PathSeparator = /
196
 
197
; Specify the dataset separator for fully rooted contexts.
198
; The default is ':'. For example, sim:/top
199
; Must not be the same character as PathSeparator.
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DatasetSeparator = :
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202
; Disable VHDL assertion messages
203
; IgnoreNote = 1
204
; IgnoreWarning = 1
205
; IgnoreError = 1
206
; IgnoreFailure = 1
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208
; Default force kind. May be freeze, drive, deposit, or default
209
; or in other terms, fixed, wired, or charged.
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; A value of "default" will use the signal kind to determine the
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; force kind, drive for resolved signals, freeze for unresolved signals
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; DefaultForceKind = freeze
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; If zero, open files when elaborated; otherwise, open files on
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; first read or write.  Default is 0.
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; DelayFileOpen = 1
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; Control VHDL files opened for write.
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;   0 = Buffered, 1 = Unbuffered
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UnbufferedOutput = 0
221
 
222
; Control the number of VHDL files open concurrently.
223
; This number should always be less than the current ulimit
224
; setting for max file descriptors.
225
;   0 = unlimited
226
ConcurrentFileLimit = 40
227
 
228
; Control the number of hierarchical regions displayed as
229
; part of a signal name shown in the Wave window.
230
; A value of zero tells VSIM to display the full name.
231
; The default is 0.
232
; WaveSignalNameWidth = 0
233
 
234
; Turn off warnings from the std_logic_arith, std_logic_unsigned
235
; and std_logic_signed packages.
236
; StdArithNoWarnings = 1
237
 
238
; Turn off warnings from the IEEE numeric_std and numeric_bit packages.
239
; NumericStdNoWarnings = 1
240
 
241
; Control the format of the (VHDL) FOR generate statement label
242
; for each iteration.  Do not quote it.
243
; The format string here must contain the conversion codes %s and %d,
244
; in that order, and no other conversion codes.  The %s represents
245
; the generate_label; the %d represents the generate parameter value
246
; at a particular generate iteration (this is the position number if
247
; the generate parameter is of an enumeration type).  Embedded whitespace
248
; is allowed (but discouraged); leading and trailing whitespace is ignored.
249
; Application of the format must result in a unique scope name over all
250
; such names in the design so that name lookup can function properly.
251
; GenerateFormat = %s__%d
252
 
253
; Specify whether checkpoint files should be compressed.
254
; The default is 1 (compressed).
255
; CheckpointCompressMode = 0
256
 
257
; List of dynamically loaded objects for Verilog PLI applications
258
; Veriuser = veriuser.sl
259
 
260
; Specify default options for the restart command. Options can be one
261
; or more of: -force -nobreakpoint -nolist -nolog -nowave
262
; DefaultRestartOptions = -force
263
 
264
; HP-UX 10.20 ONLY - Enable memory locking to speed up large designs
265
; (> 500 megabyte memory footprint). Default is disabled.
266
; Specify number of megabytes to lock.
267
; LockedMemory = 1000
268
 
269
; Turn on (1) or off (0) WLF file compression.
270
; The default is 1 (compress WLF file).
271
; WLFCompress = 0
272
 
273
; Specify whether to save all design hierarchy (1) in the WLF file
274
; or only regions containing logged signals (0).
275
; The default is 0 (save only regions with logged signals).
276
; WLFSaveAllRegions = 1
277
 
278
; WLF file time limit.  Limit WLF file by time, as closely as possible,
279
; to the specified amount of simulation time.  When the limit is exceeded
280
; the earliest times get truncated from the file.
281
; If both time and size limits are specified the most restrictive is used.
282
; UserTimeUnits are used if time units are not specified.
283
; The default is 0 (no limit).  Example: WLFTimeLimit = {100 ms}
284
; WLFTimeLimit = 0
285
 
286
; WLF file size limit.  Limit WLF file size, as closely as possible,
287
; to the specified number of megabytes.  If both time and size limits
288
; are specified then the most restrictive is used.
289
; The default is 0 (no limit).
290
; WLFSizeLimit = 1000
291
 
292
; Specify whether or not a WLF file should be deleted when the
293
; simulation ends.  A value of 1 will cause the WLF file to be deleted.
294
; The default is 0 (do not delete WLF file when simulation ends).
295
; WLFDeleteOnQuit = 1
296
 
297
; Automatic SDF compilation
298
; Disables automatic compilation of SDF files in flows that support it.
299
; Default is on, uncomment to turn off.
300
; NoAutoSDFCompile = 1
301
 
302
WLFSaveAllRegions = 1
303
DefaultRadixFlags = showbase
304
[lmc]
305
 
306
[msg_system]
307
; Change a message severity or suppress a message.
308
; The format is:  = [,...]
309
; Examples:
310
;   note = 3009
311
;   warning = 3033
312
;   error = 3010,3016
313
;   fatal = 3016,3033
314
;   suppress = 3009,3016,3043
315
; The command verror  can be used to get the complete
316
; description of a message.
317
 
318
; Control transcripting of elaboration/runtime messages.
319
; The default is to have messages appear in the transcript and
320
; recorded in the wlf file (messages that are recorded in the
321
; wlf file can be viewed in the MsgViewer).  The other settings
322
; are to send messages only to the transcript or only to the
323
; wlf file.  The valid values are
324
;    both  {default}
325
;    tran  {transcript only}
326
;    wlf   {wlf file only}
327
; msgmode = both
328
[Project]
329
; Warning -- Do not edit the project properties directly.
330
;            Property names are dynamic in nature and property
331
;            values have special syntax.  Changing property data directly
332
;            can result in a corrupt MPF file.  All project properties
333
;            can be modified through project window dialogs.
334
Project_Version = 6
335
Project_DefaultLib = work
336
Project_SortMethod = unused
337
Project_Files_Count = 15
338 4 sinx
Project_File_0 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/rtl_sim/run/sim.mpf
339
Project_File_P_0 = compile_order -1 last_compile 0 folder z_others dont_compile 1 group_id 0 file_type txt ood 1
340
Project_File_1 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/bench/vhdl/verifier.vhd
341
Project_File_P_1 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder bench last_compile 1532164414 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 7 cover_nosub 0 dont_compile 0 vhdl_use93 2008
342
Project_File_2 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/rtl/vhdl/top.vhd
343
Project_File_P_2 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder rtl last_compile 1532164414 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 10 dont_compile 0 cover_nosub 0 vhdl_use93 2008
344
Project_File_3 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/rtl/vhdl/core_top.vhd
345
Project_File_P_3 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder rtl last_compile 1532164727 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 9 dont_compile 0 cover_nosub 0 vhdl_use93 2008
346
Project_File_4 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/bench/vhdl/tc_xxxx.vhd
347
Project_File_P_4 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder bench last_compile 1532164665 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 8 cover_nosub 0 dont_compile 0 vhdl_use93 2008
348
Project_File_5 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/bench/vhdl/tb_pkg.vhd
349
Project_File_P_5 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder bench last_compile 1532164414 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 5 cover_nosub 0 dont_compile 0 vhdl_use93 2008
350
Project_File_6 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/bench/vhdl/tb_top.vhd
351
Project_File_P_6 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder bench last_compile 1532164891 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 11 cover_nosub 0 dont_compile 0 vhdl_use93 2008
352
Project_File_7 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/rtl/vhdl/packages/wishbone_pkg.vhd
353
Project_File_P_7 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder rtl last_compile 1532164414 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 2 dont_compile 0 cover_nosub 0 vhdl_use93 2008
354
Project_File_8 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/bench/vhdl/tc_top.vhd
355
Project_File_P_8 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder bench last_compile 1532164414 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 4 cover_nosub 0 dont_compile 0 vhdl_use93 2008
356
Project_File_9 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/rtl/vhdl/packages/convert_pkg.vhd
357
Project_File_P_9 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder rtl last_compile 1532164414 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 0 cover_nosub 0 dont_compile 0 vhdl_use93 2008
358
Project_File_10 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/rtl_sim/bin/init.do
359
Project_File_P_10 = compile_order -1 last_compile 0 folder z_others dont_compile 1 group_id 0 file_type tcl ood 1
360
Project_File_11 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/bench/vhdl/wishbone_bfm_pkg.vhd
361
Project_File_P_11 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder bench last_compile 1532164775 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 3 cover_nosub 0 dont_compile 0 vhdl_use93 2008
362
Project_File_12 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/bench/vhdl/stimulator.vhd
363
Project_File_P_12 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder bench last_compile 1532163339 vhdl_disableopt 0 vhdl_vital 0 cover_excludedefault 0 vhdl_warn1 1 vhdl_warn2 1 vhdl_explicit 1 vhdl_showsource 0 vhdl_warn3 1 cover_covercells 0 vhdl_0InOptions {} vhdl_warn4 1 voptflow 1 cover_optlevel 3 vhdl_options {} vhdl_warn5 1 toggle - ood 0 cover_noshort 0 compile_to work compile_order 6 cover_nosub 0 dont_compile 0 vhdl_use93 2008
364
Project_File_13 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/rtl/vhdl/packages/my_project_pkg.vhd
365
Project_File_P_13 = vhdl_novitalcheck 0 file_type vhdl group_id 0 cover_nofec 0 vhdl_nodebug 0 vhdl_1164 1 vhdl_noload 0 vhdl_synth 0 vhdl_enable0In 0 folder rtl last_compile 1532165114 vhdl_disableopt 0 cover_excludedefault 0 vhdl_vital 0 vhdl_warn1 1 vhdl_showsource 0 vhdl_explicit 1 vhdl_warn2 1 vhdl_0InOptions {} cover_covercells 0 vhdl_warn3 1 vhdl_options {} cover_optlevel 3 voptflow 1 vhdl_warn4 1 ood 0 toggle - vhdl_warn5 1 compile_to work cover_noshort 0 compile_order 1 dont_compile 0 cover_nosub 0 vhdl_use93 2008
366
Project_File_14 = D:/OpenCoresOrg/vhdl_wb_tb/vhdl_wb_tb/trunk/rtl_sim/bin/s.do
367
Project_File_P_14 = folder z_others last_compile 0 compile_order -1 file_type tcl group_id 0 dont_compile 1 ood 1
368 2 sinx
Project_Sim_Count = 0
369
Project_Folder_Count = 4
370
Project_Folder_0 = bench
371
Project_Folder_P_0 = folder {Top Level}
372
Project_Folder_1 = z_others
373
Project_Folder_P_1 = folder {Top Level}
374
Project_Folder_2 = rtl
375
Project_Folder_P_2 = folder {Top Level}
376
Project_Folder_3 = PACKAGES
377
Project_Folder_P_3 = folder PNI
378
Echo_Compile_Output = 1
379
Save_Compile_Report = 0
380
Project_Opt_Count = 0
381
ForceSoftPaths = 1
382
ProjectStatusDelay = 5000
383
VERILOG_DoubleClick = Compile
384
VERILOG_CustomDoubleClick =
385
SYSTEMVERILOG_DoubleClick = Edit
386
SYSTEMVERILOG_CustomDoubleClick =
387
VHDL_DoubleClick = Compile
388
VHDL_CustomDoubleClick =
389
PSL_DoubleClick = Edit
390
PSL_CustomDoubleClick =
391
TEXT_DoubleClick = Edit
392
TEXT_CustomDoubleClick =
393
SYSTEMC_DoubleClick = Edit
394
SYSTEMC_CustomDoubleClick =
395
TCL_DoubleClick = Edit
396
TCL_CustomDoubleClick =
397
MACRO_DoubleClick = Edit
398
MACRO_CustomDoubleClick =
399
VCD_DoubleClick = Edit
400
VCD_CustomDoubleClick =
401
SDF_DoubleClick = Edit
402
SDF_CustomDoubleClick =
403
XML_DoubleClick = Edit
404
XML_CustomDoubleClick =
405
LOGFILE_DoubleClick = Edit
406
LOGFILE_CustomDoubleClick =
407
UCDB_DoubleClick = Edit
408
UCDB_CustomDoubleClick =
409
TDB_DoubleClick = Edit
410
TDB_CustomDoubleClick =
411
UPF_DoubleClick = Edit
412
UPF_CustomDoubleClick =
413
PCF_DoubleClick = Edit
414
PCF_CustomDoubleClick =
415
PROJECT_DoubleClick = Edit
416
PROJECT_CustomDoubleClick =
417
VRM_DoubleClick = Edit
418
VRM_CustomDoubleClick =
419
DEBUGDATABASE_DoubleClick = Edit
420
DEBUGDATABASE_CustomDoubleClick =
421
DEBUGARCHIVE_DoubleClick = Edit
422
DEBUGARCHIVE_CustomDoubleClick =
423
Project_Major_Version = 10
424
Project_Minor_Version = 6

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