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[/] [wb_lpc/] [trunk/] [rtl/] [verilog/] [serirq_host.v] - Blame information for rev 20

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//////////////////////////////////////////////////////////////////////
////                                                              ////
////  $Id: serirq_host.v,v 1.2 2008-12-27 19:46:18 hharte Exp $   ////
////  serirq_host.v - SERIRQ Host Controller                      ////
////                                                              ////
////  This file is part of the Wishbone LPC Bridge project        ////
////  http://www.opencores.org/projects/wb_lpc/                   ////
////                                                              ////
////  Author:                                                     ////
////      - Howard M. Harte (hharte@opencores.org)                ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
////                                                              ////
//// Copyright (C) 2008 Howard M. Harte                           ////
////                                                              ////
//// This source file may be used and distributed without         ////
//// restriction provided that this copyright statement is not    ////
//// removed from the file and that any derivative work contains  ////
//// the original copyright notice and the associated disclaimer. ////
////                                                              ////
//// This source file is free software; you can redistribute it   ////
//// and/or modify it under the terms of the GNU Lesser General   ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any   ////
//// later version.                                               ////
////                                                              ////
//// This source is distributed in the hope that it will be       ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
//// PURPOSE.  See the GNU Lesser General Public License for more ////
//// details.                                                     ////
////                                                              ////
//// You should have received a copy of the GNU Lesser General    ////
//// Public License along with this source; if not, download it   ////
//// from http://www.opencores.org/lgpl.shtml                     ////
////                                                              ////
//////////////////////////////////////////////////////////////////////
 
`timescale 1 ns / 1 ns
 
`include "../../rtl/verilog/serirq_defines.v"
 
module serirq_host(clk_i, nrst_i,
                   serirq_mode_i, irq_o,
                   serirq_o, serirq_i, serirq_oe
);
    // Wishbone Slave Interface
    input              clk_i;
    input              nrst_i;      // Active low reset.
    input              serirq_mode_i; // Mode selection, 0=Continuous, 1=Quiet
 
    // SERIRQ Master Interface
    output reg         serirq_o;    // SERIRQ output
    input              serirq_i;    // SERIRQ Input
    output reg         serirq_oe;   // SERIRQ Output Enable
 
    output reg  [31:0] irq_o;       // IRQ Output Bus
 
    reg         [12:0] state;       // Current state
    reg          [4:0] irq_cnt;     // IRQ Frame counter
    reg          [2:0] start_cnt;   // START counter
    reg          [2:0] stop_cnt;    // STOP counter
    reg                current_mode;
 
    always @(posedge clk_i or negedge nrst_i)
        if(~nrst_i)
        begin
            state <= `SERIRQ_ST_IDLE;
            serirq_oe <= 1'b0;
            serirq_o <= 4'b1;
            irq_cnt <= 5'h00;
                start_cnt <= 3'b000;
                stop_cnt <= 2'b00;
                irq_o <= 32'hFFFFFFFF;
                current_mode <= `SERIRQ_MODE_CONTINUOUS;
        end
        else begin
            case(state)
                `SERIRQ_ST_IDLE:
                    begin
                        serirq_oe <= 1'b0;
                        start_cnt <= 3'b000;
                        stop_cnt <= 2'b00;
                        serirq_o <= 1'b1;
                        if((current_mode == `SERIRQ_MODE_QUIET) && (serirq_i == 1'b0)) begin
                            start_cnt <= 3'b010;
                            serirq_o <= 1'b0;
                            serirq_oe <= 1'b1;
                            state <= `SERIRQ_ST_START;
                        end
                        else if(current_mode == `SERIRQ_MODE_CONTINUOUS)
                        begin
                            start_cnt <= 3'b000;
                            state <= `SERIRQ_ST_START;
                        end
                        else if((current_mode == `SERIRQ_MODE_QUIET) && (serirq_mode_i == `SERIRQ_MODE_CONTINUOUS))
                        begin // Switch to Continuous mode by starting a new cycle to inform the slaves.
                            start_cnt <= 3'b000;
                            state <= `SERIRQ_ST_START;
                        end
                        else
                            state <= `SERIRQ_ST_IDLE;
                    end
                `SERIRQ_ST_START:
                    begin
                        serirq_o <= 1'b0;
                        serirq_oe <= 1'b1;
                        irq_cnt <= 5'h00;
                        start_cnt <= start_cnt + 1;
                        if(start_cnt == 3'b111) begin
                            state <= `SERIRQ_ST_START_R;
                        end
                        else begin
                            state <= `SERIRQ_ST_START;
                        end
                    end
                `SERIRQ_ST_START_R:
                    begin
                        serirq_o <= 1'b1;
                        state <= `SERIRQ_ST_START_T;
                    end
                `SERIRQ_ST_START_T:
                    begin
                        serirq_oe <= 1'b0;
                        state <= `SERIRQ_ST_IRQ;
                    end
                `SERIRQ_ST_IRQ:
                    begin
                        state <= `SERIRQ_ST_IRQ_R;
                    end
                `SERIRQ_ST_IRQ_R:
                    begin
                        irq_o[irq_cnt] <= (serirq_i == 1'b0 ? 1'b0 : 1'b1);
                        state <= `SERIRQ_ST_IRQ_T;
                    end
                `SERIRQ_ST_IRQ_T:
                    begin
                        if(irq_cnt == 5'h1f) begin
                            state <= `SERIRQ_ST_STOP;
                        end else begin
                            state <= `SERIRQ_ST_IRQ;
                            irq_cnt <= irq_cnt + 1;
                        end
                    end
                `SERIRQ_ST_STOP:
                    begin
                        serirq_o <= 1'b0;
                        serirq_oe <= 1'b1;
                        stop_cnt <= stop_cnt + 1;
                        if(stop_cnt == (serirq_mode_i ? 2'b01 : 2'b10)) begin
                            state <= `SERIRQ_ST_STOP_R;
                        end
                        else begin
                            state <= `SERIRQ_ST_STOP;
                        end
                    end
                `SERIRQ_ST_STOP_R:
                    begin
                        serirq_o <= 1'b1;
                        state <= `SERIRQ_ST_STOP_T;
                    end
                `SERIRQ_ST_STOP_T:
                    begin
                        serirq_oe <= 1'b0;
                        state <= `SERIRQ_ST_IDLE;
                        current_mode <= serirq_mode_i;
                    end
            endcase
        end
endmodule
 
 

Line No.	Rev	Author	Line
1	11	hharte	`//////////////////////////////////////////////////////////////////////`
2			`//// ////`
3	19	hharte	`//// $Id: serirq_host.v,v 1.2 2008-12-27 19:46:18 hharte Exp $ ////`
4	11	hharte	`//// serirq_host.v - SERIRQ Host Controller ////`
5			`//// ////`
6			`//// This file is part of the Wishbone LPC Bridge project ////`
7			`//// http://www.opencores.org/projects/wb_lpc/ ////`
8			`//// ////`
9			`//// Author: ////`
10			`//// - Howard M. Harte (hharte@opencores.org) ////`
11			`//// ////`
12			`//////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2008 Howard M. Harte ////`
15			`//// ////`
16			`//// This source file may be used and distributed without ////`
17			`//// restriction provided that this copyright statement is not ////`
18			`//// removed from the file and that any derivative work contains ////`
19			`//// the original copyright notice and the associated disclaimer. ////`
20			`//// ////`
21			`//// This source file is free software; you can redistribute it ////`
22			`//// and/or modify it under the terms of the GNU Lesser General ////`
23			`//// Public License as published by the Free Software Foundation; ////`
24			`//// either version 2.1 of the License, or (at your option) any ////`
25			`//// later version. ////`
26			`//// ////`
27			`//// This source is distributed in the hope that it will be ////`
28			`//// useful, but WITHOUT ANY WARRANTY; without even the implied ////`
29			`//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////`
30			`//// PURPOSE. See the GNU Lesser General Public License for more ////`
31			`//// details. ////`
32			`//// ////`
33			`//// You should have received a copy of the GNU Lesser General ////`
34			`//// Public License along with this source; if not, download it ////`
35			`//// from http://www.opencores.org/lgpl.shtml ////`
36			`//// ////`
37			`//////////////////////////////////////////////////////////////////////`
38
39			`timescale 1 ns / 1 ns
40
41			`include "../../rtl/verilog/serirq_defines.v"
42
43			`module serirq_host(clk_i, nrst_i,`
44			`serirq_mode_i, irq_o,`
45			`serirq_o, serirq_i, serirq_oe`
46			`);`
47			`// Wishbone Slave Interface`
48			`input clk_i;`
49	19	hharte	`input nrst_i; // Active low reset.`
50			`input serirq_mode_i; // Mode selection, 0=Continuous, 1=Quiet`
51	11	hharte
52			`// SERIRQ Master Interface`
53			`output reg serirq_o; // SERIRQ output`
54			`input serirq_i; // SERIRQ Input`
55			`output reg serirq_oe; // SERIRQ Output Enable`
56
57			`output reg [31:0] irq_o; // IRQ Output Bus`
58
59			`reg [12:0] state; // Current state`
60			`reg [4:0] irq_cnt; // IRQ Frame counter`
61			`reg [2:0] start_cnt; // START counter`
62			`reg [2:0] stop_cnt; // STOP counter`
63			`reg current_mode;`
64
65			`always @(posedge clk_i or negedge nrst_i)`
66			`if(~nrst_i)`
67			`begin`
68			state <= `SERIRQ_ST_IDLE;
69			`serirq_oe <= 1'b0;`
70			`serirq_o <= 4'b1;`
71			`irq_cnt <= 5'h00;`
72			`start_cnt <= 3'b000;`
73			`stop_cnt <= 2'b00;`
74			`irq_o <= 32'hFFFFFFFF;`
75			current_mode <= `SERIRQ_MODE_CONTINUOUS;
76			`end`
77			`else begin`
78			`case(state)`
79			`SERIRQ_ST_IDLE:
80			`begin`
81			`serirq_oe <= 1'b0;`
82			`start_cnt <= 3'b000;`
83			`stop_cnt <= 2'b00;`
84			`serirq_o <= 1'b1;`
85			if((current_mode == `SERIRQ_MODE_QUIET) && (serirq_i == 1'b0)) begin
86			`start_cnt <= 3'b010;`
87			`serirq_o <= 1'b0;`
88			`serirq_oe <= 1'b1;`
89			state <= `SERIRQ_ST_START;
90			`end`
91			else if(current_mode == `SERIRQ_MODE_CONTINUOUS)
92			`begin`
93			`start_cnt <= 3'b000;`
94			state <= `SERIRQ_ST_START;
95			`end`
96	19	hharte	else if((current_mode == `SERIRQ_MODE_QUIET) && (serirq_mode_i == `SERIRQ_MODE_CONTINUOUS))
97			`begin // Switch to Continuous mode by starting a new cycle to inform the slaves.`
98	11	hharte	`start_cnt <= 3'b000;`
99			state <= `SERIRQ_ST_START;
100			`end`
101			`else`
102			state <= `SERIRQ_ST_IDLE;
103			`end`
104			`SERIRQ_ST_START:
105			`begin`
106			`serirq_o <= 1'b0;`
107			`serirq_oe <= 1'b1;`
108			`irq_cnt <= 5'h00;`
109			`start_cnt <= start_cnt + 1;`
110			`if(start_cnt == 3'b111) begin`
111			state <= `SERIRQ_ST_START_R;
112			`end`
113			`else begin`
114			state <= `SERIRQ_ST_START;
115			`end`
116			`end`
117			`SERIRQ_ST_START_R:
118			`begin`
119			`serirq_o <= 1'b1;`
120			state <= `SERIRQ_ST_START_T;
121			`end`
122			`SERIRQ_ST_START_T:
123			`begin`
124			`serirq_oe <= 1'b0;`
125			state <= `SERIRQ_ST_IRQ;
126			`end`
127			`SERIRQ_ST_IRQ:
128			`begin`
129			state <= `SERIRQ_ST_IRQ_R;
130			`end`
131			`SERIRQ_ST_IRQ_R:
132			`begin`
133			`irq_o[irq_cnt] <= (serirq_i == 1'b0 ? 1'b0 : 1'b1);`
134			state <= `SERIRQ_ST_IRQ_T;
135			`end`
136			`SERIRQ_ST_IRQ_T:
137			`begin`
138			`if(irq_cnt == 5'h1f) begin`
139			state <= `SERIRQ_ST_STOP;
140			`end else begin`
141			state <= `SERIRQ_ST_IRQ;
142			`irq_cnt <= irq_cnt + 1;`
143			`end`
144			`end`
145			`SERIRQ_ST_STOP:
146			`begin`
147			`serirq_o <= 1'b0;`
148			`serirq_oe <= 1'b1;`
149			`stop_cnt <= stop_cnt + 1;`
150	19	hharte	`if(stop_cnt == (serirq_mode_i ? 2'b01 : 2'b10)) begin`
151	11	hharte	state <= `SERIRQ_ST_STOP_R;
152			`end`
153			`else begin`
154			state <= `SERIRQ_ST_STOP;
155			`end`
156			`end`
157			`SERIRQ_ST_STOP_R:
158			`begin`
159			`serirq_o <= 1'b1;`
160			state <= `SERIRQ_ST_STOP_T;
161			`end`
162			`SERIRQ_ST_STOP_T:
163			`begin`
164			`serirq_oe <= 1'b0;`
165			state <= `SERIRQ_ST_IDLE;
166			`current_mode <= serirq_mode_i;`
167			`end`
168			`endcase`
169			`end`
170			`endmodule`
171
172

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[/] [wb_lpc/] [trunk/] [rtl/] [verilog/] [serirq_host.v] - Blame information for rev 20