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<link REL="stylesheet" TYPE="text/css" HREF="/people/tantos/styles.css">
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<h1>Wishbone Monitor Controller VGA Chip</h1>
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<h2>Description</h2>
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<strong>Wishbone Monitor Controller VGA Chip</strong> adds a simple
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<a href="/cores/wb_tk/wb_async_master.shtml">asyncronous master</a>
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and <a href="/cores/wb_tk/wb_async_slave.shtml">slave</a>
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interface to the <a href="vga_core.shtml">VGA core</a> module.
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It also resolves all generics with constants thus
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before and after sythetesys simulation can be performed with the same
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test-benches. It is ideal to be used with external CPUs and SRAM-based
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pixel memory when there is enough address space available to directly
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map the whole pixel memory to the CPUs address space. No acceleration
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functions are included nor palette is incorporated. It is intended as
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a DEMO application rather than a real-world example.
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<h2>Author & Maintainer</h2>
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<p>
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<a href="/people/tantos">Andras Tantos</a>
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