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[/] [xspi/] [trunk/] [rtl/] [xspi/] [xspi_cfg.v] - Blame information for rev 6

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1 5 dinesha
//////////////////////////////////////////////////////////////////////
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////                                                              ////
3 6 dinesha
////  xSPI Interface Module                                       ////
4 5 dinesha
////                                                              ////
5 6 dinesha
////  This file is part of the xspi project                       ////
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////  https://opencores.org/projects/xspi                         ////
7 5 dinesha
////                                                              ////
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////  Description                                                 ////
9 6 dinesha
////  xspi definitions.                                           ////
10 5 dinesha
////                                                              ////
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////  To Do:                                                      ////
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////    nothing                                                   ////
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////                                                              ////
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////  Author(s):                                                  ////
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////      - Dinesh Annayya, dinesha@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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45
 
46 6 dinesha
module xspi_cfg (
47 5 dinesha
 
48 6 dinesha
            mclk,
49
            reset_n,
50 5 dinesha
 
51
        // Reg Bus Interface Signal
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            reg_cs,
53
            reg_wr,
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            reg_addr,
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            reg_wdata,
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            reg_be,
57 5 dinesha
 
58
            // Outputs
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            reg_rdata,
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            reg_ack,
61
 
62
 
63
           // configuration signal
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           cfg_tgt_sel        ,
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           cfg_op_req         , // SPI operation request
66
           cfg_op_type        , // SPI operation type
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           cfg_transfer_size  , // SPI transfer size
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           cfg_sck_period     , // sck clock period
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           cfg_sck_cs_period  , // cs setup/hold period
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           cfg_cs_byte        , // cs bit information
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           cfg_datain         , // data for transfer
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           cfg_dataout        , // data for received
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           hware_op_done      // operation done
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75
        );
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77
 
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79
input         mclk;
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input         reset_n;
81
 
82
output [1:0]  cfg_tgt_sel        ;
83
 
84
output        cfg_op_req         ; // SPI operation request
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output [1:0]  cfg_op_type        ; // SPI operation type
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output [1:0]  cfg_transfer_size  ; // SPI transfer size
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output [5:0]  cfg_sck_period     ; // sck clock period
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output [4:0]  cfg_sck_cs_period  ; // cs setup/hold period
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output [7:0]  cfg_cs_byte        ; // cs bit information
90
output [31:0] cfg_datain         ; // data for transfer
91
input  [31:0] cfg_dataout        ; // data for received
92
input         hware_op_done      ; // operation done
93
 
94
//---------------------------------
95
// Reg Bus Interface Signal
96
//---------------------------------
97
input             reg_cs         ;
98
input             reg_wr         ;
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input [3:0]       reg_addr       ;
100
input [31:0]      reg_wdata      ;
101
input [3:0]       reg_be         ;
102
 
103
// Outputs
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output [31:0]     reg_rdata      ;
105
output            reg_ack        ;
106
 
107
 
108
 
109
//-----------------------------------------------------------------------
110
// Internal Wire Declarations
111
//-----------------------------------------------------------------------
112
 
113
wire           sw_rd_en;
114
wire           sw_wr_en;
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wire  [3:0]    sw_addr ; // addressing 16 registers
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wire  [3:0]    wr_be   ;
117
 
118
reg   [31:0]  reg_rdata      ;
119
reg           reg_ack     ;
120
 
121
wire [31:0]    reg_0;  // Software_Reg_0
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wire [31:0]    reg_1;  // Software-Reg_1
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wire [31:0]    reg_2;  // Software-Reg_2
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wire [31:0]    reg_3 = 0;  // Software-Reg_3
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wire [31:0]    reg_4 = 0;  // Software-Reg_4
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wire [31:0]    reg_5 = 0;  // Software-Reg_5
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wire [31:0]    reg_6 = 0;  // Software-Reg_6
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wire [31:0]    reg_7 = 0;  // Software-Reg_7
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wire [31:0]    reg_8 = 0;  // Software-Reg_8
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wire [31:0]    reg_9 = 0;  // Software-Reg_9
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wire [31:0]    reg_10 = 0; // Software-Reg_10
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wire [31:0]    reg_11 = 0; // Software-Reg_11
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wire [31:0]    reg_12 = 0; // Software-Reg_12
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wire [31:0]    reg_13 = 0; // Software-Reg_13
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wire [31:0]    reg_14 = 0; // Software-Reg_14
136
wire [31:0]    reg_15 = 0; // Software-Reg_15
137
reg  [31:0]    reg_out;
138
 
139
//-----------------------------------------------------------------------
140
// Main code starts here
141
//-----------------------------------------------------------------------
142
 
143
//-----------------------------------------------------------------------
144
// Internal Logic Starts here
145
//-----------------------------------------------------------------------
146
    assign sw_addr       = reg_addr [3:0];
147
    assign sw_rd_en      = reg_cs & !reg_wr;
148
    assign sw_wr_en      = reg_cs & reg_wr;
149
    assign wr_be         = reg_be;
150
 
151
 
152
//-----------------------------------------------------------------------
153
// Read path mux
154
//-----------------------------------------------------------------------
155
 
156
always @ (posedge mclk or negedge reset_n)
157
begin : preg_out_Seq
158
   if (reset_n == 1'b0)
159
   begin
160
      reg_rdata [31:0]  <= 32'h0000_0000;
161
      reg_ack           <= 1'b0;
162
   end
163
   else if (sw_rd_en && !reg_ack)
164
   begin
165
      reg_rdata [31:0]  <= reg_out [31:0];
166
      reg_ack           <= 1'b1;
167
   end
168
   else if (sw_wr_en && !reg_ack)
169
      reg_ack           <= 1'b1;
170
   else
171
   begin
172
      reg_ack        <= 1'b0;
173
   end
174
end
175
 
176
 
177
//-----------------------------------------------------------------------
178
// register read enable and write enable decoding logic
179
//-----------------------------------------------------------------------
180
wire   sw_wr_en_0 = sw_wr_en & (sw_addr == 4'h0);
181
wire   sw_rd_en_0 = sw_rd_en & (sw_addr == 4'h0);
182
wire   sw_wr_en_1 = sw_wr_en & (sw_addr == 4'h1);
183
wire   sw_rd_en_1 = sw_rd_en & (sw_addr == 4'h1);
184
wire   sw_wr_en_2 = sw_wr_en & (sw_addr == 4'h2);
185
wire   sw_rd_en_2 = sw_rd_en & (sw_addr == 4'h2);
186
wire   sw_wr_en_3 = sw_wr_en & (sw_addr == 4'h3);
187
wire   sw_rd_en_3 = sw_rd_en & (sw_addr == 4'h3);
188
wire   sw_wr_en_4 = sw_wr_en & (sw_addr == 4'h4);
189
wire   sw_rd_en_4 = sw_rd_en & (sw_addr == 4'h4);
190
wire   sw_wr_en_5 = sw_wr_en & (sw_addr == 4'h5);
191
wire   sw_rd_en_5 = sw_rd_en & (sw_addr == 4'h5);
192
wire   sw_wr_en_6 = sw_wr_en & (sw_addr == 4'h6);
193
wire   sw_rd_en_6 = sw_rd_en & (sw_addr == 4'h6);
194
wire   sw_wr_en_7 = sw_wr_en & (sw_addr == 4'h7);
195
wire   sw_rd_en_7 = sw_rd_en & (sw_addr == 4'h7);
196
wire   sw_wr_en_8 = sw_wr_en & (sw_addr == 4'h8);
197
wire   sw_rd_en_8 = sw_rd_en & (sw_addr == 4'h8);
198
wire   sw_wr_en_9 = sw_wr_en & (sw_addr == 4'h9);
199
wire   sw_rd_en_9 = sw_rd_en & (sw_addr == 4'h9);
200
wire   sw_wr_en_10 = sw_wr_en & (sw_addr == 4'hA);
201
wire   sw_rd_en_10 = sw_rd_en & (sw_addr == 4'hA);
202
wire   sw_wr_en_11 = sw_wr_en & (sw_addr == 4'hB);
203
wire   sw_rd_en_11 = sw_rd_en & (sw_addr == 4'hB);
204
wire   sw_wr_en_12 = sw_wr_en & (sw_addr == 4'hC);
205
wire   sw_rd_en_12 = sw_rd_en & (sw_addr == 4'hC);
206
wire   sw_wr_en_13 = sw_wr_en & (sw_addr == 4'hD);
207
wire   sw_rd_en_13 = sw_rd_en & (sw_addr == 4'hD);
208
wire   sw_wr_en_14 = sw_wr_en & (sw_addr == 4'hE);
209
wire   sw_rd_en_14 = sw_rd_en & (sw_addr == 4'hE);
210
wire   sw_wr_en_15 = sw_wr_en & (sw_addr == 4'hF);
211
wire   sw_rd_en_15 = sw_rd_en & (sw_addr == 4'hF);
212
 
213
 
214
always @( *)
215
begin : preg_sel_Com
216
 
217
  reg_out [31:0] = 32'd0;
218
 
219
  case (sw_addr [3:0])
220
    4'b0000 : reg_out [31:0] = reg_0 [31:0];
221
    4'b0001 : reg_out [31:0] = reg_1 [31:0];
222
    4'b0010 : reg_out [31:0] = reg_2 [31:0];
223
    4'b0011 : reg_out [31:0] = reg_3 [31:0];
224
    4'b0100 : reg_out [31:0] = reg_4 [31:0];
225
    4'b0101 : reg_out [31:0] = reg_5 [31:0];
226
    4'b0110 : reg_out [31:0] = reg_6 [31:0];
227
    4'b0111 : reg_out [31:0] = reg_7 [31:0];
228
    4'b1000 : reg_out [31:0] = reg_8 [31:0];
229
    4'b1001 : reg_out [31:0] = reg_9 [31:0];
230
    4'b1010 : reg_out [31:0] = reg_10 [31:0];
231
    4'b1011 : reg_out [31:0] = reg_11 [31:0];
232
    4'b1100 : reg_out [31:0] = reg_12 [31:0];
233
    4'b1101 : reg_out [31:0] = reg_13 [31:0];
234
    4'b1110 : reg_out [31:0] = reg_14 [31:0];
235
    4'b1111 : reg_out [31:0] = reg_15 [31:0];
236
  endcase
237
end
238
 
239
 
240
 
241
//-----------------------------------------------------------------------
242
// Individual register assignments
243
//-----------------------------------------------------------------------
244
// Logic for Register 0 : SPI Control Register
245
//-----------------------------------------------------------------------
246
wire         cfg_op_req         = reg_0[31];    // cpu request
247
wire [1:0]   cfg_tgt_sel        = reg_0[24:23]; // target chip select
248
wire [1:0]   cfg_op_type        = reg_0[22:21]; // SPI operation type
249
wire [1:0]   cfg_transfer_size  = reg_0[20:19]; // SPI transfer size
250
wire [5:0]   cfg_sck_period     = reg_0[18:13]; // sck clock period
251
wire [4:0]   cfg_sck_cs_period  = reg_0[12:8];  // cs setup/hold period
252
wire [7:0]   cfg_cs_byte        = reg_0[7:0];   // cs bit information
253
 
254
generic_register #(8,0  ) u_spi_ctrl_be0 (
255
              .we            ({8{sw_wr_en_0 &
256
                                 wr_be[0]   }}  ),
257
              .data_in       (reg_wdata[7:0]    ),
258
              .reset_n       (reset_n           ),
259
              .clk           (mclk              ),
260
 
261
              //List of Outs
262
              .data_out      (reg_0[7:0]        )
263
          );
264
 
265
generic_register #(8,0  ) u_spi_ctrl_be1 (
266
              .we            ({8{sw_wr_en_0 &
267
                                wr_be[1]   }}  ),
268
              .data_in       (reg_wdata[15:8]  ),
269
              .reset_n       (reset_n           ),
270
              .clk           (mclk              ),
271
 
272
              //List of Outs
273
              .data_out      (reg_0[15:8]       )
274
          );
275
 
276
generic_register #(8,0  ) u_spi_ctrl_be2 (
277
              .we            ({8{sw_wr_en_0 &
278
                                wr_be[2]   }}  ),
279
              .data_in       (reg_wdata[23:16] ),
280
              .reset_n       (reset_n           ),
281
              .clk           (mclk              ),
282
 
283
              //List of Outs
284
              .data_out      (reg_0[23:16]       )
285
          );
286
 
287
assign reg_0[30:24] = 7'h0;
288
 
289
req_register #(0  ) u_spi_ctrl_req (
290
              .cpu_we       ({sw_wr_en_0 &
291
                             wr_be[3]   }       ),
292
              .cpu_req      (reg_wdata[31]      ),
293
              .hware_ack    (hware_op_done      ),
294
              .reset_n       (reset_n           ),
295
              .clk           (mclk              ),
296
 
297
              //List of Outs
298
              .data_out      (reg_0[31]         )
299
          );
300
 
301
 
302
 
303
 
304
//-----------------------------------------------------------------------
305
// Logic for Register 1 : SPI Data In Register
306
//-----------------------------------------------------------------------
307
wire [31:0]   cfg_datain        = reg_1[31:0];
308
 
309
generic_register #(8,0  ) u_spi_din_be0 (
310
              .we            ({8{sw_wr_en_1 &
311
                                wr_be[0]   }}  ),
312
              .data_in       (reg_wdata[7:0]    ),
313
              .reset_n       (reset_n           ),
314
              .clk           (mclk              ),
315
 
316
              //List of Outs
317
              .data_out      (reg_1[7:0]        )
318
          );
319
 
320
generic_register #(8,0  ) u_spi_din_be1 (
321
              .we            ({8{sw_wr_en_1 &
322
                                wr_be[1]   }}  ),
323
              .data_in       (reg_wdata[15:8]   ),
324
              .reset_n       (reset_n           ),
325
              .clk           (mclk              ),
326
 
327
              //List of Outs
328
              .data_out      (reg_1[15:8]       )
329
          );
330
 
331
generic_register #(8,0  ) u_spi_din_be2 (
332
              .we            ({8{sw_wr_en_1 &
333
                                wr_be[2]   }}  ),
334
              .data_in       (reg_wdata[23:16]  ),
335
              .reset_n       (reset_n           ),
336
              .clk           (mclk              ),
337
 
338
              //List of Outs
339
              .data_out      (reg_1[23:16]      )
340
          );
341
 
342
 
343
generic_register #(8,0  ) u_spi_din_be3 (
344
              .we            ({8{sw_wr_en_1 &
345
                                wr_be[3]   }}  ),
346
              .data_in       (reg_wdata[31:24]  ),
347
              .reset_n       (reset_n           ),
348
              .clk           (mclk              ),
349
 
350
              //List of Outs
351
              .data_out      (reg_1[31:24]      )
352
          );
353
 
354
 
355
//-----------------------------------------------------------------------
356
// Logic for Register 2 : SPI Data output Register
357
//-----------------------------------------------------------------------
358
assign  reg_2 = cfg_dataout;
359
 
360
 
361
 
362
endmodule

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