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[/] [xspi/] [trunk/] [rtl/] [xspi/] [xspi_core.v] - Blame information for rev 6

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1 5 dinesha
//////////////////////////////////////////////////////////////////////
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////                                                              ////
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////   xSPI Interface Module                                      ////
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////                                                              ////
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////  This file is part of the xspi project                       ////
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////  https://opencores.org/projects/xspi                         ////
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////                                                              ////
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////  Description                                                 ////
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////  xspi definitions.                                           ////
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////                                                              ////
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////  To Do:                                                      ////
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////    nothing                                                   ////
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////                                                              ////
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////  Version:                                                    ////
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////    1.0 - 26th Oct 2019, Initial version                      ////
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////  Author(s):                                                  ////
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////      - Dinesh Annayya, dinesha@opencores.org                 ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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////                                                              ////
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//// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
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////                                                              ////
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//// This source file may be used and distributed without         ////
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//// restriction provided that this copyright statement is not    ////
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//// removed from the file and that any derivative work contains  ////
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//// the original copyright notice and the associated disclaimer. ////
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////                                                              ////
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//// This source file is free software; you can redistribute it   ////
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//// and/or modify it under the terms of the GNU Lesser General   ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any   ////
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//// later version.                                               ////
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////                                                              ////
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//// This source is distributed in the hope that it will be       ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
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//// PURPOSE.  See the GNU Lesser General Public License for more ////
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//// details.                                                     ////
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////                                                              ////
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//// You should have received a copy of the GNU Lesser General    ////
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//// Public License along with this source; if not, download it   ////
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//// from http://www.opencores.org/lgpl.shtml                     ////
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////                                                              ////
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//////////////////////////////////////////////////////////////////////
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module xspi_core (
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             clk,
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             reset_n,
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        // Reg Bus Interface Signal
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             reg_cs,
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             reg_wr,
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             reg_addr,
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             reg_wdata,
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             reg_be,
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            // Outputs
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            reg_rdata,
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            reg_ack,
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          // line interface
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            sck                ,
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            so                 ,
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            si                 ,
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            cs_n
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           );
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input               clk                           ;
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input               reset_n                       ;
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//---------------------------------
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// Reg Bus Interface Signal
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//---------------------------------
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input               reg_cs                        ;
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input               reg_wr                        ;
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input [3:0]         reg_addr                      ;
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input [31:0]        reg_wdata                     ;
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input [3:0]         reg_be                        ;
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// Outputs
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output [31:0]       reg_rdata                     ;
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output              reg_ack                       ;
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//-------------------------------------------
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// Line Interface
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//-------------------------------------------
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output              sck                           ; // clock out
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output              so                            ; // serial data out
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input               si                            ; // serial data in
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output [3:0]        cs_n                          ; // cs_n
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//------------------------------------
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// Wires
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//------------------------------------
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wire [7:0]          byte_in                       ;
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wire [7:0]          byte_out                      ;
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wire  [1:0]         cfg_tgt_sel                   ;
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wire                cfg_op_req                    ; // SPI operation request
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wire  [1:0]         cfg_op_type                   ; // SPI operation type
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wire  [1:0]         cfg_transfer_size             ; // SPI transfer size
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wire  [5:0]         cfg_sck_period                ; // sck clock period
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wire  [4:0]         cfg_sck_cs_period             ; // cs setup/hold period
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wire  [7:0]         cfg_cs_byte                   ; // cs bit information
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wire  [31:0]        cfg_datain                    ; // data for transfer
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wire  [31:0]        cfg_dataout                   ; // data for received
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wire                hware_op_done                 ; // operation done
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spi_if  u_spi_if
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          (
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          . clk                         (clk                          ),
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          . reset_n                     (reset_n                      ),
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           // towards ctrl i/f
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          . sck_pe                      (sck_pe                       ),
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          . sck_int                     (sck_int                      ),
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          . cs_int_n                    (cs_int_n                     ),
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          . byte_in                     (byte_in                      ),
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          . load_byte                   (load_byte                    ),
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          . byte_out                    (byte_out                     ),
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          . shift_out                   (shift_out                    ),
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          . shift_in                    (shift_in                     ),
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          . cfg_tgt_sel                 (cfg_tgt_sel                  ),
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          . sck                         (sck                          ),
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          . so                          (so                           ),
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          . si                          (si                           ),
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          . cs_n                        (cs_n                         )
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           );
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spi_ctl  u_spi_ctrl
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       (
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          . clk                         (clk                          ),
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          . reset_n                     (reset_n                      ),
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          . cfg_op_req                  (cfg_op_req                   ),
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          . cfg_op_type                 (cfg_op_type                  ),
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          . cfg_transfer_size           (cfg_transfer_size            ),
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          . cfg_sck_period              (cfg_sck_period               ),
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          . cfg_sck_cs_period           (cfg_sck_cs_period            ),
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          . cfg_cs_byte                 (cfg_cs_byte                  ),
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          . cfg_datain                  (cfg_datain                   ),
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          . cfg_dataout                 (cfg_dataout                  ),
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          . op_done                     (hware_op_done                ),
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          . sck_int                     (sck_int                      ),
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          . cs_int_n                    (cs_int_n                     ),
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          . sck_pe                      (sck_pe                       ),
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          . sck_ne                      (sck_ne                       ),
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          . shift_out                   (shift_out                    ),
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          . shift_in                    (shift_in                     ),
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          . load_byte                   (load_byte                    ),
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          . byte_out                    (byte_out                     ),
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          . byte_in                     (byte_in                      )
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         );
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spi_cfg u_cfg (
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          . mclk                        (clk                          ),
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          . reset_n                     (reset_n                      ),
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        // Reg Bus Interface Signal
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          . reg_cs                      (reg_cs                       ),
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          . reg_wr                      (reg_wr                       ),
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          . reg_addr                    (reg_addr                     ),
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          . reg_wdata                   (reg_wdata                    ),
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          . reg_be                      (reg_be                       ),
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            // Outputs
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          . reg_rdata                   (reg_rdata                    ),
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          . reg_ack                     (reg_ack                      ),
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           // configuration signal
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          . cfg_tgt_sel                 (cfg_tgt_sel                  ),
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          . cfg_op_req                  (cfg_op_req                   ), // SPI operation request
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          . cfg_op_type                 (cfg_op_type                  ), // SPI operation type
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          . cfg_transfer_size           (cfg_transfer_size            ), // SPI transfer size
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          . cfg_sck_period              (cfg_sck_period               ), // sck clock period
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          . cfg_sck_cs_period           (cfg_sck_cs_period            ), // cs setup/hold period
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          . cfg_cs_byte                 (cfg_cs_byte                  ), // cs bit information
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          . cfg_datain                  (cfg_datain                   ), // data for transfer
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          . cfg_dataout                 (cfg_dataout                  ), // data for received
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          . hware_op_done               (hware_op_done                )  // operation done
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        );
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endmodule

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