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[/] [z80soc/] [trunk/] [V0.7.3/] [DE1/] [db/] [altsyncram_1v91.tdf] - Blame information for rev 46

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1 46 rrred
--altsyncram ADDRESS_ACLR_A="NONE" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" ENABLE_RUNTIME_MOD="NO" INIT_FILE="./ROMdata/rom.hex" LOW_POWER_MODE="AUTO" NUMWORDS_A=16384 OPERATION_MODE="ROM" OUTDATA_ACLR_A="NONE" OUTDATA_REG_A="CLOCK0" WIDTH_A=8 WIDTH_BYTEENA_A=1 WIDTHAD_A=14 address_a clock0 q_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
2
--VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ  VERSION_END
3
 
4
 
5
-- Copyright (C) 1991-2013 Altera Corporation
6
--  Your use of Altera Corporation's design tools, logic functions
7
--  and other software and tools, and its AMPP partner logic
8
--  functions, and any output files from any of the foregoing
9
--  (including device programming or simulation files), and any
10
--  associated documentation or information are expressly subject
11
--  to the terms and conditions of the Altera Program License
12
--  Subscription Agreement, Altera MegaCore Function License
13
--  Agreement, or other applicable license agreement, including,
14
--  without limitation, that your use is for the sole purpose of
15
--  programming logic devices manufactured by Altera and sold by
16
--  Altera or its authorized distributors.  Please refer to the
17
--  applicable agreement for further details.
18
 
19
 
20
FUNCTION decode_c8a (data[0..0])
21
RETURNS ( eq[1..0]);
22
FUNCTION mux_3nb (data[15..0], sel[0..0])
23
RETURNS ( result[7..0]);
24
FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
25
WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
26
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
27
 
28
--synthesis_resources = lut 9 M9K 16 reg 2
29
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
30
 
31
SUBDESIGN altsyncram_1v91
32
(
33
        address_a[13..0]        :       input;
34
        clock0  :       input;
35
        q_a[7..0]       :       output;
36
)
37
VARIABLE
38
        address_reg_a[0..0] : dffe;
39
        out_address_reg_a[0..0] : dffe;
40
        rden_decode : decode_c8a;
41
        mux2 : mux_3nb;
42
        ram_block1a0 : cycloneive_ram_block
43
                WITH (
44
                        CLK0_CORE_CLOCK_ENABLE = "ena0",
45
                        CLK0_INPUT_CLOCK_ENABLE = "none",
46
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
47
                        CONNECTIVITY_CHECKING = "OFF",
48
                        INIT_FILE = "./ROMdata/rom.hex",
49
                        INIT_FILE_LAYOUT = "port_a",
50
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
51
                        OPERATION_MODE = "rom",
52
                        PORT_A_ADDRESS_CLEAR = "none",
53
                        PORT_A_ADDRESS_WIDTH = 13,
54
                        PORT_A_DATA_OUT_CLEAR = "none",
55
                        PORT_A_DATA_OUT_CLOCK = "clock0",
56
                        PORT_A_DATA_WIDTH = 1,
57
                        PORT_A_FIRST_ADDRESS = 0,
58
                        PORT_A_FIRST_BIT_NUMBER = 0,
59
                        PORT_A_LAST_ADDRESS = 8191,
60
                        PORT_A_LOGICAL_RAM_DEPTH = 16384,
61
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
62
                        RAM_BLOCK_TYPE = "AUTO"
63
                );
64
        ram_block1a1 : cycloneive_ram_block
65
                WITH (
66
                        CLK0_CORE_CLOCK_ENABLE = "ena0",
67
                        CLK0_INPUT_CLOCK_ENABLE = "none",
68
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
69
                        CONNECTIVITY_CHECKING = "OFF",
70
                        INIT_FILE = "./ROMdata/rom.hex",
71
                        INIT_FILE_LAYOUT = "port_a",
72
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
73
                        OPERATION_MODE = "rom",
74
                        PORT_A_ADDRESS_CLEAR = "none",
75
                        PORT_A_ADDRESS_WIDTH = 13,
76
                        PORT_A_DATA_OUT_CLEAR = "none",
77
                        PORT_A_DATA_OUT_CLOCK = "clock0",
78
                        PORT_A_DATA_WIDTH = 1,
79
                        PORT_A_FIRST_ADDRESS = 0,
80
                        PORT_A_FIRST_BIT_NUMBER = 1,
81
                        PORT_A_LAST_ADDRESS = 8191,
82
                        PORT_A_LOGICAL_RAM_DEPTH = 16384,
83
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
84
                        RAM_BLOCK_TYPE = "AUTO"
85
                );
86
        ram_block1a2 : cycloneive_ram_block
87
                WITH (
88
                        CLK0_CORE_CLOCK_ENABLE = "ena0",
89
                        CLK0_INPUT_CLOCK_ENABLE = "none",
90
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
91
                        CONNECTIVITY_CHECKING = "OFF",
92
                        INIT_FILE = "./ROMdata/rom.hex",
93
                        INIT_FILE_LAYOUT = "port_a",
94
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
95
                        OPERATION_MODE = "rom",
96
                        PORT_A_ADDRESS_CLEAR = "none",
97
                        PORT_A_ADDRESS_WIDTH = 13,
98
                        PORT_A_DATA_OUT_CLEAR = "none",
99
                        PORT_A_DATA_OUT_CLOCK = "clock0",
100
                        PORT_A_DATA_WIDTH = 1,
101
                        PORT_A_FIRST_ADDRESS = 0,
102
                        PORT_A_FIRST_BIT_NUMBER = 2,
103
                        PORT_A_LAST_ADDRESS = 8191,
104
                        PORT_A_LOGICAL_RAM_DEPTH = 16384,
105
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
106
                        RAM_BLOCK_TYPE = "AUTO"
107
                );
108
        ram_block1a3 : cycloneive_ram_block
109
                WITH (
110
                        CLK0_CORE_CLOCK_ENABLE = "ena0",
111
                        CLK0_INPUT_CLOCK_ENABLE = "none",
112
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
113
                        CONNECTIVITY_CHECKING = "OFF",
114
                        INIT_FILE = "./ROMdata/rom.hex",
115
                        INIT_FILE_LAYOUT = "port_a",
116
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
117
                        OPERATION_MODE = "rom",
118
                        PORT_A_ADDRESS_CLEAR = "none",
119
                        PORT_A_ADDRESS_WIDTH = 13,
120
                        PORT_A_DATA_OUT_CLEAR = "none",
121
                        PORT_A_DATA_OUT_CLOCK = "clock0",
122
                        PORT_A_DATA_WIDTH = 1,
123
                        PORT_A_FIRST_ADDRESS = 0,
124
                        PORT_A_FIRST_BIT_NUMBER = 3,
125
                        PORT_A_LAST_ADDRESS = 8191,
126
                        PORT_A_LOGICAL_RAM_DEPTH = 16384,
127
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
128
                        RAM_BLOCK_TYPE = "AUTO"
129
                );
130
        ram_block1a4 : cycloneive_ram_block
131
                WITH (
132
                        CLK0_CORE_CLOCK_ENABLE = "ena0",
133
                        CLK0_INPUT_CLOCK_ENABLE = "none",
134
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
135
                        CONNECTIVITY_CHECKING = "OFF",
136
                        INIT_FILE = "./ROMdata/rom.hex",
137
                        INIT_FILE_LAYOUT = "port_a",
138
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
139
                        OPERATION_MODE = "rom",
140
                        PORT_A_ADDRESS_CLEAR = "none",
141
                        PORT_A_ADDRESS_WIDTH = 13,
142
                        PORT_A_DATA_OUT_CLEAR = "none",
143
                        PORT_A_DATA_OUT_CLOCK = "clock0",
144
                        PORT_A_DATA_WIDTH = 1,
145
                        PORT_A_FIRST_ADDRESS = 0,
146
                        PORT_A_FIRST_BIT_NUMBER = 4,
147
                        PORT_A_LAST_ADDRESS = 8191,
148
                        PORT_A_LOGICAL_RAM_DEPTH = 16384,
149
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
150
                        RAM_BLOCK_TYPE = "AUTO"
151
                );
152
        ram_block1a5 : cycloneive_ram_block
153
                WITH (
154
                        CLK0_CORE_CLOCK_ENABLE = "ena0",
155
                        CLK0_INPUT_CLOCK_ENABLE = "none",
156
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
157
                        CONNECTIVITY_CHECKING = "OFF",
158
                        INIT_FILE = "./ROMdata/rom.hex",
159
                        INIT_FILE_LAYOUT = "port_a",
160
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
161
                        OPERATION_MODE = "rom",
162
                        PORT_A_ADDRESS_CLEAR = "none",
163
                        PORT_A_ADDRESS_WIDTH = 13,
164
                        PORT_A_DATA_OUT_CLEAR = "none",
165
                        PORT_A_DATA_OUT_CLOCK = "clock0",
166
                        PORT_A_DATA_WIDTH = 1,
167
                        PORT_A_FIRST_ADDRESS = 0,
168
                        PORT_A_FIRST_BIT_NUMBER = 5,
169
                        PORT_A_LAST_ADDRESS = 8191,
170
                        PORT_A_LOGICAL_RAM_DEPTH = 16384,
171
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
172
                        RAM_BLOCK_TYPE = "AUTO"
173
                );
174
        ram_block1a6 : cycloneive_ram_block
175
                WITH (
176
                        CLK0_CORE_CLOCK_ENABLE = "ena0",
177
                        CLK0_INPUT_CLOCK_ENABLE = "none",
178
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
179
                        CONNECTIVITY_CHECKING = "OFF",
180
                        INIT_FILE = "./ROMdata/rom.hex",
181
                        INIT_FILE_LAYOUT = "port_a",
182
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
183
                        OPERATION_MODE = "rom",
184
                        PORT_A_ADDRESS_CLEAR = "none",
185
                        PORT_A_ADDRESS_WIDTH = 13,
186
                        PORT_A_DATA_OUT_CLEAR = "none",
187
                        PORT_A_DATA_OUT_CLOCK = "clock0",
188
                        PORT_A_DATA_WIDTH = 1,
189
                        PORT_A_FIRST_ADDRESS = 0,
190
                        PORT_A_FIRST_BIT_NUMBER = 6,
191
                        PORT_A_LAST_ADDRESS = 8191,
192
                        PORT_A_LOGICAL_RAM_DEPTH = 16384,
193
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
194
                        RAM_BLOCK_TYPE = "AUTO"
195
                );
196
        ram_block1a7 : cycloneive_ram_block
197
                WITH (
198
                        CLK0_CORE_CLOCK_ENABLE = "ena0",
199
                        CLK0_INPUT_CLOCK_ENABLE = "none",
200
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
201
                        CONNECTIVITY_CHECKING = "OFF",
202
                        INIT_FILE = "./ROMdata/rom.hex",
203
                        INIT_FILE_LAYOUT = "port_a",
204
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
205
                        OPERATION_MODE = "rom",
206
                        PORT_A_ADDRESS_CLEAR = "none",
207
                        PORT_A_ADDRESS_WIDTH = 13,
208
                        PORT_A_DATA_OUT_CLEAR = "none",
209
                        PORT_A_DATA_OUT_CLOCK = "clock0",
210
                        PORT_A_DATA_WIDTH = 1,
211
                        PORT_A_FIRST_ADDRESS = 0,
212
                        PORT_A_FIRST_BIT_NUMBER = 7,
213
                        PORT_A_LAST_ADDRESS = 8191,
214
                        PORT_A_LOGICAL_RAM_DEPTH = 16384,
215
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
216
                        RAM_BLOCK_TYPE = "AUTO"
217
                );
218
        ram_block1a8 : cycloneive_ram_block
219
                WITH (
220
                        CLK0_CORE_CLOCK_ENABLE = "ena0",
221
                        CLK0_INPUT_CLOCK_ENABLE = "none",
222
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
223
                        CONNECTIVITY_CHECKING = "OFF",
224
                        INIT_FILE = "./ROMdata/rom.hex",
225
                        INIT_FILE_LAYOUT = "port_a",
226
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
227
                        OPERATION_MODE = "rom",
228
                        PORT_A_ADDRESS_CLEAR = "none",
229
                        PORT_A_ADDRESS_WIDTH = 13,
230
                        PORT_A_DATA_OUT_CLEAR = "none",
231
                        PORT_A_DATA_OUT_CLOCK = "clock0",
232
                        PORT_A_DATA_WIDTH = 1,
233
                        PORT_A_FIRST_ADDRESS = 8192,
234
                        PORT_A_FIRST_BIT_NUMBER = 0,
235
                        PORT_A_LAST_ADDRESS = 16383,
236
                        PORT_A_LOGICAL_RAM_DEPTH = 16384,
237
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
238
                        RAM_BLOCK_TYPE = "AUTO"
239
                );
240
        ram_block1a9 : cycloneive_ram_block
241
                WITH (
242
                        CLK0_CORE_CLOCK_ENABLE = "ena0",
243
                        CLK0_INPUT_CLOCK_ENABLE = "none",
244
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
245
                        CONNECTIVITY_CHECKING = "OFF",
246
                        INIT_FILE = "./ROMdata/rom.hex",
247
                        INIT_FILE_LAYOUT = "port_a",
248
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
249
                        OPERATION_MODE = "rom",
250
                        PORT_A_ADDRESS_CLEAR = "none",
251
                        PORT_A_ADDRESS_WIDTH = 13,
252
                        PORT_A_DATA_OUT_CLEAR = "none",
253
                        PORT_A_DATA_OUT_CLOCK = "clock0",
254
                        PORT_A_DATA_WIDTH = 1,
255
                        PORT_A_FIRST_ADDRESS = 8192,
256
                        PORT_A_FIRST_BIT_NUMBER = 1,
257
                        PORT_A_LAST_ADDRESS = 16383,
258
                        PORT_A_LOGICAL_RAM_DEPTH = 16384,
259
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
260
                        RAM_BLOCK_TYPE = "AUTO"
261
                );
262
        ram_block1a10 : cycloneive_ram_block
263
                WITH (
264
                        CLK0_CORE_CLOCK_ENABLE = "ena0",
265
                        CLK0_INPUT_CLOCK_ENABLE = "none",
266
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
267
                        CONNECTIVITY_CHECKING = "OFF",
268
                        INIT_FILE = "./ROMdata/rom.hex",
269
                        INIT_FILE_LAYOUT = "port_a",
270
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
271
                        OPERATION_MODE = "rom",
272
                        PORT_A_ADDRESS_CLEAR = "none",
273
                        PORT_A_ADDRESS_WIDTH = 13,
274
                        PORT_A_DATA_OUT_CLEAR = "none",
275
                        PORT_A_DATA_OUT_CLOCK = "clock0",
276
                        PORT_A_DATA_WIDTH = 1,
277
                        PORT_A_FIRST_ADDRESS = 8192,
278
                        PORT_A_FIRST_BIT_NUMBER = 2,
279
                        PORT_A_LAST_ADDRESS = 16383,
280
                        PORT_A_LOGICAL_RAM_DEPTH = 16384,
281
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
282
                        RAM_BLOCK_TYPE = "AUTO"
283
                );
284
        ram_block1a11 : cycloneive_ram_block
285
                WITH (
286
                        CLK0_CORE_CLOCK_ENABLE = "ena0",
287
                        CLK0_INPUT_CLOCK_ENABLE = "none",
288
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
289
                        CONNECTIVITY_CHECKING = "OFF",
290
                        INIT_FILE = "./ROMdata/rom.hex",
291
                        INIT_FILE_LAYOUT = "port_a",
292
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
293
                        OPERATION_MODE = "rom",
294
                        PORT_A_ADDRESS_CLEAR = "none",
295
                        PORT_A_ADDRESS_WIDTH = 13,
296
                        PORT_A_DATA_OUT_CLEAR = "none",
297
                        PORT_A_DATA_OUT_CLOCK = "clock0",
298
                        PORT_A_DATA_WIDTH = 1,
299
                        PORT_A_FIRST_ADDRESS = 8192,
300
                        PORT_A_FIRST_BIT_NUMBER = 3,
301
                        PORT_A_LAST_ADDRESS = 16383,
302
                        PORT_A_LOGICAL_RAM_DEPTH = 16384,
303
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
304
                        RAM_BLOCK_TYPE = "AUTO"
305
                );
306
        ram_block1a12 : cycloneive_ram_block
307
                WITH (
308
                        CLK0_CORE_CLOCK_ENABLE = "ena0",
309
                        CLK0_INPUT_CLOCK_ENABLE = "none",
310
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
311
                        CONNECTIVITY_CHECKING = "OFF",
312
                        INIT_FILE = "./ROMdata/rom.hex",
313
                        INIT_FILE_LAYOUT = "port_a",
314
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
315
                        OPERATION_MODE = "rom",
316
                        PORT_A_ADDRESS_CLEAR = "none",
317
                        PORT_A_ADDRESS_WIDTH = 13,
318
                        PORT_A_DATA_OUT_CLEAR = "none",
319
                        PORT_A_DATA_OUT_CLOCK = "clock0",
320
                        PORT_A_DATA_WIDTH = 1,
321
                        PORT_A_FIRST_ADDRESS = 8192,
322
                        PORT_A_FIRST_BIT_NUMBER = 4,
323
                        PORT_A_LAST_ADDRESS = 16383,
324
                        PORT_A_LOGICAL_RAM_DEPTH = 16384,
325
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
326
                        RAM_BLOCK_TYPE = "AUTO"
327
                );
328
        ram_block1a13 : cycloneive_ram_block
329
                WITH (
330
                        CLK0_CORE_CLOCK_ENABLE = "ena0",
331
                        CLK0_INPUT_CLOCK_ENABLE = "none",
332
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
333
                        CONNECTIVITY_CHECKING = "OFF",
334
                        INIT_FILE = "./ROMdata/rom.hex",
335
                        INIT_FILE_LAYOUT = "port_a",
336
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
337
                        OPERATION_MODE = "rom",
338
                        PORT_A_ADDRESS_CLEAR = "none",
339
                        PORT_A_ADDRESS_WIDTH = 13,
340
                        PORT_A_DATA_OUT_CLEAR = "none",
341
                        PORT_A_DATA_OUT_CLOCK = "clock0",
342
                        PORT_A_DATA_WIDTH = 1,
343
                        PORT_A_FIRST_ADDRESS = 8192,
344
                        PORT_A_FIRST_BIT_NUMBER = 5,
345
                        PORT_A_LAST_ADDRESS = 16383,
346
                        PORT_A_LOGICAL_RAM_DEPTH = 16384,
347
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
348
                        RAM_BLOCK_TYPE = "AUTO"
349
                );
350
        ram_block1a14 : cycloneive_ram_block
351
                WITH (
352
                        CLK0_CORE_CLOCK_ENABLE = "ena0",
353
                        CLK0_INPUT_CLOCK_ENABLE = "none",
354
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
355
                        CONNECTIVITY_CHECKING = "OFF",
356
                        INIT_FILE = "./ROMdata/rom.hex",
357
                        INIT_FILE_LAYOUT = "port_a",
358
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
359
                        OPERATION_MODE = "rom",
360
                        PORT_A_ADDRESS_CLEAR = "none",
361
                        PORT_A_ADDRESS_WIDTH = 13,
362
                        PORT_A_DATA_OUT_CLEAR = "none",
363
                        PORT_A_DATA_OUT_CLOCK = "clock0",
364
                        PORT_A_DATA_WIDTH = 1,
365
                        PORT_A_FIRST_ADDRESS = 8192,
366
                        PORT_A_FIRST_BIT_NUMBER = 6,
367
                        PORT_A_LAST_ADDRESS = 16383,
368
                        PORT_A_LOGICAL_RAM_DEPTH = 16384,
369
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
370
                        RAM_BLOCK_TYPE = "AUTO"
371
                );
372
        ram_block1a15 : cycloneive_ram_block
373
                WITH (
374
                        CLK0_CORE_CLOCK_ENABLE = "ena0",
375
                        CLK0_INPUT_CLOCK_ENABLE = "none",
376
                        CLK0_OUTPUT_CLOCK_ENABLE = "none",
377
                        CONNECTIVITY_CHECKING = "OFF",
378
                        INIT_FILE = "./ROMdata/rom.hex",
379
                        INIT_FILE_LAYOUT = "port_a",
380
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
381
                        OPERATION_MODE = "rom",
382
                        PORT_A_ADDRESS_CLEAR = "none",
383
                        PORT_A_ADDRESS_WIDTH = 13,
384
                        PORT_A_DATA_OUT_CLEAR = "none",
385
                        PORT_A_DATA_OUT_CLOCK = "clock0",
386
                        PORT_A_DATA_WIDTH = 1,
387
                        PORT_A_FIRST_ADDRESS = 8192,
388
                        PORT_A_FIRST_BIT_NUMBER = 7,
389
                        PORT_A_LAST_ADDRESS = 16383,
390
                        PORT_A_LOGICAL_RAM_DEPTH = 16384,
391
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
392
                        RAM_BLOCK_TYPE = "AUTO"
393
                );
394
        address_a_sel[0..0]     : WIRE;
395
        address_a_wire[13..0]   : WIRE;
396
        rden_decode_addr_sel_a[0..0]    : WIRE;
397
 
398
BEGIN
399
        address_reg_a[].clk = clock0;
400
        address_reg_a[].d = address_a_sel[];
401
        out_address_reg_a[].clk = clock0;
402
        out_address_reg_a[].d = address_reg_a[].q;
403
        rden_decode.data[] = rden_decode_addr_sel_a[];
404
        mux2.data[] = ( ram_block1a[15..0].portadataout[0..0]);
405
        mux2.sel[] = out_address_reg_a[].q;
406
        ram_block1a[15..0].clk0 = clock0;
407
        ram_block1a[15..0].ena0 = ( rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..1], rden_decode.eq[1..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0], rden_decode.eq[0..0]);
408
        ram_block1a[15..0].portaaddr[] = ( address_a_wire[12..0]);
409
        ram_block1a[15..0].portare = B"1111111111111111";
410
        address_a_sel[0..0] = address_a[13..13];
411
        address_a_wire[] = address_a[];
412
        q_a[] = mux2.result[];
413
        rden_decode_addr_sel_a[0..0] = address_a_wire[13..13];
414
END;
415
--VALID FILE

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