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[/] [z80soc/] [trunk/] [V0.7.3/] [DE1/] [db/] [altsyncram_36o1.tdf] - Blame information for rev 46

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1 46 rrred
--altsyncram ADDRESS_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_INPUT_B="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" CYCLONEII_SAFE_WRITE="NO_CHANGE" DEVICE_FAMILY="Cyclone II" INIT_FILE="../ROMdata/lat9-08.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=2048 NUMWORDS_B=2048 OPERATION_MODE="BIDIR_DUAL_PORT" POWER_UP_UNINITIALIZED="FALSE" WIDTH_A=8 WIDTH_B=8 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTHAD_A=11 WIDTHAD_B=11 WRCONTROL_WRADDRESS_REG_B="CLOCK1" address_a address_b clock0 clock1 clocken1 data_a data_b q_a wren_a wren_b CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
2
--VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ  VERSION_END
3
 
4
 
5
-- Copyright (C) 1991-2013 Altera Corporation
6
--  Your use of Altera Corporation's design tools, logic functions
7
--  and other software and tools, and its AMPP partner logic
8
--  functions, and any output files from any of the foregoing
9
--  (including device programming or simulation files), and any
10
--  associated documentation or information are expressly subject
11
--  to the terms and conditions of the Altera Program License
12
--  Subscription Agreement, Altera MegaCore Function License
13
--  Agreement, or other applicable license agreement, including,
14
--  without limitation, that your use is for the sole purpose of
15
--  programming logic devices manufactured by Altera and sold by
16
--  Altera or its authorized distributors.  Please refer to the
17
--  applicable agreement for further details.
18
 
19
 
20
FUNCTION cycloneii_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbrewe)
21
WITH ( CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS, PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS, PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
22
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
23
 
24
--synthesis_resources = M4K 4
25
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
26
 
27
SUBDESIGN altsyncram_36o1
28
(
29
        address_a[10..0]        :       input;
30
        address_b[10..0]        :       input;
31
        clock0  :       input;
32
        clock1  :       input;
33
        clocken1        :       input;
34
        data_a[7..0]    :       input;
35
        data_b[7..0]    :       input;
36
        q_a[7..0]       :       output;
37
        q_b[7..0]       :       output;
38
        wren_a  :       input;
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        wren_b  :       input;
40
)
41
VARIABLE
42
        ram_block2a0 : cycloneii_ram_block
43
                WITH (
44
                        CONNECTIVITY_CHECKING = "OFF",
45
                        INIT_FILE = "../ROMdata/lat9-08.mif",
46
                        INIT_FILE_LAYOUT = "port_a",
47
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
48
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
49
                        OPERATION_MODE = "bidir_dual_port",
50
                        PORT_A_ADDRESS_WIDTH = 11,
51
                        PORT_A_DATA_WIDTH = 1,
52
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
53
                        PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
54
                        PORT_A_FIRST_ADDRESS = 0,
55
                        PORT_A_FIRST_BIT_NUMBER = 0,
56
                        PORT_A_LAST_ADDRESS = 2047,
57
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
58
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
59
                        PORT_B_ADDRESS_CLOCK = "clock1",
60
                        PORT_B_ADDRESS_WIDTH = 11,
61
                        PORT_B_DATA_IN_CLOCK = "clock1",
62
                        PORT_B_DATA_WIDTH = 1,
63
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
64
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
65
                        PORT_B_FIRST_ADDRESS = 0,
66
                        PORT_B_FIRST_BIT_NUMBER = 0,
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                        PORT_B_LAST_ADDRESS = 2047,
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                        PORT_B_LOGICAL_RAM_DEPTH = 2048,
69
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
70
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
71
                        POWER_UP_UNINITIALIZED = "false",
72
                        RAM_BLOCK_TYPE = "AUTO"
73
                );
74
        ram_block2a1 : cycloneii_ram_block
75
                WITH (
76
                        CONNECTIVITY_CHECKING = "OFF",
77
                        INIT_FILE = "../ROMdata/lat9-08.mif",
78
                        INIT_FILE_LAYOUT = "port_a",
79
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
80
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
81
                        OPERATION_MODE = "bidir_dual_port",
82
                        PORT_A_ADDRESS_WIDTH = 11,
83
                        PORT_A_DATA_WIDTH = 1,
84
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
85
                        PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
86
                        PORT_A_FIRST_ADDRESS = 0,
87
                        PORT_A_FIRST_BIT_NUMBER = 1,
88
                        PORT_A_LAST_ADDRESS = 2047,
89
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
90
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
91
                        PORT_B_ADDRESS_CLOCK = "clock1",
92
                        PORT_B_ADDRESS_WIDTH = 11,
93
                        PORT_B_DATA_IN_CLOCK = "clock1",
94
                        PORT_B_DATA_WIDTH = 1,
95
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
96
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
97
                        PORT_B_FIRST_ADDRESS = 0,
98
                        PORT_B_FIRST_BIT_NUMBER = 1,
99
                        PORT_B_LAST_ADDRESS = 2047,
100
                        PORT_B_LOGICAL_RAM_DEPTH = 2048,
101
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
102
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
103
                        POWER_UP_UNINITIALIZED = "false",
104
                        RAM_BLOCK_TYPE = "AUTO"
105
                );
106
        ram_block2a2 : cycloneii_ram_block
107
                WITH (
108
                        CONNECTIVITY_CHECKING = "OFF",
109
                        INIT_FILE = "../ROMdata/lat9-08.mif",
110
                        INIT_FILE_LAYOUT = "port_a",
111
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
112
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
113
                        OPERATION_MODE = "bidir_dual_port",
114
                        PORT_A_ADDRESS_WIDTH = 11,
115
                        PORT_A_DATA_WIDTH = 1,
116
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
117
                        PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
118
                        PORT_A_FIRST_ADDRESS = 0,
119
                        PORT_A_FIRST_BIT_NUMBER = 2,
120
                        PORT_A_LAST_ADDRESS = 2047,
121
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
122
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
123
                        PORT_B_ADDRESS_CLOCK = "clock1",
124
                        PORT_B_ADDRESS_WIDTH = 11,
125
                        PORT_B_DATA_IN_CLOCK = "clock1",
126
                        PORT_B_DATA_WIDTH = 1,
127
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
128
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
129
                        PORT_B_FIRST_ADDRESS = 0,
130
                        PORT_B_FIRST_BIT_NUMBER = 2,
131
                        PORT_B_LAST_ADDRESS = 2047,
132
                        PORT_B_LOGICAL_RAM_DEPTH = 2048,
133
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
134
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
135
                        POWER_UP_UNINITIALIZED = "false",
136
                        RAM_BLOCK_TYPE = "AUTO"
137
                );
138
        ram_block2a3 : cycloneii_ram_block
139
                WITH (
140
                        CONNECTIVITY_CHECKING = "OFF",
141
                        INIT_FILE = "../ROMdata/lat9-08.mif",
142
                        INIT_FILE_LAYOUT = "port_a",
143
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
144
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
145
                        OPERATION_MODE = "bidir_dual_port",
146
                        PORT_A_ADDRESS_WIDTH = 11,
147
                        PORT_A_DATA_WIDTH = 1,
148
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
149
                        PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
150
                        PORT_A_FIRST_ADDRESS = 0,
151
                        PORT_A_FIRST_BIT_NUMBER = 3,
152
                        PORT_A_LAST_ADDRESS = 2047,
153
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
154
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
155
                        PORT_B_ADDRESS_CLOCK = "clock1",
156
                        PORT_B_ADDRESS_WIDTH = 11,
157
                        PORT_B_DATA_IN_CLOCK = "clock1",
158
                        PORT_B_DATA_WIDTH = 1,
159
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
160
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
161
                        PORT_B_FIRST_ADDRESS = 0,
162
                        PORT_B_FIRST_BIT_NUMBER = 3,
163
                        PORT_B_LAST_ADDRESS = 2047,
164
                        PORT_B_LOGICAL_RAM_DEPTH = 2048,
165
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
166
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
167
                        POWER_UP_UNINITIALIZED = "false",
168
                        RAM_BLOCK_TYPE = "AUTO"
169
                );
170
        ram_block2a4 : cycloneii_ram_block
171
                WITH (
172
                        CONNECTIVITY_CHECKING = "OFF",
173
                        INIT_FILE = "../ROMdata/lat9-08.mif",
174
                        INIT_FILE_LAYOUT = "port_a",
175
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
176
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
177
                        OPERATION_MODE = "bidir_dual_port",
178
                        PORT_A_ADDRESS_WIDTH = 11,
179
                        PORT_A_DATA_WIDTH = 1,
180
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
181
                        PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
182
                        PORT_A_FIRST_ADDRESS = 0,
183
                        PORT_A_FIRST_BIT_NUMBER = 4,
184
                        PORT_A_LAST_ADDRESS = 2047,
185
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
186
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
187
                        PORT_B_ADDRESS_CLOCK = "clock1",
188
                        PORT_B_ADDRESS_WIDTH = 11,
189
                        PORT_B_DATA_IN_CLOCK = "clock1",
190
                        PORT_B_DATA_WIDTH = 1,
191
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
192
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
193
                        PORT_B_FIRST_ADDRESS = 0,
194
                        PORT_B_FIRST_BIT_NUMBER = 4,
195
                        PORT_B_LAST_ADDRESS = 2047,
196
                        PORT_B_LOGICAL_RAM_DEPTH = 2048,
197
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
198
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
199
                        POWER_UP_UNINITIALIZED = "false",
200
                        RAM_BLOCK_TYPE = "AUTO"
201
                );
202
        ram_block2a5 : cycloneii_ram_block
203
                WITH (
204
                        CONNECTIVITY_CHECKING = "OFF",
205
                        INIT_FILE = "../ROMdata/lat9-08.mif",
206
                        INIT_FILE_LAYOUT = "port_a",
207
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
208
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
209
                        OPERATION_MODE = "bidir_dual_port",
210
                        PORT_A_ADDRESS_WIDTH = 11,
211
                        PORT_A_DATA_WIDTH = 1,
212
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
213
                        PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
214
                        PORT_A_FIRST_ADDRESS = 0,
215
                        PORT_A_FIRST_BIT_NUMBER = 5,
216
                        PORT_A_LAST_ADDRESS = 2047,
217
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
218
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
219
                        PORT_B_ADDRESS_CLOCK = "clock1",
220
                        PORT_B_ADDRESS_WIDTH = 11,
221
                        PORT_B_DATA_IN_CLOCK = "clock1",
222
                        PORT_B_DATA_WIDTH = 1,
223
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
224
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
225
                        PORT_B_FIRST_ADDRESS = 0,
226
                        PORT_B_FIRST_BIT_NUMBER = 5,
227
                        PORT_B_LAST_ADDRESS = 2047,
228
                        PORT_B_LOGICAL_RAM_DEPTH = 2048,
229
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
230
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
231
                        POWER_UP_UNINITIALIZED = "false",
232
                        RAM_BLOCK_TYPE = "AUTO"
233
                );
234
        ram_block2a6 : cycloneii_ram_block
235
                WITH (
236
                        CONNECTIVITY_CHECKING = "OFF",
237
                        INIT_FILE = "../ROMdata/lat9-08.mif",
238
                        INIT_FILE_LAYOUT = "port_a",
239
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
240
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
241
                        OPERATION_MODE = "bidir_dual_port",
242
                        PORT_A_ADDRESS_WIDTH = 11,
243
                        PORT_A_DATA_WIDTH = 1,
244
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
245
                        PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
246
                        PORT_A_FIRST_ADDRESS = 0,
247
                        PORT_A_FIRST_BIT_NUMBER = 6,
248
                        PORT_A_LAST_ADDRESS = 2047,
249
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
250
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
251
                        PORT_B_ADDRESS_CLOCK = "clock1",
252
                        PORT_B_ADDRESS_WIDTH = 11,
253
                        PORT_B_DATA_IN_CLOCK = "clock1",
254
                        PORT_B_DATA_WIDTH = 1,
255
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
256
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
257
                        PORT_B_FIRST_ADDRESS = 0,
258
                        PORT_B_FIRST_BIT_NUMBER = 6,
259
                        PORT_B_LAST_ADDRESS = 2047,
260
                        PORT_B_LOGICAL_RAM_DEPTH = 2048,
261
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
262
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
263
                        POWER_UP_UNINITIALIZED = "false",
264
                        RAM_BLOCK_TYPE = "AUTO"
265
                );
266
        ram_block2a7 : cycloneii_ram_block
267
                WITH (
268
                        CONNECTIVITY_CHECKING = "OFF",
269
                        INIT_FILE = "../ROMdata/lat9-08.mif",
270
                        INIT_FILE_LAYOUT = "port_a",
271
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
272
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
273
                        OPERATION_MODE = "bidir_dual_port",
274
                        PORT_A_ADDRESS_WIDTH = 11,
275
                        PORT_A_DATA_WIDTH = 1,
276
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "on",
277
                        PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
278
                        PORT_A_FIRST_ADDRESS = 0,
279
                        PORT_A_FIRST_BIT_NUMBER = 7,
280
                        PORT_A_LAST_ADDRESS = 2047,
281
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
282
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
283
                        PORT_B_ADDRESS_CLOCK = "clock1",
284
                        PORT_B_ADDRESS_WIDTH = 11,
285
                        PORT_B_DATA_IN_CLOCK = "clock1",
286
                        PORT_B_DATA_WIDTH = 1,
287
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "on",
288
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
289
                        PORT_B_FIRST_ADDRESS = 0,
290
                        PORT_B_FIRST_BIT_NUMBER = 7,
291
                        PORT_B_LAST_ADDRESS = 2047,
292
                        PORT_B_LOGICAL_RAM_DEPTH = 2048,
293
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
294
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
295
                        POWER_UP_UNINITIALIZED = "false",
296
                        RAM_BLOCK_TYPE = "AUTO"
297
                );
298
        address_a_wire[10..0]   : WIRE;
299
        address_b_wire[10..0]   : WIRE;
300
 
301
BEGIN
302
        ram_block2a[7..0].clk0 = clock0;
303
        ram_block2a[7..0].clk1 = clock1;
304
        ram_block2a[7..0].ena1 = clocken1;
305
        ram_block2a[7..0].portaaddr[] = ( address_a_wire[10..0]);
306
        ram_block2a[0].portadatain[] = ( data_a[0..0]);
307
        ram_block2a[1].portadatain[] = ( data_a[1..1]);
308
        ram_block2a[2].portadatain[] = ( data_a[2..2]);
309
        ram_block2a[3].portadatain[] = ( data_a[3..3]);
310
        ram_block2a[4].portadatain[] = ( data_a[4..4]);
311
        ram_block2a[5].portadatain[] = ( data_a[5..5]);
312
        ram_block2a[6].portadatain[] = ( data_a[6..6]);
313
        ram_block2a[7].portadatain[] = ( data_a[7..7]);
314
        ram_block2a[7..0].portawe = wren_a;
315
        ram_block2a[7..0].portbaddr[] = ( address_b_wire[10..0]);
316
        ram_block2a[0].portbdatain[] = ( data_b[0..0]);
317
        ram_block2a[1].portbdatain[] = ( data_b[1..1]);
318
        ram_block2a[2].portbdatain[] = ( data_b[2..2]);
319
        ram_block2a[3].portbdatain[] = ( data_b[3..3]);
320
        ram_block2a[4].portbdatain[] = ( data_b[4..4]);
321
        ram_block2a[5].portbdatain[] = ( data_b[5..5]);
322
        ram_block2a[6].portbdatain[] = ( data_b[6..6]);
323
        ram_block2a[7].portbdatain[] = ( data_b[7..7]);
324
        ram_block2a[7..0].portbrewe = wren_b;
325
        address_a_wire[] = address_a[];
326
        address_b_wire[] = address_b[];
327
        q_a[] = ( ram_block2a[7..0].portadataout[0..0]);
328
        q_b[] = ( ram_block2a[7..0].portbdataout[0..0]);
329
END;
330
--VALID FILE

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