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[/] [z80soc/] [trunk/] [V0.7.3/] [DE1/] [db/] [altsyncram_oal1.tdf] - Blame information for rev 46

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1 46 rrred
--altsyncram ADDRESS_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_INPUT_B="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_B="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" LOW_POWER_MODE="AUTO" NUMWORDS_A=6143 NUMWORDS_B=6143 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" POWER_UP_UNINITIALIZED="FALSE" WIDTH_A=8 WIDTH_B=8 WIDTH_BYTEENA_A=1 WIDTHAD_A=13 WIDTHAD_B=13 address_a address_b clock0 clock1 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
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--VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ  VERSION_END
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-- Copyright (C) 1991-2013 Altera Corporation
6
--  Your use of Altera Corporation's design tools, logic functions
7
--  and other software and tools, and its AMPP partner logic
8
--  functions, and any output files from any of the foregoing
9
--  (including device programming or simulation files), and any
10
--  associated documentation or information are expressly subject
11
--  to the terms and conditions of the Altera Program License
12
--  Subscription Agreement, Altera MegaCore Function License
13
--  Agreement, or other applicable license agreement, including,
14
--  without limitation, that your use is for the sole purpose of
15
--  programming logic devices manufactured by Altera and sold by
16
--  Altera or its authorized distributors.  Please refer to the
17
--  applicable agreement for further details.
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FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
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WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
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RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
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--synthesis_resources = M9K 8
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OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
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27
SUBDESIGN altsyncram_oal1
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(
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        address_a[12..0]        :       input;
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        address_b[12..0]        :       input;
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        clock0  :       input;
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        clock1  :       input;
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        data_a[7..0]    :       input;
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        q_b[7..0]       :       output;
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        wren_a  :       input;
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)
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VARIABLE
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        ram_block1a0 : cycloneive_ram_block
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                WITH (
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                        CLK0_CORE_CLOCK_ENABLE = "ena0",
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                        CLK0_INPUT_CLOCK_ENABLE = "none",
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                        CLK1_CORE_CLOCK_ENABLE = "none",
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                        CLK1_INPUT_CLOCK_ENABLE = "none",
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                        CONNECTIVITY_CHECKING = "OFF",
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                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
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                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
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                        OPERATION_MODE = "dual_port",
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                        PORT_A_ADDRESS_WIDTH = 13,
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                        PORT_A_DATA_WIDTH = 1,
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                        PORT_A_FIRST_ADDRESS = 0,
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                        PORT_A_FIRST_BIT_NUMBER = 0,
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                        PORT_A_LAST_ADDRESS = 6142,
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                        PORT_A_LOGICAL_RAM_DEPTH = 6143,
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                        PORT_A_LOGICAL_RAM_WIDTH = 8,
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                        PORT_B_ADDRESS_CLEAR = "none",
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                        PORT_B_ADDRESS_CLOCK = "clock1",
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                        PORT_B_ADDRESS_WIDTH = 13,
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                        PORT_B_DATA_OUT_CLEAR = "none",
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                        PORT_B_DATA_WIDTH = 1,
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                        PORT_B_FIRST_ADDRESS = 0,
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                        PORT_B_FIRST_BIT_NUMBER = 0,
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                        PORT_B_LAST_ADDRESS = 6142,
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                        PORT_B_LOGICAL_RAM_DEPTH = 6143,
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                        PORT_B_LOGICAL_RAM_WIDTH = 8,
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                        PORT_B_READ_ENABLE_CLOCK = "clock1",
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                        POWER_UP_UNINITIALIZED = "false",
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                        RAM_BLOCK_TYPE = "AUTO"
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                );
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        ram_block1a1 : cycloneive_ram_block
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                WITH (
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                        CLK0_CORE_CLOCK_ENABLE = "ena0",
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                        CLK0_INPUT_CLOCK_ENABLE = "none",
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                        CLK1_CORE_CLOCK_ENABLE = "none",
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                        CLK1_INPUT_CLOCK_ENABLE = "none",
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                        CONNECTIVITY_CHECKING = "OFF",
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                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
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                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
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                        OPERATION_MODE = "dual_port",
79
                        PORT_A_ADDRESS_WIDTH = 13,
80
                        PORT_A_DATA_WIDTH = 1,
81
                        PORT_A_FIRST_ADDRESS = 0,
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                        PORT_A_FIRST_BIT_NUMBER = 1,
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                        PORT_A_LAST_ADDRESS = 6142,
84
                        PORT_A_LOGICAL_RAM_DEPTH = 6143,
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                        PORT_A_LOGICAL_RAM_WIDTH = 8,
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                        PORT_B_ADDRESS_CLEAR = "none",
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                        PORT_B_ADDRESS_CLOCK = "clock1",
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                        PORT_B_ADDRESS_WIDTH = 13,
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                        PORT_B_DATA_OUT_CLEAR = "none",
90
                        PORT_B_DATA_WIDTH = 1,
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                        PORT_B_FIRST_ADDRESS = 0,
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                        PORT_B_FIRST_BIT_NUMBER = 1,
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                        PORT_B_LAST_ADDRESS = 6142,
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                        PORT_B_LOGICAL_RAM_DEPTH = 6143,
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                        PORT_B_LOGICAL_RAM_WIDTH = 8,
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                        PORT_B_READ_ENABLE_CLOCK = "clock1",
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                        POWER_UP_UNINITIALIZED = "false",
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                        RAM_BLOCK_TYPE = "AUTO"
99
                );
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        ram_block1a2 : cycloneive_ram_block
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                WITH (
102
                        CLK0_CORE_CLOCK_ENABLE = "ena0",
103
                        CLK0_INPUT_CLOCK_ENABLE = "none",
104
                        CLK1_CORE_CLOCK_ENABLE = "none",
105
                        CLK1_INPUT_CLOCK_ENABLE = "none",
106
                        CONNECTIVITY_CHECKING = "OFF",
107
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
108
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
109
                        OPERATION_MODE = "dual_port",
110
                        PORT_A_ADDRESS_WIDTH = 13,
111
                        PORT_A_DATA_WIDTH = 1,
112
                        PORT_A_FIRST_ADDRESS = 0,
113
                        PORT_A_FIRST_BIT_NUMBER = 2,
114
                        PORT_A_LAST_ADDRESS = 6142,
115
                        PORT_A_LOGICAL_RAM_DEPTH = 6143,
116
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
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                        PORT_B_ADDRESS_CLEAR = "none",
118
                        PORT_B_ADDRESS_CLOCK = "clock1",
119
                        PORT_B_ADDRESS_WIDTH = 13,
120
                        PORT_B_DATA_OUT_CLEAR = "none",
121
                        PORT_B_DATA_WIDTH = 1,
122
                        PORT_B_FIRST_ADDRESS = 0,
123
                        PORT_B_FIRST_BIT_NUMBER = 2,
124
                        PORT_B_LAST_ADDRESS = 6142,
125
                        PORT_B_LOGICAL_RAM_DEPTH = 6143,
126
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
127
                        PORT_B_READ_ENABLE_CLOCK = "clock1",
128
                        POWER_UP_UNINITIALIZED = "false",
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                        RAM_BLOCK_TYPE = "AUTO"
130
                );
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        ram_block1a3 : cycloneive_ram_block
132
                WITH (
133
                        CLK0_CORE_CLOCK_ENABLE = "ena0",
134
                        CLK0_INPUT_CLOCK_ENABLE = "none",
135
                        CLK1_CORE_CLOCK_ENABLE = "none",
136
                        CLK1_INPUT_CLOCK_ENABLE = "none",
137
                        CONNECTIVITY_CHECKING = "OFF",
138
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
139
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
140
                        OPERATION_MODE = "dual_port",
141
                        PORT_A_ADDRESS_WIDTH = 13,
142
                        PORT_A_DATA_WIDTH = 1,
143
                        PORT_A_FIRST_ADDRESS = 0,
144
                        PORT_A_FIRST_BIT_NUMBER = 3,
145
                        PORT_A_LAST_ADDRESS = 6142,
146
                        PORT_A_LOGICAL_RAM_DEPTH = 6143,
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                        PORT_A_LOGICAL_RAM_WIDTH = 8,
148
                        PORT_B_ADDRESS_CLEAR = "none",
149
                        PORT_B_ADDRESS_CLOCK = "clock1",
150
                        PORT_B_ADDRESS_WIDTH = 13,
151
                        PORT_B_DATA_OUT_CLEAR = "none",
152
                        PORT_B_DATA_WIDTH = 1,
153
                        PORT_B_FIRST_ADDRESS = 0,
154
                        PORT_B_FIRST_BIT_NUMBER = 3,
155
                        PORT_B_LAST_ADDRESS = 6142,
156
                        PORT_B_LOGICAL_RAM_DEPTH = 6143,
157
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
158
                        PORT_B_READ_ENABLE_CLOCK = "clock1",
159
                        POWER_UP_UNINITIALIZED = "false",
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                        RAM_BLOCK_TYPE = "AUTO"
161
                );
162
        ram_block1a4 : cycloneive_ram_block
163
                WITH (
164
                        CLK0_CORE_CLOCK_ENABLE = "ena0",
165
                        CLK0_INPUT_CLOCK_ENABLE = "none",
166
                        CLK1_CORE_CLOCK_ENABLE = "none",
167
                        CLK1_INPUT_CLOCK_ENABLE = "none",
168
                        CONNECTIVITY_CHECKING = "OFF",
169
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
170
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
171
                        OPERATION_MODE = "dual_port",
172
                        PORT_A_ADDRESS_WIDTH = 13,
173
                        PORT_A_DATA_WIDTH = 1,
174
                        PORT_A_FIRST_ADDRESS = 0,
175
                        PORT_A_FIRST_BIT_NUMBER = 4,
176
                        PORT_A_LAST_ADDRESS = 6142,
177
                        PORT_A_LOGICAL_RAM_DEPTH = 6143,
178
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
179
                        PORT_B_ADDRESS_CLEAR = "none",
180
                        PORT_B_ADDRESS_CLOCK = "clock1",
181
                        PORT_B_ADDRESS_WIDTH = 13,
182
                        PORT_B_DATA_OUT_CLEAR = "none",
183
                        PORT_B_DATA_WIDTH = 1,
184
                        PORT_B_FIRST_ADDRESS = 0,
185
                        PORT_B_FIRST_BIT_NUMBER = 4,
186
                        PORT_B_LAST_ADDRESS = 6142,
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                        PORT_B_LOGICAL_RAM_DEPTH = 6143,
188
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
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                        PORT_B_READ_ENABLE_CLOCK = "clock1",
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                        POWER_UP_UNINITIALIZED = "false",
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                        RAM_BLOCK_TYPE = "AUTO"
192
                );
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        ram_block1a5 : cycloneive_ram_block
194
                WITH (
195
                        CLK0_CORE_CLOCK_ENABLE = "ena0",
196
                        CLK0_INPUT_CLOCK_ENABLE = "none",
197
                        CLK1_CORE_CLOCK_ENABLE = "none",
198
                        CLK1_INPUT_CLOCK_ENABLE = "none",
199
                        CONNECTIVITY_CHECKING = "OFF",
200
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
201
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
202
                        OPERATION_MODE = "dual_port",
203
                        PORT_A_ADDRESS_WIDTH = 13,
204
                        PORT_A_DATA_WIDTH = 1,
205
                        PORT_A_FIRST_ADDRESS = 0,
206
                        PORT_A_FIRST_BIT_NUMBER = 5,
207
                        PORT_A_LAST_ADDRESS = 6142,
208
                        PORT_A_LOGICAL_RAM_DEPTH = 6143,
209
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
210
                        PORT_B_ADDRESS_CLEAR = "none",
211
                        PORT_B_ADDRESS_CLOCK = "clock1",
212
                        PORT_B_ADDRESS_WIDTH = 13,
213
                        PORT_B_DATA_OUT_CLEAR = "none",
214
                        PORT_B_DATA_WIDTH = 1,
215
                        PORT_B_FIRST_ADDRESS = 0,
216
                        PORT_B_FIRST_BIT_NUMBER = 5,
217
                        PORT_B_LAST_ADDRESS = 6142,
218
                        PORT_B_LOGICAL_RAM_DEPTH = 6143,
219
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
220
                        PORT_B_READ_ENABLE_CLOCK = "clock1",
221
                        POWER_UP_UNINITIALIZED = "false",
222
                        RAM_BLOCK_TYPE = "AUTO"
223
                );
224
        ram_block1a6 : cycloneive_ram_block
225
                WITH (
226
                        CLK0_CORE_CLOCK_ENABLE = "ena0",
227
                        CLK0_INPUT_CLOCK_ENABLE = "none",
228
                        CLK1_CORE_CLOCK_ENABLE = "none",
229
                        CLK1_INPUT_CLOCK_ENABLE = "none",
230
                        CONNECTIVITY_CHECKING = "OFF",
231
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
232
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
233
                        OPERATION_MODE = "dual_port",
234
                        PORT_A_ADDRESS_WIDTH = 13,
235
                        PORT_A_DATA_WIDTH = 1,
236
                        PORT_A_FIRST_ADDRESS = 0,
237
                        PORT_A_FIRST_BIT_NUMBER = 6,
238
                        PORT_A_LAST_ADDRESS = 6142,
239
                        PORT_A_LOGICAL_RAM_DEPTH = 6143,
240
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
241
                        PORT_B_ADDRESS_CLEAR = "none",
242
                        PORT_B_ADDRESS_CLOCK = "clock1",
243
                        PORT_B_ADDRESS_WIDTH = 13,
244
                        PORT_B_DATA_OUT_CLEAR = "none",
245
                        PORT_B_DATA_WIDTH = 1,
246
                        PORT_B_FIRST_ADDRESS = 0,
247
                        PORT_B_FIRST_BIT_NUMBER = 6,
248
                        PORT_B_LAST_ADDRESS = 6142,
249
                        PORT_B_LOGICAL_RAM_DEPTH = 6143,
250
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
251
                        PORT_B_READ_ENABLE_CLOCK = "clock1",
252
                        POWER_UP_UNINITIALIZED = "false",
253
                        RAM_BLOCK_TYPE = "AUTO"
254
                );
255
        ram_block1a7 : cycloneive_ram_block
256
                WITH (
257
                        CLK0_CORE_CLOCK_ENABLE = "ena0",
258
                        CLK0_INPUT_CLOCK_ENABLE = "none",
259
                        CLK1_CORE_CLOCK_ENABLE = "none",
260
                        CLK1_INPUT_CLOCK_ENABLE = "none",
261
                        CONNECTIVITY_CHECKING = "OFF",
262
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
263
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
264
                        OPERATION_MODE = "dual_port",
265
                        PORT_A_ADDRESS_WIDTH = 13,
266
                        PORT_A_DATA_WIDTH = 1,
267
                        PORT_A_FIRST_ADDRESS = 0,
268
                        PORT_A_FIRST_BIT_NUMBER = 7,
269
                        PORT_A_LAST_ADDRESS = 6142,
270
                        PORT_A_LOGICAL_RAM_DEPTH = 6143,
271
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
272
                        PORT_B_ADDRESS_CLEAR = "none",
273
                        PORT_B_ADDRESS_CLOCK = "clock1",
274
                        PORT_B_ADDRESS_WIDTH = 13,
275
                        PORT_B_DATA_OUT_CLEAR = "none",
276
                        PORT_B_DATA_WIDTH = 1,
277
                        PORT_B_FIRST_ADDRESS = 0,
278
                        PORT_B_FIRST_BIT_NUMBER = 7,
279
                        PORT_B_LAST_ADDRESS = 6142,
280
                        PORT_B_LOGICAL_RAM_DEPTH = 6143,
281
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
282
                        PORT_B_READ_ENABLE_CLOCK = "clock1",
283
                        POWER_UP_UNINITIALIZED = "false",
284
                        RAM_BLOCK_TYPE = "AUTO"
285
                );
286
        address_a_wire[12..0]   : WIRE;
287
        address_b_wire[12..0]   : WIRE;
288
 
289
BEGIN
290
        ram_block1a[7..0].clk0 = clock0;
291
        ram_block1a[7..0].clk1 = clock1;
292
        ram_block1a[7..0].ena0 = wren_a;
293
        ram_block1a[7..0].portaaddr[] = ( address_a_wire[12..0]);
294
        ram_block1a[0].portadatain[] = ( data_a[0..0]);
295
        ram_block1a[1].portadatain[] = ( data_a[1..1]);
296
        ram_block1a[2].portadatain[] = ( data_a[2..2]);
297
        ram_block1a[3].portadatain[] = ( data_a[3..3]);
298
        ram_block1a[4].portadatain[] = ( data_a[4..4]);
299
        ram_block1a[5].portadatain[] = ( data_a[5..5]);
300
        ram_block1a[6].portadatain[] = ( data_a[6..6]);
301
        ram_block1a[7].portadatain[] = ( data_a[7..7]);
302
        ram_block1a[7..0].portawe = wren_a;
303
        ram_block1a[7..0].portbaddr[] = ( address_b_wire[12..0]);
304
        ram_block1a[7..0].portbre = B"11111111";
305
        address_a_wire[] = address_a[];
306
        address_b_wire[] = address_b[];
307
        q_b[] = ( ram_block1a[7..0].portbdataout[0..0]);
308
END;
309
--VALID FILE

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