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[/] [z80soc/] [trunk/] [V0.7.3/] [DE1/] [db/] [altsyncram_pal1.tdf] - Blame information for rev 46

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1 46 rrred
--altsyncram ADDRESS_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_INPUT_B="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" CYCLONEII_SAFE_WRITE="NO_CHANGE" DEVICE_FAMILY="Cyclone II" LOW_POWER_MODE="AUTO" NUMWORDS_A=6143 NUMWORDS_B=6143 OPERATION_MODE="BIDIR_DUAL_PORT" POWER_UP_UNINITIALIZED="FALSE" WIDTH_A=8 WIDTH_B=8 WIDTH_BYTEENA_A=1 WIDTH_BYTEENA_B=1 WIDTHAD_A=13 WIDTHAD_B=13 WRCONTROL_WRADDRESS_REG_B="CLOCK1" address_a address_b clock0 clock1 clocken1 data_a data_b q_a wren_a wren_b CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
2
--VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ  VERSION_END
3
 
4
 
5
-- Copyright (C) 1991-2013 Altera Corporation
6
--  Your use of Altera Corporation's design tools, logic functions
7
--  and other software and tools, and its AMPP partner logic
8
--  functions, and any output files from any of the foregoing
9
--  (including device programming or simulation files), and any
10
--  associated documentation or information are expressly subject
11
--  to the terms and conditions of the Altera Program License
12
--  Subscription Agreement, Altera MegaCore Function License
13
--  Agreement, or other applicable license agreement, including,
14
--  without limitation, that your use is for the sole purpose of
15
--  programming logic devices manufactured by Altera and sold by
16
--  Altera or its authorized distributors.  Please refer to the
17
--  applicable agreement for further details.
18
 
19
 
20
FUNCTION decode_1oa (data[0..0], enable)
21
RETURNS ( eq[1..0]);
22
FUNCTION mux_hib (data[15..0], sel[0..0])
23
RETURNS ( result[7..0]);
24
FUNCTION cycloneii_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbrewe)
25
WITH ( CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_DISABLE_CE_ON_INPUT_REGISTERS, PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_DISABLE_CE_ON_INPUT_REGISTERS, PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
26
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
27
 
28
--synthesis_resources = lut 20 M4K 12 reg 2
29
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
30
 
31
SUBDESIGN altsyncram_pal1
32
(
33
        address_a[12..0]        :       input;
34
        address_b[12..0]        :       input;
35
        clock0  :       input;
36
        clock1  :       input;
37
        clocken1        :       input;
38
        data_a[7..0]    :       input;
39
        data_b[7..0]    :       input;
40
        q_a[7..0]       :       output;
41
        q_b[7..0]       :       output;
42
        wren_a  :       input;
43
        wren_b  :       input;
44
)
45
VARIABLE
46
        address_reg_a[0..0] : dffe;
47
        address_reg_b[0..0] : dffe;
48
        decode3 : decode_1oa;
49
        decode4 : decode_1oa;
50
        decode_a : decode_1oa;
51
        decode_b : decode_1oa;
52
        mux5 : mux_hib;
53
        mux6 : mux_hib;
54
        ram_block2a0 : cycloneii_ram_block
55
                WITH (
56
                        CONNECTIVITY_CHECKING = "OFF",
57
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
58
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
59
                        OPERATION_MODE = "bidir_dual_port",
60
                        PORT_A_ADDRESS_WIDTH = 12,
61
                        PORT_A_DATA_WIDTH = 1,
62
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
63
                        PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
64
                        PORT_A_FIRST_ADDRESS = 0,
65
                        PORT_A_FIRST_BIT_NUMBER = 0,
66
                        PORT_A_LAST_ADDRESS = 4095,
67
                        PORT_A_LOGICAL_RAM_DEPTH = 6143,
68
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
69
                        PORT_B_ADDRESS_CLOCK = "clock1",
70
                        PORT_B_ADDRESS_WIDTH = 12,
71
                        PORT_B_DATA_IN_CLOCK = "clock1",
72
                        PORT_B_DATA_WIDTH = 1,
73
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
74
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
75
                        PORT_B_FIRST_ADDRESS = 0,
76
                        PORT_B_FIRST_BIT_NUMBER = 0,
77
                        PORT_B_LAST_ADDRESS = 4095,
78
                        PORT_B_LOGICAL_RAM_DEPTH = 6143,
79
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
80
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
81
                        POWER_UP_UNINITIALIZED = "false",
82
                        RAM_BLOCK_TYPE = "AUTO"
83
                );
84
        ram_block2a1 : cycloneii_ram_block
85
                WITH (
86
                        CONNECTIVITY_CHECKING = "OFF",
87
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
88
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
89
                        OPERATION_MODE = "bidir_dual_port",
90
                        PORT_A_ADDRESS_WIDTH = 12,
91
                        PORT_A_DATA_WIDTH = 1,
92
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
93
                        PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
94
                        PORT_A_FIRST_ADDRESS = 0,
95
                        PORT_A_FIRST_BIT_NUMBER = 1,
96
                        PORT_A_LAST_ADDRESS = 4095,
97
                        PORT_A_LOGICAL_RAM_DEPTH = 6143,
98
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
99
                        PORT_B_ADDRESS_CLOCK = "clock1",
100
                        PORT_B_ADDRESS_WIDTH = 12,
101
                        PORT_B_DATA_IN_CLOCK = "clock1",
102
                        PORT_B_DATA_WIDTH = 1,
103
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
104
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
105
                        PORT_B_FIRST_ADDRESS = 0,
106
                        PORT_B_FIRST_BIT_NUMBER = 1,
107
                        PORT_B_LAST_ADDRESS = 4095,
108
                        PORT_B_LOGICAL_RAM_DEPTH = 6143,
109
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
110
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
111
                        POWER_UP_UNINITIALIZED = "false",
112
                        RAM_BLOCK_TYPE = "AUTO"
113
                );
114
        ram_block2a2 : cycloneii_ram_block
115
                WITH (
116
                        CONNECTIVITY_CHECKING = "OFF",
117
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
118
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
119
                        OPERATION_MODE = "bidir_dual_port",
120
                        PORT_A_ADDRESS_WIDTH = 12,
121
                        PORT_A_DATA_WIDTH = 1,
122
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
123
                        PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
124
                        PORT_A_FIRST_ADDRESS = 0,
125
                        PORT_A_FIRST_BIT_NUMBER = 2,
126
                        PORT_A_LAST_ADDRESS = 4095,
127
                        PORT_A_LOGICAL_RAM_DEPTH = 6143,
128
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
129
                        PORT_B_ADDRESS_CLOCK = "clock1",
130
                        PORT_B_ADDRESS_WIDTH = 12,
131
                        PORT_B_DATA_IN_CLOCK = "clock1",
132
                        PORT_B_DATA_WIDTH = 1,
133
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
134
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
135
                        PORT_B_FIRST_ADDRESS = 0,
136
                        PORT_B_FIRST_BIT_NUMBER = 2,
137
                        PORT_B_LAST_ADDRESS = 4095,
138
                        PORT_B_LOGICAL_RAM_DEPTH = 6143,
139
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
140
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
141
                        POWER_UP_UNINITIALIZED = "false",
142
                        RAM_BLOCK_TYPE = "AUTO"
143
                );
144
        ram_block2a3 : cycloneii_ram_block
145
                WITH (
146
                        CONNECTIVITY_CHECKING = "OFF",
147
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
148
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
149
                        OPERATION_MODE = "bidir_dual_port",
150
                        PORT_A_ADDRESS_WIDTH = 12,
151
                        PORT_A_DATA_WIDTH = 1,
152
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
153
                        PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
154
                        PORT_A_FIRST_ADDRESS = 0,
155
                        PORT_A_FIRST_BIT_NUMBER = 3,
156
                        PORT_A_LAST_ADDRESS = 4095,
157
                        PORT_A_LOGICAL_RAM_DEPTH = 6143,
158
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
159
                        PORT_B_ADDRESS_CLOCK = "clock1",
160
                        PORT_B_ADDRESS_WIDTH = 12,
161
                        PORT_B_DATA_IN_CLOCK = "clock1",
162
                        PORT_B_DATA_WIDTH = 1,
163
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
164
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
165
                        PORT_B_FIRST_ADDRESS = 0,
166
                        PORT_B_FIRST_BIT_NUMBER = 3,
167
                        PORT_B_LAST_ADDRESS = 4095,
168
                        PORT_B_LOGICAL_RAM_DEPTH = 6143,
169
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
170
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
171
                        POWER_UP_UNINITIALIZED = "false",
172
                        RAM_BLOCK_TYPE = "AUTO"
173
                );
174
        ram_block2a4 : cycloneii_ram_block
175
                WITH (
176
                        CONNECTIVITY_CHECKING = "OFF",
177
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
178
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
179
                        OPERATION_MODE = "bidir_dual_port",
180
                        PORT_A_ADDRESS_WIDTH = 12,
181
                        PORT_A_DATA_WIDTH = 1,
182
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
183
                        PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
184
                        PORT_A_FIRST_ADDRESS = 0,
185
                        PORT_A_FIRST_BIT_NUMBER = 4,
186
                        PORT_A_LAST_ADDRESS = 4095,
187
                        PORT_A_LOGICAL_RAM_DEPTH = 6143,
188
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
189
                        PORT_B_ADDRESS_CLOCK = "clock1",
190
                        PORT_B_ADDRESS_WIDTH = 12,
191
                        PORT_B_DATA_IN_CLOCK = "clock1",
192
                        PORT_B_DATA_WIDTH = 1,
193
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
194
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
195
                        PORT_B_FIRST_ADDRESS = 0,
196
                        PORT_B_FIRST_BIT_NUMBER = 4,
197
                        PORT_B_LAST_ADDRESS = 4095,
198
                        PORT_B_LOGICAL_RAM_DEPTH = 6143,
199
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
200
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
201
                        POWER_UP_UNINITIALIZED = "false",
202
                        RAM_BLOCK_TYPE = "AUTO"
203
                );
204
        ram_block2a5 : cycloneii_ram_block
205
                WITH (
206
                        CONNECTIVITY_CHECKING = "OFF",
207
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
208
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
209
                        OPERATION_MODE = "bidir_dual_port",
210
                        PORT_A_ADDRESS_WIDTH = 12,
211
                        PORT_A_DATA_WIDTH = 1,
212
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
213
                        PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
214
                        PORT_A_FIRST_ADDRESS = 0,
215
                        PORT_A_FIRST_BIT_NUMBER = 5,
216
                        PORT_A_LAST_ADDRESS = 4095,
217
                        PORT_A_LOGICAL_RAM_DEPTH = 6143,
218
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
219
                        PORT_B_ADDRESS_CLOCK = "clock1",
220
                        PORT_B_ADDRESS_WIDTH = 12,
221
                        PORT_B_DATA_IN_CLOCK = "clock1",
222
                        PORT_B_DATA_WIDTH = 1,
223
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
224
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
225
                        PORT_B_FIRST_ADDRESS = 0,
226
                        PORT_B_FIRST_BIT_NUMBER = 5,
227
                        PORT_B_LAST_ADDRESS = 4095,
228
                        PORT_B_LOGICAL_RAM_DEPTH = 6143,
229
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
230
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
231
                        POWER_UP_UNINITIALIZED = "false",
232
                        RAM_BLOCK_TYPE = "AUTO"
233
                );
234
        ram_block2a6 : cycloneii_ram_block
235
                WITH (
236
                        CONNECTIVITY_CHECKING = "OFF",
237
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
238
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
239
                        OPERATION_MODE = "bidir_dual_port",
240
                        PORT_A_ADDRESS_WIDTH = 12,
241
                        PORT_A_DATA_WIDTH = 1,
242
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
243
                        PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
244
                        PORT_A_FIRST_ADDRESS = 0,
245
                        PORT_A_FIRST_BIT_NUMBER = 6,
246
                        PORT_A_LAST_ADDRESS = 4095,
247
                        PORT_A_LOGICAL_RAM_DEPTH = 6143,
248
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
249
                        PORT_B_ADDRESS_CLOCK = "clock1",
250
                        PORT_B_ADDRESS_WIDTH = 12,
251
                        PORT_B_DATA_IN_CLOCK = "clock1",
252
                        PORT_B_DATA_WIDTH = 1,
253
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
254
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
255
                        PORT_B_FIRST_ADDRESS = 0,
256
                        PORT_B_FIRST_BIT_NUMBER = 6,
257
                        PORT_B_LAST_ADDRESS = 4095,
258
                        PORT_B_LOGICAL_RAM_DEPTH = 6143,
259
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
260
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
261
                        POWER_UP_UNINITIALIZED = "false",
262
                        RAM_BLOCK_TYPE = "AUTO"
263
                );
264
        ram_block2a7 : cycloneii_ram_block
265
                WITH (
266
                        CONNECTIVITY_CHECKING = "OFF",
267
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
268
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
269
                        OPERATION_MODE = "bidir_dual_port",
270
                        PORT_A_ADDRESS_WIDTH = 12,
271
                        PORT_A_DATA_WIDTH = 1,
272
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
273
                        PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
274
                        PORT_A_FIRST_ADDRESS = 0,
275
                        PORT_A_FIRST_BIT_NUMBER = 7,
276
                        PORT_A_LAST_ADDRESS = 4095,
277
                        PORT_A_LOGICAL_RAM_DEPTH = 6143,
278
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
279
                        PORT_B_ADDRESS_CLOCK = "clock1",
280
                        PORT_B_ADDRESS_WIDTH = 12,
281
                        PORT_B_DATA_IN_CLOCK = "clock1",
282
                        PORT_B_DATA_WIDTH = 1,
283
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
284
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
285
                        PORT_B_FIRST_ADDRESS = 0,
286
                        PORT_B_FIRST_BIT_NUMBER = 7,
287
                        PORT_B_LAST_ADDRESS = 4095,
288
                        PORT_B_LOGICAL_RAM_DEPTH = 6143,
289
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
290
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
291
                        POWER_UP_UNINITIALIZED = "false",
292
                        RAM_BLOCK_TYPE = "AUTO"
293
                );
294
        ram_block2a8 : cycloneii_ram_block
295
                WITH (
296
                        CONNECTIVITY_CHECKING = "OFF",
297
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
298
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
299
                        OPERATION_MODE = "bidir_dual_port",
300
                        PORT_A_ADDRESS_WIDTH = 11,
301
                        PORT_A_DATA_WIDTH = 1,
302
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
303
                        PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
304
                        PORT_A_FIRST_ADDRESS = 4096,
305
                        PORT_A_FIRST_BIT_NUMBER = 0,
306
                        PORT_A_LAST_ADDRESS = 6142,
307
                        PORT_A_LOGICAL_RAM_DEPTH = 6143,
308
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
309
                        PORT_B_ADDRESS_CLOCK = "clock1",
310
                        PORT_B_ADDRESS_WIDTH = 11,
311
                        PORT_B_DATA_IN_CLOCK = "clock1",
312
                        PORT_B_DATA_WIDTH = 1,
313
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
314
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
315
                        PORT_B_FIRST_ADDRESS = 4096,
316
                        PORT_B_FIRST_BIT_NUMBER = 0,
317
                        PORT_B_LAST_ADDRESS = 6142,
318
                        PORT_B_LOGICAL_RAM_DEPTH = 6143,
319
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
320
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
321
                        POWER_UP_UNINITIALIZED = "false",
322
                        RAM_BLOCK_TYPE = "AUTO"
323
                );
324
        ram_block2a9 : cycloneii_ram_block
325
                WITH (
326
                        CONNECTIVITY_CHECKING = "OFF",
327
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
328
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
329
                        OPERATION_MODE = "bidir_dual_port",
330
                        PORT_A_ADDRESS_WIDTH = 11,
331
                        PORT_A_DATA_WIDTH = 1,
332
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
333
                        PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
334
                        PORT_A_FIRST_ADDRESS = 4096,
335
                        PORT_A_FIRST_BIT_NUMBER = 1,
336
                        PORT_A_LAST_ADDRESS = 6142,
337
                        PORT_A_LOGICAL_RAM_DEPTH = 6143,
338
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
339
                        PORT_B_ADDRESS_CLOCK = "clock1",
340
                        PORT_B_ADDRESS_WIDTH = 11,
341
                        PORT_B_DATA_IN_CLOCK = "clock1",
342
                        PORT_B_DATA_WIDTH = 1,
343
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
344
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
345
                        PORT_B_FIRST_ADDRESS = 4096,
346
                        PORT_B_FIRST_BIT_NUMBER = 1,
347
                        PORT_B_LAST_ADDRESS = 6142,
348
                        PORT_B_LOGICAL_RAM_DEPTH = 6143,
349
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
350
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
351
                        POWER_UP_UNINITIALIZED = "false",
352
                        RAM_BLOCK_TYPE = "AUTO"
353
                );
354
        ram_block2a10 : cycloneii_ram_block
355
                WITH (
356
                        CONNECTIVITY_CHECKING = "OFF",
357
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
358
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
359
                        OPERATION_MODE = "bidir_dual_port",
360
                        PORT_A_ADDRESS_WIDTH = 11,
361
                        PORT_A_DATA_WIDTH = 1,
362
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
363
                        PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
364
                        PORT_A_FIRST_ADDRESS = 4096,
365
                        PORT_A_FIRST_BIT_NUMBER = 2,
366
                        PORT_A_LAST_ADDRESS = 6142,
367
                        PORT_A_LOGICAL_RAM_DEPTH = 6143,
368
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
369
                        PORT_B_ADDRESS_CLOCK = "clock1",
370
                        PORT_B_ADDRESS_WIDTH = 11,
371
                        PORT_B_DATA_IN_CLOCK = "clock1",
372
                        PORT_B_DATA_WIDTH = 1,
373
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
374
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
375
                        PORT_B_FIRST_ADDRESS = 4096,
376
                        PORT_B_FIRST_BIT_NUMBER = 2,
377
                        PORT_B_LAST_ADDRESS = 6142,
378
                        PORT_B_LOGICAL_RAM_DEPTH = 6143,
379
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
380
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
381
                        POWER_UP_UNINITIALIZED = "false",
382
                        RAM_BLOCK_TYPE = "AUTO"
383
                );
384
        ram_block2a11 : cycloneii_ram_block
385
                WITH (
386
                        CONNECTIVITY_CHECKING = "OFF",
387
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
388
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
389
                        OPERATION_MODE = "bidir_dual_port",
390
                        PORT_A_ADDRESS_WIDTH = 11,
391
                        PORT_A_DATA_WIDTH = 1,
392
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
393
                        PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
394
                        PORT_A_FIRST_ADDRESS = 4096,
395
                        PORT_A_FIRST_BIT_NUMBER = 3,
396
                        PORT_A_LAST_ADDRESS = 6142,
397
                        PORT_A_LOGICAL_RAM_DEPTH = 6143,
398
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
399
                        PORT_B_ADDRESS_CLOCK = "clock1",
400
                        PORT_B_ADDRESS_WIDTH = 11,
401
                        PORT_B_DATA_IN_CLOCK = "clock1",
402
                        PORT_B_DATA_WIDTH = 1,
403
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
404
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
405
                        PORT_B_FIRST_ADDRESS = 4096,
406
                        PORT_B_FIRST_BIT_NUMBER = 3,
407
                        PORT_B_LAST_ADDRESS = 6142,
408
                        PORT_B_LOGICAL_RAM_DEPTH = 6143,
409
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
410
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
411
                        POWER_UP_UNINITIALIZED = "false",
412
                        RAM_BLOCK_TYPE = "AUTO"
413
                );
414
        ram_block2a12 : cycloneii_ram_block
415
                WITH (
416
                        CONNECTIVITY_CHECKING = "OFF",
417
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
418
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
419
                        OPERATION_MODE = "bidir_dual_port",
420
                        PORT_A_ADDRESS_WIDTH = 11,
421
                        PORT_A_DATA_WIDTH = 1,
422
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
423
                        PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
424
                        PORT_A_FIRST_ADDRESS = 4096,
425
                        PORT_A_FIRST_BIT_NUMBER = 4,
426
                        PORT_A_LAST_ADDRESS = 6142,
427
                        PORT_A_LOGICAL_RAM_DEPTH = 6143,
428
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
429
                        PORT_B_ADDRESS_CLOCK = "clock1",
430
                        PORT_B_ADDRESS_WIDTH = 11,
431
                        PORT_B_DATA_IN_CLOCK = "clock1",
432
                        PORT_B_DATA_WIDTH = 1,
433
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
434
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
435
                        PORT_B_FIRST_ADDRESS = 4096,
436
                        PORT_B_FIRST_BIT_NUMBER = 4,
437
                        PORT_B_LAST_ADDRESS = 6142,
438
                        PORT_B_LOGICAL_RAM_DEPTH = 6143,
439
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
440
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
441
                        POWER_UP_UNINITIALIZED = "false",
442
                        RAM_BLOCK_TYPE = "AUTO"
443
                );
444
        ram_block2a13 : cycloneii_ram_block
445
                WITH (
446
                        CONNECTIVITY_CHECKING = "OFF",
447
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
448
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
449
                        OPERATION_MODE = "bidir_dual_port",
450
                        PORT_A_ADDRESS_WIDTH = 11,
451
                        PORT_A_DATA_WIDTH = 1,
452
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
453
                        PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
454
                        PORT_A_FIRST_ADDRESS = 4096,
455
                        PORT_A_FIRST_BIT_NUMBER = 5,
456
                        PORT_A_LAST_ADDRESS = 6142,
457
                        PORT_A_LOGICAL_RAM_DEPTH = 6143,
458
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
459
                        PORT_B_ADDRESS_CLOCK = "clock1",
460
                        PORT_B_ADDRESS_WIDTH = 11,
461
                        PORT_B_DATA_IN_CLOCK = "clock1",
462
                        PORT_B_DATA_WIDTH = 1,
463
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
464
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
465
                        PORT_B_FIRST_ADDRESS = 4096,
466
                        PORT_B_FIRST_BIT_NUMBER = 5,
467
                        PORT_B_LAST_ADDRESS = 6142,
468
                        PORT_B_LOGICAL_RAM_DEPTH = 6143,
469
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
470
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
471
                        POWER_UP_UNINITIALIZED = "false",
472
                        RAM_BLOCK_TYPE = "AUTO"
473
                );
474
        ram_block2a14 : cycloneii_ram_block
475
                WITH (
476
                        CONNECTIVITY_CHECKING = "OFF",
477
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
478
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
479
                        OPERATION_MODE = "bidir_dual_port",
480
                        PORT_A_ADDRESS_WIDTH = 11,
481
                        PORT_A_DATA_WIDTH = 1,
482
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
483
                        PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
484
                        PORT_A_FIRST_ADDRESS = 4096,
485
                        PORT_A_FIRST_BIT_NUMBER = 6,
486
                        PORT_A_LAST_ADDRESS = 6142,
487
                        PORT_A_LOGICAL_RAM_DEPTH = 6143,
488
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
489
                        PORT_B_ADDRESS_CLOCK = "clock1",
490
                        PORT_B_ADDRESS_WIDTH = 11,
491
                        PORT_B_DATA_IN_CLOCK = "clock1",
492
                        PORT_B_DATA_WIDTH = 1,
493
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
494
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
495
                        PORT_B_FIRST_ADDRESS = 4096,
496
                        PORT_B_FIRST_BIT_NUMBER = 6,
497
                        PORT_B_LAST_ADDRESS = 6142,
498
                        PORT_B_LOGICAL_RAM_DEPTH = 6143,
499
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
500
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
501
                        POWER_UP_UNINITIALIZED = "false",
502
                        RAM_BLOCK_TYPE = "AUTO"
503
                );
504
        ram_block2a15 : cycloneii_ram_block
505
                WITH (
506
                        CONNECTIVITY_CHECKING = "OFF",
507
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
508
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
509
                        OPERATION_MODE = "bidir_dual_port",
510
                        PORT_A_ADDRESS_WIDTH = 11,
511
                        PORT_A_DATA_WIDTH = 1,
512
                        PORT_A_DISABLE_CE_ON_INPUT_REGISTERS = "off",
513
                        PORT_A_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
514
                        PORT_A_FIRST_ADDRESS = 4096,
515
                        PORT_A_FIRST_BIT_NUMBER = 7,
516
                        PORT_A_LAST_ADDRESS = 6142,
517
                        PORT_A_LOGICAL_RAM_DEPTH = 6143,
518
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
519
                        PORT_B_ADDRESS_CLOCK = "clock1",
520
                        PORT_B_ADDRESS_WIDTH = 11,
521
                        PORT_B_DATA_IN_CLOCK = "clock1",
522
                        PORT_B_DATA_WIDTH = 1,
523
                        PORT_B_DISABLE_CE_ON_INPUT_REGISTERS = "off",
524
                        PORT_B_DISABLE_CE_ON_OUTPUT_REGISTERS = "on",
525
                        PORT_B_FIRST_ADDRESS = 4096,
526
                        PORT_B_FIRST_BIT_NUMBER = 7,
527
                        PORT_B_LAST_ADDRESS = 6142,
528
                        PORT_B_LOGICAL_RAM_DEPTH = 6143,
529
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
530
                        PORT_B_READ_ENABLE_WRITE_ENABLE_CLOCK = "clock1",
531
                        POWER_UP_UNINITIALIZED = "false",
532
                        RAM_BLOCK_TYPE = "AUTO"
533
                );
534
        address_a_sel[0..0]     : WIRE;
535
        address_a_wire[12..0]   : WIRE;
536
        address_b_sel[0..0]     : WIRE;
537
        address_b_wire[12..0]   : WIRE;
538
 
539
BEGIN
540
        address_reg_a[].clk = clock0;
541
        address_reg_a[].d = address_a_sel[];
542
        address_reg_b[].clk = clock1;
543
        address_reg_b[].d = address_b_sel[];
544
        decode3.data[0..0] = address_a_wire[12..12];
545
        decode3.enable = wren_a;
546
        decode4.data[0..0] = address_b_wire[12..12];
547
        decode4.enable = wren_b;
548
        decode_a.data[0..0] = address_a_wire[12..12];
549
        decode_a.enable = B"1";
550
        decode_b.data[0..0] = address_b_wire[12..12];
551
        decode_b.enable = B"1";
552
        mux5.data[] = ( ram_block2a[15..0].portadataout[0..0]);
553
        mux5.sel[] = address_reg_a[].q;
554
        mux6.data[] = ( ram_block2a[15..0].portbdataout[0..0]);
555
        mux6.sel[] = address_reg_b[].q;
556
        ram_block2a[15..0].clk0 = clock0;
557
        ram_block2a[15..0].clk1 = clock1;
558
        ram_block2a[15..0].ena0 = ( decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..1], decode_a.eq[1..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0], decode_a.eq[0..0]);
559
        ram_block2a[15..0].ena1 = ( decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..1], decode_b.eq[1..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0], decode_b.eq[0..0]);
560
        ram_block2a[7..0].portaaddr[] = ( address_a_wire[11..0]);
561
        ram_block2a[15..8].portaaddr[] = ( address_a_wire[10..0]);
562
        ram_block2a[0].portadatain[] = ( data_a[0..0]);
563
        ram_block2a[1].portadatain[] = ( data_a[1..1]);
564
        ram_block2a[2].portadatain[] = ( data_a[2..2]);
565
        ram_block2a[3].portadatain[] = ( data_a[3..3]);
566
        ram_block2a[4].portadatain[] = ( data_a[4..4]);
567
        ram_block2a[5].portadatain[] = ( data_a[5..5]);
568
        ram_block2a[6].portadatain[] = ( data_a[6..6]);
569
        ram_block2a[7].portadatain[] = ( data_a[7..7]);
570
        ram_block2a[8].portadatain[] = ( data_a[0..0]);
571
        ram_block2a[9].portadatain[] = ( data_a[1..1]);
572
        ram_block2a[10].portadatain[] = ( data_a[2..2]);
573
        ram_block2a[11].portadatain[] = ( data_a[3..3]);
574
        ram_block2a[12].portadatain[] = ( data_a[4..4]);
575
        ram_block2a[13].portadatain[] = ( data_a[5..5]);
576
        ram_block2a[14].portadatain[] = ( data_a[6..6]);
577
        ram_block2a[15].portadatain[] = ( data_a[7..7]);
578
        ram_block2a[15..0].portawe = ( decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..1], decode3.eq[1..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0], decode3.eq[0..0]);
579
        ram_block2a[7..0].portbaddr[] = ( address_b_wire[11..0]);
580
        ram_block2a[15..8].portbaddr[] = ( address_b_wire[10..0]);
581
        ram_block2a[0].portbdatain[] = ( data_b[0..0]);
582
        ram_block2a[1].portbdatain[] = ( data_b[1..1]);
583
        ram_block2a[2].portbdatain[] = ( data_b[2..2]);
584
        ram_block2a[3].portbdatain[] = ( data_b[3..3]);
585
        ram_block2a[4].portbdatain[] = ( data_b[4..4]);
586
        ram_block2a[5].portbdatain[] = ( data_b[5..5]);
587
        ram_block2a[6].portbdatain[] = ( data_b[6..6]);
588
        ram_block2a[7].portbdatain[] = ( data_b[7..7]);
589
        ram_block2a[8].portbdatain[] = ( data_b[0..0]);
590
        ram_block2a[9].portbdatain[] = ( data_b[1..1]);
591
        ram_block2a[10].portbdatain[] = ( data_b[2..2]);
592
        ram_block2a[11].portbdatain[] = ( data_b[3..3]);
593
        ram_block2a[12].portbdatain[] = ( data_b[4..4]);
594
        ram_block2a[13].portbdatain[] = ( data_b[5..5]);
595
        ram_block2a[14].portbdatain[] = ( data_b[6..6]);
596
        ram_block2a[15].portbdatain[] = ( data_b[7..7]);
597
        ram_block2a[15..0].portbrewe = ( decode4.eq[1..1], decode4.eq[1..1], decode4.eq[1..1], decode4.eq[1..1], decode4.eq[1..1], decode4.eq[1..1], decode4.eq[1..1], decode4.eq[1..0], decode4.eq[0..0], decode4.eq[0..0], decode4.eq[0..0], decode4.eq[0..0], decode4.eq[0..0], decode4.eq[0..0], decode4.eq[0..0]);
598
        address_a_sel[0..0] = address_a[12..12];
599
        address_a_wire[] = address_a[];
600
        address_b_sel[0..0] = address_b[12..12];
601
        address_b_wire[] = address_b[];
602
        q_a[] = mux5.result[];
603
        q_b[] = mux6.result[];
604
END;
605
--VALID FILE

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