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[/] [z80soc/] [trunk/] [V0.7.3/] [DE1/] [db/] [mux_kib.tdf] - Blame information for rev 46

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1 46 rrred
--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" LPM_SIZE=4 LPM_WIDTH=8 LPM_WIDTHS=2 data result sel
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--VERSION_BEGIN 13.0 cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ  VERSION_END
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-- Copyright (C) 1991-2013 Altera Corporation
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--  Your use of Altera Corporation's design tools, logic functions
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--  and other software and tools, and its AMPP partner logic
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--  functions, and any output files from any of the foregoing
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--  (including device programming or simulation files), and any
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--  associated documentation or information are expressly subject
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--  to the terms and conditions of the Altera Program License
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--  Subscription Agreement, Altera MegaCore Function License
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--  Agreement, or other applicable license agreement, including,
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--  without limitation, that your use is for the sole purpose of
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--  programming logic devices manufactured by Altera and sold by
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--  Altera or its authorized distributors.  Please refer to the
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--  applicable agreement for further details.
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--synthesis_resources = lut 16
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SUBDESIGN mux_kib
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(
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        data[31..0]     :       input;
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        result[7..0]    :       output;
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        sel[1..0]       :       input;
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)
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VARIABLE
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        result_node[7..0]       : WIRE;
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        sel_node[1..0]  : WIRE;
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        w_data182w[3..0]        : WIRE;
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        w_data212w[3..0]        : WIRE;
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        w_data237w[3..0]        : WIRE;
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        w_data262w[3..0]        : WIRE;
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        w_data287w[3..0]        : WIRE;
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        w_data312w[3..0]        : WIRE;
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        w_data337w[3..0]        : WIRE;
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        w_data362w[3..0]        : WIRE;
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BEGIN
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        result[] = result_node[];
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        result_node[] = ( (((w_data362w[1..1] & sel_node[0..0]) & (! (((w_data362w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data362w[2..2]))))) # ((((w_data362w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data362w[2..2]))) & (w_data362w[3..3] # (! sel_node[0..0])))), (((w_data337w[1..1] & sel_node[0..0]) & (! (((w_data337w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data337w[2..2]))))) # ((((w_data337w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data337w[2..2]))) & (w_data337w[3..3] # (! sel_node[0..0])))), (((w_data312w[1..1] & sel_node[0..0]) & (! (((w_data312w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data312w[2..2]))))) # ((((w_data312w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data312w[2..2]))) & (w_data312w[3..3] # (! sel_node[0..0])))), (((w_data287w[1..1] & sel_node[0..0]) & (! (((w_data287w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data287w[2..2]))))) # ((((w_data287w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data287w[2..2]))) & (w_data287w[3..3] # (! sel_node[0..0])))), (((w_data262w[1..1] & sel_node[0..0]) & (! (((w_data262w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data262w[2..2]))))) # ((((w_data262w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data262w[2..2]))) & (w_data262w[3..3] # (! sel_node[0..0])))), (((w_data237w[1..1] & sel_node[0..0]) & (! (((w_data237w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data237w[2..2]))))) # ((((w_data237w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data237w[2..2]))) & (w_data237w[3..3] # (! sel_node[0..0])))), (((w_data212w[1..1] & sel_node[0..0]) & (! (((w_data212w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data212w[2..2]))))) # ((((w_data212w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data212w[2..2]))) & (w_data212w[3..3] # (! sel_node[0..0])))), (((w_data182w[1..1] & sel_node[0..0]) & (! (((w_data182w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data182w[2..2]))))) # ((((w_data182w[0..0] & (! sel_node[1..1])) & (! sel_node[0..0])) # (sel_node[1..1] & (sel_node[0..0] # w_data182w[2..2]))) & (w_data182w[3..3] # (! sel_node[0..0])))));
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        sel_node[] = ( sel[1..0]);
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        w_data182w[] = ( data[24..24], data[16..16], data[8..8], data[0..0]);
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        w_data212w[] = ( data[25..25], data[17..17], data[9..9], data[1..1]);
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        w_data237w[] = ( data[26..26], data[18..18], data[10..10], data[2..2]);
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        w_data262w[] = ( data[27..27], data[19..19], data[11..11], data[3..3]);
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        w_data287w[] = ( data[28..28], data[20..20], data[12..12], data[4..4]);
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        w_data312w[] = ( data[29..29], data[21..21], data[13..13], data[5..5]);
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        w_data337w[] = ( data[30..30], data[22..22], data[14..14], data[6..6]);
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        w_data362w[] = ( data[31..31], data[23..23], data[15..15], data[7..7]);
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END;
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--VALID FILE

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