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URL https://opencores.org/ocsvn/z80soc/z80soc/trunk

Subversion Repositories z80soc

[/] [z80soc/] [trunk/] [V0.7.3/] [DE1/] [db/] [z80soc.fit.qmsg] - Blame information for rev 46

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1 46 rrred
{ "Warning" "WQCU_PARALLEL_NO_LICENSE" "" "Parallel compilation is not licensed and has been disabled" {  } {  } 0 20028 "Parallel compilation is not licensed and has been disabled" 0 0 "Fitter" 0 -1 1466372529022 ""}
2
{ "Info" "IMPP_MPP_USER_DEVICE" "z80soc EP2C20F484C7 " "Selected device EP2C20F484C7 for design \"z80soc\"" {  } {  } 0 119006 "Selected device %2!s! for design \"%1!s!\"" 0 0 "Fitter" 0 -1 1466372529286 ""}
3
{ "Info" "IFITCC_FITCC_INFO_FAST_FIT_COMPILATION_ON" "" "Fitter is performing a Fast Fit compilation, which decreases Fitter effort to reduce compilation time" {  } {  } 0 171001 "Fitter is performing a Fast Fit compilation, which decreases Fitter effort to reduce compilation time" 0 0 "Fitter" 0 -1 1466372531989 ""}
4
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "LogicLock " "Feature LogicLock is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." {  } {  } 0 292013 "Feature %1!s! is only available with a valid subscription license. You can purchase a software subscription to gain full access to this feature." 0 0 "Fitter" 0 -1 1466372532466 ""}
5
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C15AF484C7 " "Device EP2C15AF484C7 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1466372534356 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C35F484C7 " "Device EP2C35F484C7 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1466372534356 ""} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP2C50F484C7 " "Device EP2C50F484C7 is compatible" {  } {  } 2 176445 "Device %1!s! is compatible" 0 0 "Quartus II" 0 -1 1466372534356 ""}  } {  } 2 176444 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "Fitter" 0 -1 1466372534356 ""}
6
{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "3 " "Fitter converted 3 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~ASDO~ C4 " "Pin ~ASDO~ is reserved at location C4" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~ASDO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~ASDO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 5261 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1466372534401 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~nCSO~ C3 " "Pin ~nCSO~ is reserved at location C3" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~nCSO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~nCSO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 5262 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1466372534401 ""} { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~LVDS91p/nCEO~ W20 " "Pin ~LVDS91p/nCEO~ is reserved at location W20" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { ~LVDS91p/nCEO~ } } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ~LVDS91p/nCEO~ } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 5263 9224 9983 0}  }  } }  } 0 169125 "Pin %1!s! is reserved at location %2!s!" 0 0 "Quartus II" 0 -1 1466372534401 ""}  } {  } 0 169124 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "Fitter" 0 -1 1466372534401 ""}
7
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1466372534430 ""}
8
{ "Critical Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "7 281 " "No exact pin location assignment(s) for 7 pins of 281 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "CLOCK_27 " "Pin CLOCK_27 not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { CLOCK_27 } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 84 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CLOCK_27 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 297 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1466372535008 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "IRDA_RXD " "Pin IRDA_RXD not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { IRDA_RXD } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 105 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { IRDA_RXD } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 301 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1466372535008 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "FL_CE_N " "Pin FL_CE_N not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { FL_CE_N } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 127 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { FL_CE_N } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 315 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1466372535008 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD_DAT " "Pin SD_DAT not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SD_DAT } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 139 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SD_DAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 320 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1466372535008 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD_DAT3 " "Pin SD_DAT3 not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SD_DAT3 } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 140 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SD_DAT3 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 321 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1466372535008 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD_CMD " "Pin SD_CMD not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SD_CMD } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 141 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SD_CMD } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 322 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1466372535008 ""} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "SD_CLK " "Pin SD_CLK not assigned to an exact location on the device" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SD_CLK } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 142 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SD_CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 323 9224 9983 0}  }  } }  } 0 169086 "Pin %1!s! not assigned to an exact location on the device" 0 0 "Quartus II" 0 -1 1466372535008 ""}  } {  } 1 169085 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "Fitter" 0 -1 1466372535008 ""}
9
{ "Critical Warning" "WSTA_SDC_NOT_FOUND" "z80soc.sdc " "Synopsys Design Constraints File file not found: 'z80soc.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." {  } {  } 1 332012 "Synopsys Design Constraints File file not found: '%1!s!'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design." 0 0 "Fitter" 0 -1 1466372538027 ""}
10
{ "Info" "ISTA_NO_CLOCK_FOUND_NO_DERIVING_MSG" "base clocks " "No user constrained base clocks found in the design" {  } {  } 0 332144 "No user constrained %1!s! found in the design" 0 0 "Fitter" 0 -1 1466372538031 ""}
11
{ "Info" "ISTA_UNKNOWN_UNATE_EDGE_ASSUMED_POS" "" "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." { { "Info" "ISTA_CLOCK_MGR_INFO" "Cell: Clk_Z80  from: datac  to: combout " "Cell: Clk_Z80  from: datac  to: combout" {  } {  } 0 332098 "%1!s!" 0 0 "Quartus II" 0 -1 1466372538141 ""}  } {  } 0 332097 "The following timing edges are non-unate.  TimeQuest will assume pos-unate behavior for these edges in the clock network." 0 0 "Fitter" 0 -1 1466372538141 ""}
12
{ "Info" "ISTA_DEFAULT_TDC_OPTIMIZATION_GOALS" "" "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ISTA_ASSUMED_DEFAULT_TDC_REQUIREMENT" "" "Assuming a default timing requirement" {  } {  } 0 332127 "Assuming a default timing requirement" 0 0 "Quartus II" 0 -1 1466372538296 ""}  } {  } 0 332128 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "Fitter" 0 -1 1466372538296 ""}
13
{ "Info" "ISTA_REPORT_CLOCKS_INFO" "Found 11 clocks " "Found 11 clocks" { { "Info" "ISTA_REPORT_CLOCKS_INFO" "  Period   Clock Name " "  Period   Clock Name" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1466372538299 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "======== ============ " "======== ============" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1466372538299 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000 clk_div:clkdiv_inst\|clock_1Khz_int " "   1.000 clk_div:clkdiv_inst\|clock_1Khz_int" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1466372538299 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000 clk_div:clkdiv_inst\|clock_1Mhz_int " "   1.000 clk_div:clkdiv_inst\|clock_1Mhz_int" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1466372538299 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000 clk_div:clkdiv_inst\|clock_10Khz_int " "   1.000 clk_div:clkdiv_inst\|clock_10Khz_int" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1466372538299 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000 clk_div:clkdiv_inst\|clock_25MHz " "   1.000 clk_div:clkdiv_inst\|clock_25MHz" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1466372538299 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000 clk_div:clkdiv_inst\|clock_25Mhz_int " "   1.000 clk_div:clkdiv_inst\|clock_25Mhz_int" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1466372538299 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000 clk_div:clkdiv_inst\|clock_100Hz " "   1.000 clk_div:clkdiv_inst\|clock_100Hz" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1466372538299 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000 clk_div:clkdiv_inst\|clock_100Khz_int " "   1.000 clk_div:clkdiv_inst\|clock_100Khz_int" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1466372538299 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000     CLOCK_50 " "   1.000     CLOCK_50" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1466372538299 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000 ps2kbd:ps2_kbd_inst\|keyboard:kbd_inst\|keyboard_clk_filtered " "   1.000 ps2kbd:ps2_kbd_inst\|keyboard:kbd_inst\|keyboard_clk_filtered" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1466372538299 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000 ps2kbd:ps2_kbd_inst\|keyboard:kbd_inst\|ready_set " "   1.000 ps2kbd:ps2_kbd_inst\|keyboard:kbd_inst\|ready_set" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1466372538299 ""} { "Info" "ISTA_REPORT_CLOCKS_INFO" "   1.000        SW\[8\] " "   1.000        SW\[8\]" {  } {  } 0 332111 "%1!s!" 0 0 "Quartus II" 0 -1 1466372538299 ""}  } {  } 0 332111 "%1!s!" 0 0 "Fitter" 0 -1 1466372538299 ""}
14
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "CLOCK_50 (placed in PIN L1 (CLK0, LVDSCLK0p, Input)) " "Automatically promoted node CLOCK_50 (placed in PIN L1 (CLK0, LVDSCLK0p, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G2 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G2" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1466372539140 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "clk_div:clkdiv_inst\|clock_357Mhz " "Destination node clk_div:clkdiv_inst\|clock_357Mhz" {  } { { "vhdl/clk_div.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/clk_div.vhd" 13 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk_div:clkdiv_inst|clock_357Mhz } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 439 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1466372539140 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "clk_div:clkdiv_inst\|clock_10MHz " "Destination node clk_div:clkdiv_inst\|clock_10MHz" {  } { { "vhdl/clk_div.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/clk_div.vhd" 12 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk_div:clkdiv_inst|clock_10MHz } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 440 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1466372539140 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1466372539140 ""}  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { CLOCK_50 } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK_50" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 85 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { CLOCK_50 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 298 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1466372539140 ""}
15
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "Clk_Z80  " "Automatically promoted node Clk_Z80 " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1466372539151 ""}  } { { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 297 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { Clk_Z80 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 1387 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1466372539151 ""}
16
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk_div:clkdiv_inst\|clock_25MHz  " "Automatically promoted node clk_div:clkdiv_inst\|clock_25MHz " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1466372539153 ""}  } { { "vhdl/clk_div.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/clk_div.vhd" 11 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk_div:clkdiv_inst|clock_25MHz } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 441 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1466372539153 ""}
17
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "ps2kbd:ps2_kbd_inst\|keyboard:kbd_inst\|keyboard_clk_filtered  " "Automatically promoted node ps2kbd:ps2_kbd_inst\|keyboard:kbd_inst\|keyboard_clk_filtered " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1466372539153 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ps2kbd:ps2_kbd_inst\|keyboard:kbd_inst\|keyboard_clk_filtered~1 " "Destination node ps2kbd:ps2_kbd_inst\|keyboard:kbd_inst\|keyboard_clk_filtered~1" {  } { { "vhdl/keyboard.VHD" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/keyboard.VHD" 27 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered~1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 3908 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1466372539153 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ps2kbd:ps2_kbd_inst\|keyboard:kbd_inst\|keyboard_clk_filtered~2 " "Destination node ps2kbd:ps2_kbd_inst\|keyboard:kbd_inst\|keyboard_clk_filtered~2" {  } { { "vhdl/keyboard.VHD" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/keyboard.VHD" 27 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered~2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 3909 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1466372539153 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ps2kbd:ps2_kbd_inst\|keyboard:kbd_inst\|keyboard_clk_filtered~3 " "Destination node ps2kbd:ps2_kbd_inst\|keyboard:kbd_inst\|keyboard_clk_filtered~3" {  } { { "vhdl/keyboard.VHD" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/keyboard.VHD" 27 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered~3 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 3910 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1466372539153 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1466372539153 ""}  } { { "vhdl/keyboard.VHD" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/keyboard.VHD" 27 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 373 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1466372539153 ""}
18
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk_div:clkdiv_inst\|clock_25Mhz_int  " "Automatically promoted node clk_div:clkdiv_inst\|clock_25Mhz_int " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1466372539163 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "clk_div:clkdiv_inst\|clock_25MHz " "Destination node clk_div:clkdiv_inst\|clock_25MHz" {  } { { "vhdl/clk_div.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/clk_div.vhd" 11 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk_div:clkdiv_inst|clock_25MHz } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 441 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1466372539163 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "clk_div:clkdiv_inst\|clock_25Mhz_int~0 " "Destination node clk_div:clkdiv_inst\|clock_25Mhz_int~0" {  } { { "vhdl/clk_div.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/clk_div.vhd" 31 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk_div:clkdiv_inst|clock_25Mhz_int~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 4102 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1466372539163 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1466372539163 ""}  } { { "vhdl/clk_div.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/clk_div.vhd" 31 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk_div:clkdiv_inst|clock_25Mhz_int } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 442 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1466372539163 ""}
19
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk_div:clkdiv_inst\|clock_100Khz_int  " "Automatically promoted node clk_div:clkdiv_inst\|clock_100Khz_int " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1466372539166 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "clk_div:clkdiv_inst\|clock_100Khz_int~0 " "Destination node clk_div:clkdiv_inst\|clock_100Khz_int~0" {  } { { "vhdl/clk_div.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/clk_div.vhd" 31 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk_div:clkdiv_inst|clock_100Khz_int~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 3932 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1466372539166 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1466372539166 ""}  } { { "vhdl/clk_div.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/clk_div.vhd" 31 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk_div:clkdiv_inst|clock_100Khz_int } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 434 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1466372539166 ""}
20
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk_div:clkdiv_inst\|clock_10Khz_int  " "Automatically promoted node clk_div:clkdiv_inst\|clock_10Khz_int " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1466372539171 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "clk_div:clkdiv_inst\|clock_10Khz_int~0 " "Destination node clk_div:clkdiv_inst\|clock_10Khz_int~0" {  } { { "vhdl/clk_div.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/clk_div.vhd" 31 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk_div:clkdiv_inst|clock_10Khz_int~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 3928 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1466372539171 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1466372539171 ""}  } { { "vhdl/clk_div.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/clk_div.vhd" 31 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk_div:clkdiv_inst|clock_10Khz_int } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 435 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1466372539171 ""}
21
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk_div:clkdiv_inst\|clock_1Khz_int  " "Automatically promoted node clk_div:clkdiv_inst\|clock_1Khz_int " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1466372539173 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "clk_div:clkdiv_inst\|clock_1Khz_int~0 " "Destination node clk_div:clkdiv_inst\|clock_1Khz_int~0" {  } { { "vhdl/clk_div.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/clk_div.vhd" 31 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk_div:clkdiv_inst|clock_1Khz_int~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 3924 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1466372539173 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1466372539173 ""}  } { { "vhdl/clk_div.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/clk_div.vhd" 31 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk_div:clkdiv_inst|clock_1Khz_int } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 436 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1466372539173 ""}
22
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk_div:clkdiv_inst\|clock_1Mhz_int  " "Automatically promoted node clk_div:clkdiv_inst\|clock_1Mhz_int " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1466372539175 ""}  } { { "vhdl/clk_div.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/clk_div.vhd" 31 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk_div:clkdiv_inst|clock_1Mhz_int } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 433 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1466372539175 ""}
23
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "clk_div:clkdiv_inst\|clock_100Hz  " "Automatically promoted node clk_div:clkdiv_inst\|clock_100Hz " { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock " "Automatically promoted destinations to use location or clock signal Global Clock" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1466372539175 ""}  } { { "vhdl/clk_div.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/clk_div.vhd" 18 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { clk_div:clkdiv_inst|clock_100Hz } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 438 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1466372539175 ""}
24
{ "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL" "SW\[9\] (placed in PIN L2 (CLK1, LVDSCLK0n, Input)) " "Automatically promoted node SW\[9\] (placed in PIN L2 (CLK1, LVDSCLK0n, Input))" { { "Info" "IFSAC_FSAC_ASSIGN_AUTO_GLOBAL_TO_SIGNAL_FANOUTS" "destinations Global Clock CLKCTRL_G1 " "Automatically promoted destinations to use location or clock signal Global Clock CLKCTRL_G1" {  } {  } 0 176355 "Automatically promoted %1!s! to use location or clock signal %2!s!" 0 0 "Quartus II" 0 -1 1466372539176 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS" "" "Following destination nodes may be non-global or may not use global or regional clocks" { { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ps2kbd:ps2_kbd_inst\|keyboard:kbd_inst\|READ_CHAR " "Destination node ps2kbd:ps2_kbd_inst\|keyboard:kbd_inst\|READ_CHAR" {  } { { "vhdl/keyboard.VHD" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/keyboard.VHD" 25 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|READ_CHAR } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 377 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1466372539176 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ps2kbd:ps2_kbd_inst\|keyboard:kbd_inst\|ready_set " "Destination node ps2kbd:ps2_kbd_inst\|keyboard:kbd_inst\|ready_set" {  } { { "vhdl/keyboard.VHD" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/keyboard.VHD" 26 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 378 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1466372539176 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ps2kbd:ps2_kbd_inst\|keyboard:kbd_inst\|scan_code\[7\]~0 " "Destination node ps2kbd:ps2_kbd_inst\|keyboard:kbd_inst\|scan_code\[7\]~0" {  } { { "vhdl/keyboard.VHD" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/keyboard.VHD" 84 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[7]~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 3901 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1466372539176 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ps2kbd:ps2_kbd_inst\|keyboard:kbd_inst\|SHIFTIN\[7\]~0 " "Destination node ps2kbd:ps2_kbd_inst\|keyboard:kbd_inst\|SHIFTIN\[7\]~0" {  } { { "vhdl/keyboard.VHD" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/keyboard.VHD" 84 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|SHIFTIN[7]~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 3906 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1466372539176 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ps2kbd:ps2_kbd_inst\|keyboard:kbd_inst\|INCNT~0 " "Destination node ps2kbd:ps2_kbd_inst\|keyboard:kbd_inst\|INCNT~0" {  } { { "vhdl/keyboard.VHD" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/keyboard.VHD" 23 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT~0 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 3912 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1466372539176 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ps2kbd:ps2_kbd_inst\|keyboard:kbd_inst\|INCNT\[0\]~1 " "Destination node ps2kbd:ps2_kbd_inst\|keyboard:kbd_inst\|INCNT\[0\]~1" {  } { { "vhdl/keyboard.VHD" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/keyboard.VHD" 84 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0]~1 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 3913 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1466372539176 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ps2kbd:ps2_kbd_inst\|keyboard:kbd_inst\|INCNT~2 " "Destination node ps2kbd:ps2_kbd_inst\|keyboard:kbd_inst\|INCNT~2" {  } { { "vhdl/keyboard.VHD" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/keyboard.VHD" 23 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT~2 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 3914 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1466372539176 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ps2kbd:ps2_kbd_inst\|keyboard:kbd_inst\|INCNT~3 " "Destination node ps2kbd:ps2_kbd_inst\|keyboard:kbd_inst\|INCNT~3" {  } { { "vhdl/keyboard.VHD" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/keyboard.VHD" 23 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT~3 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 3916 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1466372539176 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "ps2kbd:ps2_kbd_inst\|keyboard:kbd_inst\|INCNT~4 " "Destination node ps2kbd:ps2_kbd_inst\|keyboard:kbd_inst\|INCNT~4" {  } { { "vhdl/keyboard.VHD" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/keyboard.VHD" 23 -1 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT~4 } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 3918 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1466372539176 ""} { "Info" "IFSAC_FSAC_GLOBAL_UNASSIGNED_FANOUTS_SUB" "LEDR\[9\] " "Destination node LEDR\[9\]" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { LEDR[9] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "LEDR\[9\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 96 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { LEDR[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 226 9224 9983 0}  }  } }  } 0 176357 "Destination node %1!s!" 0 0 "Quartus II" 0 -1 1466372539176 ""}  } {  } 0 176356 "Following destination nodes may be non-global or may not use global or regional clocks" 0 0 "Quartus II" 0 -1 1466372539176 ""}  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SW[9] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SW\[9\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 90 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SW[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 180 9224 9983 0}  }  } }  } 0 176353 "Automatically promoted node %1!s! %2!s!" 0 0 "Fitter" 0 -1 1466372539176 ""}
25
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_REGPACKING_INFO" "" "Starting register packing" {  } {  } 0 176233 "Starting register packing" 0 0 "Fitter" 0 -1 1466372540845 ""}
26
{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Performing register packing on registers with non-logic cell location assignments" {  } {  } 1 176273 "Performing register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1466372540855 ""}
27
{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Completed register packing on registers with non-logic cell location assignments" {  } {  } 1 176274 "Completed register packing on registers with non-logic cell location assignments" 1 0 "Fitter" 0 -1 1466372540864 ""}
28
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Started Fast Input/Output/OE register processing" {  } {  } 1 176236 "Started Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1466372540881 ""}
29
{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Finished Fast Input/Output/OE register processing" {  } {  } 1 176237 "Finished Fast Input/Output/OE register processing" 1 0 "Fitter" 0 -1 1466372540900 ""}
30
{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Start inferring scan chains for DSP blocks" {  } {  } 1 176238 "Start inferring scan chains for DSP blocks" 1 0 "Fitter" 0 -1 1466372540922 ""}
31
{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Inferring scan chains for DSP blocks is complete" {  } {  } 1 176239 "Inferring scan chains for DSP blocks is complete" 1 0 "Fitter" 0 -1 1466372540924 ""}
32
{ "Extra Info" "IFSAC_FSAC_START_IO_MULT_RAM_PACKING" "" "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" {  } {  } 1 176248 "Moving registers into I/O cells, Multiplier Blocks, and RAM blocks to improve timing and density" 1 0 "Fitter" 0 -1 1466372540937 ""}
33
{ "Extra Info" "IFSAC_FSAC_FINISH_IO_MULT_RAM_PACKING" "" "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" {  } {  } 1 176249 "Finished moving registers into I/O cells, Multiplier Blocks, and RAM blocks" 1 0 "Fitter" 0 -1 1466372541505 ""}
34
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "No registers were packed into other blocks" {  } {  } 1 176219 "No registers were packed into other blocks" 0 0 "Quartus II" 0 -1 1466372541515 ""}  } {  } 0 176235 "Finished register packing" 0 0 "Fitter" 0 -1 1466372541515 ""}
35
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "7 unused 3.3V 3 4 0 " "Number of I/O pins in group: 7 (unused VREF, 3.3V VCCIO, 3 input, 4 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "I/O standards used: 3.3-V LVTTL." {  } {  } 0 176212 "I/O standards used: %1!s!" 0 0 "Quartus II" 0 -1 1466372541819 ""}  } {  } 0 176211 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "Quartus II" 0 -1 1466372541819 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Fitter" 0 -1 1466372541819 ""}
36
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.3V 40 1 " "I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 40 total pin(s) used --  1 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1466372541844 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.3V 32 1 " "I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 32 total pin(s) used --  1 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1466372541844 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 3.3V 26 17 " "I/O bank number 3 does not use VREF pins and has 3.3V VCCIO pins. 26 total pin(s) used --  17 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1466372541844 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use 3.3V 36 4 " "I/O bank number 4 does not use VREF pins and has 3.3V VCCIO pins. 36 total pin(s) used --  4 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1466372541844 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use 3.3V 36 3 " "I/O bank number 5 does not use VREF pins and has 3.3V VCCIO pins. 36 total pin(s) used --  3 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1466372541844 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use 3.3V 31 5 " "I/O bank number 6 does not use VREF pins and has 3.3V VCCIO pins. 31 total pin(s) used --  5 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1466372541844 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use 3.3V 35 5 " "I/O bank number 7 does not use VREF pins and has 3.3V VCCIO pins. 35 total pin(s) used --  5 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1466372541844 ""} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use 3.3V 41 2 " "I/O bank number 8 does not use VREF pins and has 3.3V VCCIO pins. 41 total pin(s) used --  2 pins available" {  } {  } 0 176213 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used --  %5!d! pins available" 0 0 "Quartus II" 0 -1 1466372541844 ""}  } {  } 0 176214 "Statistics of %1!s!" 0 0 "Quartus II" 0 -1 1466372541844 ""}  } {  } 0 176215 "I/O bank details %1!s! I/O pin placement" 0 0 "Fitter" 0 -1 1466372541844 ""}
37
{ "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN" "" "Ignored I/O standard assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "CLOCK_24\[0\] " "Ignored I/O standard assignment to node \"CLOCK_24\[0\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK_24\[0\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1466372542304 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "CLOCK_24\[1\] " "Ignored I/O standard assignment to node \"CLOCK_24\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK_24\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1466372542304 ""} { "Warning" "WCUT_CUT_UNATTACHED_IO_STANDARD_ASGN_SUB" "CLOCK_27\[1\] " "Ignored I/O standard assignment to node \"CLOCK_27\[1\]\"" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK_27\[1\]" } } } }  } 0 15710 "Ignored I/O standard assignment to node \"%1!s!\"" 0 0 "Quartus II" 0 -1 1466372542304 ""}  } {  } 0 15709 "Ignored I/O standard assignments to the following nodes" 0 0 "Fitter" 0 -1 1466372542304 ""}
38
{ "Warning" "WCUT_CUT_UNATTACHED_ASGN" "" "Ignored locations or region assignments to the following nodes" { { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_24\[0\] " "Node \"CLOCK_24\[0\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK_24\[0\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1466372542305 ""} { "Warning" "WCUT_CUT_UNATTACHED_ASGN_SUB" "CLOCK_24\[1\] " "Node \"CLOCK_24\[1\]\" is assigned to location or region, but does not exist in design" {  } { { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "CLOCK_24\[1\]" } } } }  } 0 15706 "Node \"%1!s!\" is assigned to location or region, but does not exist in design" 0 0 "Quartus II" 0 -1 1466372542305 ""}  } {  } 0 15705 "Ignored locations or region assignments to the following nodes" 0 0 "Fitter" 0 -1 1466372542305 ""}
39
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:08 " "Fitter preparation operations ending: elapsed time is 00:00:08" {  } {  } 0 171121 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1466372542309 ""}
40
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Fitter placement preparation operations beginning" {  } {  } 0 170189 "Fitter placement preparation operations beginning" 0 0 "Fitter" 0 -1 1466372546860 ""}
41
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:03 " "Fitter placement preparation operations ending: elapsed time is 00:00:03" {  } {  } 0 170190 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1466372550111 ""}
42
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Fitter placement operations beginning" {  } {  } 0 170191 "Fitter placement operations beginning" 0 0 "Fitter" 0 -1 1466372550198 ""}
43
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Fitter placement was successful" {  } {  } 0 170137 "Fitter placement was successful" 0 0 "Fitter" 0 -1 1466372554924 ""}
44
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:04 " "Fitter placement operations ending: elapsed time is 00:00:04" {  } {  } 0 170192 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1466372554929 ""}
45
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Fitter routing operations beginning" {  } {  } 0 170193 "Fitter routing operations beginning" 0 0 "Fitter" 0 -1 1466372556671 ""}
46
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "7 " "Router estimated average interconnect usage is 7% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "19 X25_Y14 X37_Y27 " "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X25_Y14 to location X37_Y27" {  } { { "loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 1 { 0 "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X25_Y14 to location X37_Y27"} { { 11 { 0 "Router estimated peak interconnect usage is 19% of the available device resources in the region that extends from location X25_Y14 to location X37_Y27"} 25 14 13 14 }  }  }  }  } }  } 0 170196 "Router estimated peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "Quartus II" 0 -1 1466372565928 ""}  } {  } 0 170195 "Router estimated average interconnect usage is %1!d!%% of the available device resources" 0 0 "Fitter" 0 -1 1466372565928 ""}
47
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:11 " "Fitter routing operations ending: elapsed time is 00:00:11" {  } {  } 0 170194 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1466372568873 ""}
48
{ "Info" "IVPR20K_VPR_TIMING_ANALYSIS_TIME" "4.63 " "Total time spent on timing analysis during the Fitter is 4.63 seconds." {  } {  } 0 11888 "Total time spent on timing analysis during the Fitter is %1!s! seconds." 0 0 "Fitter" 0 -1 1466372569119 ""}
49
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 306004 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1466372569149 ""}
50
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "257 " "Found 257 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "UART_TXD 0 " "Pin \"UART_TXD\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[0\] 0 " "Pin \"DRAM_DQ\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[1\] 0 " "Pin \"DRAM_DQ\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[2\] 0 " "Pin \"DRAM_DQ\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[3\] 0 " "Pin \"DRAM_DQ\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[4\] 0 " "Pin \"DRAM_DQ\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[5\] 0 " "Pin \"DRAM_DQ\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[6\] 0 " "Pin \"DRAM_DQ\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[7\] 0 " "Pin \"DRAM_DQ\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[8\] 0 " "Pin \"DRAM_DQ\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[9\] 0 " "Pin \"DRAM_DQ\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[10\] 0 " "Pin \"DRAM_DQ\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[11\] 0 " "Pin \"DRAM_DQ\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[12\] 0 " "Pin \"DRAM_DQ\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[13\] 0 " "Pin \"DRAM_DQ\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[14\] 0 " "Pin \"DRAM_DQ\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_DQ\[15\] 0 " "Pin \"DRAM_DQ\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[0\] 0 " "Pin \"FL_DQ\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[1\] 0 " "Pin \"FL_DQ\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[2\] 0 " "Pin \"FL_DQ\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[3\] 0 " "Pin \"FL_DQ\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[4\] 0 " "Pin \"FL_DQ\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[5\] 0 " "Pin \"FL_DQ\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[6\] 0 " "Pin \"FL_DQ\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_DQ\[7\] 0 " "Pin \"FL_DQ\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[0\] 0 " "Pin \"SRAM_DQ\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[1\] 0 " "Pin \"SRAM_DQ\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[2\] 0 " "Pin \"SRAM_DQ\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[3\] 0 " "Pin \"SRAM_DQ\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[4\] 0 " "Pin \"SRAM_DQ\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[5\] 0 " "Pin \"SRAM_DQ\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[6\] 0 " "Pin \"SRAM_DQ\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[7\] 0 " "Pin \"SRAM_DQ\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[8\] 0 " "Pin \"SRAM_DQ\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[9\] 0 " "Pin \"SRAM_DQ\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[10\] 0 " "Pin \"SRAM_DQ\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[11\] 0 " "Pin \"SRAM_DQ\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[12\] 0 " "Pin \"SRAM_DQ\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[13\] 0 " "Pin \"SRAM_DQ\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[14\] 0 " "Pin \"SRAM_DQ\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_DQ\[15\] 0 " "Pin \"SRAM_DQ\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "I2C_SDAT 0 " "Pin \"I2C_SDAT\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "PS2_DAT 0 " "Pin \"PS2_DAT\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "PS2_CLK 0 " "Pin \"PS2_CLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_ADCLRCK 0 " "Pin \"AUD_ADCLRCK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_DACLRCK 0 " "Pin \"AUD_DACLRCK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_BCLK 0 " "Pin \"AUD_BCLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[0\] 0 " "Pin \"GPIO_0\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[1\] 0 " "Pin \"GPIO_0\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[2\] 0 " "Pin \"GPIO_0\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[3\] 0 " "Pin \"GPIO_0\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[4\] 0 " "Pin \"GPIO_0\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[5\] 0 " "Pin \"GPIO_0\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[6\] 0 " "Pin \"GPIO_0\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[7\] 0 " "Pin \"GPIO_0\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[8\] 0 " "Pin \"GPIO_0\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[9\] 0 " "Pin \"GPIO_0\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[10\] 0 " "Pin \"GPIO_0\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[11\] 0 " "Pin \"GPIO_0\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[12\] 0 " "Pin \"GPIO_0\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[13\] 0 " "Pin \"GPIO_0\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[14\] 0 " "Pin \"GPIO_0\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[15\] 0 " "Pin \"GPIO_0\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[16\] 0 " "Pin \"GPIO_0\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[17\] 0 " "Pin \"GPIO_0\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[18\] 0 " "Pin \"GPIO_0\[18\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[19\] 0 " "Pin \"GPIO_0\[19\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[20\] 0 " "Pin \"GPIO_0\[20\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[21\] 0 " "Pin \"GPIO_0\[21\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[22\] 0 " "Pin \"GPIO_0\[22\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[23\] 0 " "Pin \"GPIO_0\[23\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[24\] 0 " "Pin \"GPIO_0\[24\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[25\] 0 " "Pin \"GPIO_0\[25\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[26\] 0 " "Pin \"GPIO_0\[26\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[27\] 0 " "Pin \"GPIO_0\[27\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[28\] 0 " "Pin \"GPIO_0\[28\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[29\] 0 " "Pin \"GPIO_0\[29\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[30\] 0 " "Pin \"GPIO_0\[30\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[31\] 0 " "Pin \"GPIO_0\[31\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[32\] 0 " "Pin \"GPIO_0\[32\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[33\] 0 " "Pin \"GPIO_0\[33\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[34\] 0 " "Pin \"GPIO_0\[34\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_0\[35\] 0 " "Pin \"GPIO_0\[35\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[0\] 0 " "Pin \"GPIO_1\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[1\] 0 " "Pin \"GPIO_1\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[2\] 0 " "Pin \"GPIO_1\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[3\] 0 " "Pin \"GPIO_1\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[4\] 0 " "Pin \"GPIO_1\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[5\] 0 " "Pin \"GPIO_1\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[6\] 0 " "Pin \"GPIO_1\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[7\] 0 " "Pin \"GPIO_1\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[8\] 0 " "Pin \"GPIO_1\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[9\] 0 " "Pin \"GPIO_1\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[10\] 0 " "Pin \"GPIO_1\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[11\] 0 " "Pin \"GPIO_1\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[12\] 0 " "Pin \"GPIO_1\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[13\] 0 " "Pin \"GPIO_1\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[14\] 0 " "Pin \"GPIO_1\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[15\] 0 " "Pin \"GPIO_1\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[16\] 0 " "Pin \"GPIO_1\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[17\] 0 " "Pin \"GPIO_1\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[18\] 0 " "Pin \"GPIO_1\[18\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[19\] 0 " "Pin \"GPIO_1\[19\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[20\] 0 " "Pin \"GPIO_1\[20\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[21\] 0 " "Pin \"GPIO_1\[21\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[22\] 0 " "Pin \"GPIO_1\[22\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[23\] 0 " "Pin \"GPIO_1\[23\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[24\] 0 " "Pin \"GPIO_1\[24\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[25\] 0 " "Pin \"GPIO_1\[25\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[26\] 0 " "Pin \"GPIO_1\[26\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[27\] 0 " "Pin \"GPIO_1\[27\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[28\] 0 " "Pin \"GPIO_1\[28\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[29\] 0 " "Pin \"GPIO_1\[29\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[30\] 0 " "Pin \"GPIO_1\[30\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[31\] 0 " "Pin \"GPIO_1\[31\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[32\] 0 " "Pin \"GPIO_1\[32\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[33\] 0 " "Pin \"GPIO_1\[33\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[34\] 0 " "Pin \"GPIO_1\[34\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "GPIO_1\[35\] 0 " "Pin \"GPIO_1\[35\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[0\] 0 " "Pin \"HEX0\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[1\] 0 " "Pin \"HEX0\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[2\] 0 " "Pin \"HEX0\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[3\] 0 " "Pin \"HEX0\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[4\] 0 " "Pin \"HEX0\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[5\] 0 " "Pin \"HEX0\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX0\[6\] 0 " "Pin \"HEX0\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[0\] 0 " "Pin \"HEX1\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[1\] 0 " "Pin \"HEX1\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[2\] 0 " "Pin \"HEX1\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[3\] 0 " "Pin \"HEX1\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[4\] 0 " "Pin \"HEX1\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[5\] 0 " "Pin \"HEX1\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX1\[6\] 0 " "Pin \"HEX1\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[0\] 0 " "Pin \"HEX2\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[1\] 0 " "Pin \"HEX2\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[2\] 0 " "Pin \"HEX2\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[3\] 0 " "Pin \"HEX2\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[4\] 0 " "Pin \"HEX2\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[5\] 0 " "Pin \"HEX2\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX2\[6\] 0 " "Pin \"HEX2\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[0\] 0 " "Pin \"HEX3\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[1\] 0 " "Pin \"HEX3\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[2\] 0 " "Pin \"HEX3\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[3\] 0 " "Pin \"HEX3\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[4\] 0 " "Pin \"HEX3\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[5\] 0 " "Pin \"HEX3\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "HEX3\[6\] 0 " "Pin \"HEX3\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[0\] 0 " "Pin \"LEDG\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[1\] 0 " "Pin \"LEDG\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[2\] 0 " "Pin \"LEDG\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[3\] 0 " "Pin \"LEDG\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[4\] 0 " "Pin \"LEDG\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[5\] 0 " "Pin \"LEDG\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[6\] 0 " "Pin \"LEDG\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDG\[7\] 0 " "Pin \"LEDG\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[0\] 0 " "Pin \"LEDR\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[1\] 0 " "Pin \"LEDR\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[2\] 0 " "Pin \"LEDR\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[3\] 0 " "Pin \"LEDR\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[4\] 0 " "Pin \"LEDR\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[5\] 0 " "Pin \"LEDR\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[6\] 0 " "Pin \"LEDR\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[7\] 0 " "Pin \"LEDR\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[8\] 0 " "Pin \"LEDR\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "LEDR\[9\] 0 " "Pin \"LEDR\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[0\] 0 " "Pin \"DRAM_ADDR\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[1\] 0 " "Pin \"DRAM_ADDR\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[2\] 0 " "Pin \"DRAM_ADDR\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[3\] 0 " "Pin \"DRAM_ADDR\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[4\] 0 " "Pin \"DRAM_ADDR\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[5\] 0 " "Pin \"DRAM_ADDR\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[6\] 0 " "Pin \"DRAM_ADDR\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[7\] 0 " "Pin \"DRAM_ADDR\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[8\] 0 " "Pin \"DRAM_ADDR\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[9\] 0 " "Pin \"DRAM_ADDR\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[10\] 0 " "Pin \"DRAM_ADDR\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_ADDR\[11\] 0 " "Pin \"DRAM_ADDR\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_LDQM 0 " "Pin \"DRAM_LDQM\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_UDQM 0 " "Pin \"DRAM_UDQM\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_WE_N 0 " "Pin \"DRAM_WE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_CAS_N 0 " "Pin \"DRAM_CAS_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_RAS_N 0 " "Pin \"DRAM_RAS_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_CS_N 0 " "Pin \"DRAM_CS_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_BA_0 0 " "Pin \"DRAM_BA_0\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_BA_1 0 " "Pin \"DRAM_BA_1\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_CLK 0 " "Pin \"DRAM_CLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "DRAM_CKE 0 " "Pin \"DRAM_CKE\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[0\] 0 " "Pin \"FL_ADDR\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569300 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[1\] 0 " "Pin \"FL_ADDR\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[2\] 0 " "Pin \"FL_ADDR\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[3\] 0 " "Pin \"FL_ADDR\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[4\] 0 " "Pin \"FL_ADDR\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[5\] 0 " "Pin \"FL_ADDR\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[6\] 0 " "Pin \"FL_ADDR\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[7\] 0 " "Pin \"FL_ADDR\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[8\] 0 " "Pin \"FL_ADDR\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[9\] 0 " "Pin \"FL_ADDR\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[10\] 0 " "Pin \"FL_ADDR\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[11\] 0 " "Pin \"FL_ADDR\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[12\] 0 " "Pin \"FL_ADDR\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[13\] 0 " "Pin \"FL_ADDR\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[14\] 0 " "Pin \"FL_ADDR\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[15\] 0 " "Pin \"FL_ADDR\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[16\] 0 " "Pin \"FL_ADDR\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[17\] 0 " "Pin \"FL_ADDR\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[18\] 0 " "Pin \"FL_ADDR\[18\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[19\] 0 " "Pin \"FL_ADDR\[19\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[20\] 0 " "Pin \"FL_ADDR\[20\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_ADDR\[21\] 0 " "Pin \"FL_ADDR\[21\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_WE_N 0 " "Pin \"FL_WE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_RST_N 0 " "Pin \"FL_RST_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_OE_N 0 " "Pin \"FL_OE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "FL_CE_N 0 " "Pin \"FL_CE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[0\] 0 " "Pin \"SRAM_ADDR\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[1\] 0 " "Pin \"SRAM_ADDR\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[2\] 0 " "Pin \"SRAM_ADDR\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[3\] 0 " "Pin \"SRAM_ADDR\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[4\] 0 " "Pin \"SRAM_ADDR\[4\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[5\] 0 " "Pin \"SRAM_ADDR\[5\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[6\] 0 " "Pin \"SRAM_ADDR\[6\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[7\] 0 " "Pin \"SRAM_ADDR\[7\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[8\] 0 " "Pin \"SRAM_ADDR\[8\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[9\] 0 " "Pin \"SRAM_ADDR\[9\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[10\] 0 " "Pin \"SRAM_ADDR\[10\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[11\] 0 " "Pin \"SRAM_ADDR\[11\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[12\] 0 " "Pin \"SRAM_ADDR\[12\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[13\] 0 " "Pin \"SRAM_ADDR\[13\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[14\] 0 " "Pin \"SRAM_ADDR\[14\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[15\] 0 " "Pin \"SRAM_ADDR\[15\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[16\] 0 " "Pin \"SRAM_ADDR\[16\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_ADDR\[17\] 0 " "Pin \"SRAM_ADDR\[17\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_UB_N 0 " "Pin \"SRAM_UB_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_LB_N 0 " "Pin \"SRAM_LB_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_WE_N 0 " "Pin \"SRAM_WE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_CE_N 0 " "Pin \"SRAM_CE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SRAM_OE_N 0 " "Pin \"SRAM_OE_N\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SD_DAT3 0 " "Pin \"SD_DAT3\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SD_CMD 0 " "Pin \"SD_CMD\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "SD_CLK 0 " "Pin \"SD_CLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "TDO 0 " "Pin \"TDO\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "I2C_SCLK 0 " "Pin \"I2C_SCLK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_HS 0 " "Pin \"VGA_HS\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_VS 0 " "Pin \"VGA_VS\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_R\[0\] 0 " "Pin \"VGA_R\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_R\[1\] 0 " "Pin \"VGA_R\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_R\[2\] 0 " "Pin \"VGA_R\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_R\[3\] 0 " "Pin \"VGA_R\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_G\[0\] 0 " "Pin \"VGA_G\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_G\[1\] 0 " "Pin \"VGA_G\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_G\[2\] 0 " "Pin \"VGA_G\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_G\[3\] 0 " "Pin \"VGA_G\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_B\[0\] 0 " "Pin \"VGA_B\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_B\[1\] 0 " "Pin \"VGA_B\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_B\[2\] 0 " "Pin \"VGA_B\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "VGA_B\[3\] 0 " "Pin \"VGA_B\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_DACDAT 0 " "Pin \"AUD_DACDAT\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "AUD_XCK 0 " "Pin \"AUD_XCK\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 306007 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "Quartus II" 0 -1 1466372569301 ""}  } {  } 0 306006 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "Fitter" 0 -1 1466372569300 ""}
51
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 306005 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1466372572195 ""}
52
{ "Info" "IDAT_DAT_STARTED" "" "Started post-fitting delay annotation" {  } {  } 0 306004 "Started post-fitting delay annotation" 0 0 "Fitter" 0 -1 1466372572607 ""}
53
{ "Info" "IDAT_DAT_COMPLETED" "" "Delay annotation completed successfully" {  } {  } 0 306005 "Delay annotation completed successfully" 0 0 "Fitter" 0 -1 1466372575354 ""}
54
{ "Info" "IFITCC_FITTER_POST_OPERATION_END" "00:00:07 " "Fitter post-fit operations ending: elapsed time is 00:00:07" {  } {  } 0 11218 "Fitter post-fit operations ending: elapsed time is %1!s!" 0 0 "Fitter" 0 -1 1466372576918 ""}
55
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 176045 "Design uses memory blocks. Violating setup or hold times of memory block address registers for either read or write operations could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0 "Fitter" 0 -1 1466372577043 ""}
56
{ "Warning" "WFITCC_FITCC_IGNORED_ASSIGNMENT" "" "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." {  } {  } 0 171167 "Found invalid Fitter assignments. See the Ignored Assignments panel in the Fitter Compilation Report for more information." 0 0 "Fitter" 0 -1 1466372577481 ""}
57
{ "Warning" "WFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE" "110 " "Following 110 pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[0\] a permanently disabled " "Pin DRAM_DQ\[0\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[0] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[0\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 108 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 74 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[1\] a permanently disabled " "Pin DRAM_DQ\[1\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[1] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[1\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 108 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 73 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[2\] a permanently disabled " "Pin DRAM_DQ\[2\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[2] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[2\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 108 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 72 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[3\] a permanently disabled " "Pin DRAM_DQ\[3\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[3] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[3\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 108 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 71 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[4\] a permanently disabled " "Pin DRAM_DQ\[4\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[4] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[4\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 108 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 70 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[5\] a permanently disabled " "Pin DRAM_DQ\[5\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[5] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[5\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 108 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 69 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[6\] a permanently disabled " "Pin DRAM_DQ\[6\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[6] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[6\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 108 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 68 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[7\] a permanently disabled " "Pin DRAM_DQ\[7\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[7] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[7\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 108 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 67 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[8\] a permanently disabled " "Pin DRAM_DQ\[8\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[8] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[8\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 108 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 66 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[9\] a permanently disabled " "Pin DRAM_DQ\[9\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[9] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[9\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 108 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 65 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[10\] a permanently disabled " "Pin DRAM_DQ\[10\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[10] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[10\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 108 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 64 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[11\] a permanently disabled " "Pin DRAM_DQ\[11\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[11] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[11\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 108 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 63 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[12\] a permanently disabled " "Pin DRAM_DQ\[12\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[12] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[12\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 108 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 62 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[13\] a permanently disabled " "Pin DRAM_DQ\[13\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[13] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[13\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 108 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 61 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[14\] a permanently disabled " "Pin DRAM_DQ\[14\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[14] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[14\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 108 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 60 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "DRAM_DQ\[15\] a permanently disabled " "Pin DRAM_DQ\[15\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { DRAM_DQ[15] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "DRAM_DQ\[15\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 108 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { DRAM_DQ[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 59 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "FL_DQ\[0\] a permanently disabled " "Pin FL_DQ\[0\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { FL_DQ[0] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[0\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 122 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { FL_DQ[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 82 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "FL_DQ\[1\] a permanently disabled " "Pin FL_DQ\[1\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { FL_DQ[1] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[1\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 122 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { FL_DQ[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 81 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "FL_DQ\[2\] a permanently disabled " "Pin FL_DQ\[2\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { FL_DQ[2] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[2\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 122 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { FL_DQ[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 80 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "FL_DQ\[3\] a permanently disabled " "Pin FL_DQ\[3\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { FL_DQ[3] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[3\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 122 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { FL_DQ[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 79 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "FL_DQ\[4\] a permanently disabled " "Pin FL_DQ\[4\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { FL_DQ[4] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[4\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 122 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { FL_DQ[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 78 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "FL_DQ\[5\] a permanently disabled " "Pin FL_DQ\[5\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { FL_DQ[5] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[5\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 122 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { FL_DQ[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 77 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "FL_DQ\[6\] a permanently disabled " "Pin FL_DQ\[6\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { FL_DQ[6] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[6\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 122 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { FL_DQ[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 76 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "FL_DQ\[7\] a permanently disabled " "Pin FL_DQ\[7\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { FL_DQ[7] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "FL_DQ\[7\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 122 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { FL_DQ[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 75 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[8\] a permanently disabled " "Pin SRAM_DQ\[8\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SRAM_DQ[8] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[8\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 130 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 58 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[9\] a permanently disabled " "Pin SRAM_DQ\[9\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SRAM_DQ[9] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[9\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 130 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 57 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[10\] a permanently disabled " "Pin SRAM_DQ\[10\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SRAM_DQ[10] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[10\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 130 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 56 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[11\] a permanently disabled " "Pin SRAM_DQ\[11\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SRAM_DQ[11] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[11\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 130 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 55 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[12\] a permanently disabled " "Pin SRAM_DQ\[12\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SRAM_DQ[12] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[12\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 130 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 96 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[13\] a permanently disabled " "Pin SRAM_DQ\[13\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SRAM_DQ[13] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[13\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 130 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 107 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[14\] a permanently disabled " "Pin SRAM_DQ\[14\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SRAM_DQ[14] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[14\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 130 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 118 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "SRAM_DQ\[15\] a permanently disabled " "Pin SRAM_DQ\[15\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { SRAM_DQ[15] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "SRAM_DQ\[15\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 130 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { SRAM_DQ[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 129 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "I2C_SDAT a permanently disabled " "Pin I2C_SDAT has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { I2C_SDAT } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "I2C_SDAT" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 151 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { I2C_SDAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 293 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "PS2_DAT a permanently disabled " "Pin PS2_DAT has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { PS2_DAT } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_DAT" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 155 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PS2_DAT } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 329 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "PS2_CLK a permanently disabled " "Pin PS2_CLK has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { PS2_CLK } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "PS2_CLK" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 156 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { PS2_CLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 330 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "AUD_ADCLRCK a permanently disabled " "Pin AUD_ADCLRCK has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { AUD_ADCLRCK } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_ADCLRCK" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 166 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { AUD_ADCLRCK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 294 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "AUD_DACLRCK a permanently disabled " "Pin AUD_DACLRCK has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { AUD_DACLRCK } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_DACLRCK" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 168 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { AUD_DACLRCK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 295 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "AUD_BCLK a permanently disabled " "Pin AUD_BCLK has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { AUD_BCLK } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "AUD_BCLK" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 170 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { AUD_BCLK } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 296 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[0\] a permanently disabled " "Pin GPIO_0\[0\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[0] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[0\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 174 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 121 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[1\] a permanently disabled " "Pin GPIO_0\[1\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[1] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[1\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 174 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 120 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[2\] a permanently disabled " "Pin GPIO_0\[2\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[2] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[2\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 174 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 119 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[3\] a permanently disabled " "Pin GPIO_0\[3\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[3] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[3\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 174 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 117 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[4\] a permanently disabled " "Pin GPIO_0\[4\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[4] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[4\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 174 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 116 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[5\] a permanently disabled " "Pin GPIO_0\[5\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[5] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[5\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 174 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 115 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[6\] a permanently disabled " "Pin GPIO_0\[6\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[6] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[6\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 174 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 114 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[7\] a permanently disabled " "Pin GPIO_0\[7\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[7] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[7\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 174 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 113 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[8\] a permanently disabled " "Pin GPIO_0\[8\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[8] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[8\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 174 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 112 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[9\] a permanently disabled " "Pin GPIO_0\[9\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[9] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[9\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 174 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 111 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[10\] a permanently disabled " "Pin GPIO_0\[10\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[10] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[10\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 174 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 110 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[11\] a permanently disabled " "Pin GPIO_0\[11\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[11] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[11\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 174 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 109 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[12\] a permanently disabled " "Pin GPIO_0\[12\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[12] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[12\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 174 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 108 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[13\] a permanently disabled " "Pin GPIO_0\[13\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[13] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[13\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 174 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 106 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[14\] a permanently disabled " "Pin GPIO_0\[14\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[14] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[14\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 174 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 105 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[15\] a permanently disabled " "Pin GPIO_0\[15\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[15] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[15\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 174 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 104 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[16\] a permanently disabled " "Pin GPIO_0\[16\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[16] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[16\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 174 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 103 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[17\] a permanently disabled " "Pin GPIO_0\[17\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[17] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[17\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 174 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 102 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[18\] a permanently disabled " "Pin GPIO_0\[18\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[18] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[18\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 174 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 101 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[19\] a permanently disabled " "Pin GPIO_0\[19\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[19] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[19\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 174 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 100 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[20\] a permanently disabled " "Pin GPIO_0\[20\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[20] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[20\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 174 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 99 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[21\] a permanently disabled " "Pin GPIO_0\[21\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[21] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[21\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 174 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 98 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[22\] a permanently disabled " "Pin GPIO_0\[22\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[22] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[22\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 174 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 97 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[23\] a permanently disabled " "Pin GPIO_0\[23\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[23] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[23\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 174 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 95 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[24\] a permanently disabled " "Pin GPIO_0\[24\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[24] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[24\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 174 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[24] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 94 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[25\] a permanently disabled " "Pin GPIO_0\[25\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[25] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[25\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 174 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[25] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 93 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[26\] a permanently disabled " "Pin GPIO_0\[26\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[26] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[26\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 174 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[26] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 92 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[27\] a permanently disabled " "Pin GPIO_0\[27\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[27] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[27\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 174 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 91 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[28\] a permanently disabled " "Pin GPIO_0\[28\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[28] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[28\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 174 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 90 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[29\] a permanently disabled " "Pin GPIO_0\[29\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[29] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[29\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 174 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 89 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[30\] a permanently disabled " "Pin GPIO_0\[30\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[30] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[30\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 174 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 88 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[31\] a permanently disabled " "Pin GPIO_0\[31\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[31] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[31\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 174 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[31] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 87 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[32\] a permanently disabled " "Pin GPIO_0\[32\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[32] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[32\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 174 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[32] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 86 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[33\] a permanently disabled " "Pin GPIO_0\[33\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[33] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[33\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 174 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[33] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 85 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[34\] a permanently disabled " "Pin GPIO_0\[34\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[34] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[34\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 174 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[34] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 84 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_0\[35\] a permanently disabled " "Pin GPIO_0\[35\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_0[35] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_0\[35\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 174 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_0[35] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 83 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[0\] a permanently disabled " "Pin GPIO_1\[0\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[0] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[0\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 175 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[0] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 159 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[1\] a permanently disabled " "Pin GPIO_1\[1\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[1] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[1\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 175 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[1] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 158 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[2\] a permanently disabled " "Pin GPIO_1\[2\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[2] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[2\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 175 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[2] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 157 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[3\] a permanently disabled " "Pin GPIO_1\[3\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[3] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[3\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 175 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[3] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 156 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[4\] a permanently disabled " "Pin GPIO_1\[4\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[4] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[4\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 175 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[4] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 155 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[5\] a permanently disabled " "Pin GPIO_1\[5\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[5] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[5\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 175 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[5] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 154 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[6\] a permanently disabled " "Pin GPIO_1\[6\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[6] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[6\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 175 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[6] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 153 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[7\] a permanently disabled " "Pin GPIO_1\[7\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[7] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[7\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 175 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[7] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 152 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[8\] a permanently disabled " "Pin GPIO_1\[8\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[8] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[8\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 175 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[8] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 151 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[9\] a permanently disabled " "Pin GPIO_1\[9\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[9] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[9\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 175 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[9] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 150 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[10\] a permanently disabled " "Pin GPIO_1\[10\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[10] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[10\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 175 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[10] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 149 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[11\] a permanently disabled " "Pin GPIO_1\[11\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[11] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[11\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 175 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[11] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 148 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[12\] a permanently disabled " "Pin GPIO_1\[12\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[12] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[12\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 175 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[12] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 147 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[13\] a permanently disabled " "Pin GPIO_1\[13\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[13] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[13\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 175 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[13] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 146 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[14\] a permanently disabled " "Pin GPIO_1\[14\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[14] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[14\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 175 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[14] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 144 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[15\] a permanently disabled " "Pin GPIO_1\[15\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[15] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[15\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 175 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[15] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 143 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[16\] a permanently disabled " "Pin GPIO_1\[16\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[16] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[16\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 175 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[16] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 142 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[17\] a permanently disabled " "Pin GPIO_1\[17\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[17] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[17\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 175 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[17] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 141 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[18\] a permanently disabled " "Pin GPIO_1\[18\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[18] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[18\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 175 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[18] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 140 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[19\] a permanently disabled " "Pin GPIO_1\[19\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[19] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[19\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 175 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[19] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 139 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[20\] a permanently disabled " "Pin GPIO_1\[20\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[20] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[20\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 175 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[20] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 138 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[21\] a permanently disabled " "Pin GPIO_1\[21\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[21] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[21\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 175 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[21] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 137 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[22\] a permanently disabled " "Pin GPIO_1\[22\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[22] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[22\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 175 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[22] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 136 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[23\] a permanently disabled " "Pin GPIO_1\[23\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[23] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[23\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 175 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[23] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 135 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[24\] a permanently disabled " "Pin GPIO_1\[24\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[24] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[24\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 175 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[24] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 134 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[25\] a permanently disabled " "Pin GPIO_1\[25\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[25] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[25\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 175 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[25] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 133 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[26\] a permanently disabled " "Pin GPIO_1\[26\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[26] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[26\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 175 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[26] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 132 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[27\] a permanently disabled " "Pin GPIO_1\[27\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[27] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[27\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 175 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[27] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 131 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[28\] a permanently disabled " "Pin GPIO_1\[28\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[28] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[28\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 175 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[28] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 130 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[29\] a permanently disabled " "Pin GPIO_1\[29\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[29] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[29\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 175 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[29] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 128 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[30\] a permanently disabled " "Pin GPIO_1\[30\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[30] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[30\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 175 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[30] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 127 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[31\] a permanently disabled " "Pin GPIO_1\[31\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[31] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[31\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 175 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[31] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 126 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[32\] a permanently disabled " "Pin GPIO_1\[32\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[32] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[32\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 175 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[32] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 125 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[33\] a permanently disabled " "Pin GPIO_1\[33\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[33] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[33\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 175 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[33] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 124 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[34\] a permanently disabled " "Pin GPIO_1\[34\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[34] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[34\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 175 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[34] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 123 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""} { "Info" "IFIOMGR_BIDIR_WITH_TRIVIAL_OUTPUT_ENABLE_SUB" "GPIO_1\[35\] a permanently disabled " "Pin GPIO_1\[35\] has a permanently disabled output enable" {  } { { "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" "" { PinPlanner "c:/altera/13.0sp1/quartus/bin64/pin_planner.ppl" { GPIO_1[35] } } } { "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" "" { Assignment "c:/altera/13.0sp1/quartus/bin64/Assignment Editor.qase" 1 { { 0 "GPIO_1\[35\]" } } } } { "vhdl/z80soc.vhd" "" { Text "F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd" 175 0 0 } } { "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/13.0sp1/quartus/bin64/TimingClosureFloorplan.fld" "" "" { GPIO_1[35] } "NODE_NAME" } } { "temporary_test_loc" "" { Generic "F:/z80soc-local/hw/0.7.3/DE1/" { { 0 { 0 ""} 0 122 9224 9983 0}  }  } }  } 0 169065 "Pin %1!s! has %2!s! output enable" 0 0 "Quartus II" 0 -1 1466372577500 ""}  } {  } 0 169064 "Following %1!d! pins have no output enable or a GND or VCC output enable - later changes to this connectivity may change fitting results" 0 0 "Fitter" 0 -1 1466372577500 ""}
58
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/z80soc-local/hw/0.7.3/DE1/z80soc.fit.smsg " "Generated suppressed messages file F:/z80soc-local/hw/0.7.3/DE1/z80soc.fit.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Fitter" 0 -1 1466372578678 ""}
59
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 14 s Quartus II 64-Bit " "Quartus II 64-Bit Fitter was successful. 0 errors, 14 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "659 " "Peak virtual memory: 659 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Quartus II" 0 -1 1466372580956 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Jun 19 14:43:00 2016 " "Processing ended: Sun Jun 19 14:43:00 2016" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Quartus II" 0 -1 1466372580956 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:57 " "Elapsed time: 00:00:57" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Quartus II" 0 -1 1466372580956 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:41 " "Total CPU time (on all processors): 00:00:41" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Quartus II" 0 -1 1466372580956 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Fitter" 0 -1 1466372580956 ""}

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