OpenCores
URL https://opencores.org/ocsvn/z80soc/z80soc/trunk

Subversion Repositories z80soc

[/] [z80soc/] [trunk/] [V0.7.3/] [DE1/] [vhdl/] [SSRAMX.vhd] - Blame information for rev 46

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 46 rrred
--
2
-- Xilinx Block RAM, 8 bit wide and variable size (Min. 512 bytes)
3
--
4
-- Version : 0247
5
--
6
-- Copyright (c) 2002 Daniel Wallner (jesus@opencores.org)
7
--
8
-- All rights reserved
9
--
10
-- Redistribution and use in source and synthezised forms, with or without
11
-- modification, are permitted provided that the following conditions are met:
12
--
13
-- Redistributions of source code must retain the above copyright notice,
14
-- this list of conditions and the following disclaimer.
15
--
16
-- Redistributions in synthesized form must reproduce the above copyright
17
-- notice, this list of conditions and the following disclaimer in the
18
-- documentation and/or other materials provided with the distribution.
19
--
20
-- Neither the name of the author nor the names of other contributors may
21
-- be used to endorse or promote products derived from this software without
22
-- specific prior written permission.
23
--
24
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
26
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
27
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
28
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
29
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
30
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
31
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
32
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
34
-- POSSIBILITY OF SUCH DAMAGE.
35
--
36
-- Please report bugs to the author, but before you do so, please
37
-- make sure that this is not a derivative work and that
38
-- you have the latest version of this file.
39
--
40
-- The latest version of this file can be found at:
41
--      http://www.opencores.org/cvsweb.shtml/t51/
42
--
43
-- Limitations :
44
--
45
-- File history :
46
--
47
--      0240 : Initial release
48
--
49
--      0242 : Changed RAMB4_S8 to map by name
50
--
51
--      0247 : Added RAMB4_S8 component declaration
52
--
53
 
54
library IEEE;
55
use IEEE.std_logic_1164.all;
56
use IEEE.numeric_std.all;
57
 
58
entity SSRAM is
59
        generic(
60
                AddrWidth       : integer := 11;
61
                DataWidth       : integer := 8
62
        );
63
        port(
64
                Clk                     : in std_logic;
65
                CE_n            : in std_logic;
66
                WE_n            : in std_logic;
67
                A                       : in std_logic_vector(AddrWidth - 1 downto 0);
68
                DIn                     : in std_logic_vector(DataWidth - 1 downto 0);
69
                DOut            : out std_logic_vector(DataWidth - 1 downto 0)
70
        );
71
end SSRAM;
72
 
73
architecture rtl of SSRAM is
74
 
75
        component RAMB4_S8
76
                port(
77
                        DO     : out std_logic_vector(7 downto 0);
78
                        ADDR   : in std_logic_vector(8 downto 0);
79
                        CLK    : in std_ulogic;
80
                        DI     : in std_logic_vector(7 downto 0);
81
                        EN     : in std_ulogic;
82
                        RST    : in std_ulogic;
83
                        WE     : in std_ulogic);
84
        end component;
85
 
86
        constant RAMs : integer := (2 ** AddrWidth) / 512;
87
 
88
        type bRAMOut_a is array(0 to RAMs - 1) of std_logic_vector(7 downto 0);
89
 
90
        signal bRAMOut : bRAMOut_a;
91
        signal biA_r : integer;
92
        signal A_r : unsigned(A'left downto 0);
93
--      signal A_i : std_logic_vector(8 downto 0);
94
        signal WEA : std_logic_vector(RAMs - 1 downto 0);
95
 
96
begin
97
 
98
        process (Clk)
99
        begin
100
                if Clk'event and Clk = '1' then
101
                        A_r <= unsigned(A);
102
                end if;
103
        end process;
104
 
105
        biA_r <= to_integer(A_r(A'left downto 9));
106
--      A_i <= std_logic_vector(A_r(8 downto 0)) when (CE_n nor WE_n) = '1' else A(8 downto 0);
107
 
108
        bG1: for I in 0 to RAMs - 1 generate
109
        begin
110
                WEA(I) <= '1' when (CE_n nor WE_n) = '1' and biA_r = I else '0';
111
                BSSRAM : RAMB4_S8
112
                        port map(
113
                                DI => DIn,
114
                                EN => '1',
115
                                WE => WEA(I),
116
                                RST => '0',
117
                                CLK => Clk,
118
                                ADDR => A,
119
                                DO => bRAMOut(I));
120
        end generate;
121
 
122
        process (biA_r, bRAMOut)
123
        begin
124
                DOut <= bRAMOut(0);
125
                for I in 1 to RAMs - 1 loop
126
                        if biA_r = I then
127
                                DOut <= bRAMOut(I);
128
                        end if;
129
                end loop;
130
        end process;
131
 
132
end;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.