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[/] [z80soc/] [trunk/] [V0.7.3/] [DE1/] [vhdl/] [decoder_7seg.vhd] - Blame information for rev 46

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Line No. Rev Author Line
1 46 rrred
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-- This design is part of:
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-- Z80SoC (Z80 System on Chip)
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-- Ronivon Candido Costa
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-- ronivon.costa@gmail.com
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--
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LIBRARY IEEE;
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USE  IEEE.STD_LOGIC_1164.all;
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USE  IEEE.STD_LOGIC_UNSIGNED.all;
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entity decoder_7seg is
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        port
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        (
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                NUMBER          : in   std_logic_vector(3 downto 0);
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                HEX_DISP        : out  std_logic_vector(6 downto 0)
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        );
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end decoder_7seg;
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architecture rtl of decoder_7seg is
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begin
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process(NUMBER)
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begin
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        case NUMBER is
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                --0 to 9
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                when "0000" => HEX_DISP <= "1000000";
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                when "0001" => HEX_DISP <= "1111001";
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                when "0010" => HEX_DISP <= "0100100";
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                when "0011" => HEX_DISP <= "0110000";
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                when "0100" => HEX_DISP <= "0011001";
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                when "0101" => HEX_DISP <= "0010010";
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                when "0110" => HEX_DISP <= "0000011";
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                when "0111" => HEX_DISP <= "1111000";
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                when "1000" => HEX_DISP <= "0000000";
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                when "1001" => HEX_DISP <= "0011000";
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                -- A to F
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                when "1010" => HEX_DISP <= "0001000";
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                when "1011" => HEX_DISP <= "0000011";
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                when "1100" => HEX_DISP <= "1000110";
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                when "1101" => HEX_DISP <= "0100001";
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                when "1110" => HEX_DISP <= "0000110";
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                when "1111" => HEX_DISP <= "0001110";
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                when others => HEX_DISP <= "1111111";
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        end case;
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end process;
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end rtl;
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