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[/] [z80soc/] [trunk/] [V0.7.3/] [DE1/] [z80soc.map.rpt] - Blame information for rev 46

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1 46 rrred
Analysis & Synthesis report for z80soc
2
Sun Jun 19 14:41:59 2016
3
Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
4
 
5
 
6
---------------------
7
; Table of Contents ;
8
---------------------
9
  1. Legal Notice
10
  2. Analysis & Synthesis Summary
11
  3. Analysis & Synthesis Settings
12
  4. Parallel Compilation
13
  5. Analysis & Synthesis Source Files Read
14
  6. Analysis & Synthesis Resource Usage Summary
15
  7. Analysis & Synthesis Resource Utilization by Entity
16
  8. Analysis & Synthesis RAM Summary
17
  9. Analysis & Synthesis IP Cores Summary
18
 10. Registers Removed During Synthesis
19
 11. Removed Registers Triggering Further Register Optimizations
20
 12. General Register Statistics
21
 13. Inverted Register Statistics
22
 14. Multiplexer Restructuring Statistics (Restructuring Performed)
23
 15. Source assignments for vram:vram_inst|altsyncram:altsyncram_component|altsyncram_66l1:auto_generated
24
 16. Source assignments for vram:vram_inst|altsyncram:altsyncram_component|altsyncram_66l1:auto_generated|altsyncram_pal1:altsyncram1
25
 17. Source assignments for charram:cram|altsyncram:altsyncram_component|altsyncram_h1o1:auto_generated
26
 18. Source assignments for charram:cram|altsyncram:altsyncram_component|altsyncram_h1o1:auto_generated|altsyncram_36o1:altsyncram1
27
 19. Source assignments for rom:rom_inst|altsyncram:altsyncram_component|altsyncram_tr91:auto_generated
28
 20. Parameter Settings for User Entity Instance: T80se:z80_inst
29
 21. Parameter Settings for User Entity Instance: T80se:z80_inst|T80:u0
30
 22. Parameter Settings for User Entity Instance: T80se:z80_inst|T80:u0|T80_MCode:mcode
31
 23. Parameter Settings for User Entity Instance: T80se:z80_inst|T80:u0|T80_ALU:alu
32
 24. Parameter Settings for User Entity Instance: vram:vram_inst|altsyncram:altsyncram_component
33
 25. Parameter Settings for User Entity Instance: charram:cram|altsyncram:altsyncram_component
34
 26. Parameter Settings for User Entity Instance: rom:rom_inst|altsyncram:altsyncram_component
35
 27. altsyncram Parameter Settings by Entity Instance
36
 28. Port Connectivity Checks: "clk_div:clkdiv_inst"
37
 29. Port Connectivity Checks: "video:video_inst|VGA_SYNC:vga_sync_inst"
38
 30. Port Connectivity Checks: "video:video_inst"
39
 31. Port Connectivity Checks: "T80se:z80_inst|T80:u0"
40
 32. Port Connectivity Checks: "T80se:z80_inst"
41
 33. Elapsed Time Per Partition
42
 34. Analysis & Synthesis Messages
43
 
44
 
45
 
46
----------------
47
; Legal Notice ;
48
----------------
49
Copyright (C) 1991-2013 Altera Corporation
50
Your use of Altera Corporation's design tools, logic functions
51
and other software and tools, and its AMPP partner logic
52
functions, and any output files from any of the foregoing
53
(including device programming or simulation files), and any
54
associated documentation or information are expressly subject
55
to the terms and conditions of the Altera Program License
56
Subscription Agreement, Altera MegaCore Function License
57
Agreement, or other applicable license agreement, including,
58
without limitation, that your use is for the sole purpose of
59
programming logic devices manufactured by Altera and sold by
60
Altera or its authorized distributors.  Please refer to the
61
applicable agreement for further details.
62
 
63
 
64
 
65
+--------------------------------------------------------------------------------------+
66
; Analysis & Synthesis Summary                                                         ;
67
+------------------------------------+-------------------------------------------------+
68
; Analysis & Synthesis Status        ; Successful - Sun Jun 19 14:41:59 2016           ;
69
; Quartus II 64-Bit Version          ; 13.0.1 Build 232 06/12/2013 SP 1 SJ Web Edition ;
70
; Revision Name                      ; z80soc                                          ;
71
; Top-level Entity Name              ; Z80SOC                                          ;
72
; Family                             ; Cyclone II                                      ;
73
; Total logic elements               ; 2,705                                           ;
74
;     Total combinational functions  ; 2,464                                           ;
75
;     Dedicated logic registers      ; 535                                             ;
76
; Total registers                    ; 535                                             ;
77
; Total pins                         ; 281                                             ;
78
; Total virtual pins                 ; 0                                               ;
79
; Total memory bits                  ; 196,600                                         ;
80
; Embedded Multiplier 9-bit elements ; 0                                               ;
81
; Total PLLs                         ; 0                                               ;
82
+------------------------------------+-------------------------------------------------+
83
 
84
 
85
+----------------------------------------------------------------------------------------------------------------------+
86
; Analysis & Synthesis Settings                                                                                        ;
87
+----------------------------------------------------------------------------+--------------------+--------------------+
88
; Option                                                                     ; Setting            ; Default Value      ;
89
+----------------------------------------------------------------------------+--------------------+--------------------+
90
; Device                                                                     ; EP2C20F484C7       ;                    ;
91
; Top-level entity name                                                      ; z80soc             ; z80soc             ;
92
; Family name                                                                ; Cyclone II         ; Cyclone IV GX      ;
93
; Use smart compilation                                                      ; On                 ; Off                ;
94
; Auto Shift Register Replacement                                            ; Off                ; Auto               ;
95
; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On                 ; On                 ;
96
; Enable compact report table                                                ; Off                ; Off                ;
97
; Restructure Multiplexers                                                   ; Auto               ; Auto               ;
98
; Create Debugging Nodes for IP Cores                                        ; Off                ; Off                ;
99
; Preserve fewer node names                                                  ; On                 ; On                 ;
100
; Disable OpenCore Plus hardware evaluation                                  ; Off                ; Off                ;
101
; Verilog Version                                                            ; Verilog_2001       ; Verilog_2001       ;
102
; VHDL Version                                                               ; VHDL_1993          ; VHDL_1993          ;
103
; State Machine Processing                                                   ; Auto               ; Auto               ;
104
; Safe State Machine                                                         ; Off                ; Off                ;
105
; Extract Verilog State Machines                                             ; On                 ; On                 ;
106
; Extract VHDL State Machines                                                ; On                 ; On                 ;
107
; Ignore Verilog initial constructs                                          ; Off                ; Off                ;
108
; Iteration limit for constant Verilog loops                                 ; 5000               ; 5000               ;
109
; Iteration limit for non-constant Verilog loops                             ; 250                ; 250                ;
110
; Add Pass-Through Logic to Inferred RAMs                                    ; On                 ; On                 ;
111
; Infer RAMs from Raw Logic                                                  ; On                 ; On                 ;
112
; Parallel Synthesis                                                         ; On                 ; On                 ;
113
; DSP Block Balancing                                                        ; Auto               ; Auto               ;
114
; NOT Gate Push-Back                                                         ; On                 ; On                 ;
115
; Power-Up Don't Care                                                        ; On                 ; On                 ;
116
; Remove Redundant Logic Cells                                               ; Off                ; Off                ;
117
; Remove Duplicate Registers                                                 ; On                 ; On                 ;
118
; Ignore CARRY Buffers                                                       ; Off                ; Off                ;
119
; Ignore CASCADE Buffers                                                     ; Off                ; Off                ;
120
; Ignore GLOBAL Buffers                                                      ; Off                ; Off                ;
121
; Ignore ROW GLOBAL Buffers                                                  ; Off                ; Off                ;
122
; Ignore LCELL Buffers                                                       ; Off                ; Off                ;
123
; Ignore SOFT Buffers                                                        ; On                 ; On                 ;
124
; Limit AHDL Integers to 32 Bits                                             ; Off                ; Off                ;
125
; Optimization Technique                                                     ; Balanced           ; Balanced           ;
126
; Carry Chain Length                                                         ; 70                 ; 70                 ;
127
; Auto Carry Chains                                                          ; On                 ; On                 ;
128
; Auto Open-Drain Pins                                                       ; On                 ; On                 ;
129
; Perform WYSIWYG Primitive Resynthesis                                      ; Off                ; Off                ;
130
; Auto ROM Replacement                                                       ; On                 ; On                 ;
131
; Auto RAM Replacement                                                       ; On                 ; On                 ;
132
; Allow Shift Register Merging across Hierarchies                            ; Auto               ; Auto               ;
133
; Auto Clock Enable Replacement                                              ; On                 ; On                 ;
134
; Strict RAM Replacement                                                     ; Off                ; Off                ;
135
; Allow Synchronous Control Signals                                          ; On                 ; On                 ;
136
; Force Use of Synchronous Clear Signals                                     ; Off                ; Off                ;
137
; Auto RAM to Logic Cell Conversion                                          ; Off                ; Off                ;
138
; Auto Resource Sharing                                                      ; Off                ; Off                ;
139
; Allow Any RAM Size For Recognition                                         ; Off                ; Off                ;
140
; Allow Any ROM Size For Recognition                                         ; Off                ; Off                ;
141
; Allow Any Shift Register Size For Recognition                              ; Off                ; Off                ;
142
; Use LogicLock Constraints during Resource Balancing                        ; On                 ; On                 ;
143
; Ignore translate_off and synthesis_off directives                          ; Off                ; Off                ;
144
; Timing-Driven Synthesis                                                    ; Off                ; Off                ;
145
; Report Parameter Settings                                                  ; On                 ; On                 ;
146
; Report Source Assignments                                                  ; On                 ; On                 ;
147
; Report Connectivity Checks                                                 ; On                 ; On                 ;
148
; Ignore Maximum Fan-Out Assignments                                         ; Off                ; Off                ;
149
; Synchronization Register Chain Length                                      ; 2                  ; 2                  ;
150
; PowerPlay Power Optimization                                               ; Normal compilation ; Normal compilation ;
151
; HDL message level                                                          ; Level2             ; Level2             ;
152
; Suppress Register Optimization Related Messages                            ; Off                ; Off                ;
153
; Number of Removed Registers Reported in Synthesis Report                   ; 5000               ; 5000               ;
154
; Number of Swept Nodes Reported in Synthesis Report                         ; 5000               ; 5000               ;
155
; Number of Inverted Registers Reported in Synthesis Report                  ; 100                ; 100                ;
156
; Clock MUX Protection                                                       ; On                 ; On                 ;
157
; Auto Gated Clock Conversion                                                ; Off                ; Off                ;
158
; Block Design Naming                                                        ; Auto               ; Auto               ;
159
; SDC constraint protection                                                  ; Off                ; Off                ;
160
; Synthesis Effort                                                           ; Auto               ; Auto               ;
161
; Shift Register Replacement - Allow Asynchronous Clear Signal               ; On                 ; On                 ;
162
; Pre-Mapping Resynthesis Optimization                                       ; Off                ; Off                ;
163
; Analysis & Synthesis Message Level                                         ; Medium             ; Medium             ;
164
; Disable Register Merging Across Hierarchies                                ; Auto               ; Auto               ;
165
; Resource Aware Inference For Block RAM                                     ; On                 ; On                 ;
166
; Synthesis Seed                                                             ; 1                  ; 1                  ;
167
+----------------------------------------------------------------------------+--------------------+--------------------+
168
 
169
 
170
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
171
+-------------------------------------+
172
; Parallel Compilation                ;
173
+----------------------------+--------+
174
; Processors                 ; Number ;
175
+----------------------------+--------+
176
; Number detected on machine ; 2      ;
177
; Maximum allowed            ; 1      ;
178
+----------------------------+--------+
179
 
180
 
181
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
182
; Analysis & Synthesis Source Files Read                                                                                                                                          ;
183
+----------------------------------+-----------------+----------------------------------------+-------------------------------------------------------------------------+---------+
184
; File Name with User-Entered Path ; Used in Netlist ; File Type                              ; File Name with Absolute Path                                            ; Library ;
185
+----------------------------------+-----------------+----------------------------------------+-------------------------------------------------------------------------+---------+
186
; memoryCores/vram.vhd             ; yes             ; User Wizard-Generated File             ; F:/z80soc-local/hw/0.7.3/DE1/memoryCores/vram.vhd                       ;         ;
187
; memoryCores/charram.vhd          ; yes             ; User Wizard-Generated File             ; F:/z80soc-local/hw/0.7.3/DE1/memoryCores/charram.vhd                    ;         ;
188
; memoryCores/rom.vhd              ; yes             ; User Wizard-Generated File             ; F:/z80soc-local/hw/0.7.3/DE1/memoryCores/rom.vhd                        ;         ;
189
; vhdl/keyboard.VHD                ; yes             ; User VHDL File                         ; F:/z80soc-local/hw/0.7.3/DE1/vhdl/keyboard.VHD                          ;         ;
190
; vhdl/ps2bkd.vhd                  ; yes             ; User VHDL File                         ; F:/z80soc-local/hw/0.7.3/DE1/vhdl/ps2bkd.vhd                            ;         ;
191
; vhdl/T80.vhd                     ; yes             ; User VHDL File                         ; F:/z80soc-local/hw/0.7.3/DE1/vhdl/T80.vhd                               ;         ;
192
; vhdl/T80_ALU.vhd                 ; yes             ; User VHDL File                         ; F:/z80soc-local/hw/0.7.3/DE1/vhdl/T80_ALU.vhd                           ;         ;
193
; vhdl/T80_MCode.vhd               ; yes             ; User VHDL File                         ; F:/z80soc-local/hw/0.7.3/DE1/vhdl/T80_MCode.vhd                         ;         ;
194
; vhdl/T80_Pack.vhd                ; yes             ; User VHDL File                         ; F:/z80soc-local/hw/0.7.3/DE1/vhdl/T80_Pack.vhd                          ;         ;
195
; vhdl/T80_Reg.vhd                 ; yes             ; User VHDL File                         ; F:/z80soc-local/hw/0.7.3/DE1/vhdl/T80_Reg.vhd                           ;         ;
196
; vhdl/T80se.vhd                   ; yes             ; User VHDL File                         ; F:/z80soc-local/hw/0.7.3/DE1/vhdl/T80se.vhd                             ;         ;
197
; vhdl/video.vhd                   ; yes             ; User VHDL File                         ; F:/z80soc-local/hw/0.7.3/DE1/vhdl/video.vhd                             ;         ;
198
; vhdl/clk_div.vhd                 ; yes             ; User VHDL File                         ; F:/z80soc-local/hw/0.7.3/DE1/vhdl/clk_div.vhd                           ;         ;
199
; vhdl/decoder_7seg.vhd            ; yes             ; User VHDL File                         ; F:/z80soc-local/hw/0.7.3/DE1/vhdl/decoder_7seg.vhd                      ;         ;
200
; vhdl/z80soc.vhd                  ; yes             ; User VHDL File                         ; F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc.vhd                            ;         ;
201
; vhdl/vga_sync.vhd                ; yes             ; User VHDL File                         ; F:/z80soc-local/hw/0.7.3/DE1/vhdl/vga_sync.vhd                          ;         ;
202
; vhdl/z80soc_pack.vhd             ; yes             ; User VHDL File                         ; F:/z80soc-local/hw/0.7.3/DE1/vhdl/z80soc_pack.vhd                       ;         ;
203
; altsyncram.tdf                   ; yes             ; Megafunction                           ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altsyncram.tdf        ;         ;
204
; stratix_ram_block.inc            ; yes             ; Megafunction                           ; c:/altera/13.0sp1/quartus/libraries/megafunctions/stratix_ram_block.inc ;         ;
205
; lpm_mux.inc                      ; yes             ; Megafunction                           ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_mux.inc           ;         ;
206
; lpm_decode.inc                   ; yes             ; Megafunction                           ; c:/altera/13.0sp1/quartus/libraries/megafunctions/lpm_decode.inc        ;         ;
207
; aglobal130.inc                   ; yes             ; Megafunction                           ; c:/altera/13.0sp1/quartus/libraries/megafunctions/aglobal130.inc        ;         ;
208
; a_rdenreg.inc                    ; yes             ; Megafunction                           ; c:/altera/13.0sp1/quartus/libraries/megafunctions/a_rdenreg.inc         ;         ;
209
; altrom.inc                       ; yes             ; Megafunction                           ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altrom.inc            ;         ;
210
; altram.inc                       ; yes             ; Megafunction                           ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altram.inc            ;         ;
211
; altdpram.inc                     ; yes             ; Megafunction                           ; c:/altera/13.0sp1/quartus/libraries/megafunctions/altdpram.inc          ;         ;
212
; db/altsyncram_66l1.tdf           ; yes             ; Auto-Generated Megafunction            ; F:/z80soc-local/hw/0.7.3/DE1/db/altsyncram_66l1.tdf                     ;         ;
213
; db/altsyncram_pal1.tdf           ; yes             ; Auto-Generated Megafunction            ; F:/z80soc-local/hw/0.7.3/DE1/db/altsyncram_pal1.tdf                     ;         ;
214
; db/decode_1oa.tdf                ; yes             ; Auto-Generated Megafunction            ; F:/z80soc-local/hw/0.7.3/DE1/db/decode_1oa.tdf                          ;         ;
215
; db/mux_hib.tdf                   ; yes             ; Auto-Generated Megafunction            ; F:/z80soc-local/hw/0.7.3/DE1/db/mux_hib.tdf                             ;         ;
216
; db/altsyncram_h1o1.tdf           ; yes             ; Auto-Generated Megafunction            ; F:/z80soc-local/hw/0.7.3/DE1/db/altsyncram_h1o1.tdf                     ;         ;
217
; db/altsyncram_36o1.tdf           ; yes             ; Auto-Generated Megafunction            ; F:/z80soc-local/hw/0.7.3/DE1/db/altsyncram_36o1.tdf                     ;         ;
218
; ../ROMdata/lat9-08.mif           ; yes             ; Auto-Found Memory Initialization File  ; F:/z80soc-local/hw/0.7.3/ROMdata/lat9-08.mif                            ;         ;
219
; db/altsyncram_tr91.tdf           ; yes             ; Auto-Generated Megafunction            ; F:/z80soc-local/hw/0.7.3/DE1/db/altsyncram_tr91.tdf                     ;         ;
220
; ../ROMdata/rom.hex               ; yes             ; Auto-Found Memory Initialization File  ; F:/z80soc-local/hw/0.7.3/ROMdata/rom.hex                                ;         ;
221
; db/decode_4oa.tdf                ; yes             ; Auto-Generated Megafunction            ; F:/z80soc-local/hw/0.7.3/DE1/db/decode_4oa.tdf                          ;         ;
222
; db/mux_kib.tdf                   ; yes             ; Auto-Generated Megafunction            ; F:/z80soc-local/hw/0.7.3/DE1/db/mux_kib.tdf                             ;         ;
223
+----------------------------------+-----------------+----------------------------------------+-------------------------------------------------------------------------+---------+
224
 
225
 
226
+-------------------------------------------------------+
227
; Analysis & Synthesis Resource Usage Summary           ;
228
+---------------------------------------------+---------+
229
; Resource                                    ; Usage   ;
230
+---------------------------------------------+---------+
231
; Estimated Total logic elements              ; 2,705   ;
232
;                                             ;         ;
233
; Total combinational functions               ; 2464    ;
234
; Logic element usage by number of LUT inputs ;         ;
235
;     -- 4 input functions                    ; 1731    ;
236
;     -- 3 input functions                    ; 454     ;
237
;     -- <=2 input functions                  ; 279     ;
238
;                                             ;         ;
239
; Logic elements by mode                      ;         ;
240
;     -- normal mode                          ; 2278    ;
241
;     -- arithmetic mode                      ; 186     ;
242
;                                             ;         ;
243
; Total registers                             ; 535     ;
244
;     -- Dedicated logic registers            ; 535     ;
245
;     -- I/O registers                        ; 0       ;
246
;                                             ;         ;
247
; I/O pins                                    ; 281     ;
248
; Total memory bits                           ; 196600  ;
249
; Embedded Multiplier 9-bit elements          ; 0       ;
250
; Maximum fan-out node                        ; Clk_Z80 ;
251
; Maximum fan-out                             ; 409     ;
252
; Total fan-out                               ; 11670   ;
253
; Average fan-out                             ; 3.50    ;
254
+---------------------------------------------+---------+
255
 
256
 
257
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
258
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                                                         ;
259
+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------+--------------+
260
; Compilation Hierarchy Node                ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                                                                  ; Library Name ;
261
+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------+--------------+
262
; |Z80SOC                                   ; 2464 (110)        ; 535 (65)     ; 196600      ; 0            ; 0       ; 0         ; 281  ; 0            ; |Z80SOC                                                                                                                              ; work         ;
263
;    |T80se:z80_inst|                       ; 2037 (10)         ; 345 (12)     ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Z80SOC|T80se:z80_inst                                                                                                               ; work         ;
264
;       |T80:u0|                            ; 2027 (838)        ; 333 (205)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Z80SOC|T80se:z80_inst|T80:u0                                                                                                        ; work         ;
265
;          |T80_ALU:alu|                    ; 458 (458)         ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Z80SOC|T80se:z80_inst|T80:u0|T80_ALU:alu                                                                                            ; work         ;
266
;          |T80_MCode:mcode|                ; 475 (475)         ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Z80SOC|T80se:z80_inst|T80:u0|T80_MCode:mcode                                                                                        ; work         ;
267
;          |T80_Reg:Regs|                   ; 256 (256)         ; 128 (128)    ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Z80SOC|T80se:z80_inst|T80:u0|T80_Reg:Regs                                                                                           ; work         ;
268
;    |charram:cram|                         ; 0 (0)             ; 0 (0)        ; 16384       ; 0            ; 0       ; 0         ; 0    ; 0            ; |Z80SOC|charram:cram                                                                                                                 ; work         ;
269
;       |altsyncram:altsyncram_component|   ; 0 (0)             ; 0 (0)        ; 16384       ; 0            ; 0       ; 0         ; 0    ; 0            ; |Z80SOC|charram:cram|altsyncram:altsyncram_component                                                                                 ; work         ;
270
;          |altsyncram_h1o1:auto_generated| ; 0 (0)             ; 0 (0)        ; 16384       ; 0            ; 0       ; 0         ; 0    ; 0            ; |Z80SOC|charram:cram|altsyncram:altsyncram_component|altsyncram_h1o1:auto_generated                                                  ; work         ;
271
;             |altsyncram_36o1:altsyncram1| ; 0 (0)             ; 0 (0)        ; 16384       ; 0            ; 0       ; 0         ; 0    ; 0            ; |Z80SOC|charram:cram|altsyncram:altsyncram_component|altsyncram_h1o1:auto_generated|altsyncram_36o1:altsyncram1                      ; work         ;
272
;    |clk_div:clkdiv_inst|                  ; 33 (33)           ; 36 (36)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Z80SOC|clk_div:clkdiv_inst                                                                                                          ; work         ;
273
;    |decoder_7seg:DISPHEX0|                ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Z80SOC|decoder_7seg:DISPHEX0                                                                                                        ; work         ;
274
;    |decoder_7seg:DISPHEX1|                ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Z80SOC|decoder_7seg:DISPHEX1                                                                                                        ; work         ;
275
;    |decoder_7seg:DISPHEX2|                ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Z80SOC|decoder_7seg:DISPHEX2                                                                                                        ; work         ;
276
;    |decoder_7seg:DISPHEX3|                ; 7 (7)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Z80SOC|decoder_7seg:DISPHEX3                                                                                                        ; work         ;
277
;    |ps2kbd:ps2_kbd_inst|                  ; 144 (128)         ; 35 (2)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Z80SOC|ps2kbd:ps2_kbd_inst                                                                                                          ; work         ;
278
;       |keyboard:kbd_inst|                 ; 16 (16)           ; 33 (33)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Z80SOC|ps2kbd:ps2_kbd_inst|keyboard:kbd_inst                                                                                        ; work         ;
279
;    |rom:rom_inst|                         ; 20 (0)            ; 4 (0)        ; 131072      ; 0            ; 0       ; 0         ; 0    ; 0            ; |Z80SOC|rom:rom_inst                                                                                                                 ; work         ;
280
;       |altsyncram:altsyncram_component|   ; 20 (0)            ; 4 (0)        ; 131072      ; 0            ; 0       ; 0         ; 0    ; 0            ; |Z80SOC|rom:rom_inst|altsyncram:altsyncram_component                                                                                 ; work         ;
281
;          |altsyncram_tr91:auto_generated| ; 20 (0)            ; 4 (4)        ; 131072      ; 0            ; 0       ; 0         ; 0    ; 0            ; |Z80SOC|rom:rom_inst|altsyncram:altsyncram_component|altsyncram_tr91:auto_generated                                                  ; work         ;
282
;             |decode_4oa:deep_decode|      ; 4 (4)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Z80SOC|rom:rom_inst|altsyncram:altsyncram_component|altsyncram_tr91:auto_generated|decode_4oa:deep_decode                           ; work         ;
283
;             |mux_kib:mux2|                ; 16 (16)           ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Z80SOC|rom:rom_inst|altsyncram:altsyncram_component|altsyncram_tr91:auto_generated|mux_kib:mux2                                     ; work         ;
284
;    |video:video_inst|                     ; 80 (22)           ; 49 (0)       ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Z80SOC|video:video_inst                                                                                                             ; work         ;
285
;       |VGA_SYNC:vga_sync_inst|            ; 58 (58)           ; 49 (49)      ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Z80SOC|video:video_inst|VGA_SYNC:vga_sync_inst                                                                                      ; work         ;
286
;    |vram:vram_inst|                       ; 12 (0)            ; 1 (0)        ; 49144       ; 0            ; 0       ; 0         ; 0    ; 0            ; |Z80SOC|vram:vram_inst                                                                                                               ; work         ;
287
;       |altsyncram:altsyncram_component|   ; 12 (0)            ; 1 (0)        ; 49144       ; 0            ; 0       ; 0         ; 0    ; 0            ; |Z80SOC|vram:vram_inst|altsyncram:altsyncram_component                                                                               ; work         ;
288
;          |altsyncram_66l1:auto_generated| ; 12 (0)            ; 1 (0)        ; 49144       ; 0            ; 0       ; 0         ; 0    ; 0            ; |Z80SOC|vram:vram_inst|altsyncram:altsyncram_component|altsyncram_66l1:auto_generated                                                ; work         ;
289
;             |altsyncram_pal1:altsyncram1| ; 12 (0)            ; 1 (1)        ; 49144       ; 0            ; 0       ; 0         ; 0    ; 0            ; |Z80SOC|vram:vram_inst|altsyncram:altsyncram_component|altsyncram_66l1:auto_generated|altsyncram_pal1:altsyncram1                    ; work         ;
290
;                |decode_1oa:decode4|       ; 4 (4)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Z80SOC|vram:vram_inst|altsyncram:altsyncram_component|altsyncram_66l1:auto_generated|altsyncram_pal1:altsyncram1|decode_1oa:decode4 ; work         ;
291
;                |mux_hib:mux5|             ; 8 (8)             ; 0 (0)        ; 0           ; 0            ; 0       ; 0         ; 0    ; 0            ; |Z80SOC|vram:vram_inst|altsyncram:altsyncram_component|altsyncram_66l1:auto_generated|altsyncram_pal1:altsyncram1|mux_hib:mux5       ; work         ;
292
+-------------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------------------------------------------------+--------------+
293
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
294
 
295
 
296
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
297
; Analysis & Synthesis RAM Summary                                                                                                                                                                                                           ;
298
+----------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+--------+------------------------+
299
; Name                                                                                                                 ; Type ; Mode           ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size   ; MIF                    ;
300
+----------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+--------+------------------------+
301
; charram:cram|altsyncram:altsyncram_component|altsyncram_h1o1:auto_generated|altsyncram_36o1:altsyncram1|ALTSYNCRAM   ; AUTO ; True Dual Port ; 2048         ; 8            ; 2048         ; 8            ; 16384  ; ../ROMdata/lat9-08.mif ;
302
; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_tr91:auto_generated|ALTSYNCRAM                               ; AUTO ; ROM            ; 16384        ; 8            ; --           ; --           ; 131072 ; ../ROMdata/rom.hex     ;
303
; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_66l1:auto_generated|altsyncram_pal1:altsyncram1|ALTSYNCRAM ; AUTO ; True Dual Port ; 6143         ; 8            ; 6143         ; 8            ; 49144  ; None                   ;
304
+----------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+--------+------------------------+
305
 
306
 
307
+-----------------------------------------------------------------------------------------------------------------------------------------------+
308
; Analysis & Synthesis IP Cores Summary                                                                                                         ;
309
+--------+--------------+---------+--------------+--------------+------------------------+------------------------------------------------------+
310
; Vendor ; IP Core Name ; Version ; Release Date ; License Type ; Entity Instance        ; IP Include File                                      ;
311
+--------+--------------+---------+--------------+--------------+------------------------+------------------------------------------------------+
312
; Altera ; RAM: 2-PORT  ; N/A     ; N/A          ; N/A          ; |Z80SOC|charram:cram   ; F:/z80soc-local/hw/0.7.3/DE1/memoryCores/charram.vhd ;
313
; Altera ; ROM: 1-PORT  ; N/A     ; N/A          ; N/A          ; |Z80SOC|rom:rom_inst   ; F:/z80soc-local/hw/0.7.3/DE1/memoryCores/rom.vhd     ;
314
; Altera ; RAM: 2-PORT  ; N/A     ; N/A          ; N/A          ; |Z80SOC|vram:vram_inst ; F:/z80soc-local/hw/0.7.3/DE1/memoryCores/vram.vhd    ;
315
+--------+--------------+---------+--------------+--------------+------------------------+------------------------------------------------------+
316
 
317
 
318
+----------------------------------------------------------------------------------------------------------+
319
; Registers Removed During Synthesis                                                                       ;
320
+---------------------------------------------------------+------------------------------------------------+
321
; Register name                                           ; Reason for Removal                             ;
322
+---------------------------------------------------------+------------------------------------------------+
323
; video:video_inst|VGA_SYNC:vga_sync_inst|green_out[3]    ; Stuck at GND due to stuck port data_in         ;
324
; video:video_inst|VGA_SYNC:vga_sync_inst|red_out[0..3]   ; Stuck at GND due to stuck port data_in         ;
325
; T80se:z80_inst|T80:u0|OldNMI_n                          ; Lost fanout                                    ;
326
; T80se:z80_inst|T80:u0|BusReq_s                          ; Stuck at GND due to stuck port data_in         ;
327
; T80se:z80_inst|T80:u0|INT_s                             ; Stuck at GND due to stuck port data_in         ;
328
; T80se:z80_inst|T80:u0|BusAck                            ; Stuck at GND due to stuck port data_in         ;
329
; video:video_inst|VGA_SYNC:vga_sync_inst|green_out[0..2] ; Stuck at GND due to stuck port data_in         ;
330
; T80se:z80_inst|T80:u0|IntE_FF1                          ; Lost fanout                                    ;
331
; T80se:z80_inst|T80:u0|NMI_s                             ; Stuck at GND due to stuck port data_in         ;
332
; T80se:z80_inst|T80:u0|IntCycle                          ; Stuck at GND due to stuck port data_in         ;
333
; T80se:z80_inst|T80:u0|IStatus[0,1]                      ; Lost fanout                                    ;
334
; T80se:z80_inst|T80:u0|NMICycle                          ; Stuck at GND due to stuck port data_in         ;
335
; T80se:z80_inst|T80:u0|Auto_Wait_t2                      ; Lost fanout                                    ;
336
; T80se:z80_inst|T80:u0|Auto_Wait_t1                      ; Lost fanout                                    ;
337
; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_row[9]    ; Stuck at GND due to stuck port data_in         ;
338
; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|clock_enable      ; Merged with clk_div:clkdiv_inst|count_10Mhz[0] ;
339
; Total Number of Removed Registers = 22                  ;                                                ;
340
+---------------------------------------------------------+------------------------------------------------+
341
 
342
 
343
+---------------------------------------------------------------------------------------------------------------------------------+
344
; Removed Registers Triggering Further Register Optimizations                                                                     ;
345
+--------------------------------+---------------------------+--------------------------------------------------------------------+
346
; Register name                  ; Reason for Removal        ; Registers Removed due to This Register                             ;
347
+--------------------------------+---------------------------+--------------------------------------------------------------------+
348
; T80se:z80_inst|T80:u0|BusReq_s ; Stuck at GND              ; T80se:z80_inst|T80:u0|BusAck, T80se:z80_inst|T80:u0|Auto_Wait_t2,  ;
349
;                                ; due to stuck port data_in ; T80se:z80_inst|T80:u0|Auto_Wait_t1                                 ;
350
; T80se:z80_inst|T80:u0|IntCycle ; Stuck at GND              ; T80se:z80_inst|T80:u0|IStatus[0], T80se:z80_inst|T80:u0|IStatus[1] ;
351
;                                ; due to stuck port data_in ;                                                                    ;
352
; T80se:z80_inst|T80:u0|INT_s    ; Stuck at GND              ; T80se:z80_inst|T80:u0|IntE_FF1                                     ;
353
;                                ; due to stuck port data_in ;                                                                    ;
354
+--------------------------------+---------------------------+--------------------------------------------------------------------+
355
 
356
 
357
+------------------------------------------------------+
358
; General Register Statistics                          ;
359
+----------------------------------------------+-------+
360
; Statistic                                    ; Value ;
361
+----------------------------------------------+-------+
362
; Total registers                              ; 535   ;
363
; Number of registers using Synchronous Clear  ; 7     ;
364
; Number of registers using Synchronous Load   ; 25    ;
365
; Number of registers using Asynchronous Clear ; 176   ;
366
; Number of registers using Asynchronous Load  ; 0     ;
367
; Number of registers using Clock Enable       ; 356   ;
368
; Number of registers using Preset             ; 0     ;
369
+----------------------------------------------+-------+
370
 
371
 
372
+---------------------------------------------------+
373
; Inverted Register Statistics                      ;
374
+-----------------------------------------+---------+
375
; Inverted Register                       ; Fan out ;
376
+-----------------------------------------+---------+
377
; T80se:z80_inst|WR_n                     ; 3       ;
378
; T80se:z80_inst|MREQ_n                   ; 6       ;
379
; T80se:z80_inst|RD_n                     ; 4       ;
380
; T80se:z80_inst|IORQ_n                   ; 2       ;
381
; T80se:z80_inst|T80:u0|MCycle[0]         ; 92      ;
382
; T80se:z80_inst|T80:u0|F[6]              ; 11      ;
383
; T80se:z80_inst|T80:u0|F[0]              ; 14      ;
384
; T80se:z80_inst|T80:u0|F[2]              ; 8       ;
385
; T80se:z80_inst|T80:u0|F[7]              ; 7       ;
386
; T80se:z80_inst|T80:u0|SP[0]             ; 5       ;
387
; T80se:z80_inst|T80:u0|SP[1]             ; 5       ;
388
; T80se:z80_inst|T80:u0|SP[2]             ; 5       ;
389
; T80se:z80_inst|T80:u0|SP[3]             ; 5       ;
390
; T80se:z80_inst|T80:u0|SP[4]             ; 5       ;
391
; T80se:z80_inst|T80:u0|SP[5]             ; 5       ;
392
; T80se:z80_inst|T80:u0|SP[6]             ; 5       ;
393
; T80se:z80_inst|T80:u0|SP[7]             ; 5       ;
394
; T80se:z80_inst|T80:u0|SP[8]             ; 5       ;
395
; T80se:z80_inst|T80:u0|ACC[0]            ; 7       ;
396
; T80se:z80_inst|T80:u0|SP[9]             ; 5       ;
397
; T80se:z80_inst|T80:u0|ACC[1]            ; 7       ;
398
; T80se:z80_inst|T80:u0|SP[10]            ; 5       ;
399
; T80se:z80_inst|T80:u0|ACC[2]            ; 7       ;
400
; T80se:z80_inst|T80:u0|SP[11]            ; 5       ;
401
; T80se:z80_inst|T80:u0|ACC[3]            ; 9       ;
402
; T80se:z80_inst|T80:u0|SP[12]            ; 5       ;
403
; T80se:z80_inst|T80:u0|ACC[4]            ; 7       ;
404
; T80se:z80_inst|T80:u0|SP[13]            ; 5       ;
405
; T80se:z80_inst|T80:u0|ACC[5]            ; 9       ;
406
; T80se:z80_inst|T80:u0|SP[14]            ; 5       ;
407
; T80se:z80_inst|T80:u0|ACC[6]            ; 7       ;
408
; T80se:z80_inst|T80:u0|SP[15]            ; 5       ;
409
; T80se:z80_inst|T80:u0|ACC[7]            ; 7       ;
410
; T80se:z80_inst|T80:u0|F[1]              ; 20      ;
411
; T80se:z80_inst|T80:u0|F[4]              ; 8       ;
412
; \random:rand_temp[15]                   ; 2       ;
413
; T80se:z80_inst|T80:u0|Fp[6]             ; 1       ;
414
; T80se:z80_inst|T80:u0|Fp[0]             ; 1       ;
415
; T80se:z80_inst|T80:u0|Fp[2]             ; 1       ;
416
; T80se:z80_inst|T80:u0|Fp[7]             ; 1       ;
417
; T80se:z80_inst|T80:u0|Ap[0]             ; 1       ;
418
; T80se:z80_inst|T80:u0|Ap[1]             ; 1       ;
419
; T80se:z80_inst|T80:u0|Ap[2]             ; 1       ;
420
; T80se:z80_inst|T80:u0|Ap[3]             ; 1       ;
421
; T80se:z80_inst|T80:u0|Ap[4]             ; 1       ;
422
; T80se:z80_inst|T80:u0|Ap[5]             ; 1       ;
423
; T80se:z80_inst|T80:u0|Ap[6]             ; 1       ;
424
; T80se:z80_inst|T80:u0|Ap[7]             ; 1       ;
425
; T80se:z80_inst|T80:u0|F[5]              ; 2       ;
426
; T80se:z80_inst|T80:u0|Fp[1]             ; 1       ;
427
; T80se:z80_inst|T80:u0|Fp[4]             ; 1       ;
428
; T80se:z80_inst|T80:u0|F[3]              ; 2       ;
429
; T80se:z80_inst|T80:u0|Fp[5]             ; 1       ;
430
; T80se:z80_inst|T80:u0|Fp[3]             ; 1       ;
431
; Total number of inverted registers = 54 ;         ;
432
+-----------------------------------------+---------+
433
 
434
 
435
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
436
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                           ;
437
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------+
438
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                 ;
439
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------+
440
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |Z80SOC|T80se:z80_inst|T80:u0|ALU_Op_r[2]                  ;
441
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; Yes        ; |Z80SOC|T80se:z80_inst|T80:u0|RegAddrC[1]                  ;
442
; 3:1                ; 4 bits    ; 8 LEs         ; 8 LEs                ; 0 LEs                  ; Yes        ; |Z80SOC|T80se:z80_inst|T80:u0|Read_To_Reg_r[2]             ;
443
; 3:1                ; 10 bits   ; 20 LEs        ; 10 LEs               ; 10 LEs                 ; Yes        ; |Z80SOC|video:video_inst|VGA_SYNC:vga_sync_inst|v_count[2] ;
444
; 4:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; Yes        ; |Z80SOC|T80se:z80_inst|T80:u0|XY_State[0]                  ;
445
; 6:1                ; 8 bits    ; 32 LEs        ; 8 LEs                ; 24 LEs                 ; Yes        ; |Z80SOC|T80se:z80_inst|T80:u0|IR[7]                        ;
446
; 5:1                ; 2 bits    ; 6 LEs         ; 4 LEs                ; 2 LEs                  ; Yes        ; |Z80SOC|T80se:z80_inst|T80:u0|MCycle[2]                    ;
447
; 5:1                ; 8 bits    ; 24 LEs        ; 8 LEs                ; 16 LEs                 ; Yes        ; |Z80SOC|ps2_ascii_reg1[1]                                  ;
448
; 5:1                ; 4 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; Yes        ; |Z80SOC|ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0]     ;
449
; 4:1                ; 7 bits    ; 14 LEs        ; 7 LEs                ; 7 LEs                  ; Yes        ; |Z80SOC|T80se:z80_inst|T80:u0|R[2]                         ;
450
; 11:1               ; 8 bits    ; 56 LEs        ; 48 LEs               ; 8 LEs                  ; Yes        ; |Z80SOC|T80se:z80_inst|T80:u0|BusB[7]                      ;
451
; 12:1               ; 8 bits    ; 64 LEs        ; 32 LEs               ; 32 LEs                 ; Yes        ; |Z80SOC|T80se:z80_inst|T80:u0|BusA[1]                      ;
452
; 7:1                ; 2 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |Z80SOC|T80se:z80_inst|T80:u0|ISet[0]                      ;
453
; 6:1                ; 5 bits    ; 20 LEs        ; 10 LEs               ; 10 LEs                 ; Yes        ; |Z80SOC|T80se:z80_inst|T80:u0|TmpAddr[0]                   ;
454
; 6:1                ; 3 bits    ; 12 LEs        ; 6 LEs                ; 6 LEs                  ; Yes        ; |Z80SOC|T80se:z80_inst|T80:u0|TmpAddr[3]                   ;
455
; 6:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |Z80SOC|T80se:z80_inst|T80:u0|TmpAddr[10]                  ;
456
; 11:1               ; 7 bits    ; 49 LEs        ; 21 LEs               ; 28 LEs                 ; Yes        ; |Z80SOC|T80se:z80_inst|T80:u0|PC[1]                        ;
457
; 11:1               ; 8 bits    ; 56 LEs        ; 32 LEs               ; 24 LEs                 ; Yes        ; |Z80SOC|T80se:z80_inst|T80:u0|PC[11]                       ;
458
; 17:1               ; 8 bits    ; 88 LEs        ; 32 LEs               ; 56 LEs                 ; Yes        ; |Z80SOC|T80se:z80_inst|T80:u0|A[1]                         ;
459
; 17:1               ; 8 bits    ; 88 LEs        ; 40 LEs               ; 48 LEs                 ; Yes        ; |Z80SOC|T80se:z80_inst|T80:u0|A[8]                         ;
460
; 5:1                ; 8 bits    ; 24 LEs        ; 24 LEs               ; 0 LEs                  ; Yes        ; |Z80SOC|T80se:z80_inst|T80:u0|DO[7]                        ;
461
; 7:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |Z80SOC|T80se:z80_inst|T80:u0|SP[4]                        ;
462
; 7:1                ; 8 bits    ; 32 LEs        ; 16 LEs               ; 16 LEs                 ; Yes        ; |Z80SOC|T80se:z80_inst|T80:u0|SP[8]                        ;
463
; 8:1                ; 8 bits    ; 40 LEs        ; 24 LEs               ; 16 LEs                 ; Yes        ; |Z80SOC|T80se:z80_inst|T80:u0|ACC[3]                       ;
464
; 18:1               ; 2 bits    ; 24 LEs        ; 12 LEs               ; 12 LEs                 ; Yes        ; |Z80SOC|T80se:z80_inst|T80:u0|F[3]                         ;
465
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; No         ; |Z80SOC|T80se:z80_inst|T80:u0|T80_ALU:alu|Q_t              ;
466
; 3:1                ; 2 bits    ; 4 LEs         ; 2 LEs                ; 2 LEs                  ; No         ; |Z80SOC|T80se:z80_inst|T80:u0|T80_MCode:mcode|Mux47        ;
467
; 4:1                ; 3 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; No         ; |Z80SOC|T80se:z80_inst|T80:u0|T80_ALU:alu|DAA_Q[2]         ;
468
; 3:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |Z80SOC|T80se:z80_inst|T80:u0|Save_Mux[1]                  ;
469
; 8:1                ; 16 bits   ; 80 LEs        ; 80 LEs               ; 0 LEs                  ; No         ; |Z80SOC|T80se:z80_inst|T80:u0|T80_Reg:Regs|Mux43           ;
470
; 8:1                ; 8 bits    ; 40 LEs        ; 16 LEs               ; 24 LEs                 ; No         ; |Z80SOC|T80se:z80_inst|T80:u0|T80_ALU:alu|Mux14            ;
471
; 4:1                ; 2 bits    ; 4 LEs         ; 4 LEs                ; 0 LEs                  ; No         ; |Z80SOC|T80se:z80_inst|T80:u0|T80_ALU:alu|DAA_Q[7]         ;
472
; 4:1                ; 16 bits   ; 32 LEs        ; 32 LEs               ; 0 LEs                  ; No         ; |Z80SOC|T80se:z80_inst|T80:u0|RegDIH[3]                    ;
473
; 8:1                ; 16 bits   ; 80 LEs        ; 80 LEs               ; 0 LEs                  ; No         ; |Z80SOC|T80se:z80_inst|T80:u0|T80_Reg:Regs|Mux22           ;
474
; 8:1                ; 16 bits   ; 80 LEs        ; 80 LEs               ; 0 LEs                  ; No         ; |Z80SOC|T80se:z80_inst|T80:u0|T80_Reg:Regs|Mux5            ;
475
; 5:1                ; 2 bits    ; 6 LEs         ; 6 LEs                ; 0 LEs                  ; No         ; |Z80SOC|T80se:z80_inst|T80:u0|RegAddrA[1]                  ;
476
; 17:1               ; 4 bits    ; 44 LEs        ; 24 LEs               ; 20 LEs                 ; No         ; |Z80SOC|T80se:z80_inst|T80:u0|Save_Mux[6]                  ;
477
; 19:1               ; 2 bits    ; 24 LEs        ; 4 LEs                ; 20 LEs                 ; No         ; |Z80SOC|T80se:z80_inst|T80:u0|RegWEH                       ;
478
; 10:1               ; 2 bits    ; 12 LEs        ; 12 LEs               ; 0 LEs                  ; No         ; |Z80SOC|T80se:z80_inst|T80:u0|Save_Mux[7]                  ;
479
; 20:1               ; 4 bits    ; 52 LEs        ; 48 LEs               ; 4 LEs                  ; No         ; |Z80SOC|DI_CPU[6]                                          ;
480
; 20:1               ; 4 bits    ; 52 LEs        ; 52 LEs               ; 0 LEs                  ; No         ; |Z80SOC|DI_CPU[3]                                          ;
481
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------+
482
 
483
 
484
+------------------------------------------------------------------------------------------------------+
485
; Source assignments for vram:vram_inst|altsyncram:altsyncram_component|altsyncram_66l1:auto_generated ;
486
+---------------------------------+--------------------+------+----------------------------------------+
487
; Assignment                      ; Value              ; From ; To                                     ;
488
+---------------------------------+--------------------+------+----------------------------------------+
489
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                      ;
490
+---------------------------------+--------------------+------+----------------------------------------+
491
 
492
 
493
+----------------------------------------------------------------------------------------------------------------------------------+
494
; Source assignments for vram:vram_inst|altsyncram:altsyncram_component|altsyncram_66l1:auto_generated|altsyncram_pal1:altsyncram1 ;
495
+---------------------------------+--------------------+------+--------------------------------------------------------------------+
496
; Assignment                      ; Value              ; From ; To                                                                 ;
497
+---------------------------------+--------------------+------+--------------------------------------------------------------------+
498
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                  ;
499
+---------------------------------+--------------------+------+--------------------------------------------------------------------+
500
 
501
 
502
+----------------------------------------------------------------------------------------------------+
503
; Source assignments for charram:cram|altsyncram:altsyncram_component|altsyncram_h1o1:auto_generated ;
504
+---------------------------------+--------------------+------+--------------------------------------+
505
; Assignment                      ; Value              ; From ; To                                   ;
506
+---------------------------------+--------------------+------+--------------------------------------+
507
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                    ;
508
+---------------------------------+--------------------+------+--------------------------------------+
509
 
510
 
511
+--------------------------------------------------------------------------------------------------------------------------------+
512
; Source assignments for charram:cram|altsyncram:altsyncram_component|altsyncram_h1o1:auto_generated|altsyncram_36o1:altsyncram1 ;
513
+---------------------------------+--------------------+------+------------------------------------------------------------------+
514
; Assignment                      ; Value              ; From ; To                                                               ;
515
+---------------------------------+--------------------+------+------------------------------------------------------------------+
516
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                                ;
517
+---------------------------------+--------------------+------+------------------------------------------------------------------+
518
 
519
 
520
+----------------------------------------------------------------------------------------------------+
521
; Source assignments for rom:rom_inst|altsyncram:altsyncram_component|altsyncram_tr91:auto_generated ;
522
+---------------------------------+--------------------+------+--------------------------------------+
523
; Assignment                      ; Value              ; From ; To                                   ;
524
+---------------------------------+--------------------+------+--------------------------------------+
525
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                    ;
526
+---------------------------------+--------------------+------+--------------------------------------+
527
 
528
 
529
+-------------------------------------------------------------+
530
; Parameter Settings for User Entity Instance: T80se:z80_inst ;
531
+----------------+-------+------------------------------------+
532
; Parameter Name ; Value ; Type                               ;
533
+----------------+-------+------------------------------------+
534
; mode           ; 0     ; Signed Integer                     ;
535
; t2write        ; 1     ; Signed Integer                     ;
536
; iowait         ; 1     ; Signed Integer                     ;
537
+----------------+-------+------------------------------------+
538
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
539
 
540
 
541
+--------------------------------------------------------------------+
542
; Parameter Settings for User Entity Instance: T80se:z80_inst|T80:u0 ;
543
+----------------+-------+-------------------------------------------+
544
; Parameter Name ; Value ; Type                                      ;
545
+----------------+-------+-------------------------------------------+
546
; mode           ; 0     ; Signed Integer                            ;
547
; iowait         ; 1     ; Signed Integer                            ;
548
; flag_c         ; 0     ; Signed Integer                            ;
549
; flag_n         ; 1     ; Signed Integer                            ;
550
; flag_p         ; 2     ; Signed Integer                            ;
551
; flag_x         ; 3     ; Signed Integer                            ;
552
; flag_h         ; 4     ; Signed Integer                            ;
553
; flag_y         ; 5     ; Signed Integer                            ;
554
; flag_z         ; 6     ; Signed Integer                            ;
555
; flag_s         ; 7     ; Signed Integer                            ;
556
+----------------+-------+-------------------------------------------+
557
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
558
 
559
 
560
+------------------------------------------------------------------------------------+
561
; Parameter Settings for User Entity Instance: T80se:z80_inst|T80:u0|T80_MCode:mcode ;
562
+----------------+-------+-----------------------------------------------------------+
563
; Parameter Name ; Value ; Type                                                      ;
564
+----------------+-------+-----------------------------------------------------------+
565
; mode           ; 0     ; Signed Integer                                            ;
566
; flag_c         ; 0     ; Signed Integer                                            ;
567
; flag_n         ; 1     ; Signed Integer                                            ;
568
; flag_p         ; 2     ; Signed Integer                                            ;
569
; flag_x         ; 3     ; Signed Integer                                            ;
570
; flag_h         ; 4     ; Signed Integer                                            ;
571
; flag_y         ; 5     ; Signed Integer                                            ;
572
; flag_z         ; 6     ; Signed Integer                                            ;
573
; flag_s         ; 7     ; Signed Integer                                            ;
574
+----------------+-------+-----------------------------------------------------------+
575
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
576
 
577
 
578
+--------------------------------------------------------------------------------+
579
; Parameter Settings for User Entity Instance: T80se:z80_inst|T80:u0|T80_ALU:alu ;
580
+----------------+-------+-------------------------------------------------------+
581
; Parameter Name ; Value ; Type                                                  ;
582
+----------------+-------+-------------------------------------------------------+
583
; mode           ; 0     ; Signed Integer                                        ;
584
; flag_c         ; 0     ; Signed Integer                                        ;
585
; flag_n         ; 1     ; Signed Integer                                        ;
586
; flag_p         ; 2     ; Signed Integer                                        ;
587
; flag_x         ; 3     ; Signed Integer                                        ;
588
; flag_h         ; 4     ; Signed Integer                                        ;
589
; flag_y         ; 5     ; Signed Integer                                        ;
590
; flag_z         ; 6     ; Signed Integer                                        ;
591
; flag_s         ; 7     ; Signed Integer                                        ;
592
+----------------+-------+-------------------------------------------------------+
593
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
594
 
595
 
596
+---------------------------------------------------------------------------------------------+
597
; Parameter Settings for User Entity Instance: vram:vram_inst|altsyncram:altsyncram_component ;
598
+------------------------------------+----------------------+---------------------------------+
599
; Parameter Name                     ; Value                ; Type                            ;
600
+------------------------------------+----------------------+---------------------------------+
601
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                         ;
602
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                      ;
603
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                    ;
604
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                    ;
605
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                  ;
606
; WIDTH_BYTEENA                      ; 1                    ; Untyped                         ;
607
; OPERATION_MODE                     ; DUAL_PORT            ; Untyped                         ;
608
; WIDTH_A                            ; 8                    ; Signed Integer                  ;
609
; WIDTHAD_A                          ; 13                   ; Signed Integer                  ;
610
; NUMWORDS_A                         ; 6143                 ; Signed Integer                  ;
611
; OUTDATA_REG_A                      ; UNREGISTERED         ; Untyped                         ;
612
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                         ;
613
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                         ;
614
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                         ;
615
; INDATA_ACLR_A                      ; NONE                 ; Untyped                         ;
616
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                         ;
617
; WIDTH_B                            ; 8                    ; Signed Integer                  ;
618
; WIDTHAD_B                          ; 13                   ; Signed Integer                  ;
619
; NUMWORDS_B                         ; 6143                 ; Signed Integer                  ;
620
; INDATA_REG_B                       ; CLOCK1               ; Untyped                         ;
621
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                         ;
622
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                         ;
623
; ADDRESS_REG_B                      ; CLOCK1               ; Untyped                         ;
624
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                         ;
625
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                         ;
626
; INDATA_ACLR_B                      ; NONE                 ; Untyped                         ;
627
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                         ;
628
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                         ;
629
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                         ;
630
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                         ;
631
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                         ;
632
; WIDTH_BYTEENA_A                    ; 1                    ; Signed Integer                  ;
633
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                         ;
634
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                         ;
635
; BYTE_SIZE                          ; 8                    ; Untyped                         ;
636
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                         ;
637
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                         ;
638
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                         ;
639
; INIT_FILE                          ; UNUSED               ; Untyped                         ;
640
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                         ;
641
; MAXIMUM_DEPTH                      ; 0                    ; Untyped                         ;
642
; CLOCK_ENABLE_INPUT_A               ; BYPASS               ; Untyped                         ;
643
; CLOCK_ENABLE_INPUT_B               ; BYPASS               ; Untyped                         ;
644
; CLOCK_ENABLE_OUTPUT_A              ; BYPASS               ; Untyped                         ;
645
; CLOCK_ENABLE_OUTPUT_B              ; BYPASS               ; Untyped                         ;
646
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                         ;
647
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                         ;
648
; ENABLE_ECC                         ; FALSE                ; Untyped                         ;
649
; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                ; Untyped                         ;
650
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                         ;
651
; DEVICE_FAMILY                      ; Cyclone II           ; Untyped                         ;
652
; CBXI_PARAMETER                     ; altsyncram_66l1      ; Untyped                         ;
653
+------------------------------------+----------------------+---------------------------------+
654
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
655
 
656
 
657
+-------------------------------------------------------------------------------------------+
658
; Parameter Settings for User Entity Instance: charram:cram|altsyncram:altsyncram_component ;
659
+------------------------------------+------------------------+-----------------------------+
660
; Parameter Name                     ; Value                  ; Type                        ;
661
+------------------------------------+------------------------+-----------------------------+
662
; BYTE_SIZE_BLOCK                    ; 8                      ; Untyped                     ;
663
; AUTO_CARRY_CHAINS                  ; ON                     ; AUTO_CARRY                  ;
664
; IGNORE_CARRY_BUFFERS               ; OFF                    ; IGNORE_CARRY                ;
665
; AUTO_CASCADE_CHAINS                ; ON                     ; AUTO_CASCADE                ;
666
; IGNORE_CASCADE_BUFFERS             ; OFF                    ; IGNORE_CASCADE              ;
667
; WIDTH_BYTEENA                      ; 1                      ; Untyped                     ;
668
; OPERATION_MODE                     ; DUAL_PORT              ; Untyped                     ;
669
; WIDTH_A                            ; 8                      ; Signed Integer              ;
670
; WIDTHAD_A                          ; 11                     ; Signed Integer              ;
671
; NUMWORDS_A                         ; 2048                   ; Signed Integer              ;
672
; OUTDATA_REG_A                      ; UNREGISTERED           ; Untyped                     ;
673
; ADDRESS_ACLR_A                     ; NONE                   ; Untyped                     ;
674
; OUTDATA_ACLR_A                     ; NONE                   ; Untyped                     ;
675
; WRCONTROL_ACLR_A                   ; NONE                   ; Untyped                     ;
676
; INDATA_ACLR_A                      ; NONE                   ; Untyped                     ;
677
; BYTEENA_ACLR_A                     ; NONE                   ; Untyped                     ;
678
; WIDTH_B                            ; 8                      ; Signed Integer              ;
679
; WIDTHAD_B                          ; 11                     ; Signed Integer              ;
680
; NUMWORDS_B                         ; 2048                   ; Signed Integer              ;
681
; INDATA_REG_B                       ; CLOCK1                 ; Untyped                     ;
682
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1                 ; Untyped                     ;
683
; RDCONTROL_REG_B                    ; CLOCK1                 ; Untyped                     ;
684
; ADDRESS_REG_B                      ; CLOCK1                 ; Untyped                     ;
685
; OUTDATA_REG_B                      ; UNREGISTERED           ; Untyped                     ;
686
; BYTEENA_REG_B                      ; CLOCK1                 ; Untyped                     ;
687
; INDATA_ACLR_B                      ; NONE                   ; Untyped                     ;
688
; WRCONTROL_ACLR_B                   ; NONE                   ; Untyped                     ;
689
; ADDRESS_ACLR_B                     ; NONE                   ; Untyped                     ;
690
; OUTDATA_ACLR_B                     ; NONE                   ; Untyped                     ;
691
; RDCONTROL_ACLR_B                   ; NONE                   ; Untyped                     ;
692
; BYTEENA_ACLR_B                     ; NONE                   ; Untyped                     ;
693
; WIDTH_BYTEENA_A                    ; 1                      ; Signed Integer              ;
694
; WIDTH_BYTEENA_B                    ; 1                      ; Untyped                     ;
695
; RAM_BLOCK_TYPE                     ; AUTO                   ; Untyped                     ;
696
; BYTE_SIZE                          ; 8                      ; Untyped                     ;
697
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE              ; Untyped                     ;
698
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ   ; Untyped                     ;
699
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ   ; Untyped                     ;
700
; INIT_FILE                          ; ../ROMdata/lat9-08.mif ; Untyped                     ;
701
; INIT_FILE_LAYOUT                   ; PORT_A                 ; Untyped                     ;
702
; MAXIMUM_DEPTH                      ; 0                      ; Untyped                     ;
703
; CLOCK_ENABLE_INPUT_A               ; BYPASS                 ; Untyped                     ;
704
; CLOCK_ENABLE_INPUT_B               ; BYPASS                 ; Untyped                     ;
705
; CLOCK_ENABLE_OUTPUT_A              ; BYPASS                 ; Untyped                     ;
706
; CLOCK_ENABLE_OUTPUT_B              ; BYPASS                 ; Untyped                     ;
707
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN        ; Untyped                     ;
708
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN        ; Untyped                     ;
709
; ENABLE_ECC                         ; FALSE                  ; Untyped                     ;
710
; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                  ; Untyped                     ;
711
; WIDTH_ECCSTATUS                    ; 3                      ; Untyped                     ;
712
; DEVICE_FAMILY                      ; Cyclone II             ; Untyped                     ;
713
; CBXI_PARAMETER                     ; altsyncram_h1o1        ; Untyped                     ;
714
+------------------------------------+------------------------+-----------------------------+
715
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
716
 
717
 
718
+-------------------------------------------------------------------------------------------+
719
; Parameter Settings for User Entity Instance: rom:rom_inst|altsyncram:altsyncram_component ;
720
+------------------------------------+----------------------+-------------------------------+
721
; Parameter Name                     ; Value                ; Type                          ;
722
+------------------------------------+----------------------+-------------------------------+
723
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                       ;
724
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                    ;
725
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                  ;
726
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                  ;
727
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                ;
728
; WIDTH_BYTEENA                      ; 1                    ; Untyped                       ;
729
; OPERATION_MODE                     ; ROM                  ; Untyped                       ;
730
; WIDTH_A                            ; 8                    ; Signed Integer                ;
731
; WIDTHAD_A                          ; 14                   ; Signed Integer                ;
732
; NUMWORDS_A                         ; 16384                ; Signed Integer                ;
733
; OUTDATA_REG_A                      ; CLOCK0               ; Untyped                       ;
734
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                       ;
735
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                       ;
736
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                       ;
737
; INDATA_ACLR_A                      ; NONE                 ; Untyped                       ;
738
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                       ;
739
; WIDTH_B                            ; 1                    ; Untyped                       ;
740
; WIDTHAD_B                          ; 1                    ; Untyped                       ;
741
; NUMWORDS_B                         ; 1                    ; Untyped                       ;
742
; INDATA_REG_B                       ; CLOCK1               ; Untyped                       ;
743
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                       ;
744
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                       ;
745
; ADDRESS_REG_B                      ; CLOCK1               ; Untyped                       ;
746
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                       ;
747
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                       ;
748
; INDATA_ACLR_B                      ; NONE                 ; Untyped                       ;
749
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                       ;
750
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                       ;
751
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                       ;
752
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                       ;
753
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                       ;
754
; WIDTH_BYTEENA_A                    ; 1                    ; Signed Integer                ;
755
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                       ;
756
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                       ;
757
; BYTE_SIZE                          ; 8                    ; Untyped                       ;
758
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                       ;
759
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                       ;
760
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                       ;
761
; INIT_FILE                          ; ../ROMdata/rom.hex   ; Untyped                       ;
762
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                       ;
763
; MAXIMUM_DEPTH                      ; 0                    ; Untyped                       ;
764
; CLOCK_ENABLE_INPUT_A               ; BYPASS               ; Untyped                       ;
765
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                       ;
766
; CLOCK_ENABLE_OUTPUT_A              ; BYPASS               ; Untyped                       ;
767
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                       ;
768
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                       ;
769
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                       ;
770
; ENABLE_ECC                         ; FALSE                ; Untyped                       ;
771
; ECC_PIPELINE_STAGE_ENABLED         ; FALSE                ; Untyped                       ;
772
; WIDTH_ECCSTATUS                    ; 3                    ; Untyped                       ;
773
; DEVICE_FAMILY                      ; Cyclone II           ; Untyped                       ;
774
; CBXI_PARAMETER                     ; altsyncram_tr91      ; Untyped                       ;
775
+------------------------------------+----------------------+-------------------------------+
776
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
777
 
778
 
779
+--------------------------------------------------------------------------------------------+
780
; altsyncram Parameter Settings by Entity Instance                                           ;
781
+-------------------------------------------+------------------------------------------------+
782
; Name                                      ; Value                                          ;
783
+-------------------------------------------+------------------------------------------------+
784
; Number of entity instances                ; 3                                              ;
785
; Entity Instance                           ; vram:vram_inst|altsyncram:altsyncram_component ;
786
;     -- OPERATION_MODE                     ; DUAL_PORT                                      ;
787
;     -- WIDTH_A                            ; 8                                              ;
788
;     -- NUMWORDS_A                         ; 6143                                           ;
789
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                   ;
790
;     -- WIDTH_B                            ; 8                                              ;
791
;     -- NUMWORDS_B                         ; 6143                                           ;
792
;     -- ADDRESS_REG_B                      ; CLOCK1                                         ;
793
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                   ;
794
;     -- RAM_BLOCK_TYPE                     ; AUTO                                           ;
795
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                      ;
796
; Entity Instance                           ; charram:cram|altsyncram:altsyncram_component   ;
797
;     -- OPERATION_MODE                     ; DUAL_PORT                                      ;
798
;     -- WIDTH_A                            ; 8                                              ;
799
;     -- NUMWORDS_A                         ; 2048                                           ;
800
;     -- OUTDATA_REG_A                      ; UNREGISTERED                                   ;
801
;     -- WIDTH_B                            ; 8                                              ;
802
;     -- NUMWORDS_B                         ; 2048                                           ;
803
;     -- ADDRESS_REG_B                      ; CLOCK1                                         ;
804
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                   ;
805
;     -- RAM_BLOCK_TYPE                     ; AUTO                                           ;
806
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                      ;
807
; Entity Instance                           ; rom:rom_inst|altsyncram:altsyncram_component   ;
808
;     -- OPERATION_MODE                     ; ROM                                            ;
809
;     -- WIDTH_A                            ; 8                                              ;
810
;     -- NUMWORDS_A                         ; 16384                                          ;
811
;     -- OUTDATA_REG_A                      ; CLOCK0                                         ;
812
;     -- WIDTH_B                            ; 1                                              ;
813
;     -- NUMWORDS_B                         ; 1                                              ;
814
;     -- ADDRESS_REG_B                      ; CLOCK1                                         ;
815
;     -- OUTDATA_REG_B                      ; UNREGISTERED                                   ;
816
;     -- RAM_BLOCK_TYPE                     ; AUTO                                           ;
817
;     -- READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                                      ;
818
+-------------------------------------------+------------------------------------------------+
819
 
820
 
821
+------------------------------------------------------------------------------------------------------------------------+
822
; Port Connectivity Checks: "clk_div:clkdiv_inst"                                                                        ;
823
+--------------+--------+----------+-------------------------------------------------------------------------------------+
824
; Port         ; Type   ; Severity ; Details                                                                             ;
825
+--------------+--------+----------+-------------------------------------------------------------------------------------+
826
; clock_1mhz   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
827
; clock_100khz ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
828
; clock_10khz  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
829
; clock_1khz   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
830
; clock_10hz   ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
831
; clock_1hz    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
832
+--------------+--------+----------+-------------------------------------------------------------------------------------+
833
 
834
 
835
+--------------------------------------------------------------------------------------------------------------------+
836
; Port Connectivity Checks: "video:video_inst|VGA_SYNC:vga_sync_inst"                                                ;
837
+----------+--------+----------+-------------------------------------------------------------------------------------+
838
; Port     ; Type   ; Severity ; Details                                                                             ;
839
+----------+--------+----------+-------------------------------------------------------------------------------------+
840
; red      ; Input  ; Info     ; Stuck at GND                                                                        ;
841
; green    ; Input  ; Info     ; Stuck at GND                                                                        ;
842
; video_on ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
843
+----------+--------+----------+-------------------------------------------------------------------------------------+
844
 
845
 
846
+-------------------------------------------------------------------------------------------------------------------------+
847
; Port Connectivity Checks: "video:video_inst"                                                                            ;
848
+---------------+--------+----------+-------------------------------------------------------------------------------------+
849
; Port          ; Type   ; Severity ; Details                                                                             ;
850
+---------------+--------+----------+-------------------------------------------------------------------------------------+
851
; vram_addr[13] ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
852
; vram_wren     ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
853
; cram_web      ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
854
+---------------+--------+----------+-------------------------------------------------------------------------------------+
855
 
856
 
857
+----------------------------------------------------------------------------------------------------------------+
858
; Port Connectivity Checks: "T80se:z80_inst|T80:u0"                                                              ;
859
+------+--------+----------+-------------------------------------------------------------------------------------+
860
; Port ; Type   ; Severity ; Details                                                                             ;
861
+------+--------+----------+-------------------------------------------------------------------------------------+
862
; inte ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
863
; stop ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
864
+------+--------+----------+-------------------------------------------------------------------------------------+
865
 
866
 
867
+-------------------------------------------------------------------------------------------------------------------+
868
; Port Connectivity Checks: "T80se:z80_inst"                                                                        ;
869
+---------+--------+----------+-------------------------------------------------------------------------------------+
870
; Port    ; Type   ; Severity ; Details                                                                             ;
871
+---------+--------+----------+-------------------------------------------------------------------------------------+
872
; clken   ; Input  ; Info     ; Stuck at VCC                                                                        ;
873
; wait_n  ; Input  ; Info     ; Stuck at VCC                                                                        ;
874
; int_n   ; Input  ; Info     ; Stuck at VCC                                                                        ;
875
; nmi_n   ; Input  ; Info     ; Stuck at VCC                                                                        ;
876
; busrq_n ; Input  ; Info     ; Stuck at VCC                                                                        ;
877
; m1_n    ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
878
; rfsh_n  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
879
; halt_n  ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
880
; busak_n ; Output ; Info     ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ;
881
+---------+--------+----------+-------------------------------------------------------------------------------------+
882
 
883
 
884
+-------------------------------+
885
; Elapsed Time Per Partition    ;
886
+----------------+--------------+
887
; Partition Name ; Elapsed Time ;
888
+----------------+--------------+
889
; Top            ; 00:00:41     ;
890
+----------------+--------------+
891
 
892
 
893
+-------------------------------+
894
; Analysis & Synthesis Messages ;
895
+-------------------------------+
896
Info: *******************************************************************
897
Info: Running Quartus II 64-Bit Analysis & Synthesis
898
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
899
    Info: Processing started: Sun Jun 19 14:40:54 2016
900
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off z80soc -c z80soc
901
Warning (20028): Parallel compilation is not licensed and has been disabled
902
Info (12021): Found 2 design units, including 1 entities, in source file memorycores/vram.vhd
903
    Info (12022): Found design unit 1: vram-SYN
904
    Info (12023): Found entity 1: vram
905
Info (12021): Found 2 design units, including 1 entities, in source file memorycores/charram.vhd
906
    Info (12022): Found design unit 1: charram-SYN
907
    Info (12023): Found entity 1: charram
908
Info (12021): Found 2 design units, including 1 entities, in source file vhdl/lcd.vhd
909
    Info (12022): Found design unit 1: LCD-RTL
910
    Info (12023): Found entity 1: LCD
911
Info (12021): Found 2 design units, including 1 entities, in source file memorycores/rom.vhd
912
    Info (12022): Found design unit 1: rom-SYN
913
    Info (12023): Found entity 1: rom
914
Info (12021): Found 2 design units, including 1 entities, in source file vhdl/keyboard.vhd
915
    Info (12022): Found design unit 1: keyboard-a
916
    Info (12023): Found entity 1: keyboard
917
Info (12021): Found 2 design units, including 1 entities, in source file vhdl/ps2bkd.vhd
918
    Info (12022): Found design unit 1: ps2kbd-rtl
919
    Info (12023): Found entity 1: ps2kbd
920
Info (12021): Found 2 design units, including 1 entities, in source file vhdl/t80.vhd
921
    Info (12022): Found design unit 1: T80-rtl
922
    Info (12023): Found entity 1: T80
923
Info (12021): Found 2 design units, including 1 entities, in source file vhdl/t80_alu.vhd
924
    Info (12022): Found design unit 1: T80_ALU-rtl
925
    Info (12023): Found entity 1: T80_ALU
926
Info (12021): Found 2 design units, including 1 entities, in source file vhdl/t80_mcode.vhd
927
    Info (12022): Found design unit 1: T80_MCode-rtl
928
    Info (12023): Found entity 1: T80_MCode
929
Info (12021): Found 1 design units, including 0 entities, in source file vhdl/t80_pack.vhd
930
    Info (12022): Found design unit 1: T80_Pack
931
Info (12021): Found 2 design units, including 1 entities, in source file vhdl/t80_reg.vhd
932
    Info (12022): Found design unit 1: T80_Reg-rtl
933
    Info (12023): Found entity 1: T80_Reg
934
Info (12021): Found 2 design units, including 1 entities, in source file vhdl/t80se.vhd
935
    Info (12022): Found design unit 1: T80se-rtl
936
    Info (12023): Found entity 1: T80se
937
Info (12021): Found 2 design units, including 1 entities, in source file vhdl/char_rom.vhd
938
    Info (12022): Found design unit 1: Char_ROM-a
939
    Info (12023): Found entity 1: Char_ROM
940
Info (12021): Found 2 design units, including 1 entities, in source file vhdl/video.vhd
941
    Info (12022): Found design unit 1: video-A
942
    Info (12023): Found entity 1: video
943
Info (12021): Found 2 design units, including 1 entities, in source file vhdl/clk_div.vhd
944
    Info (12022): Found design unit 1: clk_div-a
945
    Info (12023): Found entity 1: clk_div
946
Info (12021): Found 2 design units, including 1 entities, in source file vhdl/decoder_7seg.vhd
947
    Info (12022): Found design unit 1: decoder_7seg-rtl
948
    Info (12023): Found entity 1: decoder_7seg
949
Info (12021): Found 2 design units, including 1 entities, in source file vhdl/z80soc.vhd
950
    Info (12022): Found design unit 1: Z80SOC-rtl
951
    Info (12023): Found entity 1: Z80SOC
952
Info (12021): Found 2 design units, including 1 entities, in source file vhdl/vga_sync.vhd
953
    Info (12022): Found design unit 1: VGA_SYNC-a
954
    Info (12023): Found entity 1: VGA_SYNC
955
Info (12021): Found 1 design units, including 0 entities, in source file vhdl/z80soc_pack.vhd
956
    Info (12022): Found design unit 1: z80soc_pack
957
Info (12127): Elaborating entity "z80soc" for the top level hierarchy
958
Warning (10541): VHDL Signal Declaration warning at z80soc.vhd(140): used implicit default value for signal "SD_DAT3" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
959
Warning (10541): VHDL Signal Declaration warning at z80soc.vhd(141): used implicit default value for signal "SD_CMD" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
960
Warning (10541): VHDL Signal Declaration warning at z80soc.vhd(142): used implicit default value for signal "SD_CLK" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.
961
Warning (10036): Verilog HDL or VHDL warning at z80soc.vhd(310): object "clk1mhz" assigned a value but never read
962
Warning (10036): Verilog HDL or VHDL warning at z80soc.vhd(314): object "clk10hz" assigned a value but never read
963
Warning (10036): Verilog HDL or VHDL warning at z80soc.vhd(315): object "clk1hz" assigned a value but never read
964
Warning (10036): Verilog HDL or VHDL warning at z80soc.vhd(317): object "clk1khz" assigned a value but never read
965
Warning (10036): Verilog HDL or VHDL warning at z80soc.vhd(336): object "vram_web" assigned a value but never read
966
Warning (10036): Verilog HDL or VHDL warning at z80soc.vhd(347): object "cram_web" assigned a value but never read
967
Warning (10540): VHDL Signal Declaration warning at z80soc.vhd(362): used explicit default value for signal "Z80SOC_Arch_reg" because signal was never assigned a value
968
Warning (10540): VHDL Signal Declaration warning at z80soc.vhd(364): used explicit default value for signal "RAMTOP_reg" because signal was never assigned a value
969
Warning (10540): VHDL Signal Declaration warning at z80soc.vhd(365): used explicit default value for signal "RAMBOTT_reg" because signal was never assigned a value
970
Warning (10540): VHDL Signal Declaration warning at z80soc.vhd(366): used explicit default value for signal "VRAM_reg" because signal was never assigned a value
971
Warning (10540): VHDL Signal Declaration warning at z80soc.vhd(367): used explicit default value for signal "STACK_reg" because signal was never assigned a value
972
Warning (10540): VHDL Signal Declaration warning at z80soc.vhd(368): used explicit default value for signal "CHARRAM_reg" because signal was never assigned a value
973
Warning (10540): VHDL Signal Declaration warning at z80soc.vhd(369): used explicit default value for signal "VIDCOLS_reg" because signal was never assigned a value
974
Warning (10540): VHDL Signal Declaration warning at z80soc.vhd(370): used explicit default value for signal "VIDROWS_reg" because signal was never assigned a value
975
Info (12128): Elaborating entity "T80se" for hierarchy "T80se:z80_inst"
976
Info (12128): Elaborating entity "T80" for hierarchy "T80se:z80_inst|T80:u0"
977
Info (12128): Elaborating entity "T80_MCode" for hierarchy "T80se:z80_inst|T80:u0|T80_MCode:mcode"
978
Info (12128): Elaborating entity "T80_ALU" for hierarchy "T80se:z80_inst|T80:u0|T80_ALU:alu"
979
Info (12128): Elaborating entity "T80_Reg" for hierarchy "T80se:z80_inst|T80:u0|T80_Reg:Regs"
980
Info (12128): Elaborating entity "video" for hierarchy "video:video_inst"
981
Warning (10036): Verilog HDL or VHDL warning at video.vhd(54): object "video_on_sig" assigned a value but never read
982
Info (12128): Elaborating entity "VGA_SYNC" for hierarchy "video:video_inst|VGA_SYNC:vga_sync_inst"
983
Info (12128): Elaborating entity "vram" for hierarchy "vram:vram_inst"
984
Info (12128): Elaborating entity "altsyncram" for hierarchy "vram:vram_inst|altsyncram:altsyncram_component"
985
Info (12130): Elaborated megafunction instantiation "vram:vram_inst|altsyncram:altsyncram_component"
986
Info (12133): Instantiated megafunction "vram:vram_inst|altsyncram:altsyncram_component" with the following parameter:
987
    Info (12134): Parameter "address_reg_b" = "CLOCK1"
988
    Info (12134): Parameter "clock_enable_input_a" = "BYPASS"
989
    Info (12134): Parameter "clock_enable_input_b" = "BYPASS"
990
    Info (12134): Parameter "clock_enable_output_a" = "BYPASS"
991
    Info (12134): Parameter "clock_enable_output_b" = "BYPASS"
992
    Info (12134): Parameter "intended_device_family" = "Cyclone II"
993
    Info (12134): Parameter "lpm_type" = "altsyncram"
994
    Info (12134): Parameter "numwords_a" = "6143"
995
    Info (12134): Parameter "numwords_b" = "6143"
996
    Info (12134): Parameter "operation_mode" = "DUAL_PORT"
997
    Info (12134): Parameter "outdata_aclr_b" = "NONE"
998
    Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED"
999
    Info (12134): Parameter "power_up_uninitialized" = "FALSE"
1000
    Info (12134): Parameter "widthad_a" = "13"
1001
    Info (12134): Parameter "widthad_b" = "13"
1002
    Info (12134): Parameter "width_a" = "8"
1003
    Info (12134): Parameter "width_b" = "8"
1004
    Info (12134): Parameter "width_byteena_a" = "1"
1005
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_66l1.tdf
1006
    Info (12023): Found entity 1: altsyncram_66l1
1007
Info (12128): Elaborating entity "altsyncram_66l1" for hierarchy "vram:vram_inst|altsyncram:altsyncram_component|altsyncram_66l1:auto_generated"
1008
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_pal1.tdf
1009
    Info (12023): Found entity 1: altsyncram_pal1
1010
Info (12128): Elaborating entity "altsyncram_pal1" for hierarchy "vram:vram_inst|altsyncram:altsyncram_component|altsyncram_66l1:auto_generated|altsyncram_pal1:altsyncram1"
1011
Warning (287013): Variable or input pin "clocken1" is defined but never used.
1012
Info (12021): Found 1 design units, including 1 entities, in source file db/decode_1oa.tdf
1013
    Info (12023): Found entity 1: decode_1oa
1014
Info (12128): Elaborating entity "decode_1oa" for hierarchy "vram:vram_inst|altsyncram:altsyncram_component|altsyncram_66l1:auto_generated|altsyncram_pal1:altsyncram1|decode_1oa:decode3"
1015
Info (12128): Elaborating entity "decode_1oa" for hierarchy "vram:vram_inst|altsyncram:altsyncram_component|altsyncram_66l1:auto_generated|altsyncram_pal1:altsyncram1|decode_1oa:decode_a"
1016
Info (12021): Found 1 design units, including 1 entities, in source file db/mux_hib.tdf
1017
    Info (12023): Found entity 1: mux_hib
1018
Info (12128): Elaborating entity "mux_hib" for hierarchy "vram:vram_inst|altsyncram:altsyncram_component|altsyncram_66l1:auto_generated|altsyncram_pal1:altsyncram1|mux_hib:mux5"
1019
Info (12128): Elaborating entity "charram" for hierarchy "charram:cram"
1020
Info (12128): Elaborating entity "altsyncram" for hierarchy "charram:cram|altsyncram:altsyncram_component"
1021
Info (12130): Elaborated megafunction instantiation "charram:cram|altsyncram:altsyncram_component"
1022
Info (12133): Instantiated megafunction "charram:cram|altsyncram:altsyncram_component" with the following parameter:
1023
    Info (12134): Parameter "address_reg_b" = "CLOCK1"
1024
    Info (12134): Parameter "clock_enable_input_a" = "BYPASS"
1025
    Info (12134): Parameter "clock_enable_input_b" = "BYPASS"
1026
    Info (12134): Parameter "clock_enable_output_a" = "BYPASS"
1027
    Info (12134): Parameter "clock_enable_output_b" = "BYPASS"
1028
    Info (12134): Parameter "init_file" = "../ROMdata/lat9-08.mif"
1029
    Info (12134): Parameter "intended_device_family" = "Cyclone II"
1030
    Info (12134): Parameter "lpm_type" = "altsyncram"
1031
    Info (12134): Parameter "numwords_a" = "2048"
1032
    Info (12134): Parameter "numwords_b" = "2048"
1033
    Info (12134): Parameter "operation_mode" = "DUAL_PORT"
1034
    Info (12134): Parameter "outdata_aclr_b" = "NONE"
1035
    Info (12134): Parameter "outdata_reg_b" = "UNREGISTERED"
1036
    Info (12134): Parameter "power_up_uninitialized" = "FALSE"
1037
    Info (12134): Parameter "widthad_a" = "11"
1038
    Info (12134): Parameter "widthad_b" = "11"
1039
    Info (12134): Parameter "width_a" = "8"
1040
    Info (12134): Parameter "width_b" = "8"
1041
    Info (12134): Parameter "width_byteena_a" = "1"
1042
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_h1o1.tdf
1043
    Info (12023): Found entity 1: altsyncram_h1o1
1044
Info (12128): Elaborating entity "altsyncram_h1o1" for hierarchy "charram:cram|altsyncram:altsyncram_component|altsyncram_h1o1:auto_generated"
1045
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_36o1.tdf
1046
    Info (12023): Found entity 1: altsyncram_36o1
1047
Info (12128): Elaborating entity "altsyncram_36o1" for hierarchy "charram:cram|altsyncram:altsyncram_component|altsyncram_h1o1:auto_generated|altsyncram_36o1:altsyncram1"
1048
Info (12128): Elaborating entity "rom" for hierarchy "rom:rom_inst"
1049
Info (12128): Elaborating entity "altsyncram" for hierarchy "rom:rom_inst|altsyncram:altsyncram_component"
1050
Info (12130): Elaborated megafunction instantiation "rom:rom_inst|altsyncram:altsyncram_component"
1051
Info (12133): Instantiated megafunction "rom:rom_inst|altsyncram:altsyncram_component" with the following parameter:
1052
    Info (12134): Parameter "address_aclr_a" = "NONE"
1053
    Info (12134): Parameter "clock_enable_input_a" = "BYPASS"
1054
    Info (12134): Parameter "clock_enable_output_a" = "BYPASS"
1055
    Info (12134): Parameter "init_file" = "../ROMdata/rom.hex"
1056
    Info (12134): Parameter "intended_device_family" = "Cyclone IV E"
1057
    Info (12134): Parameter "lpm_hint" = "ENABLE_RUNTIME_MOD=NO"
1058
    Info (12134): Parameter "lpm_type" = "altsyncram"
1059
    Info (12134): Parameter "numwords_a" = "16384"
1060
    Info (12134): Parameter "operation_mode" = "ROM"
1061
    Info (12134): Parameter "outdata_aclr_a" = "NONE"
1062
    Info (12134): Parameter "outdata_reg_a" = "CLOCK0"
1063
    Info (12134): Parameter "widthad_a" = "14"
1064
    Info (12134): Parameter "width_a" = "8"
1065
    Info (12134): Parameter "width_byteena_a" = "1"
1066
Info (12021): Found 1 design units, including 1 entities, in source file db/altsyncram_tr91.tdf
1067
    Info (12023): Found entity 1: altsyncram_tr91
1068
Info (12128): Elaborating entity "altsyncram_tr91" for hierarchy "rom:rom_inst|altsyncram:altsyncram_component|altsyncram_tr91:auto_generated"
1069
Warning (113007): Byte addressed memory initialization file "rom.hex" was read in the word-addressed format
1070
Warning (113015): Width of data items in "rom.hex" is greater than the memory width. Wrapping data items to subsequent addresses. Found 509 warnings, reporting 10
1071
    Warning (113009): Data at line (1) of memory initialization file "rom.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
1072
    Warning (113009): Data at line (2) of memory initialization file "rom.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
1073
    Warning (113009): Data at line (3) of memory initialization file "rom.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
1074
    Warning (113009): Data at line (4) of memory initialization file "rom.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
1075
    Warning (113009): Data at line (5) of memory initialization file "rom.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
1076
    Warning (113009): Data at line (6) of memory initialization file "rom.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
1077
    Warning (113009): Data at line (7) of memory initialization file "rom.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
1078
    Warning (113009): Data at line (8) of memory initialization file "rom.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
1079
    Warning (113009): Data at line (9) of memory initialization file "rom.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
1080
    Warning (113009): Data at line (10) of memory initialization file "rom.hex" is too wide to fit in one memory word. Wrapping data to subsequent addresses.
1081
Critical Warning (127005): Memory depth (16384) in the design file differs from memory depth (8364) in the Memory Initialization File "F:/z80soc-local/hw/0.7.3/ROMdata/rom.hex" -- setting initial value for remaining addresses to 0
1082
Info (12021): Found 1 design units, including 1 entities, in source file db/decode_4oa.tdf
1083
    Info (12023): Found entity 1: decode_4oa
1084
Info (12128): Elaborating entity "decode_4oa" for hierarchy "rom:rom_inst|altsyncram:altsyncram_component|altsyncram_tr91:auto_generated|decode_4oa:deep_decode"
1085
Info (12021): Found 1 design units, including 1 entities, in source file db/mux_kib.tdf
1086
    Info (12023): Found entity 1: mux_kib
1087
Info (12128): Elaborating entity "mux_kib" for hierarchy "rom:rom_inst|altsyncram:altsyncram_component|altsyncram_tr91:auto_generated|mux_kib:mux2"
1088
Info (12128): Elaborating entity "clk_div" for hierarchy "clk_div:clkdiv_inst"
1089
Info (12128): Elaborating entity "decoder_7seg" for hierarchy "decoder_7seg:DISPHEX0"
1090
Info (12128): Elaborating entity "ps2kbd" for hierarchy "ps2kbd:ps2_kbd_inst"
1091
Warning (10492): VHDL Process Statement warning at ps2bkd.vhd(58): signal "caps" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
1092
Warning (10492): VHDL Process Statement warning at ps2bkd.vhd(58): signal "scan_code_sig" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
1093
Info (12128): Elaborating entity "keyboard" for hierarchy "ps2kbd:ps2_kbd_inst|keyboard:kbd_inst"
1094
Warning (19016): Clock multiplexers are found and protected
1095
    Warning (19017): Found clock multiplexer Clk_Z80
1096
Warning (13046): Tri-state node(s) do not directly drive top-level pin(s)
1097
    Warning (13049): Converted tri-state buffer "DI_CPU[0]" feeding internal logic into a wire
1098
    Warning (13049): Converted tri-state buffer "DI_CPU[1]" feeding internal logic into a wire
1099
    Warning (13049): Converted tri-state buffer "DI_CPU[2]" feeding internal logic into a wire
1100
    Warning (13049): Converted tri-state buffer "DI_CPU[3]" feeding internal logic into a wire
1101
    Warning (13049): Converted tri-state buffer "DI_CPU[4]" feeding internal logic into a wire
1102
    Warning (13049): Converted tri-state buffer "DI_CPU[5]" feeding internal logic into a wire
1103
    Warning (13049): Converted tri-state buffer "DI_CPU[6]" feeding internal logic into a wire
1104
    Warning (13049): Converted tri-state buffer "DI_CPU[7]" feeding internal logic into a wire
1105
Warning (12069): Ignored assignment(s) for "CLOCK_27[0]" because "CLOCK_27" is not a bus or array
1106
Warning (12069): Ignored assignment(s) for "CLOCK_27[1]" because "CLOCK_27" is not a bus or array
1107
Warning (13039): The following bidir pins have no drivers
1108
    Warning (13040): Bidir "PS2_DAT" has no driver
1109
    Warning (13040): Bidir "PS2_CLK" has no driver
1110
Warning (13027): Removed fan-outs from the following always-disabled I/O buffers
1111
    Warning (13028): Removed fan-out from the always-disabled I/O buffer "SRAM_DQ[8]" to the node "SRAM_DQ[8]"
1112
    Warning (13028): Removed fan-out from the always-disabled I/O buffer "SRAM_DQ[9]" to the node "SRAM_DQ[9]"
1113
    Warning (13028): Removed fan-out from the always-disabled I/O buffer "SRAM_DQ[10]" to the node "SRAM_DQ[10]"
1114
    Warning (13028): Removed fan-out from the always-disabled I/O buffer "SRAM_DQ[11]" to the node "SRAM_DQ[11]"
1115
    Warning (13028): Removed fan-out from the always-disabled I/O buffer "SRAM_DQ[12]" to the node "SRAM_DQ[12]"
1116
    Warning (13028): Removed fan-out from the always-disabled I/O buffer "SRAM_DQ[13]" to the node "SRAM_DQ[13]"
1117
    Warning (13028): Removed fan-out from the always-disabled I/O buffer "SRAM_DQ[14]" to the node "SRAM_DQ[14]"
1118
    Warning (13028): Removed fan-out from the always-disabled I/O buffer "SRAM_DQ[15]" to the node "SRAM_DQ[15]"
1119
Info (13000): Registers with preset signals will power-up high
1120
Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
1121
Warning (13024): Output pins are stuck at VCC or GND
1122
    Warning (13410): Pin "DRAM_ADDR[0]" is stuck at GND
1123
    Warning (13410): Pin "DRAM_ADDR[1]" is stuck at GND
1124
    Warning (13410): Pin "DRAM_ADDR[2]" is stuck at GND
1125
    Warning (13410): Pin "DRAM_ADDR[3]" is stuck at GND
1126
    Warning (13410): Pin "DRAM_ADDR[4]" is stuck at GND
1127
    Warning (13410): Pin "DRAM_ADDR[5]" is stuck at GND
1128
    Warning (13410): Pin "DRAM_ADDR[6]" is stuck at GND
1129
    Warning (13410): Pin "DRAM_ADDR[7]" is stuck at GND
1130
    Warning (13410): Pin "DRAM_ADDR[8]" is stuck at GND
1131
    Warning (13410): Pin "DRAM_ADDR[9]" is stuck at GND
1132
    Warning (13410): Pin "DRAM_ADDR[10]" is stuck at GND
1133
    Warning (13410): Pin "DRAM_ADDR[11]" is stuck at GND
1134
    Warning (13410): Pin "DRAM_LDQM" is stuck at GND
1135
    Warning (13410): Pin "DRAM_UDQM" is stuck at GND
1136
    Warning (13410): Pin "DRAM_WE_N" is stuck at VCC
1137
    Warning (13410): Pin "DRAM_CAS_N" is stuck at VCC
1138
    Warning (13410): Pin "DRAM_RAS_N" is stuck at VCC
1139
    Warning (13410): Pin "DRAM_CS_N" is stuck at VCC
1140
    Warning (13410): Pin "DRAM_BA_0" is stuck at GND
1141
    Warning (13410): Pin "DRAM_BA_1" is stuck at GND
1142
    Warning (13410): Pin "DRAM_CLK" is stuck at GND
1143
    Warning (13410): Pin "DRAM_CKE" is stuck at GND
1144
    Warning (13410): Pin "FL_ADDR[0]" is stuck at GND
1145
    Warning (13410): Pin "FL_ADDR[1]" is stuck at GND
1146
    Warning (13410): Pin "FL_ADDR[2]" is stuck at GND
1147
    Warning (13410): Pin "FL_ADDR[3]" is stuck at GND
1148
    Warning (13410): Pin "FL_ADDR[4]" is stuck at GND
1149
    Warning (13410): Pin "FL_ADDR[5]" is stuck at GND
1150
    Warning (13410): Pin "FL_ADDR[6]" is stuck at GND
1151
    Warning (13410): Pin "FL_ADDR[7]" is stuck at GND
1152
    Warning (13410): Pin "FL_ADDR[8]" is stuck at GND
1153
    Warning (13410): Pin "FL_ADDR[9]" is stuck at GND
1154
    Warning (13410): Pin "FL_ADDR[10]" is stuck at GND
1155
    Warning (13410): Pin "FL_ADDR[11]" is stuck at GND
1156
    Warning (13410): Pin "FL_ADDR[12]" is stuck at GND
1157
    Warning (13410): Pin "FL_ADDR[13]" is stuck at GND
1158
    Warning (13410): Pin "FL_ADDR[14]" is stuck at GND
1159
    Warning (13410): Pin "FL_ADDR[15]" is stuck at GND
1160
    Warning (13410): Pin "FL_ADDR[16]" is stuck at GND
1161
    Warning (13410): Pin "FL_ADDR[17]" is stuck at GND
1162
    Warning (13410): Pin "FL_ADDR[18]" is stuck at GND
1163
    Warning (13410): Pin "FL_ADDR[19]" is stuck at GND
1164
    Warning (13410): Pin "FL_ADDR[20]" is stuck at GND
1165
    Warning (13410): Pin "FL_ADDR[21]" is stuck at GND
1166
    Warning (13410): Pin "FL_WE_N" is stuck at VCC
1167
    Warning (13410): Pin "FL_RST_N" is stuck at GND
1168
    Warning (13410): Pin "FL_OE_N" is stuck at VCC
1169
    Warning (13410): Pin "FL_CE_N" is stuck at VCC
1170
    Warning (13410): Pin "SRAM_ADDR[16]" is stuck at GND
1171
    Warning (13410): Pin "SRAM_ADDR[17]" is stuck at GND
1172
    Warning (13410): Pin "SRAM_UB_N" is stuck at VCC
1173
    Warning (13410): Pin "SRAM_LB_N" is stuck at GND
1174
    Warning (13410): Pin "SRAM_CE_N" is stuck at GND
1175
    Warning (13410): Pin "SD_DAT3" is stuck at GND
1176
    Warning (13410): Pin "SD_CMD" is stuck at GND
1177
    Warning (13410): Pin "SD_CLK" is stuck at GND
1178
    Warning (13410): Pin "TDO" is stuck at GND
1179
    Warning (13410): Pin "I2C_SCLK" is stuck at GND
1180
    Warning (13410): Pin "VGA_R[0]" is stuck at GND
1181
    Warning (13410): Pin "VGA_R[1]" is stuck at GND
1182
    Warning (13410): Pin "VGA_R[2]" is stuck at GND
1183
    Warning (13410): Pin "VGA_R[3]" is stuck at GND
1184
    Warning (13410): Pin "VGA_G[0]" is stuck at GND
1185
    Warning (13410): Pin "VGA_G[1]" is stuck at GND
1186
    Warning (13410): Pin "VGA_G[2]" is stuck at GND
1187
    Warning (13410): Pin "VGA_G[3]" is stuck at GND
1188
    Warning (13410): Pin "AUD_DACDAT" is stuck at GND
1189
    Warning (13410): Pin "AUD_XCK" is stuck at GND
1190
Info (17049): 6 registers lost all their fanouts during netlist optimizations.
1191
Info (16010): Generating hard_block partition "hard_block:auto_generated_inst"
1192
    Info (16011): Adding 0 node(s), including 0 DDIO, 0 PLL, 0 transceiver and 0 LCELL
1193
Warning (21074): Design contains 9 input pin(s) that do not drive logic
1194
    Warning (15610): No output dependent on input pin "CLOCK_27"
1195
    Warning (15610): No output dependent on input pin "EXT_CLOCK"
1196
    Warning (15610): No output dependent on input pin "UART_RXD"
1197
    Warning (15610): No output dependent on input pin "IRDA_RXD"
1198
    Warning (15610): No output dependent on input pin "SD_DAT"
1199
    Warning (15610): No output dependent on input pin "TDI"
1200
    Warning (15610): No output dependent on input pin "TCK"
1201
    Warning (15610): No output dependent on input pin "TCS"
1202
    Warning (15610): No output dependent on input pin "AUD_ADCDAT"
1203
Info (21057): Implemented 3088 device resources after synthesis - the final resource count might be different
1204
    Info (21058): Implemented 24 input pins
1205
    Info (21059): Implemented 139 output pins
1206
    Info (21060): Implemented 118 bidirectional pins
1207
    Info (21061): Implemented 2751 logic cells
1208
    Info (21064): Implemented 56 RAM segments
1209
Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 139 warnings
1210
    Info: Peak virtual memory: 544 megabytes
1211
    Info: Processing ended: Sun Jun 19 14:41:59 2016
1212
    Info: Elapsed time: 00:01:05
1213
    Info: Total CPU time (on all processors): 00:00:45
1214
 
1215
 

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