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TimeQuest Timing Analyzer report for 073DE2115e

Sun Jun 19 13:46:22 2016

Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition

---------------------

; Table of Contents ;

---------------------

  1. Legal Notice

  2. TimeQuest Timing Analyzer Summary

  3. Parallel Compilation

  4. Clocks

  5. Slow 1200mV 85C Model Fmax Summary

  6. Timing Closure Recommendations

  7. Slow 1200mV 85C Model Setup Summary

  8. Slow 1200mV 85C Model Hold Summary

  9. Slow 1200mV 85C Model Recovery Summary

 10. Slow 1200mV 85C Model Removal Summary

 11. Slow 1200mV 85C Model Minimum Pulse Width Summary

 12. Slow 1200mV 85C Model Setup: 'SW[16]'

 13. Slow 1200mV 85C Model Setup: 'LCD:lcd_inst|clk_400hz_enable'

 14. Slow 1200mV 85C Model Setup: 'CLOCK_50'

 15. Slow 1200mV 85C Model Setup: 'clk_div:clkdiv_inst|clock_25MHz'

 16. Slow 1200mV 85C Model Setup: 'clk_div:clkdiv_inst|clock_100Hz'

 17. Slow 1200mV 85C Model Setup: 'T80se:z80_inst|MREQ_n'

 18. Slow 1200mV 85C Model Setup: 'ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered'

 19. Slow 1200mV 85C Model Setup: 'clk_div:clkdiv_inst|clock_25Mhz_int'

 20. Slow 1200mV 85C Model Setup: 'clk_div:clkdiv_inst|clock_1Mhz_int'

 21. Slow 1200mV 85C Model Setup: 'clk_div:clkdiv_inst|clock_100Khz_int'

 22. Slow 1200mV 85C Model Setup: 'clk_div:clkdiv_inst|clock_10Khz_int'

 23. Slow 1200mV 85C Model Setup: 'clk_div:clkdiv_inst|clock_1Khz_int'

 24. Slow 1200mV 85C Model Hold: 'SW[16]'

 25. Slow 1200mV 85C Model Hold: 'ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered'

 26. Slow 1200mV 85C Model Hold: 'CLOCK_50'

 27. Slow 1200mV 85C Model Hold: 'T80se:z80_inst|MREQ_n'

 28. Slow 1200mV 85C Model Hold: 'clk_div:clkdiv_inst|clock_100Khz_int'

 29. Slow 1200mV 85C Model Hold: 'clk_div:clkdiv_inst|clock_10Khz_int'

 30. Slow 1200mV 85C Model Hold: 'clk_div:clkdiv_inst|clock_1Mhz_int'

 31. Slow 1200mV 85C Model Hold: 'clk_div:clkdiv_inst|clock_25MHz'

 32. Slow 1200mV 85C Model Hold: 'clk_div:clkdiv_inst|clock_1Khz_int'

 33. Slow 1200mV 85C Model Hold: 'clk_div:clkdiv_inst|clock_100Hz'

 34. Slow 1200mV 85C Model Hold: 'clk_div:clkdiv_inst|clock_25Mhz_int'

 35. Slow 1200mV 85C Model Hold: 'LCD:lcd_inst|clk_400hz_enable'

 36. Slow 1200mV 85C Model Recovery: 'ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set'

 37. Slow 1200mV 85C Model Removal: 'ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set'

 38. Slow 1200mV 85C Model Minimum Pulse Width: 'SW[16]'

 39. Slow 1200mV 85C Model Minimum Pulse Width: 'CLOCK_50'

 40. Slow 1200mV 85C Model Minimum Pulse Width: 'clk_div:clkdiv_inst|clock_25MHz'

 41. Slow 1200mV 85C Model Minimum Pulse Width: 'ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered'

 42. Slow 1200mV 85C Model Minimum Pulse Width: 'LCD:lcd_inst|clk_400hz_enable'

 43. Slow 1200mV 85C Model Minimum Pulse Width: 'clk_div:clkdiv_inst|clock_25Mhz_int'

 44. Slow 1200mV 85C Model Minimum Pulse Width: 'clk_div:clkdiv_inst|clock_100Khz_int'

 45. Slow 1200mV 85C Model Minimum Pulse Width: 'clk_div:clkdiv_inst|clock_10Khz_int'

 46. Slow 1200mV 85C Model Minimum Pulse Width: 'clk_div:clkdiv_inst|clock_1Khz_int'

 47. Slow 1200mV 85C Model Minimum Pulse Width: 'clk_div:clkdiv_inst|clock_1Mhz_int'

 48. Slow 1200mV 85C Model Minimum Pulse Width: 'clk_div:clkdiv_inst|clock_100Hz'

 49. Slow 1200mV 85C Model Minimum Pulse Width: 'ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set'

 50. Slow 1200mV 85C Model Minimum Pulse Width: 'T80se:z80_inst|MREQ_n'

 51. Setup Times

 52. Hold Times

 53. Clock to Output Times

 54. Minimum Clock to Output Times

 55. Output Enable Times

 56. Minimum Output Enable Times

 57. Output Disable Times

 58. Minimum Output Disable Times

 59. Slow 1200mV 85C Model Metastability Report

 60. Slow 1200mV 0C Model Fmax Summary

 61. Slow 1200mV 0C Model Setup Summary

 62. Slow 1200mV 0C Model Hold Summary

 63. Slow 1200mV 0C Model Recovery Summary

 64. Slow 1200mV 0C Model Removal Summary

 65. Slow 1200mV 0C Model Minimum Pulse Width Summary

 66. Slow 1200mV 0C Model Setup: 'SW[16]'

 67. Slow 1200mV 0C Model Setup: 'LCD:lcd_inst|clk_400hz_enable'

 68. Slow 1200mV 0C Model Setup: 'CLOCK_50'

 69. Slow 1200mV 0C Model Setup: 'clk_div:clkdiv_inst|clock_25MHz'

 70. Slow 1200mV 0C Model Setup: 'clk_div:clkdiv_inst|clock_100Hz'

 71. Slow 1200mV 0C Model Setup: 'T80se:z80_inst|MREQ_n'

 72. Slow 1200mV 0C Model Setup: 'ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered'

 73. Slow 1200mV 0C Model Setup: 'clk_div:clkdiv_inst|clock_25Mhz_int'

 74. Slow 1200mV 0C Model Setup: 'clk_div:clkdiv_inst|clock_1Mhz_int'

 75. Slow 1200mV 0C Model Setup: 'clk_div:clkdiv_inst|clock_100Khz_int'

 76. Slow 1200mV 0C Model Setup: 'clk_div:clkdiv_inst|clock_10Khz_int'

 77. Slow 1200mV 0C Model Setup: 'clk_div:clkdiv_inst|clock_1Khz_int'

 78. Slow 1200mV 0C Model Hold: 'SW[16]'

 79. Slow 1200mV 0C Model Hold: 'ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered'

 80. Slow 1200mV 0C Model Hold: 'CLOCK_50'

 81. Slow 1200mV 0C Model Hold: 'clk_div:clkdiv_inst|clock_100Khz_int'

 82. Slow 1200mV 0C Model Hold: 'clk_div:clkdiv_inst|clock_10Khz_int'

 83. Slow 1200mV 0C Model Hold: 'clk_div:clkdiv_inst|clock_1Mhz_int'

 84. Slow 1200mV 0C Model Hold: 'T80se:z80_inst|MREQ_n'

 85. Slow 1200mV 0C Model Hold: 'clk_div:clkdiv_inst|clock_25MHz'

 86. Slow 1200mV 0C Model Hold: 'clk_div:clkdiv_inst|clock_1Khz_int'

 87. Slow 1200mV 0C Model Hold: 'clk_div:clkdiv_inst|clock_100Hz'

 88. Slow 1200mV 0C Model Hold: 'clk_div:clkdiv_inst|clock_25Mhz_int'

 89. Slow 1200mV 0C Model Hold: 'LCD:lcd_inst|clk_400hz_enable'

 90. Slow 1200mV 0C Model Recovery: 'ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set'

 91. Slow 1200mV 0C Model Removal: 'ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set'

 92. Slow 1200mV 0C Model Minimum Pulse Width: 'SW[16]'

 93. Slow 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'

 94. Slow 1200mV 0C Model Minimum Pulse Width: 'clk_div:clkdiv_inst|clock_25MHz'

 95. Slow 1200mV 0C Model Minimum Pulse Width: 'ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered'

 96. Slow 1200mV 0C Model Minimum Pulse Width: 'LCD:lcd_inst|clk_400hz_enable'

 97. Slow 1200mV 0C Model Minimum Pulse Width: 'clk_div:clkdiv_inst|clock_25Mhz_int'

 98. Slow 1200mV 0C Model Minimum Pulse Width: 'clk_div:clkdiv_inst|clock_100Khz_int'

 99. Slow 1200mV 0C Model Minimum Pulse Width: 'clk_div:clkdiv_inst|clock_10Khz_int'

100. Slow 1200mV 0C Model Minimum Pulse Width: 'clk_div:clkdiv_inst|clock_1Khz_int'

101. Slow 1200mV 0C Model Minimum Pulse Width: 'clk_div:clkdiv_inst|clock_1Mhz_int'

102. Slow 1200mV 0C Model Minimum Pulse Width: 'clk_div:clkdiv_inst|clock_100Hz'

103. Slow 1200mV 0C Model Minimum Pulse Width: 'ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set'

104. Slow 1200mV 0C Model Minimum Pulse Width: 'T80se:z80_inst|MREQ_n'

105. Setup Times

106. Hold Times

107. Clock to Output Times

108. Minimum Clock to Output Times

109. Output Enable Times

110. Minimum Output Enable Times

111. Output Disable Times

112. Minimum Output Disable Times

113. Slow 1200mV 0C Model Metastability Report

114. Fast 1200mV 0C Model Setup Summary

115. Fast 1200mV 0C Model Hold Summary

116. Fast 1200mV 0C Model Recovery Summary

117. Fast 1200mV 0C Model Removal Summary

118. Fast 1200mV 0C Model Minimum Pulse Width Summary

119. Fast 1200mV 0C Model Setup: 'LCD:lcd_inst|clk_400hz_enable'

120. Fast 1200mV 0C Model Setup: 'SW[16]'

121. Fast 1200mV 0C Model Setup: 'CLOCK_50'

122. Fast 1200mV 0C Model Setup: 'clk_div:clkdiv_inst|clock_100Hz'

123. Fast 1200mV 0C Model Setup: 'clk_div:clkdiv_inst|clock_25MHz'

124. Fast 1200mV 0C Model Setup: 'T80se:z80_inst|MREQ_n'

125. Fast 1200mV 0C Model Setup: 'ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered'

126. Fast 1200mV 0C Model Setup: 'clk_div:clkdiv_inst|clock_25Mhz_int'

127. Fast 1200mV 0C Model Setup: 'clk_div:clkdiv_inst|clock_100Khz_int'

128. Fast 1200mV 0C Model Setup: 'clk_div:clkdiv_inst|clock_1Mhz_int'

129. Fast 1200mV 0C Model Setup: 'clk_div:clkdiv_inst|clock_10Khz_int'

130. Fast 1200mV 0C Model Setup: 'clk_div:clkdiv_inst|clock_1Khz_int'

131. Fast 1200mV 0C Model Hold: 'SW[16]'

132. Fast 1200mV 0C Model Hold: 'ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered'

133. Fast 1200mV 0C Model Hold: 'CLOCK_50'

134. Fast 1200mV 0C Model Hold: 'T80se:z80_inst|MREQ_n'

135. Fast 1200mV 0C Model Hold: 'clk_div:clkdiv_inst|clock_100Khz_int'

136. Fast 1200mV 0C Model Hold: 'clk_div:clkdiv_inst|clock_10Khz_int'

137. Fast 1200mV 0C Model Hold: 'clk_div:clkdiv_inst|clock_1Mhz_int'

138. Fast 1200mV 0C Model Hold: 'clk_div:clkdiv_inst|clock_25MHz'

139. Fast 1200mV 0C Model Hold: 'clk_div:clkdiv_inst|clock_1Khz_int'

140. Fast 1200mV 0C Model Hold: 'clk_div:clkdiv_inst|clock_100Hz'

141. Fast 1200mV 0C Model Hold: 'clk_div:clkdiv_inst|clock_25Mhz_int'

142. Fast 1200mV 0C Model Hold: 'LCD:lcd_inst|clk_400hz_enable'

143. Fast 1200mV 0C Model Recovery: 'ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set'

144. Fast 1200mV 0C Model Removal: 'ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set'

145. Fast 1200mV 0C Model Minimum Pulse Width: 'SW[16]'

146. Fast 1200mV 0C Model Minimum Pulse Width: 'CLOCK_50'

147. Fast 1200mV 0C Model Minimum Pulse Width: 'clk_div:clkdiv_inst|clock_25MHz'

148. Fast 1200mV 0C Model Minimum Pulse Width: 'ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered'

149. Fast 1200mV 0C Model Minimum Pulse Width: 'LCD:lcd_inst|clk_400hz_enable'

150. Fast 1200mV 0C Model Minimum Pulse Width: 'clk_div:clkdiv_inst|clock_25Mhz_int'

151. Fast 1200mV 0C Model Minimum Pulse Width: 'clk_div:clkdiv_inst|clock_100Khz_int'

152. Fast 1200mV 0C Model Minimum Pulse Width: 'clk_div:clkdiv_inst|clock_10Khz_int'

153. Fast 1200mV 0C Model Minimum Pulse Width: 'clk_div:clkdiv_inst|clock_1Khz_int'

154. Fast 1200mV 0C Model Minimum Pulse Width: 'clk_div:clkdiv_inst|clock_1Mhz_int'

155. Fast 1200mV 0C Model Minimum Pulse Width: 'clk_div:clkdiv_inst|clock_100Hz'

156. Fast 1200mV 0C Model Minimum Pulse Width: 'ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set'

157. Fast 1200mV 0C Model Minimum Pulse Width: 'T80se:z80_inst|MREQ_n'

158. Setup Times

159. Hold Times

160. Clock to Output Times

161. Minimum Clock to Output Times

162. Output Enable Times

163. Minimum Output Enable Times

164. Output Disable Times

165. Minimum Output Disable Times

166. Fast 1200mV 0C Model Metastability Report

167. Multicorner Timing Analysis Summary

168. Setup Times

169. Hold Times

170. Clock to Output Times

171. Minimum Clock to Output Times

172. Board Trace Model Assignments

173. Input Transition Times

174. Signal Integrity Metrics (Slow 1200mv 0c Model)

175. Signal Integrity Metrics (Slow 1200mv 85c Model)

176. Signal Integrity Metrics (Fast 1200mv 0c Model)

177. Setup Transfers

178. Hold Transfers

179. Recovery Transfers

180. Removal Transfers

181. Report TCCS

182. Report RSKM

183. Unconstrained Paths

184. TimeQuest Timing Analyzer Messages

----------------

; Legal Notice ;

----------------

Copyright (C) 1991-2013 Altera Corporation

Your use of Altera Corporation's design tools, logic functions

and other software and tools, and its AMPP partner logic

functions, and any output files from any of the foregoing

(including device programming or simulation files), and any

associated documentation or information are expressly subject

to the terms and conditions of the Altera Program License

Subscription Agreement, Altera MegaCore Function License

Agreement, or other applicable license agreement, including,

without limitation, that your use is for the sole purpose of

programming logic devices manufactured by Altera and sold by

Altera or its authorized distributors.  Please refer to the

applicable agreement for further details.

+----------------------------------------------------------------------------------------+

; TimeQuest Timing Analyzer Summary                                                      ;

+--------------------+-------------------------------------------------------------------+

; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;

; Revision Name      ; 073DE2115e                                                        ;

; Device Family      ; Cyclone IV E                                                      ;

; Device Name        ; EP4CE115F29C7                                                     ;

; Timing Models      ; Final                                                             ;

; Delay Model        ; Combined                                                          ;

; Rise/Fall Delays   ; Enabled                                                           ;

+--------------------+-------------------------------------------------------------------+

Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.

+-------------------------------------+

; Parallel Compilation                ;

+----------------------------+--------+

; Processors                 ; Number ;

+----------------------------+--------+

; Number detected on machine ; 2      ;

; Maximum allowed            ; 1      ;

+----------------------------+--------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

; Clocks                                                                                                                                                                                                                                                                                   ;

+-------------------------------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------------------------------+

; Clock Name                                                  ; Type ; Period ; Frequency  ; Rise  ; Fall  ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets                                                         ;

+-------------------------------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------------------------------+

; clk_div:clkdiv_inst|clock_1Khz_int                          ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { clk_div:clkdiv_inst|clock_1Khz_int }                          ;

; clk_div:clkdiv_inst|clock_1Mhz_int                          ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { clk_div:clkdiv_inst|clock_1Mhz_int }                          ;

; clk_div:clkdiv_inst|clock_10Khz_int                         ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { clk_div:clkdiv_inst|clock_10Khz_int }                         ;

; clk_div:clkdiv_inst|clock_25MHz                             ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { clk_div:clkdiv_inst|clock_25MHz }                             ;

; clk_div:clkdiv_inst|clock_25Mhz_int                         ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { clk_div:clkdiv_inst|clock_25Mhz_int }                         ;

; clk_div:clkdiv_inst|clock_100Hz                             ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { clk_div:clkdiv_inst|clock_100Hz }                             ;

; clk_div:clkdiv_inst|clock_100Khz_int                        ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { clk_div:clkdiv_inst|clock_100Khz_int }                        ;

; CLOCK_50                                                    ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { CLOCK_50 }                                                    ;

; LCD:lcd_inst|clk_400hz_enable                               ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { LCD:lcd_inst|clk_400hz_enable }                               ;

; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered } ;

; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set             ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set }             ;

; SW[16]                                                      ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { SW[16] }                                                      ;

; T80se:z80_inst|MREQ_n                                       ; Base ; 1.000  ; 1000.0 MHz ; 0.000 ; 0.500 ;            ;           ;             ;       ;        ;           ;            ;          ;        ;        ; { T80se:z80_inst|MREQ_n }                                       ;

+-------------------------------------------------------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-----------------------------------------------------------------+

+---------------------------------------------------------------------------------------------------------------------------------------------+

; Slow 1200mV 85C Model Fmax Summary                                                                                                          ;

+------------+-----------------+-------------------------------------------------------------+------------------------------------------------+

; Fmax       ; Restricted Fmax ; Clock Name                                                  ; Note                                           ;

+------------+-----------------+-------------------------------------------------------------+------------------------------------------------+

; 73.86 MHz  ; 73.86 MHz       ; SW[16]                                                      ;                                                ;

; 149.37 MHz ; 149.37 MHz      ; clk_div:clkdiv_inst|clock_25MHz                             ;                                                ;

; 234.58 MHz ; 234.58 MHz      ; CLOCK_50                                                    ;                                                ;

; 306.56 MHz ; 306.56 MHz      ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ;                                                ;

; 527.7 MHz  ; 437.64 MHz      ; clk_div:clkdiv_inst|clock_25Mhz_int                         ; limit due to minimum period restriction (tmin) ;

; 605.69 MHz ; 437.64 MHz      ; clk_div:clkdiv_inst|clock_1Mhz_int                          ; limit due to minimum period restriction (tmin) ;

; 653.59 MHz ; 437.64 MHz      ; clk_div:clkdiv_inst|clock_100Khz_int                        ; limit due to minimum period restriction (tmin) ;

; 657.46 MHz ; 437.64 MHz      ; clk_div:clkdiv_inst|clock_10Khz_int                         ; limit due to minimum period restriction (tmin) ;

; 840.34 MHz ; 437.64 MHz      ; clk_div:clkdiv_inst|clock_1Khz_int                          ; limit due to minimum period restriction (tmin) ;

; 920.81 MHz ; 437.64 MHz      ; clk_div:clkdiv_inst|clock_100Hz                             ; limit due to minimum period restriction (tmin) ;

+------------+-----------------+-------------------------------------------------------------+------------------------------------------------+

This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.

----------------------------------

; Timing Closure Recommendations ;

----------------------------------

HTML report is unavailable in plain text report export.

+---------------------------------------------------------------------------------------+

; Slow 1200mV 85C Model Setup Summary                                                   ;

+-------------------------------------------------------------+---------+---------------+

; Clock                                                       ; Slack   ; End Point TNS ;

+-------------------------------------------------------------+---------+---------------+

; SW[16]                                                      ; -12.540 ; -3745.302     ;

; LCD:lcd_inst|clk_400hz_enable                               ; -11.704 ; -88.730       ;

; CLOCK_50                                                    ; -7.823  ; -185.058      ;

; clk_div:clkdiv_inst|clock_25MHz                             ; -5.695  ; -252.613      ;

; clk_div:clkdiv_inst|clock_100Hz                             ; -5.245  ; -10.490       ;

; T80se:z80_inst|MREQ_n                                       ; -2.601  ; -435.678      ;

; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; -2.262  ; -38.292       ;

; clk_div:clkdiv_inst|clock_25Mhz_int                         ; -0.895  ; -4.526        ;

; clk_div:clkdiv_inst|clock_1Mhz_int                          ; -0.651  ; -1.066        ;

; clk_div:clkdiv_inst|clock_100Khz_int                        ; -0.530  ; -0.826        ;

; clk_div:clkdiv_inst|clock_10Khz_int                         ; -0.521  ; -0.804        ;

; clk_div:clkdiv_inst|clock_1Khz_int                          ; -0.190  ; -0.495        ;

+-------------------------------------------------------------+---------+---------------+

+--------------------------------------------------------------------------------------+

; Slow 1200mV 85C Model Hold Summary                                                   ;

+-------------------------------------------------------------+--------+---------------+

; Clock                                                       ; Slack  ; End Point TNS ;

+-------------------------------------------------------------+--------+---------------+

; SW[16]                                                      ; -2.980 ; -135.492      ;

; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; -0.439 ; -0.439        ;

; CLOCK_50                                                    ; -0.254 ; -0.669        ;

; T80se:z80_inst|MREQ_n                                       ; 0.033  ; 0.000         ;

; clk_div:clkdiv_inst|clock_100Khz_int                        ; 0.079  ; 0.000         ;

; clk_div:clkdiv_inst|clock_10Khz_int                         ; 0.098  ; 0.000         ;

; clk_div:clkdiv_inst|clock_1Mhz_int                          ; 0.189  ; 0.000         ;

; clk_div:clkdiv_inst|clock_25MHz                             ; 0.343  ; 0.000         ;

; clk_div:clkdiv_inst|clock_1Khz_int                          ; 0.440  ; 0.000         ;

; clk_div:clkdiv_inst|clock_100Hz                             ; 0.454  ; 0.000         ;

; clk_div:clkdiv_inst|clock_25Mhz_int                         ; 0.472  ; 0.000         ;

; LCD:lcd_inst|clk_400hz_enable                               ; 2.342  ; 0.000         ;

+-------------------------------------------------------------+--------+---------------+

+--------------------------------------------------------------------------+

; Slow 1200mV 85C Model Recovery Summary                                   ;

+-------------------------------------------------+--------+---------------+

; Clock                                           ; Slack  ; End Point TNS ;

+-------------------------------------------------+--------+---------------+

; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set ; -2.630 ; -2.630        ;

+-------------------------------------------------+--------+---------------+

+-------------------------------------------------------------------------+

; Slow 1200mV 85C Model Removal Summary                                   ;

+-------------------------------------------------+-------+---------------+

; Clock                                           ; Slack ; End Point TNS ;

+-------------------------------------------------+-------+---------------+

; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set ; 3.090 ; 0.000         ;

+-------------------------------------------------+-------+---------------+

+--------------------------------------------------------------------------------------+

; Slow 1200mV 85C Model Minimum Pulse Width Summary                                    ;

+-------------------------------------------------------------+--------+---------------+

; Clock                                                       ; Slack  ; End Point TNS ;

+-------------------------------------------------------------+--------+---------------+

; SW[16]                                                      ; -3.000 ; -612.867      ;

; CLOCK_50                                                    ; -3.000 ; -141.780      ;

; clk_div:clkdiv_inst|clock_25MHz                             ; -2.693 ; -178.641      ;

; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; -1.285 ; -29.555       ;

; LCD:lcd_inst|clk_400hz_enable                               ; -1.285 ; -10.280       ;

; clk_div:clkdiv_inst|clock_25Mhz_int                         ; -1.285 ; -7.710        ;

; clk_div:clkdiv_inst|clock_100Khz_int                        ; -1.285 ; -5.140        ;

; clk_div:clkdiv_inst|clock_10Khz_int                         ; -1.285 ; -5.140        ;

; clk_div:clkdiv_inst|clock_1Khz_int                          ; -1.285 ; -5.140        ;

; clk_div:clkdiv_inst|clock_1Mhz_int                          ; -1.285 ; -5.140        ;

; clk_div:clkdiv_inst|clock_100Hz                             ; -1.285 ; -2.570        ;

; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set             ; -1.285 ; -1.285        ;

; T80se:z80_inst|MREQ_n                                       ; 0.320  ; 0.000         ;

+-------------------------------------------------------------+--------+---------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------+

; Slow 1200mV 85C Model Setup: 'SW[16]'                                                                                                                            ;

+---------+---------------------------------+------------------------------------------------+--------------+-------------+--------------+------------+------------+

; Slack   ; From Node                       ; To Node                                        ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;

+---------+---------------------------------+------------------------------------------------+--------------+-------------+--------------+------------+------------+

; -12.540 ; T80se:z80_inst|T80:u0|IR[6]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[7][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.089     ; 13.449     ;

; -12.536 ; T80se:z80_inst|T80:u0|IR[6]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[5][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.089     ; 13.445     ;

; -12.487 ; T80se:z80_inst|T80:u0|MCycle[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[7][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.122     ; 13.363     ;

; -12.485 ; T80se:z80_inst|T80:u0|IR[1]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[7][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.122     ; 13.361     ;

; -12.483 ; T80se:z80_inst|T80:u0|MCycle[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[5][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.122     ; 13.359     ;

; -12.481 ; T80se:z80_inst|T80:u0|IR[1]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[5][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.122     ; 13.357     ;

; -12.480 ; T80se:z80_inst|T80:u0|IR[6]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[6][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.083     ; 13.395     ;

; -12.478 ; T80se:z80_inst|T80:u0|IR[6]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[0][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.083     ; 13.393     ;

; -12.474 ; T80se:z80_inst|T80:u0|MCycle[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[7][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.122     ; 13.350     ;

; -12.470 ; T80se:z80_inst|T80:u0|MCycle[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[5][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.122     ; 13.346     ;

; -12.461 ; T80se:z80_inst|T80:u0|F[0]      ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[7][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.089     ; 13.370     ;

; -12.457 ; T80se:z80_inst|T80:u0|F[0]      ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[5][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.089     ; 13.366     ;

; -12.450 ; T80se:z80_inst|T80:u0|MCycle[1] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[7][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.122     ; 13.326     ;

; -12.446 ; T80se:z80_inst|T80:u0|MCycle[1] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[5][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.122     ; 13.322     ;

; -12.442 ; T80se:z80_inst|T80:u0|IR[5]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[7][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.089     ; 13.351     ;

; -12.438 ; T80se:z80_inst|T80:u0|IR[5]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[5][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.089     ; 13.347     ;

; -12.433 ; T80se:z80_inst|T80:u0|IR[2]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[7][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.122     ; 13.309     ;

; -12.429 ; T80se:z80_inst|T80:u0|IR[2]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[5][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.122     ; 13.305     ;

; -12.427 ; T80se:z80_inst|T80:u0|MCycle[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[6][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.116     ; 13.309     ;

; -12.425 ; T80se:z80_inst|T80:u0|MCycle[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[0][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.116     ; 13.307     ;

; -12.425 ; T80se:z80_inst|T80:u0|IR[1]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[6][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.116     ; 13.307     ;

; -12.423 ; T80se:z80_inst|T80:u0|IR[1]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[0][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.116     ; 13.305     ;

; -12.418 ; T80se:z80_inst|T80:u0|F[2]      ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[7][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.116     ; 13.300     ;

; -12.414 ; T80se:z80_inst|T80:u0|F[2]      ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[5][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.116     ; 13.296     ;

; -12.414 ; T80se:z80_inst|T80:u0|MCycle[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[6][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.116     ; 13.296     ;

; -12.413 ; T80se:z80_inst|T80:u0|IR[4]     ; T80se:z80_inst|T80:u0|A[14]                    ; SW[16]       ; SW[16]      ; 1.000        ; -2.770     ; 10.641     ;

; -12.412 ; T80se:z80_inst|T80:u0|MCycle[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[0][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.116     ; 13.294     ;

; -12.401 ; T80se:z80_inst|T80:u0|F[0]      ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[6][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.083     ; 13.316     ;

; -12.399 ; T80se:z80_inst|T80:u0|F[0]      ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[0][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.083     ; 13.314     ;

; -12.396 ; T80se:z80_inst|T80:u0|IR[4]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[7][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.089     ; 13.305     ;

; -12.392 ; T80se:z80_inst|T80:u0|IR[4]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[5][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.089     ; 13.301     ;

; -12.390 ; T80se:z80_inst|T80:u0|MCycle[1] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[6][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.116     ; 13.272     ;

; -12.388 ; T80se:z80_inst|T80:u0|MCycle[1] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[0][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.116     ; 13.270     ;

; -12.382 ; T80se:z80_inst|T80:u0|IR[5]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[6][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.083     ; 13.297     ;

; -12.380 ; T80se:z80_inst|T80:u0|F[7]      ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[7][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.116     ; 13.262     ;

; -12.380 ; T80se:z80_inst|T80:u0|IR[5]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[0][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.083     ; 13.295     ;

; -12.377 ; T80se:z80_inst|T80:u0|MCycle[0] ; T80se:z80_inst|T80:u0|A[14]                    ; SW[16]       ; SW[16]      ; 1.000        ; -2.779     ; 10.596     ;

; -12.377 ; T80se:z80_inst|T80:u0|IR[0]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[7][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.121     ; 13.254     ;

; -12.376 ; T80se:z80_inst|T80:u0|F[7]      ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[5][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.116     ; 13.258     ;

; -12.373 ; T80se:z80_inst|T80:u0|IR[2]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[6][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.116     ; 13.255     ;

; -12.373 ; T80se:z80_inst|T80:u0|IR[0]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[5][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.121     ; 13.250     ;

; -12.371 ; T80se:z80_inst|T80:u0|IR[2]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[0][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.116     ; 13.253     ;

; -12.358 ; T80se:z80_inst|T80:u0|F[2]      ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[6][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.110     ; 13.246     ;

; -12.356 ; T80se:z80_inst|T80:u0|F[2]      ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[0][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.110     ; 13.244     ;

; -12.339 ; T80se:z80_inst|T80:u0|F[0]      ; T80se:z80_inst|T80:u0|A[14]                    ; SW[16]       ; SW[16]      ; 1.000        ; -2.770     ; 10.567     ;

; -12.336 ; T80se:z80_inst|T80:u0|IR[4]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[6][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.083     ; 13.251     ;

; -12.335 ; T80se:z80_inst|T80:u0|IR[7]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[7][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.122     ; 13.211     ;

; -12.334 ; T80se:z80_inst|T80:u0|IR[4]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[0][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.083     ; 13.249     ;

; -12.331 ; T80se:z80_inst|T80:u0|IR[7]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[5][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.122     ; 13.207     ;

; -12.320 ; T80se:z80_inst|T80:u0|F[7]      ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[6][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.110     ; 13.208     ;

; -12.318 ; T80se:z80_inst|T80:u0|F[7]      ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[0][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.110     ; 13.206     ;

; -12.317 ; T80se:z80_inst|T80:u0|IR[0]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[6][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.115     ; 13.200     ;

; -12.315 ; T80se:z80_inst|T80:u0|IR[0]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[0][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.115     ; 13.198     ;

; -12.315 ; T80se:z80_inst|T80:u0|F[6]      ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[7][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.089     ; 13.224     ;

; -12.311 ; T80se:z80_inst|T80:u0|F[6]      ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[5][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.089     ; 13.220     ;

; -12.293 ; T80se:z80_inst|T80:u0|IR[6]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[3][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.082     ; 13.209     ;

; -12.289 ; T80se:z80_inst|T80:u0|IR[6]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[2][3] ; SW[16]       ; SW[16]      ; 1.000        ; -0.087     ; 13.200     ;

; -12.288 ; T80se:z80_inst|T80:u0|IR[6]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[1][3] ; SW[16]       ; SW[16]      ; 1.000        ; -0.087     ; 13.199     ;

; -12.275 ; T80se:z80_inst|T80:u0|IR[7]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[6][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.116     ; 13.157     ;

; -12.273 ; T80se:z80_inst|T80:u0|F[2]      ; T80se:z80_inst|T80:u0|A[14]                    ; SW[16]       ; SW[16]      ; 1.000        ; -2.773     ; 10.498     ;

; -12.273 ; T80se:z80_inst|T80:u0|IR[7]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[0][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.116     ; 13.155     ;

; -12.269 ; T80se:z80_inst|T80:u0|IR[5]     ; T80se:z80_inst|T80:u0|A[14]                    ; SW[16]       ; SW[16]      ; 1.000        ; -2.770     ; 10.497     ;

; -12.259 ; T80se:z80_inst|T80:u0|IR[4]     ; T80se:z80_inst|T80:u0|A[9]                     ; SW[16]       ; SW[16]      ; 1.000        ; -2.757     ; 10.500     ;

; -12.259 ; T80se:z80_inst|T80:u0|IR[2]     ; T80se:z80_inst|T80:u0|A[14]                    ; SW[16]       ; SW[16]      ; 1.000        ; -2.779     ; 10.478     ;

; -12.255 ; T80se:z80_inst|T80:u0|F[6]      ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[6][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.083     ; 13.170     ;

; -12.253 ; T80se:z80_inst|T80:u0|F[6]      ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[0][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.083     ; 13.168     ;

; -12.252 ; T80se:z80_inst|T80:u0|IR[4]     ; T80se:z80_inst|T80:u0|A[8]                     ; SW[16]       ; SW[16]      ; 1.000        ; -2.757     ; 10.493     ;

; -12.244 ; T80se:z80_inst|T80:u0|IR[6]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[3][3] ; SW[16]       ; SW[16]      ; 1.000        ; -0.088     ; 13.154     ;

; -12.244 ; T80se:z80_inst|T80:u0|IR[6]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[0][3] ; SW[16]       ; SW[16]      ; 1.000        ; -0.088     ; 13.154     ;

; -12.242 ; T80se:z80_inst|T80:u0|IR[6]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[5][3] ; SW[16]       ; SW[16]      ; 1.000        ; -0.086     ; 13.154     ;

; -12.242 ; T80se:z80_inst|T80:u0|IR[6]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[4][3] ; SW[16]       ; SW[16]      ; 1.000        ; -0.086     ; 13.154     ;

; -12.240 ; T80se:z80_inst|T80:u0|MCycle[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[3][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.115     ; 13.123     ;

; -12.239 ; T80se:z80_inst|T80:u0|IR[3]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[7][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.089     ; 13.148     ;

; -12.238 ; T80se:z80_inst|T80:u0|IR[1]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[3][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.115     ; 13.121     ;

; -12.236 ; T80se:z80_inst|T80:u0|MCycle[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[2][3] ; SW[16]       ; SW[16]      ; 1.000        ; -0.120     ; 13.114     ;

; -12.235 ; T80se:z80_inst|T80:u0|F[7]      ; T80se:z80_inst|T80:u0|A[14]                    ; SW[16]       ; SW[16]      ; 1.000        ; -2.773     ; 10.460     ;

; -12.235 ; T80se:z80_inst|T80:u0|MCycle[2] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[1][3] ; SW[16]       ; SW[16]      ; 1.000        ; -0.120     ; 13.113     ;

; -12.235 ; T80se:z80_inst|T80:u0|IR[3]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[5][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.089     ; 13.144     ;

; -12.234 ; T80se:z80_inst|T80:u0|IR[1]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[2][3] ; SW[16]       ; SW[16]      ; 1.000        ; -0.120     ; 13.112     ;

; -12.233 ; T80se:z80_inst|T80:u0|IR[1]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[1][3] ; SW[16]       ; SW[16]      ; 1.000        ; -0.120     ; 13.111     ;

; -12.232 ; T80se:z80_inst|T80:u0|IR[6]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[4][6] ; SW[16]       ; SW[16]      ; 1.000        ; -0.086     ; 13.144     ;

; -12.229 ; T80se:z80_inst|T80:u0|IR[7]     ; T80se:z80_inst|T80:u0|A[14]                    ; SW[16]       ; SW[16]      ; 1.000        ; -2.779     ; 10.448     ;

; -12.227 ; T80se:z80_inst|T80:u0|MCycle[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[3][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.115     ; 13.110     ;

; -12.223 ; T80se:z80_inst|T80:u0|MCycle[2] ; T80se:z80_inst|T80:u0|A[14]                    ; SW[16]       ; SW[16]      ; 1.000        ; -2.779     ; 10.442     ;

; -12.223 ; T80se:z80_inst|T80:u0|MCycle[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[2][3] ; SW[16]       ; SW[16]      ; 1.000        ; -0.120     ; 13.101     ;

; -12.222 ; T80se:z80_inst|T80:u0|MCycle[0] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[1][3] ; SW[16]       ; SW[16]      ; 1.000        ; -0.120     ; 13.100     ;

; -12.214 ; T80se:z80_inst|T80:u0|IR[6]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[2][5] ; SW[16]       ; SW[16]      ; 1.000        ; -0.087     ; 13.125     ;

; -12.214 ; T80se:z80_inst|T80:u0|F[0]      ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[3][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.082     ; 13.130     ;

; -12.212 ; T80se:z80_inst|T80:u0|IR[6]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[1][5] ; SW[16]       ; SW[16]      ; 1.000        ; -0.087     ; 13.123     ;

; -12.211 ; T80se:z80_inst|T80:u0|MCycle[0] ; T80se:z80_inst|T80:u0|A[9]                     ; SW[16]       ; SW[16]      ; 1.000        ; -2.766     ; 10.443     ;

; -12.210 ; T80se:z80_inst|T80:u0|F[0]      ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[2][3] ; SW[16]       ; SW[16]      ; 1.000        ; -0.087     ; 13.121     ;

; -12.209 ; T80se:z80_inst|T80:u0|F[0]      ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[1][3] ; SW[16]       ; SW[16]      ; 1.000        ; -0.087     ; 13.120     ;

; -12.205 ; T80se:z80_inst|T80:u0|IR[1]     ; T80se:z80_inst|T80:u0|A[14]                    ; SW[16]       ; SW[16]      ; 1.000        ; -2.779     ; 10.424     ;

; -12.203 ; T80se:z80_inst|T80:u0|MCycle[1] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[3][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.115     ; 13.086     ;

; -12.202 ; T80se:z80_inst|T80:u0|IR[4]     ; T80se:z80_inst|T80:u0|A[15]                    ; SW[16]       ; SW[16]      ; 1.000        ; -2.770     ; 10.430     ;

; -12.199 ; T80se:z80_inst|T80:u0|MCycle[1] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[2][3] ; SW[16]       ; SW[16]      ; 1.000        ; -0.120     ; 13.077     ;

; -12.198 ; T80se:z80_inst|T80:u0|MCycle[1] ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[1][3] ; SW[16]       ; SW[16]      ; 1.000        ; -0.120     ; 13.076     ;

; -12.196 ; T80se:z80_inst|T80:u0|IR[6]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[2][1] ; SW[16]       ; SW[16]      ; 1.000        ; -0.087     ; 13.107     ;

; -12.195 ; T80se:z80_inst|T80:u0|MCycle[0] ; T80se:z80_inst|T80:u0|A[8]                     ; SW[16]       ; SW[16]      ; 1.000        ; -2.766     ; 10.427     ;

; -12.195 ; T80se:z80_inst|T80:u0|IR[5]     ; T80se:z80_inst|T80:u0|T80_Reg:Regs|RegsH[3][7] ; SW[16]       ; SW[16]      ; 1.000        ; -0.082     ; 13.111     ;

+---------+---------------------------------+------------------------------------------------+--------------+-------------+--------------+------------+------------+

+----------------------------------------------------------------------------------------------------------------------------------------------+

; Slow 1200mV 85C Model Setup: 'LCD:lcd_inst|clk_400hz_enable'                                                                                 ;

+---------+----------------+------------------+-----------------------+-------------------------------+--------------+------------+------------+

; Slack   ; From Node      ; To Node          ; Launch Clock          ; Latch Clock                   ; Relationship ; Clock Skew ; Data Delay ;

+---------+----------------+------------------+-----------------------+-------------------------------+--------------+------------+------------+

; -11.704 ; lcdvram[28][0] ; next_char_sig[0] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.153     ; 4.059      ;

; -11.460 ; lcdvram[19][0] ; next_char_sig[0] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.784     ; 3.184      ;

; -11.453 ; lcdvram[31][0] ; next_char_sig[0] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.726     ; 3.235      ;

; -11.372 ; lcdvram[20][3] ; next_char_sig[3] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.410     ; 3.470      ;

; -11.283 ; lcdvram[31][5] ; next_char_sig[5] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.633     ; 3.158      ;

; -11.250 ; lcdvram[22][0] ; next_char_sig[0] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -7.815     ; 3.943      ;

; -11.250 ; lcdvram[30][0] ; next_char_sig[0] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -7.875     ; 3.883      ;

; -11.154 ; lcdvram[22][3] ; next_char_sig[3] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -7.770     ; 3.892      ;

; -11.137 ; lcdvram[22][5] ; next_char_sig[5] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -7.720     ; 3.925      ;

; -11.098 ; lcdvram[19][1] ; next_char_sig[1] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.713     ; 2.893      ;

; -11.042 ; lcdvram[10][7] ; next_char_sig[7] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -7.046     ; 4.504      ;

; -11.019 ; lcdvram[16][0] ; next_char_sig[0] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.686     ; 2.841      ;

; -11.013 ; lcdvram[16][3] ; next_char_sig[3] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.822     ; 2.699      ;

; -10.986 ; lcdvram[3][7]  ; next_char_sig[7] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -7.035     ; 4.459      ;

; -10.971 ; lcdvram[31][2] ; next_char_sig[2] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.686     ; 2.793      ;

; -10.954 ; lcdvram[19][3] ; next_char_sig[3] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.590     ; 2.872      ;

; -10.944 ; lcdvram[16][5] ; next_char_sig[5] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.744     ; 2.708      ;

; -10.923 ; lcdvram[17][0] ; next_char_sig[0] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.478     ; 2.953      ;

; -10.916 ; lcdvram[6][0]  ; next_char_sig[0] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -7.409     ; 4.015      ;

; -10.913 ; lcdvram[19][7] ; next_char_sig[7] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.813     ; 2.608      ;

; -10.841 ; lcdvram[17][2] ; next_char_sig[2] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.495     ; 2.854      ;

; -10.829 ; lcdvram[27][3] ; next_char_sig[3] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.506     ; 2.831      ;

; -10.801 ; lcdvram[19][6] ; next_char_sig[6] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.693     ; 2.616      ;

; -10.791 ; lcdvram[0][5]  ; next_char_sig[5] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -7.541     ; 3.758      ;

; -10.770 ; lcdvram[4][0]  ; next_char_sig[0] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -7.116     ; 4.162      ;

; -10.768 ; lcdvram[27][1] ; next_char_sig[1] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.443     ; 2.833      ;

; -10.745 ; lcdvram[17][7] ; next_char_sig[7] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.518     ; 2.735      ;

; -10.740 ; lcdvram[24][0] ; next_char_sig[0] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.570     ; 2.678      ;

; -10.738 ; lcdvram[28][3] ; next_char_sig[3] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.267     ; 2.979      ;

; -10.733 ; lcdvram[17][1] ; next_char_sig[1] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.400     ; 2.841      ;

; -10.731 ; lcdvram[19][5] ; next_char_sig[5] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.508     ; 2.731      ;

; -10.721 ; lcdvram[20][0] ; next_char_sig[0] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.402     ; 2.827      ;

; -10.716 ; lcdvram[18][1] ; next_char_sig[1] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -7.949     ; 3.275      ;

; -10.714 ; lcdvram[16][2] ; next_char_sig[2] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.678     ; 2.544      ;

; -10.710 ; lcdvram[23][0] ; next_char_sig[0] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -7.774     ; 3.444      ;

; -10.691 ; lcdvram[17][5] ; next_char_sig[5] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.406     ; 2.793      ;

; -10.686 ; lcdvram[28][7] ; next_char_sig[7] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.147     ; 3.047      ;

; -10.681 ; lcdvram[18][2] ; next_char_sig[2] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.198     ; 2.991      ;

; -10.670 ; lcdvram[20][5] ; next_char_sig[5] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.315     ; 2.863      ;

; -10.645 ; lcdvram[1][6]  ; next_char_sig[6] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -6.905     ; 4.248      ;

; -10.641 ; lcdvram[20][7] ; next_char_sig[7] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.267     ; 2.882      ;

; -10.625 ; lcdvram[25][0] ; next_char_sig[0] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.317     ; 2.816      ;

; -10.623 ; lcdvram[6][6]  ; next_char_sig[6] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -7.073     ; 4.058      ;

; -10.609 ; lcdvram[22][1] ; next_char_sig[1] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -7.560     ; 3.557      ;

; -10.605 ; lcdvram[16][1] ; next_char_sig[1] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.744     ; 2.369      ;

; -10.581 ; lcdvram[27][7] ; next_char_sig[7] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.543     ; 2.546      ;

; -10.549 ; lcdvram[23][6] ; next_char_sig[6] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -7.689     ; 3.368      ;

; -10.527 ; lcdvram[24][7] ; next_char_sig[7] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.414     ; 2.621      ;

; -10.517 ; lcdvram[6][2]  ; next_char_sig[2] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -7.220     ; 3.805      ;

; -10.482 ; lcdvram[28][6] ; next_char_sig[6] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.028     ; 2.962      ;

; -10.474 ; lcdvram[18][5] ; next_char_sig[5] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.112     ; 2.870      ;

; -10.459 ; lcdvram[6][4]  ; next_char_sig[4] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -7.513     ; 3.454      ;

; -10.455 ; lcdvram[27][5] ; next_char_sig[5] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.561     ; 2.402      ;

; -10.454 ; lcdvram[17][3] ; next_char_sig[3] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.460     ; 2.502      ;

; -10.453 ; lcdvram[4][6]  ; next_char_sig[6] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -7.015     ; 3.946      ;

; -10.445 ; lcdvram[17][6] ; next_char_sig[6] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.402     ; 2.551      ;

; -10.441 ; lcdvram[0][0]  ; next_char_sig[0] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -7.199     ; 3.750      ;

; -10.438 ; lcdvram[31][1] ; next_char_sig[1] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.630     ; 2.316      ;

; -10.438 ; lcdvram[16][6] ; next_char_sig[6] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.586     ; 2.360      ;

; -10.426 ; lcdvram[18][0] ; next_char_sig[0] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.197     ; 2.737      ;

; -10.414 ; lcdvram[24][6] ; next_char_sig[6] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.469     ; 2.453      ;

; -10.412 ; lcdvram[30][2] ; next_char_sig[2] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -7.870     ; 3.050      ;

; -10.397 ; lcdvram[19][2] ; next_char_sig[2] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.619     ; 2.286      ;

; -10.394 ; lcdvram[1][4]  ; next_char_sig[4] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -6.701     ; 4.201      ;

; -10.386 ; lcdvram[16][7] ; next_char_sig[7] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.693     ; 2.201      ;

; -10.368 ; lcdvram[18][3] ; next_char_sig[3] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.119     ; 2.757      ;

; -10.350 ; lcdvram[20][6] ; next_char_sig[6] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.339     ; 2.519      ;

; -10.338 ; lcdvram[20][1] ; next_char_sig[1] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.138     ; 2.708      ;

; -10.331 ; lcdvram[2][7]  ; next_char_sig[7] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -6.672     ; 4.167      ;

; -10.317 ; lcdvram[21][2] ; next_char_sig[2] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.057     ; 2.768      ;

; -10.298 ; lcdvram[24][5] ; next_char_sig[5] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.278     ; 2.528      ;

; -10.283 ; lcdvram[31][7] ; next_char_sig[7] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.730     ; 2.061      ;

; -10.276 ; lcdvram[28][2] ; next_char_sig[2] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.281     ; 2.503      ;

; -10.259 ; lcdvram[25][1] ; next_char_sig[1] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.254     ; 2.513      ;

; -10.255 ; lcdvram[29][1] ; next_char_sig[1] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -7.453     ; 3.310      ;

; -10.229 ; lcdvram[21][7] ; next_char_sig[7] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.089     ; 2.648      ;

; -10.228 ; lcdvram[25][7] ; next_char_sig[7] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.333     ; 2.403      ;

; -10.208 ; lcdvram[21][0] ; next_char_sig[0] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.232     ; 2.484      ;

; -10.205 ; lcdvram[26][7] ; next_char_sig[7] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -7.763     ; 2.950      ;

; -10.200 ; lcdvram[22][6] ; next_char_sig[6] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -7.673     ; 3.035      ;

; -10.191 ; lcdvram[17][4] ; next_char_sig[4] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.142     ; 2.557      ;

; -10.190 ; lcdvram[0][1]  ; next_char_sig[1] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -6.832     ; 3.866      ;

; -10.189 ; lcdvram[0][6]  ; next_char_sig[6] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -6.574     ; 4.123      ;

; -10.188 ; lcdvram[7][2]  ; next_char_sig[2] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -6.964     ; 3.732      ;

; -10.185 ; lcdvram[4][2]  ; next_char_sig[2] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -7.115     ; 3.578      ;

; -10.184 ; lcdvram[27][2] ; next_char_sig[2] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.497     ; 2.195      ;

; -10.181 ; lcdvram[8][7]  ; next_char_sig[7] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -6.803     ; 3.886      ;

; -10.173 ; lcdvram[30][1] ; next_char_sig[1] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -7.745     ; 2.936      ;

; -10.167 ; lcdvram[25][3] ; next_char_sig[3] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.503     ; 2.172      ;

; -10.162 ; lcdvram[24][4] ; next_char_sig[4] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.224     ; 2.446      ;

; -10.148 ; lcdvram[31][6] ; next_char_sig[6] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.609     ; 2.047      ;

; -10.142 ; lcdvram[26][0] ; next_char_sig[0] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -7.929     ; 2.721      ;

; -10.130 ; lcdvram[25][6] ; next_char_sig[6] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.218     ; 2.420      ;

; -10.122 ; lcdvram[27][6] ; next_char_sig[6] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.423     ; 2.207      ;

; -10.087 ; lcdvram[24][2] ; next_char_sig[2] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.382     ; 2.213      ;

; -10.082 ; lcdvram[20][2] ; next_char_sig[2] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.242     ; 2.348      ;

; -10.050 ; lcdvram[11][2] ; next_char_sig[2] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -7.005     ; 3.553      ;

; -10.034 ; lcdvram[11][3] ; next_char_sig[3] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -6.680     ; 3.862      ;

; -10.030 ; lcdvram[23][7] ; next_char_sig[7] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -7.788     ; 2.750      ;

; -10.029 ; lcdvram[25][2] ; next_char_sig[2] ; T80se:z80_inst|MREQ_n ; LCD:lcd_inst|clk_400hz_enable ; 0.500        ; -8.494     ; 2.043      ;

+---------+----------------+------------------+-----------------------+-------------------------------+--------------+------------+------------+

+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

; Slow 1200mV 85C Model Setup: 'CLOCK_50'                                                                                                                                                                            ;

+--------+----------------------------------------------------+---------------------------------+-------------------------------------------------------------+-------------+--------------+------------+------------+

; Slack  ; From Node                                          ; To Node                         ; Launch Clock                                                ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;

+--------+----------------------------------------------------+---------------------------------+-------------------------------------------------------------+-------------+--------------+------------+------------+

; -7.823 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[3] ; ps2_ascii_reg1[2]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.495     ; 7.316      ;

; -7.754 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[0] ; ps2_ascii_reg1[2]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.495     ; 7.247      ;

; -7.736 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[3] ; ps2_ascii_reg1[1]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.506     ; 7.218      ;

; -7.736 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[3] ; ps2_ascii_reg1[6]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.506     ; 7.218      ;

; -7.736 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[3] ; ps2_ascii_reg1[5]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.506     ; 7.218      ;

; -7.667 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[0] ; ps2_ascii_reg1[1]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.506     ; 7.149      ;

; -7.667 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[0] ; ps2_ascii_reg1[6]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.506     ; 7.149      ;

; -7.667 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[0] ; ps2_ascii_reg1[5]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.506     ; 7.149      ;

; -7.644 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[3] ; ps2_ascii_reg1[7]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.507     ; 7.125      ;

; -7.644 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[3] ; ps2_ascii_reg1[3]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.507     ; 7.125      ;

; -7.644 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[3] ; ps2_ascii_reg1[0]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.507     ; 7.125      ;

; -7.644 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[3] ; ps2_ascii_reg1[4]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.507     ; 7.125      ;

; -7.575 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[0] ; ps2_ascii_reg1[7]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.507     ; 7.056      ;

; -7.575 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[0] ; ps2_ascii_reg1[3]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.507     ; 7.056      ;

; -7.575 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[0] ; ps2_ascii_reg1[0]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.507     ; 7.056      ;

; -7.575 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[0] ; ps2_ascii_reg1[4]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.507     ; 7.056      ;

; -7.296 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[2] ; ps2_ascii_reg1[2]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.496     ; 6.788      ;

; -7.268 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[5] ; ps2_ascii_reg1[2]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.495     ; 6.761      ;

; -7.260 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[1] ; ps2_ascii_reg1[2]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.495     ; 6.753      ;

; -7.243 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[4] ; ps2_ascii_reg1[2]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.495     ; 6.736      ;

; -7.209 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[2] ; ps2_ascii_reg1[1]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.507     ; 6.690      ;

; -7.209 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[2] ; ps2_ascii_reg1[6]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.507     ; 6.690      ;

; -7.209 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[2] ; ps2_ascii_reg1[5]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.507     ; 6.690      ;

; -7.183 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[6] ; ps2_ascii_reg1[2]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.495     ; 6.676      ;

; -7.173 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[1] ; ps2_ascii_reg1[1]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.506     ; 6.655      ;

; -7.173 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[1] ; ps2_ascii_reg1[6]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.506     ; 6.655      ;

; -7.173 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[1] ; ps2_ascii_reg1[5]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.506     ; 6.655      ;

; -7.158 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[5] ; ps2_ascii_reg1[1]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.506     ; 6.640      ;

; -7.158 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[5] ; ps2_ascii_reg1[6]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.506     ; 6.640      ;

; -7.158 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[5] ; ps2_ascii_reg1[5]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.506     ; 6.640      ;

; -7.156 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[4] ; ps2_ascii_reg1[1]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.506     ; 6.638      ;

; -7.156 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[4] ; ps2_ascii_reg1[6]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.506     ; 6.638      ;

; -7.156 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[4] ; ps2_ascii_reg1[5]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.506     ; 6.638      ;

; -7.117 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[2] ; ps2_ascii_reg1[7]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.508     ; 6.597      ;

; -7.117 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[2] ; ps2_ascii_reg1[3]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.508     ; 6.597      ;

; -7.117 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[2] ; ps2_ascii_reg1[0]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.508     ; 6.597      ;

; -7.117 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[2] ; ps2_ascii_reg1[4]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.508     ; 6.597      ;

; -7.096 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[6] ; ps2_ascii_reg1[1]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.506     ; 6.578      ;

; -7.096 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[6] ; ps2_ascii_reg1[6]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.506     ; 6.578      ;

; -7.096 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[6] ; ps2_ascii_reg1[5]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.506     ; 6.578      ;

; -7.081 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[1] ; ps2_ascii_reg1[7]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.507     ; 6.562      ;

; -7.081 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[1] ; ps2_ascii_reg1[3]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.507     ; 6.562      ;

; -7.081 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[1] ; ps2_ascii_reg1[0]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.507     ; 6.562      ;

; -7.081 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[1] ; ps2_ascii_reg1[4]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.507     ; 6.562      ;

; -7.064 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[4] ; ps2_ascii_reg1[7]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.507     ; 6.545      ;

; -7.064 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[4] ; ps2_ascii_reg1[3]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.507     ; 6.545      ;

; -7.064 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[4] ; ps2_ascii_reg1[0]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.507     ; 6.545      ;

; -7.064 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[4] ; ps2_ascii_reg1[4]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.507     ; 6.545      ;

; -7.058 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[5] ; ps2_ascii_reg1[7]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.507     ; 6.539      ;

; -7.058 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[5] ; ps2_ascii_reg1[3]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.507     ; 6.539      ;

; -7.058 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[5] ; ps2_ascii_reg1[0]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.507     ; 6.539      ;

; -7.058 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[5] ; ps2_ascii_reg1[4]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.507     ; 6.539      ;

; -7.004 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[6] ; ps2_ascii_reg1[7]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.507     ; 6.485      ;

; -7.004 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[6] ; ps2_ascii_reg1[3]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.507     ; 6.485      ;

; -7.004 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[6] ; ps2_ascii_reg1[0]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.507     ; 6.485      ;

; -7.004 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[6] ; ps2_ascii_reg1[4]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.507     ; 6.485      ;

; -6.481 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[0] ; ps2_read                        ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.507     ; 5.962      ;

; -6.363 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[3] ; ps2_read                        ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.507     ; 5.844      ;

; -5.987 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[1] ; ps2_read                        ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.507     ; 5.468      ;

; -5.836 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[2] ; ps2_read                        ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.508     ; 5.316      ;

; -5.828 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[5] ; ps2_read                        ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.507     ; 5.309      ;

; -5.783 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[4] ; ps2_read                        ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.507     ; 5.264      ;

; -5.694 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[6] ; ps2_read                        ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.507     ; 5.175      ;

; -5.282 ; LCDON_reg                                          ; LCD:lcd_inst|LCD_ON             ; SW[16]                                                      ; CLOCK_50    ; 1.000        ; -4.988     ; 1.272      ;

; -5.023 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[7] ; ps2_ascii_reg1[2]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.497     ; 4.514      ;

; -4.936 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[7] ; ps2_ascii_reg1[1]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.508     ; 4.416      ;

; -4.936 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[7] ; ps2_ascii_reg1[6]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.508     ; 4.416      ;

; -4.936 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[7] ; ps2_ascii_reg1[5]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.508     ; 4.416      ;

; -4.844 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[7] ; ps2_ascii_reg1[7]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.509     ; 4.323      ;

; -4.844 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[7] ; ps2_ascii_reg1[3]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.509     ; 4.323      ;

; -4.844 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[7] ; ps2_ascii_reg1[0]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.509     ; 4.323      ;

; -4.844 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[7] ; ps2_ascii_reg1[4]               ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.509     ; 4.323      ;

; -3.689 ; ps2kbd:ps2_kbd_inst|caps[0]                        ; ps2_ascii_reg1[2]               ; clk_div:clkdiv_inst|clock_100Hz                             ; CLOCK_50    ; 1.000        ; 1.594      ; 6.281      ;

; -3.602 ; ps2kbd:ps2_kbd_inst|caps[0]                        ; ps2_ascii_reg1[1]               ; clk_div:clkdiv_inst|clock_100Hz                             ; CLOCK_50    ; 1.000        ; 1.583      ; 6.183      ;

; -3.602 ; ps2kbd:ps2_kbd_inst|caps[0]                        ; ps2_ascii_reg1[6]               ; clk_div:clkdiv_inst|clock_100Hz                             ; CLOCK_50    ; 1.000        ; 1.583      ; 6.183      ;

; -3.602 ; ps2kbd:ps2_kbd_inst|caps[0]                        ; ps2_ascii_reg1[5]               ; clk_div:clkdiv_inst|clock_100Hz                             ; CLOCK_50    ; 1.000        ; 1.583      ; 6.183      ;

; -3.510 ; ps2kbd:ps2_kbd_inst|caps[0]                        ; ps2_ascii_reg1[7]               ; clk_div:clkdiv_inst|clock_100Hz                             ; CLOCK_50    ; 1.000        ; 1.582      ; 6.090      ;

; -3.510 ; ps2kbd:ps2_kbd_inst|caps[0]                        ; ps2_ascii_reg1[3]               ; clk_div:clkdiv_inst|clock_100Hz                             ; CLOCK_50    ; 1.000        ; 1.582      ; 6.090      ;

; -3.510 ; ps2kbd:ps2_kbd_inst|caps[0]                        ; ps2_ascii_reg1[0]               ; clk_div:clkdiv_inst|clock_100Hz                             ; CLOCK_50    ; 1.000        ; 1.582      ; 6.090      ;

; -3.510 ; ps2kbd:ps2_kbd_inst|caps[0]                        ; ps2_ascii_reg1[4]               ; clk_div:clkdiv_inst|clock_100Hz                             ; CLOCK_50    ; 1.000        ; 1.582      ; 6.090      ;

; -3.459 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[7] ; ps2_read                        ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; CLOCK_50    ; 1.000        ; -1.509     ; 2.938      ;

; -3.263 ; LCD:lcd_inst|clk_count_400hz[7]                    ; LCD:lcd_inst|clk_count_400hz[0] ; CLOCK_50                                                    ; CLOCK_50    ; 1.000        ; -0.081     ; 4.180      ;

; -3.263 ; LCD:lcd_inst|clk_count_400hz[7]                    ; LCD:lcd_inst|clk_count_400hz[1] ; CLOCK_50                                                    ; CLOCK_50    ; 1.000        ; -0.081     ; 4.180      ;

; -3.263 ; LCD:lcd_inst|clk_count_400hz[7]                    ; LCD:lcd_inst|clk_count_400hz[2] ; CLOCK_50                                                    ; CLOCK_50    ; 1.000        ; -0.081     ; 4.180      ;

; -3.263 ; LCD:lcd_inst|clk_count_400hz[7]                    ; LCD:lcd_inst|clk_count_400hz[3] ; CLOCK_50                                                    ; CLOCK_50    ; 1.000        ; -0.081     ; 4.180      ;

; -3.263 ; LCD:lcd_inst|clk_count_400hz[7]                    ; LCD:lcd_inst|clk_count_400hz[4] ; CLOCK_50                                                    ; CLOCK_50    ; 1.000        ; -0.081     ; 4.180      ;

; -3.263 ; LCD:lcd_inst|clk_count_400hz[7]                    ; LCD:lcd_inst|clk_count_400hz[5] ; CLOCK_50                                                    ; CLOCK_50    ; 1.000        ; -0.081     ; 4.180      ;

; -3.263 ; LCD:lcd_inst|clk_count_400hz[7]                    ; LCD:lcd_inst|clk_count_400hz[6] ; CLOCK_50                                                    ; CLOCK_50    ; 1.000        ; -0.081     ; 4.180      ;

; -3.263 ; LCD:lcd_inst|clk_count_400hz[7]                    ; LCD:lcd_inst|clk_count_400hz[7] ; CLOCK_50                                                    ; CLOCK_50    ; 1.000        ; -0.081     ; 4.180      ;

; -3.263 ; LCD:lcd_inst|clk_count_400hz[7]                    ; LCD:lcd_inst|clk_count_400hz[8] ; CLOCK_50                                                    ; CLOCK_50    ; 1.000        ; -0.081     ; 4.180      ;

; -3.263 ; LCD:lcd_inst|clk_count_400hz[7]                    ; LCD:lcd_inst|clk_count_400hz[9] ; CLOCK_50                                                    ; CLOCK_50    ; 1.000        ; -0.081     ; 4.180      ;

; -3.255 ; LCD:lcd_inst|clk_count_400hz[8]                    ; LCD:lcd_inst|clk_count_400hz[0] ; CLOCK_50                                                    ; CLOCK_50    ; 1.000        ; -0.081     ; 4.172      ;

; -3.255 ; LCD:lcd_inst|clk_count_400hz[8]                    ; LCD:lcd_inst|clk_count_400hz[1] ; CLOCK_50                                                    ; CLOCK_50    ; 1.000        ; -0.081     ; 4.172      ;

; -3.255 ; LCD:lcd_inst|clk_count_400hz[8]                    ; LCD:lcd_inst|clk_count_400hz[2] ; CLOCK_50                                                    ; CLOCK_50    ; 1.000        ; -0.081     ; 4.172      ;

; -3.255 ; LCD:lcd_inst|clk_count_400hz[8]                    ; LCD:lcd_inst|clk_count_400hz[3] ; CLOCK_50                                                    ; CLOCK_50    ; 1.000        ; -0.081     ; 4.172      ;

; -3.255 ; LCD:lcd_inst|clk_count_400hz[8]                    ; LCD:lcd_inst|clk_count_400hz[4] ; CLOCK_50                                                    ; CLOCK_50    ; 1.000        ; -0.081     ; 4.172      ;

; -3.255 ; LCD:lcd_inst|clk_count_400hz[8]                    ; LCD:lcd_inst|clk_count_400hz[5] ; CLOCK_50                                                    ; CLOCK_50    ; 1.000        ; -0.081     ; 4.172      ;

; -3.255 ; LCD:lcd_inst|clk_count_400hz[8]                    ; LCD:lcd_inst|clk_count_400hz[6] ; CLOCK_50                                                    ; CLOCK_50    ; 1.000        ; -0.081     ; 4.172      ;

; -3.255 ; LCD:lcd_inst|clk_count_400hz[8]                    ; LCD:lcd_inst|clk_count_400hz[7] ; CLOCK_50                                                    ; CLOCK_50    ; 1.000        ; -0.081     ; 4.172      ;

; -3.255 ; LCD:lcd_inst|clk_count_400hz[8]                    ; LCD:lcd_inst|clk_count_400hz[8] ; CLOCK_50                                                    ; CLOCK_50    ; 1.000        ; -0.081     ; 4.172      ;

+--------+----------------------------------------------------+---------------------------------+-------------------------------------------------------------+-------------+--------------+------------+------------+

+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

; Slow 1200mV 85C Model Setup: 'clk_div:clkdiv_inst|clock_25MHz'                                                                                                                                                                                                                                                                                      ;

+--------+---------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------+---------------------------------+---------------------------------+--------------+------------+------------+

; Slack  ; From Node                                                                                                     ; To Node                                                                                                       ; Launch Clock                    ; Latch Clock                     ; Relationship ; Clock Skew ; Data Delay ;

+--------+---------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------+---------------------------------+---------------------------------+--------------+------------+------------+

; -5.695 ; charram:cram|altsyncram:altsyncram_component|altsyncram_l4o1:auto_generated|ram_block1a0~portb_address_reg0   ; video:video_inst|VGA_SYNC:vga_sync_inst|blue_out[0]                                                           ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -0.373     ; 6.320      ;

; -5.694 ; charram:cram|altsyncram:altsyncram_component|altsyncram_l4o1:auto_generated|ram_block1a0~portb_address_reg0   ; video:video_inst|VGA_SYNC:vga_sync_inst|blue_out[3]                                                           ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -0.373     ; 6.319      ;

; -5.692 ; charram:cram|altsyncram:altsyncram_component|altsyncram_l4o1:auto_generated|ram_block1a0~portb_address_reg0   ; video:video_inst|VGA_SYNC:vga_sync_inst|blue_out[1]                                                           ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -0.373     ; 6.317      ;

; -5.496 ; charram:cram|altsyncram:altsyncram_component|altsyncram_l4o1:auto_generated|ram_block1a4~portb_address_reg0   ; video:video_inst|VGA_SYNC:vga_sync_inst|blue_out[0]                                                           ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -0.359     ; 6.135      ;

; -5.495 ; charram:cram|altsyncram:altsyncram_component|altsyncram_l4o1:auto_generated|ram_block1a4~portb_address_reg0   ; video:video_inst|VGA_SYNC:vga_sync_inst|blue_out[3]                                                           ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -0.359     ; 6.134      ;

; -5.494 ; charram:cram|altsyncram:altsyncram_component|altsyncram_l4o1:auto_generated|ram_block1a4~portb_address_reg0   ; video:video_inst|VGA_SYNC:vga_sync_inst|blue_out[1]                                                           ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -0.359     ; 6.133      ;

; -5.318 ; charram:cram|altsyncram:altsyncram_component|altsyncram_l4o1:auto_generated|ram_block1a0~portb_address_reg0   ; video:video_inst|VGA_SYNC:vga_sync_inst|blue_out[2]                                                           ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -0.373     ; 5.943      ;

; -5.119 ; charram:cram|altsyncram:altsyncram_component|altsyncram_l4o1:auto_generated|ram_block1a4~portb_address_reg0   ; video:video_inst|VGA_SYNC:vga_sync_inst|blue_out[2]                                                           ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -0.359     ; 5.758      ;

; -4.574 ; T80se:z80_inst|T80:u0|A[4]                                                                                    ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a8~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -2.200     ; 3.402      ;

; -4.514 ; T80se:z80_inst|T80:u0|A[2]                                                                                    ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a8~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -2.200     ; 3.342      ;

; -4.478 ; T80se:z80_inst|T80:u0|A[4]                                                                                    ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a0~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -2.237     ; 3.269      ;

; -4.469 ; T80se:z80_inst|T80:u0|A[10]                                                                                   ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a4~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -2.027     ; 3.470      ;

; -4.464 ; T80se:z80_inst|T80:u0|A[10]                                                                                   ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a8~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -2.002     ; 3.490      ;

; -4.441 ; T80se:z80_inst|T80:u0|A[10]                                                                                   ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a5~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -2.017     ; 3.452      ;

; -4.289 ; T80se:z80_inst|T80:u0|A[13]                                                                                   ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a8~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -1.673     ; 3.644      ;

; -4.280 ; T80se:z80_inst|T80:u0|A[8]                                                                                    ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a8~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -1.727     ; 3.581      ;

; -4.278 ; T80se:z80_inst|T80:u0|A[3]                                                                                    ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a8~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -2.200     ; 3.106      ;

; -4.195 ; T80se:z80_inst|T80:u0|A[8]                                                                                    ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a0~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -1.764     ; 3.459      ;

; -4.165 ; T80se:z80_inst|T80:u0|A[4]                                                                                    ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a11~porta_address_reg0  ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -2.232     ; 2.961      ;

; -4.148 ; T80se:z80_inst|T80:u0|A[10]                                                                                   ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a11~porta_address_reg0  ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -2.034     ; 3.142      ;

; -4.126 ; T80se:z80_inst|T80:u0|A[4]                                                                                    ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a14~porta_address_reg0  ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -2.234     ; 2.920      ;

; -4.126 ; T80se:z80_inst|T80:u0|A[2]                                                                                    ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a5~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -2.215     ; 2.939      ;

; -4.121 ; T80se:z80_inst|T80:u0|A[4]                                                                                    ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a4~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -2.225     ; 2.924      ;

; -4.119 ; T80se:z80_inst|T80:u0|A[10]                                                                                   ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a14~porta_address_reg0  ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -2.036     ; 3.111      ;

; -4.115 ; T80se:z80_inst|T80:u0|A[4]                                                                                    ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a5~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -2.215     ; 2.928      ;

; -4.091 ; T80se:z80_inst|T80:u0|A[10]                                                                                   ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a7~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -2.012     ; 3.107      ;

; -4.069 ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a7~portb_address_reg0 ; charram:cram|altsyncram:altsyncram_component|altsyncram_l4o1:auto_generated|ram_block1a4~portb_address_reg0   ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -0.058     ; 5.049      ;

; -4.066 ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a7~portb_address_reg0 ; charram:cram|altsyncram:altsyncram_component|altsyncram_l4o1:auto_generated|ram_block1a0~portb_address_reg0   ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -0.046     ; 5.058      ;

; -4.064 ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a0~portb_address_reg0 ; charram:cram|altsyncram:altsyncram_component|altsyncram_l4o1:auto_generated|ram_block1a0~portb_address_reg0   ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -0.047     ; 5.055      ;

; -4.057 ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a5~portb_address_reg0 ; charram:cram|altsyncram:altsyncram_component|altsyncram_l4o1:auto_generated|ram_block1a4~portb_address_reg0   ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -0.057     ; 5.038      ;

; -4.046 ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a5~portb_address_reg0 ; charram:cram|altsyncram:altsyncram_component|altsyncram_l4o1:auto_generated|ram_block1a0~portb_address_reg0   ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -0.045     ; 5.039      ;

; -4.033 ; T80se:z80_inst|T80:u0|A[13]                                                                                   ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a7~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -1.683     ; 3.378      ;

; -4.003 ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a0~portb_address_reg0 ; charram:cram|altsyncram:altsyncram_component|altsyncram_l4o1:auto_generated|ram_block1a4~portb_address_reg0   ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -0.059     ; 4.982      ;

; -3.960 ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a2~portb_address_reg0 ; charram:cram|altsyncram:altsyncram_component|altsyncram_l4o1:auto_generated|ram_block1a0~portb_address_reg0   ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -0.047     ; 4.951      ;

; -3.945 ; T80se:z80_inst|T80:u0|A[5]                                                                                    ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a8~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -2.200     ; 2.773      ;

; -3.918 ; T80se:z80_inst|T80:u0|A[8]                                                                                    ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a11~porta_address_reg0  ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -1.759     ; 3.187      ;

; -3.913 ; T80se:z80_inst|T80:u0|A[8]                                                                                    ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a14~porta_address_reg0  ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -1.761     ; 3.180      ;

; -3.903 ; T80se:z80_inst|T80:u0|A[13]                                                                                   ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a5~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -1.688     ; 3.243      ;

; -3.891 ; T80se:z80_inst|T80:u0|A[13]                                                                                   ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a4~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -1.698     ; 3.221      ;

; -3.886 ; T80se:z80_inst|T80:u0|A[8]                                                                                    ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a5~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -1.742     ; 3.172      ;

; -3.877 ; T80se:z80_inst|T80:u0|A[3]                                                                                    ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a0~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -2.237     ; 2.668      ;

; -3.862 ; T80se:z80_inst|T80:u0|A[8]                                                                                    ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a4~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -1.752     ; 3.138      ;

; -3.854 ; T80se:z80_inst|T80:u0|A[5]                                                                                    ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a4~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -2.225     ; 2.657      ;

; -3.835 ; T80se:z80_inst|T80:u0|A[4]                                                                                    ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a7~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -2.210     ; 2.653      ;

; -3.835 ; T80se:z80_inst|T80:u0|A[5]                                                                                    ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a5~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -2.215     ; 2.648      ;

; -3.828 ; T80se:z80_inst|T80:u0|A[3]                                                                                    ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a14~porta_address_reg0  ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -2.234     ; 2.622      ;

; -3.827 ; T80se:z80_inst|T80:u0|A[2]                                                                                    ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a4~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -2.225     ; 2.630      ;

; -3.792 ; T80se:z80_inst|T80:u0|A[3]                                                                                    ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a7~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -2.210     ; 2.610      ;

; -3.786 ; T80se:z80_inst|T80:u0|A[2]                                                                                    ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a11~porta_address_reg0  ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -2.232     ; 2.582      ;

; -3.781 ; T80se:z80_inst|T80:u0|A[10]                                                                                   ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a0~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -2.039     ; 2.770      ;

; -3.778 ; T80se:z80_inst|T80:u0|A[2]                                                                                    ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a7~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -2.210     ; 2.596      ;

; -3.776 ; T80se:z80_inst|T80:u0|A[2]                                                                                    ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a14~porta_address_reg0  ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -2.234     ; 2.570      ;

; -3.709 ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_row[8]                                                          ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a5~portb_address_reg0 ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; 0.187      ; 4.934      ;

; -3.698 ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_row[8]                                                          ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a0~portb_address_reg0 ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; 0.189      ; 4.925      ;

; -3.698 ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_row[6]                                                          ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a5~portb_address_reg0 ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; 0.187      ; 4.923      ;

; -3.694 ; T80se:z80_inst|T80:u0|A[4]                                                                                    ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a6~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -2.201     ; 2.521      ;

; -3.693 ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_row[4]                                                          ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a5~portb_address_reg0 ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; 0.187      ; 4.918      ;

; -3.689 ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a2~portb_address_reg0 ; charram:cram|altsyncram:altsyncram_component|altsyncram_l4o1:auto_generated|ram_block1a4~portb_address_reg0   ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -0.059     ; 4.668      ;

; -3.687 ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_row[6]                                                          ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a0~portb_address_reg0 ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; 0.189      ; 4.914      ;

; -3.682 ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_row[4]                                                          ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a0~portb_address_reg0 ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; 0.189      ; 4.909      ;

; -3.662 ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_row[8]                                                          ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a7~portb_address_reg0 ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; 0.188      ; 4.888      ;

; -3.661 ; T80se:z80_inst|T80:u0|A[10]                                                                                   ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a10~porta_address_reg0  ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -2.027     ; 2.662      ;

; -3.651 ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_row[6]                                                          ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a7~portb_address_reg0 ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; 0.188      ; 4.877      ;

; -3.646 ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_row[4]                                                          ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a7~portb_address_reg0 ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; 0.188      ; 4.872      ;

; -3.642 ; T80se:z80_inst|T80:u0|A[9]                                                                                    ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a4~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -1.752     ; 2.918      ;

; -3.640 ; T80se:z80_inst|T80:u0|A[4]                                                                                    ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a12~porta_address_reg0  ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -2.203     ; 2.465      ;

; -3.632 ; T80se:z80_inst|T80:u0|A[4]                                                                                    ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a9~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -2.202     ; 2.458      ;

; -3.632 ; T80se:z80_inst|T80:u0|A[9]                                                                                    ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a8~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -1.727     ; 2.933      ;

; -3.625 ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_row[8]                                                          ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a2~portb_address_reg0 ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; 0.189      ; 4.852      ;

; -3.615 ; T80se:z80_inst|T80:u0|A[10]                                                                                   ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a15~porta_address_reg0  ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -2.020     ; 2.623      ;

; -3.614 ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_row[6]                                                          ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a2~portb_address_reg0 ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; 0.189      ; 4.841      ;

; -3.609 ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_row[4]                                                          ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a2~portb_address_reg0 ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; 0.189      ; 4.836      ;

; -3.605 ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_row[3]                                                          ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a5~portb_address_reg0 ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; 0.187      ; 4.830      ;

; -3.601 ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_row[5]                                                          ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a5~portb_address_reg0 ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; 0.187      ; 4.826      ;

; -3.600 ; T80se:z80_inst|T80:u0|A[3]                                                                                    ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a2~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -2.234     ; 2.394      ;

; -3.597 ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_row[3]                                                          ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a7~portb_address_reg0 ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; 0.188      ; 4.823      ;

; -3.594 ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_row[3]                                                          ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a0~portb_address_reg0 ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; 0.189      ; 4.821      ;

; -3.590 ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_row[5]                                                          ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a0~portb_address_reg0 ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; 0.189      ; 4.817      ;

; -3.582 ; T80se:z80_inst|T80:u0|A[13]                                                                                   ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a2~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -1.707     ; 2.903      ;

; -3.580 ; T80se:z80_inst|T80:u0|A[3]                                                                                    ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a11~porta_address_reg0  ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -2.232     ; 2.376      ;

; -3.578 ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_row[5]                                                          ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a7~portb_address_reg0 ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; 0.188      ; 4.804      ;

; -3.575 ; T80se:z80_inst|T80:u0|A[3]                                                                                    ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a4~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -2.225     ; 2.378      ;

; -3.574 ; T80se:z80_inst|T80:u0|A[7]                                                                                    ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a7~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -1.730     ; 2.872      ;

; -3.566 ; T80se:z80_inst|T80:u0|A[3]                                                                                    ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a5~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -2.215     ; 2.379      ;

; -3.555 ; T80se:z80_inst|T80:u0|A[5]                                                                                    ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a7~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -2.210     ; 2.373      ;

; -3.554 ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_row[3]                                                          ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a2~portb_address_reg0 ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; 0.189      ; 4.781      ;

; -3.552 ; T80se:z80_inst|T80:u0|A[13]                                                                                   ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a3~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -1.702     ; 2.878      ;

; -3.549 ; T80se:z80_inst|T80:u0|A[4]                                                                                    ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a15~porta_address_reg0  ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -2.218     ; 2.359      ;

; -3.540 ; T80se:z80_inst|T80:u0|A[13]                                                                                   ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a0~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -1.710     ; 2.858      ;

; -3.536 ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_row[3]                                                          ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a1~portb_address_reg0 ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; 0.201      ; 4.775      ;

; -3.535 ; T80se:z80_inst|T80:u0|A[4]                                                                                    ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a3~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -2.229     ; 2.334      ;

; -3.535 ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_row[5]                                                          ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a2~portb_address_reg0 ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; 0.189      ; 4.762      ;

; -3.525 ; T80se:z80_inst|T80:u0|A[4]                                                                                    ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a1~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -2.222     ; 2.331      ;

; -3.520 ; T80se:z80_inst|T80:u0|A[4]                                                                                    ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a10~porta_address_reg0  ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -2.225     ; 2.323      ;

; -3.519 ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_row[8]                                                          ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a1~portb_address_reg0 ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; 0.201      ; 4.758      ;

; -3.517 ; T80se:z80_inst|T80:u0|A[13]                                                                                   ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a10~porta_address_reg0  ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -1.698     ; 2.847      ;

; -3.517 ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_row[5]                                                          ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a1~portb_address_reg0 ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; 0.201      ; 4.756      ;

; -3.511 ; T80se:z80_inst|T80:u0|A[12]                                                                                   ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a8~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -1.673     ; 2.866      ;

; -3.510 ; video:video_inst|VGA_SYNC:vga_sync_inst|pixel_row[6]                                                          ; vram:vram_inst|altsyncram:altsyncram_component|altsyncram_oal1:auto_generated|ram_block1a1~portb_address_reg0 ; clk_div:clkdiv_inst|clock_25MHz ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; 0.201      ; 4.749      ;

; -3.508 ; T80se:z80_inst|T80:u0|A[2]                                                                                    ; rom:rom_inst|altsyncram:altsyncram_component|altsyncram_f0a1:auto_generated|ram_block1a0~porta_address_reg0   ; SW[16]                          ; clk_div:clkdiv_inst|clock_25MHz ; 1.000        ; -2.237     ; 2.299      ;

+--------+---------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------+---------------------------------+---------------------------------+--------------+------------+------------+

+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

; Slow 1200mV 85C Model Setup: 'clk_div:clkdiv_inst|clock_100Hz'                                                                                                                                                                     ;

+--------+----------------------------------------------------+-----------------------------+-------------------------------------------------------------+---------------------------------+--------------+------------+------------+

; Slack  ; From Node                                          ; To Node                     ; Launch Clock                                                ; Latch Clock                     ; Relationship ; Clock Skew ; Data Delay ;

+--------+----------------------------------------------------+-----------------------------+-------------------------------------------------------------+---------------------------------+--------------+------------+------------+

; -5.245 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[3] ; ps2kbd:ps2_kbd_inst|caps[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; clk_div:clkdiv_inst|clock_100Hz ; 1.000        ; -3.162     ; 3.091      ;

; -5.245 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[3] ; ps2kbd:ps2_kbd_inst|caps[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; clk_div:clkdiv_inst|clock_100Hz ; 1.000        ; -3.162     ; 3.091      ;

; -4.788 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[1] ; ps2kbd:ps2_kbd_inst|caps[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; clk_div:clkdiv_inst|clock_100Hz ; 1.000        ; -3.162     ; 2.634      ;

; -4.788 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[1] ; ps2kbd:ps2_kbd_inst|caps[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; clk_div:clkdiv_inst|clock_100Hz ; 1.000        ; -3.162     ; 2.634      ;

; -4.785 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[6] ; ps2kbd:ps2_kbd_inst|caps[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; clk_div:clkdiv_inst|clock_100Hz ; 1.000        ; -3.162     ; 2.631      ;

; -4.785 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[6] ; ps2kbd:ps2_kbd_inst|caps[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; clk_div:clkdiv_inst|clock_100Hz ; 1.000        ; -3.162     ; 2.631      ;

; -4.753 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[2] ; ps2kbd:ps2_kbd_inst|caps[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; clk_div:clkdiv_inst|clock_100Hz ; 1.000        ; -3.163     ; 2.598      ;

; -4.753 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[2] ; ps2kbd:ps2_kbd_inst|caps[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; clk_div:clkdiv_inst|clock_100Hz ; 1.000        ; -3.163     ; 2.598      ;

; -4.718 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[0] ; ps2kbd:ps2_kbd_inst|caps[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; clk_div:clkdiv_inst|clock_100Hz ; 1.000        ; -3.162     ; 2.564      ;

; -4.718 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[0] ; ps2kbd:ps2_kbd_inst|caps[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; clk_div:clkdiv_inst|clock_100Hz ; 1.000        ; -3.162     ; 2.564      ;

; -4.708 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[5] ; ps2kbd:ps2_kbd_inst|caps[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; clk_div:clkdiv_inst|clock_100Hz ; 1.000        ; -3.162     ; 2.554      ;

; -4.708 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[5] ; ps2kbd:ps2_kbd_inst|caps[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; clk_div:clkdiv_inst|clock_100Hz ; 1.000        ; -3.162     ; 2.554      ;

; -4.644 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[7] ; ps2kbd:ps2_kbd_inst|caps[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; clk_div:clkdiv_inst|clock_100Hz ; 1.000        ; -3.164     ; 2.488      ;

; -4.644 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[7] ; ps2kbd:ps2_kbd_inst|caps[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; clk_div:clkdiv_inst|clock_100Hz ; 1.000        ; -3.164     ; 2.488      ;

; -4.601 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[4] ; ps2kbd:ps2_kbd_inst|caps[0] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; clk_div:clkdiv_inst|clock_100Hz ; 1.000        ; -3.162     ; 2.447      ;

; -4.601 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[4] ; ps2kbd:ps2_kbd_inst|caps[1] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; clk_div:clkdiv_inst|clock_100Hz ; 1.000        ; -3.162     ; 2.447      ;

; -0.086 ; ps2kbd:ps2_kbd_inst|caps[0]                        ; ps2kbd:ps2_kbd_inst|caps[1] ; clk_div:clkdiv_inst|clock_100Hz                             ; clk_div:clkdiv_inst|clock_100Hz ; 1.000        ; -0.046     ; 1.058      ;

; 0.176  ; ps2kbd:ps2_kbd_inst|caps[1]                        ; ps2kbd:ps2_kbd_inst|caps[0] ; clk_div:clkdiv_inst|clock_100Hz                             ; clk_div:clkdiv_inst|clock_100Hz ; 1.000        ; -0.046     ; 0.796      ;

+--------+----------------------------------------------------+-----------------------------+-------------------------------------------------------------+---------------------------------+--------------+------------+------------+

+---------------------------------------------------------------------------------------------------------------------------------------+

; Slow 1200mV 85C Model Setup: 'T80se:z80_inst|MREQ_n'                                                                                  ;

+--------+-----------------------------+----------------+--------------+-----------------------+--------------+------------+------------+

; Slack  ; From Node                   ; To Node        ; Launch Clock ; Latch Clock           ; Relationship ; Clock Skew ; Data Delay ;

+--------+-----------------------------+----------------+--------------+-----------------------+--------------+------------+------------+

; -2.601 ; T80se:z80_inst|T80:u0|DO[7] ; lcdvram[10][7] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.326      ; 2.591      ;

; -2.588 ; T80se:z80_inst|T80:u0|DO[5] ; lcdvram[8][5]  ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; -0.065     ; 2.173      ;

; -2.565 ; T80se:z80_inst|T80:u0|DO[7] ; lcdvram[5][7]  ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.007      ; 2.170      ;

; -2.560 ; T80se:z80_inst|T80:u0|DO[0] ; lcdvram[29][0] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.842      ; 3.032      ;

; -2.507 ; T80se:z80_inst|T80:u0|DO[7] ; lcdvram[11][7] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; -0.152     ; 1.858      ;

; -2.491 ; T80se:z80_inst|T80:u0|DO[7] ; lcdvram[13][7] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.298      ; 1.704      ;

; -2.471 ; T80se:z80_inst|T80:u0|DO[1] ; lcdvram[29][1] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.820      ; 2.891      ;

; -2.417 ; T80se:z80_inst|T80:u0|DO[3] ; lcdvram[29][3] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.827      ; 2.843      ;

; -2.415 ; T80se:z80_inst|T80:u0|DO[2] ; lcdvram[2][2]  ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.083      ; 2.141      ;

; -2.351 ; T80se:z80_inst|T80:u0|DO[5] ; lcdvram[5][5]  ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.271      ; 2.131      ;

; -2.330 ; T80se:z80_inst|T80:u0|DO[6] ; lcdvram[29][6] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.839      ; 2.768      ;

; -2.326 ; T80se:z80_inst|T80:u0|DO[0] ; lcdvram[0][0]  ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.514      ; 2.303      ;

; -2.326 ; T80se:z80_inst|T80:u0|DO[4] ; lcdvram[26][4] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 1.033      ; 2.955      ;

; -2.280 ; T80se:z80_inst|T80:u0|DO[4] ; lcdvram[3][4]  ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; -0.683     ; 0.908      ;

; -2.276 ; T80se:z80_inst|T80:u0|DO[3] ; lcdvram[8][3]  ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.090      ; 1.971      ;

; -2.237 ; T80se:z80_inst|T80:u0|DO[2] ; lcdvram[13][2] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.093      ; 2.110      ;

; -2.213 ; T80se:z80_inst|T80:u0|DO[7] ; lcdvram[29][7] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.997      ; 2.990      ;

; -2.198 ; T80se:z80_inst|T80:u0|DO[2] ; lcdvram[5][2]  ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.132      ; 2.109      ;

; -2.190 ; T80se:z80_inst|T80:u0|DO[1] ; lcdvram[5][1]  ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.239      ; 1.746      ;

; -2.176 ; T80se:z80_inst|T80:u0|DO[6] ; lcdvram[0][6]  ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.007      ; 1.957      ;

; -2.174 ; T80se:z80_inst|T80:u0|DO[1] ; lcdvram[8][1]  ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; -0.211     ; 1.433      ;

; -2.164 ; T80se:z80_inst|T80:u0|DO[5] ; lcdvram[11][5] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.011      ; 1.493      ;

; -2.153 ; T80se:z80_inst|T80:u0|DO[2] ; lcdvram[10][2] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.389      ; 2.192      ;

; -2.153 ; T80se:z80_inst|T80:u0|DO[1] ; lcdvram[30][1] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 1.143      ; 2.889      ;

; -2.152 ; T80se:z80_inst|T80:u0|DO[4] ; lcdvram[30][4] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 1.199      ; 2.954      ;

; -2.142 ; T80se:z80_inst|T80:u0|DO[3] ; lcdvram[5][3]  ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.009      ; 1.780      ;

; -2.141 ; T80se:z80_inst|T80:u0|DO[1] ; lcdvram[21][1] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 1.348      ; 3.092      ;

; -2.114 ; T80se:z80_inst|T80:u0|DO[0] ; lcdvram[30][0] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 1.184      ; 2.897      ;

; -2.107 ; T80se:z80_inst|T80:u0|DO[1] ; lcdvram[11][1] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; -0.001     ; 1.418      ;

; -2.102 ; T80se:z80_inst|T80:u0|DO[1] ; lcdvram[24][1] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 1.628      ; 3.335      ;

; -2.090 ; T80se:z80_inst|T80:u0|DO[0] ; lcdvram[3][0]  ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; -0.685     ; 0.716      ;

; -2.080 ; T80se:z80_inst|T80:u0|DO[0] ; lcdvram[11][0] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.215      ; 2.073      ;

; -2.077 ; T80se:z80_inst|T80:u0|DO[3] ; lcdvram[11][3] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.009      ; 1.439      ;

; -2.067 ; T80se:z80_inst|T80:u0|DO[7] ; lcdvram[3][7]  ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.343      ; 2.188      ;

; -2.051 ; T80se:z80_inst|T80:u0|DO[5] ; lcdvram[25][5] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 1.612      ; 3.262      ;

; -2.039 ; T80se:z80_inst|T80:u0|DO[2] ; lcdvram[21][2] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 1.333      ; 2.975      ;

; -2.010 ; T80se:z80_inst|T80:u0|DO[2] ; lcdvram[8][2]  ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.331      ; 1.849      ;

; -2.006 ; T80se:z80_inst|T80:u0|DO[5] ; lcdvram[15][5] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.332      ; 1.937      ;

; -2.003 ; T80se:z80_inst|T80:u0|DO[4] ; lcdvram[8][4]  ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; -0.097     ; 1.430      ;

; -1.998 ; T80se:z80_inst|T80:u0|DO[5] ; lcdvram[29][5] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.995      ; 2.771      ;

; -1.991 ; T80se:z80_inst|T80:u0|DO[7] ; lcdvram[25][7] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 1.607      ; 3.197      ;

; -1.991 ; T80se:z80_inst|T80:u0|DO[3] ; lcdvram[24][3] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 1.647      ; 3.243      ;

; -1.984 ; T80se:z80_inst|T80:u0|DO[7] ; lcdvram[8][7]  ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.139      ; 1.895      ;

; -1.977 ; T80se:z80_inst|T80:u0|DO[6] ; lcdvram[25][6] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 1.605      ; 3.174      ;

; -1.974 ; T80se:z80_inst|T80:u0|DO[7] ; lcdvram[18][7] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 1.313      ; 2.885      ;

; -1.973 ; T80se:z80_inst|T80:u0|DO[3] ; lcdvram[20][3] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 1.722      ; 2.785      ;

; -1.968 ; T80se:z80_inst|T80:u0|DO[0] ; lcdvram[8][0]  ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.320      ; 2.073      ;

; -1.962 ; T80se:z80_inst|T80:u0|DO[2] ; lcdvram[29][2] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.853      ; 2.589      ;

; -1.955 ; T80se:z80_inst|T80:u0|DO[5] ; lcdvram[3][5]  ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.068      ; 1.492      ;

; -1.945 ; T80se:z80_inst|T80:u0|DO[7] ; lcdvram[7][7]  ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.487      ; 2.212      ;

; -1.942 ; T80se:z80_inst|T80:u0|DO[5] ; lcdvram[10][5] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.086      ; 1.491      ;

; -1.937 ; T80se:z80_inst|T80:u0|DO[3] ; lcdvram[10][3] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; -0.342     ; 0.906      ;

; -1.933 ; T80se:z80_inst|T80:u0|DO[1] ; lcdvram[22][1] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.965      ; 2.671      ;

; -1.932 ; T80se:z80_inst|T80:u0|DO[5] ; lcdvram[0][5]  ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.914      ; 2.510      ;

; -1.931 ; T80se:z80_inst|T80:u0|DO[2] ; lcdvram[3][2]  ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; -0.575     ; 0.981      ;

; -1.929 ; T80se:z80_inst|T80:u0|DO[2] ; lcdvram[25][2] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 1.775      ; 3.167      ;

; -1.927 ; T80se:z80_inst|T80:u0|DO[7] ; lcdvram[9][7]  ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.290      ; 1.858      ;

; -1.927 ; T80se:z80_inst|T80:u0|DO[2] ; lcdvram[24][2] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 1.643      ; 3.350      ;

; -1.914 ; T80se:z80_inst|T80:u0|DO[1] ; lcdvram[20][1] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 1.520      ; 3.027      ;

; -1.906 ; T80se:z80_inst|T80:u0|DO[2] ; lcdvram[16][2] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 1.929      ; 3.436      ;

; -1.905 ; T80se:z80_inst|T80:u0|DO[3] ; lcdvram[14][3] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.529      ; 1.762      ;

; -1.903 ; T80se:z80_inst|T80:u0|DO[4] ; lcdvram[25][4] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 1.581      ; 3.085      ;

; -1.903 ; T80se:z80_inst|T80:u0|DO[3] ; lcdvram[3][3]  ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.066      ; 1.439      ;

; -1.901 ; T80se:z80_inst|T80:u0|DO[6] ; lcdvram[13][6] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.094      ; 1.457      ;

; -1.898 ; T80se:z80_inst|T80:u0|DO[1] ; lcdvram[10][1] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; -0.296     ; 1.266      ;

; -1.889 ; T80se:z80_inst|T80:u0|DO[2] ; lcdvram[11][2] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.294      ; 1.825      ;

; -1.883 ; T80se:z80_inst|T80:u0|DO[7] ; lcdvram[6][7]  ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.540      ; 2.208      ;

; -1.882 ; T80se:z80_inst|T80:u0|DO[6] ; lcdvram[5][6]  ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.073      ; 1.727      ;

; -1.867 ; T80se:z80_inst|T80:u0|DO[4] ; lcdvram[20][4] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 1.514      ; 2.974      ;

; -1.866 ; T80se:z80_inst|T80:u0|DO[6] ; lcdvram[3][6]  ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; -0.575     ; 0.884      ;

; -1.859 ; T80se:z80_inst|T80:u0|DO[4] ; lcdvram[10][4] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; -0.609     ; 1.023      ;

; -1.858 ; T80se:z80_inst|T80:u0|DO[1] ; lcdvram[13][1] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.330      ; 1.968      ;

; -1.857 ; T80se:z80_inst|T80:u0|DO[6] ; lcdvram[26][6] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 1.030      ; 2.488      ;

; -1.854 ; T80se:z80_inst|T80:u0|DO[1] ; lcdvram[25][1] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 1.630      ; 3.091      ;

; -1.852 ; T80se:z80_inst|T80:u0|DO[6] ; lcdvram[2][6]  ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.053      ; 1.570      ;

; -1.851 ; T80se:z80_inst|T80:u0|DO[7] ; lcdvram[26][7] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 1.020      ; 2.645      ;

; -1.848 ; T80se:z80_inst|T80:u0|DO[4] ; lcdvram[24][4] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 1.789      ; 3.416      ;

; -1.840 ; T80se:z80_inst|T80:u0|DO[4] ; lcdvram[16][4] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 1.910      ; 3.530      ;

; -1.833 ; T80se:z80_inst|T80:u0|DO[0] ; lcdvram[5][0]  ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.074      ; 1.506      ;

; -1.832 ; T80se:z80_inst|T80:u0|DO[4] ; lcdvram[18][4] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 1.497      ; 3.117      ;

; -1.829 ; T80se:z80_inst|T80:u0|DO[4] ; lcdvram[15][4] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.707      ; 2.184      ;

; -1.829 ; T80se:z80_inst|T80:u0|DO[3] ; lcdvram[22][3] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 1.108      ; 2.405      ;

; -1.824 ; T80se:z80_inst|T80:u0|DO[7] ; lcdvram[21][7] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 1.351      ; 2.948      ;

; -1.823 ; T80se:z80_inst|T80:u0|DO[6] ; lcdvram[7][6]  ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.289      ; 1.704      ;

; -1.823 ; T80se:z80_inst|T80:u0|DO[7] ; lcdvram[24][7] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 1.661      ; 3.257      ;

; -1.816 ; T80se:z80_inst|T80:u0|DO[1] ; lcdvram[18][1] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 1.332      ; 2.920      ;

; -1.807 ; T80se:z80_inst|T80:u0|DO[2] ; lcdvram[26][2] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 1.195      ; 2.787      ;

; -1.803 ; T80se:z80_inst|T80:u0|DO[4] ; lcdvram[29][4] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.979      ; 2.566      ;

; -1.800 ; T80se:z80_inst|T80:u0|DO[4] ; lcdvram[11][4] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; -0.561     ; 0.904      ;

; -1.794 ; T80se:z80_inst|T80:u0|DO[0] ; lcdvram[2][0]  ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; -0.549     ; 0.715      ;

; -1.791 ; T80se:z80_inst|T80:u0|DO[2] ; lcdvram[7][2]  ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.288      ; 1.679      ;

; -1.788 ; T80se:z80_inst|T80:u0|DO[0] ; lcdvram[7][0]  ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.293      ; 1.680      ;

; -1.786 ; T80se:z80_inst|T80:u0|DO[2] ; lcdvram[9][2]  ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.599      ; 1.847      ;

; -1.785 ; T80se:z80_inst|T80:u0|DO[7] ; lcdvram[20][7] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 1.545      ; 2.930      ;

; -1.785 ; T80se:z80_inst|T80:u0|DO[0] ; lcdvram[10][0] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 0.501      ; 2.072      ;

; -1.784 ; T80se:z80_inst|T80:u0|DO[5] ; lcdvram[21][5] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 1.341      ; 2.724      ;

; -1.784 ; T80se:z80_inst|T80:u0|DO[1] ; lcdvram[2][1]  ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; -0.142     ; 1.105      ;

; -1.780 ; T80se:z80_inst|T80:u0|DO[0] ; lcdvram[26][0] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 1.195      ; 2.761      ;

; -1.777 ; T80se:z80_inst|T80:u0|DO[3] ; lcdvram[18][3] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 1.437      ; 2.992      ;

; -1.775 ; T80se:z80_inst|T80:u0|DO[3] ; lcdvram[21][3] ; SW[16]       ; T80se:z80_inst|MREQ_n ; 0.500        ; 1.348      ; 2.902      ;

+--------+-----------------------------+----------------+--------------+-----------------------+--------------+------------+------------+

+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+

; Slow 1200mV 85C Model Setup: 'ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered'                                                                                                                                                                                          ;

+--------+--------------------------------------------------+----------------------------------------------------+-------------------------------------------------------------+-------------------------------------------------------------+--------------+------------+------------+

; Slack  ; From Node                                        ; To Node                                            ; Launch Clock                                                ; Latch Clock                                                 ; Relationship ; Clock Skew ; Data Delay ;

+--------+--------------------------------------------------+----------------------------------------------------+-------------------------------------------------------------+-------------------------------------------------------------+--------------+------------+------------+

; -2.262 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1]   ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set    ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000        ; -0.080     ; 3.180      ;

; -2.257 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0]   ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set    ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000        ; -0.080     ; 3.175      ;

; -2.102 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[0]   ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[5] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000        ; -0.078     ; 3.022      ;

; -2.089 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[1]   ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|scan_code[5] ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000        ; -0.078     ; 3.009      ;

; -2.088 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[3]   ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set    ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000        ; -0.080     ; 3.006      ;

; -1.971 ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|INCNT[2]   ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|ready_set    ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; ps2kbd:ps2_kbd_inst|keyboard:kbd_inst|keyboard_clk_filtered ; 1.000        ; -0.080     ; 2.889      ;