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URL https://opencores.org/ocsvn/z80soc/z80soc/trunk

Subversion Repositories z80soc

[/] [z80soc/] [trunk/] [V0.7.3/] [DE2115/] [db/] [073DE2115d.lpc.html] - Blame information for rev 46

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Line No. Rev Author Line
1 46 rrred
<TABLE>
2
<TR  bgcolor="#C0C0C0">
3
<TH>Hierarchy</TH>
4
<TH>Input</TH>
5
<TH>Constant Input</TH>
6
<TH>Unused Input</TH>
7
<TH>Floating Input</TH>
8
<TH>Output</TH>
9
<TH>Constant Output</TH>
10
<TH>Unused Output</TH>
11
<TH>Floating Output</TH>
12
<TH>Bidir</TH>
13
<TH>Constant Bidir</TH>
14
<TH>Unused Bidir</TH>
15
<TH>Input only Bidir</TH>
16
<TH>Output only Bidir</TH>
17
</TR>
18
<TR >
19
<TD >lcd_inst</TD>
20
<TD >11</TD>
21
<TD >2</TD>
22
<TD >0</TD>
23
<TD >2</TD>
24
<TD >11</TD>
25
<TD >2</TD>
26
<TD >2</TD>
27
<TD >2</TD>
28
<TD >8</TD>
29
<TD >0</TD>
30
<TD >0</TD>
31
<TD >0</TD>
32
<TD >0</TD>
33
</TR>
34
<TR >
35
<TD >ps2_kbd_inst|kbd_inst</TD>
36
<TD >5</TD>
37
<TD >0</TD>
38
<TD >0</TD>
39
<TD >0</TD>
40
<TD >9</TD>
41
<TD >0</TD>
42
<TD >0</TD>
43
<TD >0</TD>
44
<TD >0</TD>
45
<TD >0</TD>
46
<TD >0</TD>
47
<TD >0</TD>
48
<TD >0</TD>
49
</TR>
50
<TR >
51
<TD >ps2_kbd_inst</TD>
52
<TD >4</TD>
53
<TD >0</TD>
54
<TD >0</TD>
55
<TD >0</TD>
56
<TD >9</TD>
57
<TD >0</TD>
58
<TD >0</TD>
59
<TD >0</TD>
60
<TD >2</TD>
61
<TD >0</TD>
62
<TD >0</TD>
63
<TD >0</TD>
64
<TD >0</TD>
65
</TR>
66
<TR >
67
<TD >DISPHEX7</TD>
68
<TD >4</TD>
69
<TD >0</TD>
70
<TD >0</TD>
71
<TD >0</TD>
72
<TD >7</TD>
73
<TD >0</TD>
74
<TD >0</TD>
75
<TD >0</TD>
76
<TD >0</TD>
77
<TD >0</TD>
78
<TD >0</TD>
79
<TD >0</TD>
80
<TD >0</TD>
81
</TR>
82
<TR >
83
<TD >DISPHEX6</TD>
84
<TD >4</TD>
85
<TD >0</TD>
86
<TD >0</TD>
87
<TD >0</TD>
88
<TD >7</TD>
89
<TD >0</TD>
90
<TD >0</TD>
91
<TD >0</TD>
92
<TD >0</TD>
93
<TD >0</TD>
94
<TD >0</TD>
95
<TD >0</TD>
96
<TD >0</TD>
97
</TR>
98
<TR >
99
<TD >DISPHEX5</TD>
100
<TD >4</TD>
101
<TD >0</TD>
102
<TD >0</TD>
103
<TD >0</TD>
104
<TD >7</TD>
105
<TD >0</TD>
106
<TD >0</TD>
107
<TD >0</TD>
108
<TD >0</TD>
109
<TD >0</TD>
110
<TD >0</TD>
111
<TD >0</TD>
112
<TD >0</TD>
113
</TR>
114
<TR >
115
<TD >DISPHEX4</TD>
116
<TD >4</TD>
117
<TD >0</TD>
118
<TD >0</TD>
119
<TD >0</TD>
120
<TD >7</TD>
121
<TD >0</TD>
122
<TD >0</TD>
123
<TD >0</TD>
124
<TD >0</TD>
125
<TD >0</TD>
126
<TD >0</TD>
127
<TD >0</TD>
128
<TD >0</TD>
129
</TR>
130
<TR >
131
<TD >DISPHEX3</TD>
132
<TD >4</TD>
133
<TD >0</TD>
134
<TD >0</TD>
135
<TD >0</TD>
136
<TD >7</TD>
137
<TD >0</TD>
138
<TD >0</TD>
139
<TD >0</TD>
140
<TD >0</TD>
141
<TD >0</TD>
142
<TD >0</TD>
143
<TD >0</TD>
144
<TD >0</TD>
145
</TR>
146
<TR >
147
<TD >DISPHEX2</TD>
148
<TD >4</TD>
149
<TD >0</TD>
150
<TD >0</TD>
151
<TD >0</TD>
152
<TD >7</TD>
153
<TD >0</TD>
154
<TD >0</TD>
155
<TD >0</TD>
156
<TD >0</TD>
157
<TD >0</TD>
158
<TD >0</TD>
159
<TD >0</TD>
160
<TD >0</TD>
161
</TR>
162
<TR >
163
<TD >DISPHEX1</TD>
164
<TD >4</TD>
165
<TD >0</TD>
166
<TD >0</TD>
167
<TD >0</TD>
168
<TD >7</TD>
169
<TD >0</TD>
170
<TD >0</TD>
171
<TD >0</TD>
172
<TD >0</TD>
173
<TD >0</TD>
174
<TD >0</TD>
175
<TD >0</TD>
176
<TD >0</TD>
177
</TR>
178
<TR >
179
<TD >DISPHEX0</TD>
180
<TD >4</TD>
181
<TD >0</TD>
182
<TD >0</TD>
183
<TD >0</TD>
184
<TD >7</TD>
185
<TD >0</TD>
186
<TD >0</TD>
187
<TD >0</TD>
188
<TD >0</TD>
189
<TD >0</TD>
190
<TD >0</TD>
191
<TD >0</TD>
192
<TD >0</TD>
193
</TR>
194
<TR >
195
<TD >clkdiv_inst</TD>
196
<TD >1</TD>
197
<TD >5</TD>
198
<TD >0</TD>
199
<TD >5</TD>
200
<TD >10</TD>
201
<TD >5</TD>
202
<TD >5</TD>
203
<TD >5</TD>
204
<TD >0</TD>
205
<TD >0</TD>
206
<TD >0</TD>
207
<TD >0</TD>
208
<TD >0</TD>
209
</TR>
210
<TR >
211
<TD >rom_inst|altsyncram_component|auto_generated|mux2</TD>
212
<TD >17</TD>
213
<TD >0</TD>
214
<TD >0</TD>
215
<TD >0</TD>
216
<TD >8</TD>
217
<TD >0</TD>
218
<TD >0</TD>
219
<TD >0</TD>
220
<TD >0</TD>
221
<TD >0</TD>
222
<TD >0</TD>
223
<TD >0</TD>
224
<TD >0</TD>
225
</TR>
226
<TR >
227
<TD >rom_inst|altsyncram_component|auto_generated|rden_decode</TD>
228
<TD >1</TD>
229
<TD >0</TD>
230
<TD >0</TD>
231
<TD >0</TD>
232
<TD >2</TD>
233
<TD >0</TD>
234
<TD >0</TD>
235
<TD >0</TD>
236
<TD >0</TD>
237
<TD >0</TD>
238
<TD >0</TD>
239
<TD >0</TD>
240
<TD >0</TD>
241
</TR>
242
<TR >
243
<TD >rom_inst|altsyncram_component|auto_generated</TD>
244
<TD >15</TD>
245
<TD >0</TD>
246
<TD >0</TD>
247
<TD >0</TD>
248
<TD >8</TD>
249
<TD >0</TD>
250
<TD >0</TD>
251
<TD >0</TD>
252
<TD >0</TD>
253
<TD >0</TD>
254
<TD >0</TD>
255
<TD >0</TD>
256
<TD >0</TD>
257
</TR>
258
<TR >
259
<TD >rom_inst</TD>
260
<TD >15</TD>
261
<TD >0</TD>
262
<TD >0</TD>
263
<TD >0</TD>
264
<TD >8</TD>
265
<TD >0</TD>
266
<TD >0</TD>
267
<TD >0</TD>
268
<TD >0</TD>
269
<TD >0</TD>
270
<TD >0</TD>
271
<TD >0</TD>
272
<TD >0</TD>
273
</TR>
274
<TR >
275
<TD >cram|altsyncram_component|auto_generated</TD>
276
<TD >33</TD>
277
<TD >0</TD>
278
<TD >0</TD>
279
<TD >0</TD>
280
<TD >8</TD>
281
<TD >0</TD>
282
<TD >0</TD>
283
<TD >0</TD>
284
<TD >0</TD>
285
<TD >0</TD>
286
<TD >0</TD>
287
<TD >0</TD>
288
<TD >0</TD>
289
</TR>
290
<TR >
291
<TD >cram</TD>
292
<TD >33</TD>
293
<TD >0</TD>
294
<TD >0</TD>
295
<TD >0</TD>
296
<TD >8</TD>
297
<TD >0</TD>
298
<TD >0</TD>
299
<TD >0</TD>
300
<TD >0</TD>
301
<TD >0</TD>
302
<TD >0</TD>
303
<TD >0</TD>
304
<TD >0</TD>
305
</TR>
306
<TR >
307
<TD >vram_inst|altsyncram_component|auto_generated</TD>
308
<TD >37</TD>
309
<TD >0</TD>
310
<TD >0</TD>
311
<TD >0</TD>
312
<TD >8</TD>
313
<TD >0</TD>
314
<TD >0</TD>
315
<TD >0</TD>
316
<TD >0</TD>
317
<TD >0</TD>
318
<TD >0</TD>
319
<TD >0</TD>
320
<TD >0</TD>
321
</TR>
322
<TR >
323
<TD >vram_inst</TD>
324
<TD >37</TD>
325
<TD >0</TD>
326
<TD >0</TD>
327
<TD >0</TD>
328
<TD >8</TD>
329
<TD >0</TD>
330
<TD >0</TD>
331
<TD >0</TD>
332
<TD >0</TD>
333
<TD >0</TD>
334
<TD >0</TD>
335
<TD >0</TD>
336
<TD >0</TD>
337
</TR>
338
<TR >
339
<TD >video_inst|vga_sync_inst</TD>
340
<TD >13</TD>
341
<TD >9</TD>
342
<TD >0</TD>
343
<TD >9</TD>
344
<TD >36</TD>
345
<TD >9</TD>
346
<TD >9</TD>
347
<TD >9</TD>
348
<TD >0</TD>
349
<TD >0</TD>
350
<TD >0</TD>
351
<TD >0</TD>
352
<TD >0</TD>
353
</TR>
354
<TR >
355
<TD >video_inst</TD>
356
<TD >17</TD>
357
<TD >3</TD>
358
<TD >0</TD>
359
<TD >3</TD>
360
<TD >42</TD>
361
<TD >3</TD>
362
<TD >3</TD>
363
<TD >3</TD>
364
<TD >0</TD>
365
<TD >0</TD>
366
<TD >0</TD>
367
<TD >0</TD>
368
<TD >0</TD>
369
</TR>
370
<TR >
371
<TD >z80_inst|u0|Regs</TD>
372
<TD >29</TD>
373
<TD >0</TD>
374
<TD >0</TD>
375
<TD >0</TD>
376
<TD >48</TD>
377
<TD >0</TD>
378
<TD >0</TD>
379
<TD >0</TD>
380
<TD >0</TD>
381
<TD >0</TD>
382
<TD >0</TD>
383
<TD >0</TD>
384
<TD >0</TD>
385
</TR>
386
<TR >
387
<TD >z80_inst|u0|alu</TD>
388
<TD >38</TD>
389
<TD >0</TD>
390
<TD >0</TD>
391
<TD >0</TD>
392
<TD >16</TD>
393
<TD >0</TD>
394
<TD >0</TD>
395
<TD >0</TD>
396
<TD >0</TD>
397
<TD >0</TD>
398
<TD >0</TD>
399
<TD >0</TD>
400
<TD >0</TD>
401
</TR>
402
<TR >
403
<TD >z80_inst|u0|mcode</TD>
404
<TD >23</TD>
405
<TD >0</TD>
406
<TD >4</TD>
407
<TD >0</TD>
408
<TD >68</TD>
409
<TD >0</TD>
410
<TD >0</TD>
411
<TD >0</TD>
412
<TD >0</TD>
413
<TD >0</TD>
414
<TD >0</TD>
415
<TD >0</TD>
416
<TD >0</TD>
417
</TR>
418
<TR >
419
<TD >z80_inst|u0</TD>
420
<TD >23</TD>
421
<TD >2</TD>
422
<TD >0</TD>
423
<TD >2</TD>
424
<TD >40</TD>
425
<TD >2</TD>
426
<TD >2</TD>
427
<TD >2</TD>
428
<TD >0</TD>
429
<TD >0</TD>
430
<TD >0</TD>
431
<TD >0</TD>
432
<TD >0</TD>
433
</TR>
434
<TR >
435
<TD >z80_inst</TD>
436
<TD >15</TD>
437
<TD >9</TD>
438
<TD >0</TD>
439
<TD >9</TD>
440
<TD >32</TD>
441
<TD >9</TD>
442
<TD >9</TD>
443
<TD >9</TD>
444
<TD >0</TD>
445
<TD >0</TD>
446
<TD >0</TD>
447
<TD >0</TD>
448
<TD >0</TD>
449
</TR>
450
</TABLE>

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