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[/] [z80soc/] [trunk/] [V0.7.3/] [DE2115/] [db/] [altsyncram_l4o1.tdf] - Blame information for rev 46

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1 46 rrred
--altsyncram ADDRESS_REG_B="CLOCK1" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CLOCK_ENABLE_INPUT_A="BYPASS" CLOCK_ENABLE_INPUT_B="BYPASS" CLOCK_ENABLE_OUTPUT_A="BYPASS" CLOCK_ENABLE_OUTPUT_B="BYPASS" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="Cyclone IV E" INIT_FILE="./ROMdata/lat9-08.mif" LOW_POWER_MODE="AUTO" NUMWORDS_A=2048 NUMWORDS_B=2048 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" POWER_UP_UNINITIALIZED="FALSE" WIDTH_A=8 WIDTH_B=8 WIDTH_BYTEENA_A=1 WIDTHAD_A=11 WIDTHAD_B=11 address_a address_b clock0 clock1 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
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--VERSION_BEGIN 13.0 cbx_altsyncram 2013:06:12:18:03:43:SJ cbx_cycloneii 2013:06:12:18:03:43:SJ cbx_lpm_add_sub 2013:06:12:18:03:43:SJ cbx_lpm_compare 2013:06:12:18:03:43:SJ cbx_lpm_decode 2013:06:12:18:03:43:SJ cbx_lpm_mux 2013:06:12:18:03:43:SJ cbx_mgl 2013:06:12:18:05:10:SJ cbx_stratix 2013:06:12:18:03:43:SJ cbx_stratixii 2013:06:12:18:03:43:SJ cbx_stratixiii 2013:06:12:18:03:43:SJ cbx_stratixv 2013:06:12:18:03:43:SJ cbx_util_mgl 2013:06:12:18:03:43:SJ  VERSION_END
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-- Copyright (C) 1991-2013 Altera Corporation
6
--  Your use of Altera Corporation's design tools, logic functions
7
--  and other software and tools, and its AMPP partner logic
8
--  functions, and any output files from any of the foregoing
9
--  (including device programming or simulation files), and any
10
--  associated documentation or information are expressly subject
11
--  to the terms and conditions of the Altera Program License
12
--  Subscription Agreement, Altera MegaCore Function License
13
--  Agreement, or other applicable license agreement, including,
14
--  without limitation, that your use is for the sole purpose of
15
--  programming logic devices manufactured by Altera and sold by
16
--  Altera or its authorized distributors.  Please refer to the
17
--  applicable agreement for further details.
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19
 
20
FUNCTION cycloneive_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
21
WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
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RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);
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--synthesis_resources = M9K 2
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OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";
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27
SUBDESIGN altsyncram_l4o1
28
(
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        address_a[10..0]        :       input;
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        address_b[10..0]        :       input;
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        clock0  :       input;
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        clock1  :       input;
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        data_a[7..0]    :       input;
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        q_b[7..0]       :       output;
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        wren_a  :       input;
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)
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VARIABLE
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        ram_block1a0 : cycloneive_ram_block
39
                WITH (
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                        CLK0_CORE_CLOCK_ENABLE = "ena0",
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                        CLK0_INPUT_CLOCK_ENABLE = "none",
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                        CLK1_CORE_CLOCK_ENABLE = "none",
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                        CLK1_INPUT_CLOCK_ENABLE = "none",
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                        CONNECTIVITY_CHECKING = "OFF",
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                        INIT_FILE = "./ROMdata/lat9-08.mif",
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                        INIT_FILE_LAYOUT = "port_b",
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                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
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                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
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                        OPERATION_MODE = "dual_port",
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                        PORT_A_ADDRESS_WIDTH = 11,
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                        PORT_A_DATA_WIDTH = 1,
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                        PORT_A_FIRST_ADDRESS = 0,
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                        PORT_A_FIRST_BIT_NUMBER = 0,
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                        PORT_A_LAST_ADDRESS = 2047,
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                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
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                        PORT_A_LOGICAL_RAM_WIDTH = 8,
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                        PORT_B_ADDRESS_CLEAR = "none",
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                        PORT_B_ADDRESS_CLOCK = "clock1",
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                        PORT_B_ADDRESS_WIDTH = 11,
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                        PORT_B_DATA_OUT_CLEAR = "none",
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                        PORT_B_DATA_WIDTH = 1,
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                        PORT_B_FIRST_ADDRESS = 0,
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                        PORT_B_FIRST_BIT_NUMBER = 0,
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                        PORT_B_LAST_ADDRESS = 2047,
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                        PORT_B_LOGICAL_RAM_DEPTH = 2048,
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                        PORT_B_LOGICAL_RAM_WIDTH = 8,
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                        PORT_B_READ_ENABLE_CLOCK = "clock1",
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                        POWER_UP_UNINITIALIZED = "false",
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                        RAM_BLOCK_TYPE = "AUTO"
70
                );
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        ram_block1a1 : cycloneive_ram_block
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                WITH (
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                        CLK0_CORE_CLOCK_ENABLE = "ena0",
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                        CLK0_INPUT_CLOCK_ENABLE = "none",
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                        CLK1_CORE_CLOCK_ENABLE = "none",
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                        CLK1_INPUT_CLOCK_ENABLE = "none",
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                        CONNECTIVITY_CHECKING = "OFF",
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                        INIT_FILE = "./ROMdata/lat9-08.mif",
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                        INIT_FILE_LAYOUT = "port_b",
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                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
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                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
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                        OPERATION_MODE = "dual_port",
83
                        PORT_A_ADDRESS_WIDTH = 11,
84
                        PORT_A_DATA_WIDTH = 1,
85
                        PORT_A_FIRST_ADDRESS = 0,
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                        PORT_A_FIRST_BIT_NUMBER = 1,
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                        PORT_A_LAST_ADDRESS = 2047,
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                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
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                        PORT_A_LOGICAL_RAM_WIDTH = 8,
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                        PORT_B_ADDRESS_CLEAR = "none",
91
                        PORT_B_ADDRESS_CLOCK = "clock1",
92
                        PORT_B_ADDRESS_WIDTH = 11,
93
                        PORT_B_DATA_OUT_CLEAR = "none",
94
                        PORT_B_DATA_WIDTH = 1,
95
                        PORT_B_FIRST_ADDRESS = 0,
96
                        PORT_B_FIRST_BIT_NUMBER = 1,
97
                        PORT_B_LAST_ADDRESS = 2047,
98
                        PORT_B_LOGICAL_RAM_DEPTH = 2048,
99
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
100
                        PORT_B_READ_ENABLE_CLOCK = "clock1",
101
                        POWER_UP_UNINITIALIZED = "false",
102
                        RAM_BLOCK_TYPE = "AUTO"
103
                );
104
        ram_block1a2 : cycloneive_ram_block
105
                WITH (
106
                        CLK0_CORE_CLOCK_ENABLE = "ena0",
107
                        CLK0_INPUT_CLOCK_ENABLE = "none",
108
                        CLK1_CORE_CLOCK_ENABLE = "none",
109
                        CLK1_INPUT_CLOCK_ENABLE = "none",
110
                        CONNECTIVITY_CHECKING = "OFF",
111
                        INIT_FILE = "./ROMdata/lat9-08.mif",
112
                        INIT_FILE_LAYOUT = "port_b",
113
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
114
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
115
                        OPERATION_MODE = "dual_port",
116
                        PORT_A_ADDRESS_WIDTH = 11,
117
                        PORT_A_DATA_WIDTH = 1,
118
                        PORT_A_FIRST_ADDRESS = 0,
119
                        PORT_A_FIRST_BIT_NUMBER = 2,
120
                        PORT_A_LAST_ADDRESS = 2047,
121
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
122
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
123
                        PORT_B_ADDRESS_CLEAR = "none",
124
                        PORT_B_ADDRESS_CLOCK = "clock1",
125
                        PORT_B_ADDRESS_WIDTH = 11,
126
                        PORT_B_DATA_OUT_CLEAR = "none",
127
                        PORT_B_DATA_WIDTH = 1,
128
                        PORT_B_FIRST_ADDRESS = 0,
129
                        PORT_B_FIRST_BIT_NUMBER = 2,
130
                        PORT_B_LAST_ADDRESS = 2047,
131
                        PORT_B_LOGICAL_RAM_DEPTH = 2048,
132
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
133
                        PORT_B_READ_ENABLE_CLOCK = "clock1",
134
                        POWER_UP_UNINITIALIZED = "false",
135
                        RAM_BLOCK_TYPE = "AUTO"
136
                );
137
        ram_block1a3 : cycloneive_ram_block
138
                WITH (
139
                        CLK0_CORE_CLOCK_ENABLE = "ena0",
140
                        CLK0_INPUT_CLOCK_ENABLE = "none",
141
                        CLK1_CORE_CLOCK_ENABLE = "none",
142
                        CLK1_INPUT_CLOCK_ENABLE = "none",
143
                        CONNECTIVITY_CHECKING = "OFF",
144
                        INIT_FILE = "./ROMdata/lat9-08.mif",
145
                        INIT_FILE_LAYOUT = "port_b",
146
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
147
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
148
                        OPERATION_MODE = "dual_port",
149
                        PORT_A_ADDRESS_WIDTH = 11,
150
                        PORT_A_DATA_WIDTH = 1,
151
                        PORT_A_FIRST_ADDRESS = 0,
152
                        PORT_A_FIRST_BIT_NUMBER = 3,
153
                        PORT_A_LAST_ADDRESS = 2047,
154
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
155
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
156
                        PORT_B_ADDRESS_CLEAR = "none",
157
                        PORT_B_ADDRESS_CLOCK = "clock1",
158
                        PORT_B_ADDRESS_WIDTH = 11,
159
                        PORT_B_DATA_OUT_CLEAR = "none",
160
                        PORT_B_DATA_WIDTH = 1,
161
                        PORT_B_FIRST_ADDRESS = 0,
162
                        PORT_B_FIRST_BIT_NUMBER = 3,
163
                        PORT_B_LAST_ADDRESS = 2047,
164
                        PORT_B_LOGICAL_RAM_DEPTH = 2048,
165
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
166
                        PORT_B_READ_ENABLE_CLOCK = "clock1",
167
                        POWER_UP_UNINITIALIZED = "false",
168
                        RAM_BLOCK_TYPE = "AUTO"
169
                );
170
        ram_block1a4 : cycloneive_ram_block
171
                WITH (
172
                        CLK0_CORE_CLOCK_ENABLE = "ena0",
173
                        CLK0_INPUT_CLOCK_ENABLE = "none",
174
                        CLK1_CORE_CLOCK_ENABLE = "none",
175
                        CLK1_INPUT_CLOCK_ENABLE = "none",
176
                        CONNECTIVITY_CHECKING = "OFF",
177
                        INIT_FILE = "./ROMdata/lat9-08.mif",
178
                        INIT_FILE_LAYOUT = "port_b",
179
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
180
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
181
                        OPERATION_MODE = "dual_port",
182
                        PORT_A_ADDRESS_WIDTH = 11,
183
                        PORT_A_DATA_WIDTH = 1,
184
                        PORT_A_FIRST_ADDRESS = 0,
185
                        PORT_A_FIRST_BIT_NUMBER = 4,
186
                        PORT_A_LAST_ADDRESS = 2047,
187
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
188
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
189
                        PORT_B_ADDRESS_CLEAR = "none",
190
                        PORT_B_ADDRESS_CLOCK = "clock1",
191
                        PORT_B_ADDRESS_WIDTH = 11,
192
                        PORT_B_DATA_OUT_CLEAR = "none",
193
                        PORT_B_DATA_WIDTH = 1,
194
                        PORT_B_FIRST_ADDRESS = 0,
195
                        PORT_B_FIRST_BIT_NUMBER = 4,
196
                        PORT_B_LAST_ADDRESS = 2047,
197
                        PORT_B_LOGICAL_RAM_DEPTH = 2048,
198
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
199
                        PORT_B_READ_ENABLE_CLOCK = "clock1",
200
                        POWER_UP_UNINITIALIZED = "false",
201
                        RAM_BLOCK_TYPE = "AUTO"
202
                );
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        ram_block1a5 : cycloneive_ram_block
204
                WITH (
205
                        CLK0_CORE_CLOCK_ENABLE = "ena0",
206
                        CLK0_INPUT_CLOCK_ENABLE = "none",
207
                        CLK1_CORE_CLOCK_ENABLE = "none",
208
                        CLK1_INPUT_CLOCK_ENABLE = "none",
209
                        CONNECTIVITY_CHECKING = "OFF",
210
                        INIT_FILE = "./ROMdata/lat9-08.mif",
211
                        INIT_FILE_LAYOUT = "port_b",
212
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
213
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
214
                        OPERATION_MODE = "dual_port",
215
                        PORT_A_ADDRESS_WIDTH = 11,
216
                        PORT_A_DATA_WIDTH = 1,
217
                        PORT_A_FIRST_ADDRESS = 0,
218
                        PORT_A_FIRST_BIT_NUMBER = 5,
219
                        PORT_A_LAST_ADDRESS = 2047,
220
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
221
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
222
                        PORT_B_ADDRESS_CLEAR = "none",
223
                        PORT_B_ADDRESS_CLOCK = "clock1",
224
                        PORT_B_ADDRESS_WIDTH = 11,
225
                        PORT_B_DATA_OUT_CLEAR = "none",
226
                        PORT_B_DATA_WIDTH = 1,
227
                        PORT_B_FIRST_ADDRESS = 0,
228
                        PORT_B_FIRST_BIT_NUMBER = 5,
229
                        PORT_B_LAST_ADDRESS = 2047,
230
                        PORT_B_LOGICAL_RAM_DEPTH = 2048,
231
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
232
                        PORT_B_READ_ENABLE_CLOCK = "clock1",
233
                        POWER_UP_UNINITIALIZED = "false",
234
                        RAM_BLOCK_TYPE = "AUTO"
235
                );
236
        ram_block1a6 : cycloneive_ram_block
237
                WITH (
238
                        CLK0_CORE_CLOCK_ENABLE = "ena0",
239
                        CLK0_INPUT_CLOCK_ENABLE = "none",
240
                        CLK1_CORE_CLOCK_ENABLE = "none",
241
                        CLK1_INPUT_CLOCK_ENABLE = "none",
242
                        CONNECTIVITY_CHECKING = "OFF",
243
                        INIT_FILE = "./ROMdata/lat9-08.mif",
244
                        INIT_FILE_LAYOUT = "port_b",
245
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
246
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
247
                        OPERATION_MODE = "dual_port",
248
                        PORT_A_ADDRESS_WIDTH = 11,
249
                        PORT_A_DATA_WIDTH = 1,
250
                        PORT_A_FIRST_ADDRESS = 0,
251
                        PORT_A_FIRST_BIT_NUMBER = 6,
252
                        PORT_A_LAST_ADDRESS = 2047,
253
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
254
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
255
                        PORT_B_ADDRESS_CLEAR = "none",
256
                        PORT_B_ADDRESS_CLOCK = "clock1",
257
                        PORT_B_ADDRESS_WIDTH = 11,
258
                        PORT_B_DATA_OUT_CLEAR = "none",
259
                        PORT_B_DATA_WIDTH = 1,
260
                        PORT_B_FIRST_ADDRESS = 0,
261
                        PORT_B_FIRST_BIT_NUMBER = 6,
262
                        PORT_B_LAST_ADDRESS = 2047,
263
                        PORT_B_LOGICAL_RAM_DEPTH = 2048,
264
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
265
                        PORT_B_READ_ENABLE_CLOCK = "clock1",
266
                        POWER_UP_UNINITIALIZED = "false",
267
                        RAM_BLOCK_TYPE = "AUTO"
268
                );
269
        ram_block1a7 : cycloneive_ram_block
270
                WITH (
271
                        CLK0_CORE_CLOCK_ENABLE = "ena0",
272
                        CLK0_INPUT_CLOCK_ENABLE = "none",
273
                        CLK1_CORE_CLOCK_ENABLE = "none",
274
                        CLK1_INPUT_CLOCK_ENABLE = "none",
275
                        CONNECTIVITY_CHECKING = "OFF",
276
                        INIT_FILE = "./ROMdata/lat9-08.mif",
277
                        INIT_FILE_LAYOUT = "port_b",
278
                        LOGICAL_RAM_NAME = "ALTSYNCRAM",
279
                        MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
280
                        OPERATION_MODE = "dual_port",
281
                        PORT_A_ADDRESS_WIDTH = 11,
282
                        PORT_A_DATA_WIDTH = 1,
283
                        PORT_A_FIRST_ADDRESS = 0,
284
                        PORT_A_FIRST_BIT_NUMBER = 7,
285
                        PORT_A_LAST_ADDRESS = 2047,
286
                        PORT_A_LOGICAL_RAM_DEPTH = 2048,
287
                        PORT_A_LOGICAL_RAM_WIDTH = 8,
288
                        PORT_B_ADDRESS_CLEAR = "none",
289
                        PORT_B_ADDRESS_CLOCK = "clock1",
290
                        PORT_B_ADDRESS_WIDTH = 11,
291
                        PORT_B_DATA_OUT_CLEAR = "none",
292
                        PORT_B_DATA_WIDTH = 1,
293
                        PORT_B_FIRST_ADDRESS = 0,
294
                        PORT_B_FIRST_BIT_NUMBER = 7,
295
                        PORT_B_LAST_ADDRESS = 2047,
296
                        PORT_B_LOGICAL_RAM_DEPTH = 2048,
297
                        PORT_B_LOGICAL_RAM_WIDTH = 8,
298
                        PORT_B_READ_ENABLE_CLOCK = "clock1",
299
                        POWER_UP_UNINITIALIZED = "false",
300
                        RAM_BLOCK_TYPE = "AUTO"
301
                );
302
        address_a_wire[10..0]   : WIRE;
303
        address_b_wire[10..0]   : WIRE;
304
 
305
BEGIN
306
        ram_block1a[7..0].clk0 = clock0;
307
        ram_block1a[7..0].clk1 = clock1;
308
        ram_block1a[7..0].ena0 = wren_a;
309
        ram_block1a[7..0].portaaddr[] = ( address_a_wire[10..0]);
310
        ram_block1a[0].portadatain[] = ( data_a[0..0]);
311
        ram_block1a[1].portadatain[] = ( data_a[1..1]);
312
        ram_block1a[2].portadatain[] = ( data_a[2..2]);
313
        ram_block1a[3].portadatain[] = ( data_a[3..3]);
314
        ram_block1a[4].portadatain[] = ( data_a[4..4]);
315
        ram_block1a[5].portadatain[] = ( data_a[5..5]);
316
        ram_block1a[6].portadatain[] = ( data_a[6..6]);
317
        ram_block1a[7].portadatain[] = ( data_a[7..7]);
318
        ram_block1a[7..0].portawe = wren_a;
319
        ram_block1a[7..0].portbaddr[] = ( address_b_wire[10..0]);
320
        ram_block1a[7..0].portbre = B"11111111";
321
        address_a_wire[] = address_a[];
322
        address_b_wire[] = address_b[];
323
        q_b[] = ( ram_block1a[7..0].portbdataout[0..0]);
324
END;
325
--VALID FILE

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